opcodes/ChangeLog

   1 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
   2
   3         * aarch64-opc.c (print_immediate_offset_address): Don't print the
   4         immediate for the writeback form of ldraa/ldrab if it is 0.
   5         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
   6         * aarch64-opc-2.c: Regenerated.
   7
   8 2019-10-30  Jan Beulich  <jbeulich@suse.com>
   9
  10         * i386-gen.c (operand_type_shorthands): Delete.
  11         (operand_type_init): Expand previous shorthands.
  12         (set_bitfield_from_shorthand): Rename back to ...
  13         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
  14         of operand_type_init[].
  15         (set_bitfield): Adjust call to the above function.
  16         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
  17         RegXMM, RegYMM, RegZMM): Define.
  18         * i386-reg.tbl: Expand prior shorthands.
  19
  20 2019-10-30  Jan Beulich  <jbeulich@suse.com>
  21
  22         * i386-gen.c (output_i386_opcode): Change order of fields
  23         emitted to output.
  24         * i386-opc.h (struct insn_template): Move operands field.
  25         Convert extension_opcode field to unsigned short.
  26         * i386-tbl.h: Re-generate.
  27
  28 2019-10-30  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
  31         of W.
  32         * i386-opc.h (W): Extend comment.
  33         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
  34         general purpose variants not allowing for byte operands.
  35         * i386-tbl.h: Re-generate.
  36
  37 2019-10-29  Nick Clifton  <nickc@redhat.com>
  38
  39         * tic30-dis.c (print_branch): Correct size of operand array.
  40
  41 2019-10-29  Nick Clifton  <nickc@redhat.com>
  42
  43         * d30v-dis.c (print_insn): Check that operand index is valid
  44         before attempting to access the operands array.
  45
  46 2019-10-29  Nick Clifton  <nickc@redhat.com>
  47
  48         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
  49         locating the bit to be tested.
  50
  51 2019-10-29  Nick Clifton  <nickc@redhat.com>
  52
  53         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
  54         values.
  55         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
  56         (print_insn_s12z):  Check for illegal size values.
  57
  58 2019-10-28  Nick Clifton  <nickc@redhat.com>
  59
  60         * csky-dis.c (csky_chars_to_number): Check for a negative
  61         count. Use an unsigned integer to construct the return value.
  62
  63 2019-10-28  Nick Clifton  <nickc@redhat.com>
  64
  65         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
  66         operand buffer.  Set value to 15 not 13.
  67         (get_register_operand): Use OPERAND_BUFFER_LEN.
  68         (get_indirect_operand): Likewise.
  69         (print_two_operand): Likewise.
  70         (print_three_operand): Likewise.
  71         (print_oar_insn): Likewise.
  72
  73 2019-10-28  Nick Clifton  <nickc@redhat.com>
  74
  75         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
  76         (bit_extract_simple): Likewise.
  77         (bit_copy): Likewise.
  78         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
  79         index_offset array are not accessed.
  80
  81 2019-10-28  Nick Clifton  <nickc@redhat.com>
  82
  83         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
  84         operand.
  85
  86 2019-10-25  Nick Clifton  <nickc@redhat.com>
  87
  88         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
  89         access to opcodes.op array element.
  90
  91 2019-10-23  Nick Clifton  <nickc@redhat.com>
  92
  93         * rx-dis.c (get_register_name): Fix spelling typo in error
  94         message.
  95         (get_condition_name, get_flag_name, get_double_register_name)
  96         (get_double_register_high_name, get_double_register_low_name)
  97         (get_double_control_register_name, get_double_condition_name)
  98         (get_opsize_name, get_size_name): Likewise.
  99
 100 2019-10-22  Nick Clifton  <nickc@redhat.com>
 101
 102         * rx-dis.c (get_size_name): New function.  Provides safe
 103         access to name array.
 104         (get_opsize_name): Likewise.
 105         (print_insn_rx): Use the accessor functions.
 106
 107 2019-10-16  Nick Clifton  <nickc@redhat.com>
 108
 109         * rx-dis.c (get_register_name): New function.  Provides safe
 110         access to name array.
 111         (get_condition_name, get_flag_name, get_double_register_name)
 112         (get_double_register_high_name, get_double_register_low_name)
 113         (get_double_control_register_name, get_double_condition_name):
 114         Likewise.
 115         (print_insn_rx): Use the accessor functions.
 116
 117 2019-10-09  Nick Clifton  <nickc@redhat.com>
 118
 119         PR 25041
 120         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 121         instructions.
 122
 123 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 124
 125         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 126         (cmpsd): Likewise. Move EsSeg to other operand.
 127         * opcodes/i386-tbl.h: Re-generate.
 128
 129 2019-09-23  Alan Modra  <amodra@gmail.com>
 130
 131         * m68k-dis.c: Include cpu-m68k.h
 132
 133 2019-09-23  Alan Modra  <amodra@gmail.com>
 134
 135         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 136         "elf/mips.h" earlier.
 137
 138 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 139
 140         PR gas/25012
 141         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 142         with SReg operand.
 143         * i386-tbl.h: Re-generate.
 144
 145 2019-09-18  Alan Modra  <amodra@gmail.com>
 146
 147         * arc-ext.c: Update throughout for bfd section macro changes.
 148
 149 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 150
 151         * Makefile.in: Re-generate.
 152         * configure: Re-generate.
 153
 154 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 155
 156         * riscv-opc.c (riscv_opcodes): Change subset field
 157         to insn_class field for all instructions.
 158         (riscv_insn_types): Likewise.
 159
 160 2019-09-16  Phil Blundell  <pb@pbcl.net>
 161
 162         * configure: Regenerated.
 163
 164 2019-09-10  Miod Vallat  <miod@online.fr>
 165
 166         PR 24982
 167         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 168
 169 2019-09-09  Phil Blundell  <pb@pbcl.net>
 170
 171         binutils 2.33 branch created.
 172
 173 2019-09-03  Nick Clifton  <nickc@redhat.com>
 174
 175         PR 24961
 176         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 177         greater than zero before indexing via (bufcnt -1).
 178
 179 2019-09-03  Nick Clifton  <nickc@redhat.com>
 180
 181         PR 24958
 182         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 183         (MAX_SPEC_REG_NAME_LEN): Define.
 184         (struct mmix_dis_info): Use defined constants for array lengths.
 185         (get_reg_name): New function.
 186         (get_sprec_reg_name): New function.
 187         (print_insn_mmix): Use new functions.
 188
 189 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 190
 191         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 192         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 193         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 194
 195 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 196
 197         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 198         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 199         (aarch64_sys_reg_supported_p): Update checks for the above.
 200
 201 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 202
 203         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 204         cases MVE_SQRSHRL and MVE_UQRSHLL.
 205         (print_insn_mve): Add case for specifier 'k' to check
 206         specific bit of the instruction.
 207
 208 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 209
 210         PR 24854
 211         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 212         encountering an unknown machine type.
 213         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 214         cases return -1 rather than calling abort.
 215
 216 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 219         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 220         IgnoreSize.
 221         * i386-tbl.h: Re-generate.
 222
 223 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 224
 225         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 226         instructions.
 227
 228 2019-07-30  Mel Chen <mel.chen@sifive.com>
 229
 230         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 231         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 232
 233         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 234         fscsr.
 235
 236 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 237
 238         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 239         and MPY class instructions.
 240         (parse_option): Add nps400 option.
 241         (print_arc_disassembler_options): Add nps400 info.
 242
 243 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 244
 245         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 246         (bspop): Likewise.
 247         (modapp): Likewise.
 248         * arc-opc.c (RAD_CHK): Add.
 249         * arc-tbl.h: Regenerate.
 250
 251 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 252
 253         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 254         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 255
 256 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 257
 258         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 259         instructions as UNPREDICTABLE.
 260
 261 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 262
 263         * bpf-desc.c: Regenerated.
 264
 265 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 266
 267         * i386-gen.c (static_assert): Define.
 268         (main): Use it.
 269         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 270         (Opcode_Modifier_Num): ... this.
 271         (Mem): Delete.
 272
 273 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 274
 275         * i386-gen.c (operand_types): Move RegMem ...
 276         (opcode_modifiers): ... here.
 277         * i386-opc.h (RegMem): Move to opcode modifer enum.
 278         (union i386_operand_type): Move regmem field ...
 279         (struct i386_opcode_modifier): ... here.
 280         * i386-opc.tbl (RegMem): Define.
 281         (mov, movq): Move RegMem on segment, control, debug, and test
 282         register flavors.
 283         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 284         to non-SSE2AVX flavor.
 285         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 286         Move RegMem on register only flavors. Drop IgnoreSize from
 287         legacy encoding flavors.
 288         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 289         flavors.
 290         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 291         register only flavors.
 292         (vmovd): Move RegMem and drop IgnoreSize on register only
 293         flavor. Change opcode and operand order to store form.
 294         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 295
 296 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 297
 298         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 299         entries.
 300         * i386-opc.h (SReg2, SReg3): Replace by ...
 301         (SReg): ... this.
 302         (union i386_operand_type): Replace sreg fields.
 303         * i386-opc.tbl (mov, ): Use SReg.
 304         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 305         register flavors.
 306         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 307         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 308
 309 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 310
 311         * bpf-desc.c: Regenerate.
 312         * bpf-opc.c: Likewise.
 313         * bpf-opc.h: Likewise.
 314
 315 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 316
 317         * bpf-desc.c: Regenerate.
 318         * bpf-opc.c: Likewise.
 319
 320 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 321
 322         * arm-dis.c (print_insn_coprocessor): Rename index to
 323         index_operand.
 324
 325 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 326
 327         * riscv-opc.c (riscv_insn_types): Add r4 type.
 328
 329         * riscv-opc.c (riscv_insn_types): Add b and j type.
 330
 331         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 332         format for sb type and correct s type.
 333
 334 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 335
 336         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 337         SVE FMOV alias of FCPY.
 338
 339 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 340
 341         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 342         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 343
 344 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 345
 346         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 347         registers in an instruction prefixed by MOVPRFX.
 348
 349 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 350
 351         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 352         sve_size_13 icode to account for variant behaviour of
 353         pmull{t,b}.
 354         * aarch64-dis-2.c: Regenerate.
 355         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 356         sve_size_13 icode to account for variant behaviour of
 357         pmull{t,b}.
 358         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 359         (OP_SVE_VVV_Q_D): Add new qualifier.
 360         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 361         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 362         AES and those not.
 363
 364 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 365
 366         * opcodes/i386-gen.c (operand_type_init): Remove
 367         OPERAND_TYPE_VEC_IMM4 entry.
 368         (operand_types): Remove Vec_Imm4.
 369         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 370         (union i386_operand_type): Remove vec_imm4.
 371         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 372         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 373
 374 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 375
 376         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 377         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 378         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 379         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 380         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 381         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 382         * i386-tbl.h: Re-generate.
 383
 384 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 385
 386         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 387         register operands.
 388         * i386-tbl.h: Re-generate.
 389
 390 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-opc.tbl (C): New.
 393         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 394         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 395         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 396         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 397         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 398         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 399         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 400         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 401         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 402         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 403         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 404         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 405         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 406         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 407         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 408         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 409         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 410         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 411         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 412         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 413         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 414         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 415         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 416         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 417         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 418         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 419         flavors.
 420         * i386-tbl.h: Re-generate.
 421
 422 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 423
 424         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 425         register operands.
 426         * i386-tbl.h: Re-generate.
 427
 428 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 429
 430         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 431         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 432         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 433         * i386-tbl.h: Re-generate.
 434
 435 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 436
 437         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 438         Disp8MemShift from register only templates.
 439         * i386-tbl.h: Re-generate.
 440
 441 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 442
 443         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 444         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 445         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 446         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 447         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 448         EVEX_W_0F11_P_3_M_1): Delete.
 449         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 450         EVEX_W_0F11_P_3): New.
 451         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 452         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 453         MOD_EVEX_0F11_PREFIX_3 table entries.
 454         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 455         PREFIX_EVEX_0F11 table entries.
 456         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 457         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 458         EVEX_W_0F11_P_3_M_{0,1} table entries.
 459
 460 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 461
 462         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 463         Delete.
 464
 465 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 466
 467         PR binutils/24719
 468         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 469         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 470         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 471         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 472         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 473         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 474         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 475         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 476         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 477         PREFIX_EVEX_0F38C6_REG_6 entries.
 478         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 479         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 480         EVEX_W_0F38C7_R_6_P_2 entries.
 481         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 482         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 483         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 484         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 485         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 486         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 487         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 488
 489 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 492         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 493         VEX_LEN_0F2D_P_3): Delete.
 494         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 495         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 496         (prefix_table): ... here.
 497
 498 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-dis.c (Iq): Delete.
 501         (Id): New.
 502         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 503         TBM insns.
 504         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 505         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 506         (OP_E_memory): Also honor needindex when deciding whether an
 507         address size prefix needs printing.
 508         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 509
 510 2019-06-26  Jim Wilson  <jimw@sifive.com>
 511
 512         PR binutils/24739
 513         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 514         Set info->display_endian to info->endian_code.
 515
 516 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 517
 518         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 519         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 520         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 521         OPERAND_TYPE_ACC64 entries.
 522         * i386-init.h: Re-generate.
 523
 524 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 525
 526         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 527         Delete.
 528         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 529         of dqa_mode.
 530         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 531         entries here.
 532         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 533         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 534
 535 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 536
 537         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 538         variables.
 539
 540 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 541
 542         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 543         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 544         movnti.
 545         * i386-opc.tbl (movnti): Add IgnoreSize.
 546         * i386-tbl.h: Re-generate.
 547
 548 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 549
 550         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 551         * i386-tbl.h: Re-generate.
 552
 553 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 554
 555         * i386-dis-evex.h: Break into ...
 556         * i386-dis-evex-len.h: New file.
 557         * i386-dis-evex-mod.h: Likewise.
 558         * i386-dis-evex-prefix.h: Likewise.
 559         * i386-dis-evex-reg.h: Likewise.
 560         * i386-dis-evex-w.h: Likewise.
 561         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 562         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 563         i386-dis-evex-mod.h.
 564
 565 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 566
 567         PR binutils/24700
 568         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 569         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 570         EVEX_W_0F385B_P_2.
 571         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 572         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 573         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 574         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 575         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 576         EVEX_LEN_0F385B_P_2_W_1.
 577         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 578         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 579         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 580         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 581         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 582         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 583         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 584         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 585         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 586         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 587
 588 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 589
 590         PR binutils/24691
 591         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 592         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 593         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 594         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 595         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 596         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 597         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 598         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 599         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 600         EVEX_LEN_0F3A43_P_2_W_1.
 601         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 602         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 603         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 604         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 605         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 606         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 607         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 608         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 609         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 610         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 611         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 612         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 613
 614 2019-06-14  Nick Clifton  <nickc@redhat.com>
 615
 616         * po/fr.po; Updated French translation.
 617
 618 2019-06-13  Stafford Horne  <shorne@gmail.com>
 619
 620         * or1k-asm.c: Regenerated.
 621         * or1k-desc.c: Regenerated.
 622         * or1k-desc.h: Regenerated.
 623         * or1k-dis.c: Regenerated.
 624         * or1k-ibld.c: Regenerated.
 625         * or1k-opc.c: Regenerated.
 626         * or1k-opc.h: Regenerated.
 627         * or1k-opinst.c: Regenerated.
 628
 629 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 630
 631         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 632
 633 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 634
 635         PR binutils/24633
 636         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 637         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 638         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 639         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 640         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 641         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 642         EVEX_LEN_0F3A1B_P_2_W_1.
 643         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 644         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 645         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 646         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 647         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 648         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 649         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 650         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 651
 652 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 653
 654         PR binutils/24626
 655         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 656         EVEX.vvvv when disassembling VEX and EVEX instructions.
 657         (OP_VEX): Set vex.register_specifier to 0 after readding
 658         vex.register_specifier.
 659         (OP_Vex_2src_1): Likewise.
 660         (OP_Vex_2src_2): Likewise.
 661         (OP_LWP_E): Likewise.
 662         (OP_EX_Vex): Don't check vex.register_specifier.
 663         (OP_XMM_Vex): Likewise.
 664
 665 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 666             Lili Cui  <lili.cui@intel.com>
 667
 668         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 669         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 670         instructions.
 671         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 672         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 673         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 674         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 675         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 676         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 677         * i386-init.h: Regenerated.
 678         * i386-tbl.h: Likewise.
 679
 680 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 681             Lili Cui  <lili.cui@intel.com>
 682
 683         * doc/c-i386.texi: Document enqcmd.
 684         * testsuite/gas/i386/enqcmd-intel.d: New file.
 685         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 686         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 687         * testsuite/gas/i386/enqcmd.d: Likewise.
 688         * testsuite/gas/i386/enqcmd.s: Likewise.
 689         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 690         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 691         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 692         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 693         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 694         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 695         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 696         and x86-64-enqcmd.
 697
 698 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 699
 700         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 701
 702 2019-06-03  Alan Modra  <amodra@gmail.com>
 703
 704         * ppc-dis.c (prefix_opcd_indices): Correct size.
 705
 706 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 707
 708         PR gas/24625
 709         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 710         Disp8ShiftVL.
 711         * i386-tbl.h: Regenerated.
 712
 713 2019-05-24  Alan Modra  <amodra@gmail.com>
 714
 715         * po/POTFILES.in: Regenerate.
 716
 717 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 718             Alan Modra  <amodra@gmail.com>
 719
 720         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 721         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 722         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 723         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 724         XTOP>): Define and add entries.
 725         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 726         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 727         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 728         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 729
 730 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 731             Alan Modra  <amodra@gmail.com>
 732
 733         * ppc-dis.c (ppc_opts): Add "future" entry.
 734         (PREFIX_OPCD_SEGS): Define.
 735         (prefix_opcd_indices): New array.
 736         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 737         (lookup_prefix): New function.
 738         (print_insn_powerpc): Handle 64-bit prefix instructions.
 739         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 740         (PMRR, POWERXX): Define.
 741         (prefix_opcodes): New instruction table.
 742         (prefix_num_opcodes): New constant.
 743
 744 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 745
 746         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 747         * configure: Regenerated.
 748         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 749         and cpu/bpf.opc.
 750         (HFILES): Add bpf-desc.h and bpf-opc.h.
 751         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 752         bpf-ibld.c and bpf-opc.c.
 753         (BPF_DEPS): Define.
 754         * Makefile.in: Regenerated.
 755         * disassemble.c (ARCH_bpf): Define.
 756         (disassembler): Add case for bfd_arch_bpf.
 757         (disassemble_init_for_target): Likewise.
 758         (enum epbf_isa_attr): Define.
 759         * disassemble.h: extern print_insn_bpf.
 760         * bpf-asm.c: Generated.
 761         * bpf-opc.h: Likewise.
 762         * bpf-opc.c: Likewise.
 763         * bpf-ibld.c: Likewise.
 764         * bpf-dis.c: Likewise.
 765         * bpf-desc.h: Likewise.
 766         * bpf-desc.c: Likewise.
 767
 768 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 769
 770         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 771         and VMSR with the new operands.
 772
 773 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 774
 775         * arm-dis.c (enum mve_instructions): New enum
 776         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 777         and cneg.
 778         (mve_opcodes): New instructions as above.
 779         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 780         csneg and csel.
 781         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 782
 783 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 784
 785         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 786         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 787         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 788         uqshl, urshrl and urshr.
 789         (is_mve_okay_in_it): Add new instructions to TRUE list.
 790         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 791         (print_insn_mve): Updated to accept new %j,
 792         %<bitfield>m and %<bitfield>n patterns.
 793
 794 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 795
 796         * mips-opc.c (mips_builtin_opcodes): Change source register
 797         constraint for DAUI.
 798
 799 2019-05-20  Nick Clifton  <nickc@redhat.com>
 800
 801         * po/fr.po: Updated French translation.
 802
 803 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 804             Michael Collison <michael.collison@arm.com>
 805
 806         * arm-dis.c (thumb32_opcodes): Add new instructions.
 807         (enum mve_instructions): Likewise.
 808         (enum mve_undefined): Add new reasons.
 809         (is_mve_encoding_conflict): Handle new instructions.
 810         (is_mve_undefined): Likewise.
 811         (is_mve_unpredictable): Likewise.
 812         (print_mve_undefined): Likewise.
 813         (print_mve_size): Likewise.
 814
 815 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 816             Michael Collison <michael.collison@arm.com>
 817
 818         * arm-dis.c (thumb32_opcodes): Add new instructions.
 819         (enum mve_instructions): Likewise.
 820         (is_mve_encoding_conflict): Handle new instructions.
 821         (is_mve_undefined): Likewise.
 822         (is_mve_unpredictable): Likewise.
 823         (print_mve_size): Likewise.
 824
 825 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 826             Michael Collison <michael.collison@arm.com>
 827
 828         * arm-dis.c (thumb32_opcodes): Add new instructions.
 829         (enum mve_instructions): Likewise.
 830         (is_mve_encoding_conflict): Likewise.
 831         (is_mve_unpredictable): Likewise.
 832         (print_mve_size): Likewise.
 833
 834 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 835             Michael Collison <michael.collison@arm.com>
 836
 837         * arm-dis.c (thumb32_opcodes): Add new instructions.
 838         (enum mve_instructions): Likewise.
 839         (is_mve_encoding_conflict): Handle new instructions.
 840         (is_mve_undefined): Likewise.
 841         (is_mve_unpredictable): Likewise.
 842         (print_mve_size): Likewise.
 843
 844 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 845             Michael Collison <michael.collison@arm.com>
 846
 847         * arm-dis.c (thumb32_opcodes): Add new instructions.
 848         (enum mve_instructions): Likewise.
 849         (is_mve_encoding_conflict): Handle new instructions.
 850         (is_mve_undefined): Likewise.
 851         (is_mve_unpredictable): Likewise.
 852         (print_mve_size): Likewise.
 853         (print_insn_mve): Likewise.
 854
 855 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 856             Michael Collison <michael.collison@arm.com>
 857
 858         * arm-dis.c (thumb32_opcodes): Add new instructions.
 859         (print_insn_thumb32): Handle new instructions.
 860
 861 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 862             Michael Collison <michael.collison@arm.com>
 863
 864         * arm-dis.c (enum mve_instructions): Add new instructions.
 865         (enum mve_undefined): Add new reasons.
 866         (is_mve_encoding_conflict): Handle new instructions.
 867         (is_mve_undefined): Likewise.
 868         (is_mve_unpredictable): Likewise.
 869         (print_mve_undefined): Likewise.
 870         (print_mve_size): Likewise.
 871         (print_mve_shift_n): Likewise.
 872         (print_insn_mve): Likewise.
 873
 874 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 875             Michael Collison <michael.collison@arm.com>
 876
 877         * arm-dis.c (enum mve_instructions): Add new instructions.
 878         (is_mve_encoding_conflict): Handle new instructions.
 879         (is_mve_unpredictable): Likewise.
 880         (print_mve_rotate): Likewise.
 881         (print_mve_size): Likewise.
 882         (print_insn_mve): Likewise.
 883
 884 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 885             Michael Collison <michael.collison@arm.com>
 886
 887         * arm-dis.c (enum mve_instructions): Add new instructions.
 888         (is_mve_encoding_conflict): Handle new instructions.
 889         (is_mve_unpredictable): Likewise.
 890         (print_mve_size): Likewise.
 891         (print_insn_mve): Likewise.
 892
 893 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 894             Michael Collison <michael.collison@arm.com>
 895
 896         * arm-dis.c (enum mve_instructions): Add new instructions.
 897         (enum mve_undefined): Add new reasons.
 898         (is_mve_encoding_conflict): Handle new instructions.
 899         (is_mve_undefined): Likewise.
 900         (is_mve_unpredictable): Likewise.
 901         (print_mve_undefined): Likewise.
 902         (print_mve_size): Likewise.
 903         (print_insn_mve): Likewise.
 904
 905 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 906             Michael Collison <michael.collison@arm.com>
 907
 908         * arm-dis.c (enum mve_instructions): Add new instructions.
 909         (is_mve_encoding_conflict): Handle new instructions.
 910         (is_mve_undefined): Likewise.
 911         (is_mve_unpredictable): Likewise.
 912         (print_mve_size): Likewise.
 913         (print_insn_mve): Likewise.
 914
 915 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 916             Michael Collison <michael.collison@arm.com>
 917
 918         * arm-dis.c (enum mve_instructions): Add new instructions.
 919         (enum mve_unpredictable): Add new reasons.
 920         (enum mve_undefined): Likewise.
 921         (is_mve_okay_in_it): Handle new isntructions.
 922         (is_mve_encoding_conflict): Likewise.
 923         (is_mve_undefined): Likewise.
 924         (is_mve_unpredictable): Likewise.
 925         (print_mve_vmov_index): Likewise.
 926         (print_simd_imm8): Likewise.
 927         (print_mve_undefined): Likewise.
 928         (print_mve_unpredictable): Likewise.
 929         (print_mve_size): Likewise.
 930         (print_insn_mve): Likewise.
 931
 932 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 933             Michael Collison <michael.collison@arm.com>
 934
 935         * arm-dis.c (enum mve_instructions): Add new instructions.
 936         (enum mve_unpredictable): Add new reasons.
 937         (enum mve_undefined): Likewise.
 938         (is_mve_encoding_conflict): Handle new instructions.
 939         (is_mve_undefined): Likewise.
 940         (is_mve_unpredictable): Likewise.
 941         (print_mve_undefined): Likewise.
 942         (print_mve_unpredictable): Likewise.
 943         (print_mve_rounding_mode): Likewise.
 944         (print_mve_vcvt_size): Likewise.
 945         (print_mve_size): Likewise.
 946         (print_insn_mve): Likewise.
 947
 948 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 949             Michael Collison <michael.collison@arm.com>
 950
 951         * arm-dis.c (enum mve_instructions): Add new instructions.
 952         (enum mve_unpredictable): Add new reasons.
 953         (enum mve_undefined): Likewise.
 954         (is_mve_undefined): Handle new instructions.
 955         (is_mve_unpredictable): Likewise.
 956         (print_mve_undefined): Likewise.
 957         (print_mve_unpredictable): Likewise.
 958         (print_mve_size): Likewise.
 959         (print_insn_mve): Likewise.
 960
 961 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 962             Michael Collison <michael.collison@arm.com>
 963
 964         * arm-dis.c (enum mve_instructions): Add new instructions.
 965         (enum mve_undefined): Add new reasons.
 966         (insns): Add new instructions.
 967         (is_mve_encoding_conflict):
 968         (print_mve_vld_str_addr): New print function.
 969         (is_mve_undefined): Handle new instructions.
 970         (is_mve_unpredictable): Likewise.
 971         (print_mve_undefined): Likewise.
 972         (print_mve_size): Likewise.
 973         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 974         (print_insn_mve):  Handle new operands.
 975
 976 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 977             Michael Collison <michael.collison@arm.com>
 978
 979         * arm-dis.c (enum mve_instructions): Add new instructions.
 980         (enum mve_unpredictable): Add new reasons.
 981         (is_mve_encoding_conflict): Handle new instructions.
 982         (is_mve_unpredictable): Likewise.
 983         (mve_opcodes): Add new instructions.
 984         (print_mve_unpredictable): Handle new reasons.
 985         (print_mve_register_blocks): New print function.
 986         (print_mve_size): Handle new instructions.
 987         (print_insn_mve): Likewise.
 988
 989 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 990             Michael Collison <michael.collison@arm.com>
 991
 992         * arm-dis.c (enum mve_instructions): Add new instructions.
 993         (enum mve_unpredictable): Add new reasons.
 994         (enum mve_undefined): Likewise.
 995         (is_mve_encoding_conflict): Handle new instructions.
 996         (is_mve_undefined): Likewise.
 997         (is_mve_unpredictable): Likewise.
 998         (coprocessor_opcodes): Move NEON VDUP from here...
 999         (neon_opcodes): ... to here.
1000         (mve_opcodes): Add new instructions.
1001         (print_mve_undefined):  Handle new reasons.
1002         (print_mve_unpredictable): Likewise.
1003         (print_mve_size): Handle new instructions.
1004         (print_insn_neon): Handle vdup.
1005         (print_insn_mve): Handle new operands.
1006
1007 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1008             Michael Collison <michael.collison@arm.com>
1009
1010         * arm-dis.c (enum mve_instructions): Add new instructions.
1011         (enum mve_unpredictable): Add new values.
1012         (mve_opcodes): Add new instructions.
1013         (vec_condnames): New array with vector conditions.
1014         (mve_predicatenames): New array with predicate suffixes.
1015         (mve_vec_sizename): New array with vector sizes.
1016         (enum vpt_pred_state): New enum with vector predication states.
1017         (struct vpt_block): New struct type for vpt blocks.
1018         (vpt_block_state): Global struct to keep track of state.
1019         (mve_extract_pred_mask): New helper function.
1020         (num_instructions_vpt_block): Likewise.
1021         (mark_outside_vpt_block): Likewise.
1022         (mark_inside_vpt_block): Likewise.
1023         (invert_next_predicate_state): Likewise.
1024         (update_next_predicate_state): Likewise.
1025         (update_vpt_block_state): Likewise.
1026         (is_vpt_instruction): Likewise.
1027         (is_mve_encoding_conflict): Add entries for new instructions.
1028         (is_mve_unpredictable): Likewise.
1029         (print_mve_unpredictable): Handle new cases.
1030         (print_instruction_predicate): Likewise.
1031         (print_mve_size): New function.
1032         (print_vec_condition): New function.
1033         (print_insn_mve): Handle vpt blocks and new print operands.
1034
1035 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1036
1037         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1038         8, 14 and 15 for Armv8.1-M Mainline.
1039
1040 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1041             Michael Collison <michael.collison@arm.com>
1042
1043         * arm-dis.c (enum mve_instructions): New enum.
1044         (enum mve_unpredictable): Likewise.
1045         (enum mve_undefined): Likewise.
1046         (struct mopcode32): New struct.
1047         (is_mve_okay_in_it): New function.
1048         (is_mve_architecture): Likewise.
1049         (arm_decode_field): Likewise.
1050         (arm_decode_field_multiple): Likewise.
1051         (is_mve_encoding_conflict): Likewise.
1052         (is_mve_undefined): Likewise.
1053         (is_mve_unpredictable): Likewise.
1054         (print_mve_undefined): Likewise.
1055         (print_mve_unpredictable): Likewise.
1056         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1057         (print_insn_mve): New function.
1058         (print_insn_thumb32): Handle MVE architecture.
1059         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1060
1061 2019-05-10  Nick Clifton  <nickc@redhat.com>
1062
1063         PR 24538
1064         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1065         end of the table prematurely.
1066
1067 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1068
1069         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1070         macros for R6.
1071
1072 2019-05-11  Alan Modra  <amodra@gmail.com>
1073
1074         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1075         when -Mraw is in effect.
1076
1077 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1078
1079         * aarch64-dis-2.c: Regenerate.
1080         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1081         (OP_SVE_BBB): New variant set.
1082         (OP_SVE_DDDD): New variant set.
1083         (OP_SVE_HHH): New variant set.
1084         (OP_SVE_HHHU): New variant set.
1085         (OP_SVE_SSS): New variant set.
1086         (OP_SVE_SSSU): New variant set.
1087         (OP_SVE_SHH): New variant set.
1088         (OP_SVE_SBBU): New variant set.
1089         (OP_SVE_DSS): New variant set.
1090         (OP_SVE_DHHU): New variant set.
1091         (OP_SVE_VMV_HSD_BHS): New variant set.
1092         (OP_SVE_VVU_HSD_BHS): New variant set.
1093         (OP_SVE_VVVU_SD_BH): New variant set.
1094         (OP_SVE_VVVU_BHSD): New variant set.
1095         (OP_SVE_VVV_QHD_DBS): New variant set.
1096         (OP_SVE_VVV_HSD_BHS): New variant set.
1097         (OP_SVE_VVV_HSD_BHS2): New variant set.
1098         (OP_SVE_VVV_BHS_HSD): New variant set.
1099         (OP_SVE_VV_BHS_HSD): New variant set.
1100         (OP_SVE_VVV_SD): New variant set.
1101         (OP_SVE_VVU_BHS_HSD): New variant set.
1102         (OP_SVE_VZVV_SD): New variant set.
1103         (OP_SVE_VZVV_BH): New variant set.
1104         (OP_SVE_VZV_SD): New variant set.
1105         (aarch64_opcode_table): Add sve2 instructions.
1106
1107 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1108
1109         * aarch64-asm-2.c: Regenerated.
1110         * aarch64-dis-2.c: Regenerated.
1111         * aarch64-opc-2.c: Regenerated.
1112         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1113         for SVE_SHLIMM_UNPRED_22.
1114         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1115         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1116         operand.
1117
1118 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1119
1120         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1121         sve_size_tsz_bhs iclass encode.
1122         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1123         sve_size_tsz_bhs iclass decode.
1124
1125 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1126
1127         * aarch64-asm-2.c: Regenerated.
1128         * aarch64-dis-2.c: Regenerated.
1129         * aarch64-opc-2.c: Regenerated.
1130         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1131         for SVE_Zm4_11_INDEX.
1132         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1133         (fields): Handle SVE_i2h field.
1134         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1135         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1136
1137 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1138
1139         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1140         sve_shift_tsz_bhsd iclass encode.
1141         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1142         sve_shift_tsz_bhsd iclass decode.
1143
1144 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1145
1146         * aarch64-asm-2.c: Regenerated.
1147         * aarch64-dis-2.c: Regenerated.
1148         * aarch64-opc-2.c: Regenerated.
1149         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1150         (aarch64_encode_variant_using_iclass): Handle
1151         sve_shift_tsz_hsd iclass encode.
1152         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1153         sve_shift_tsz_hsd iclass decode.
1154         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1155         for SVE_SHRIMM_UNPRED_22.
1156         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1157         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1158         operand.
1159
1160 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1161
1162         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1163         sve_size_013 iclass encode.
1164         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1165         sve_size_013 iclass decode.
1166
1167 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1168
1169         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1170         sve_size_bh iclass encode.
1171         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1172         sve_size_bh iclass decode.
1173
1174 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1175
1176         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1177         sve_size_sd2 iclass encode.
1178         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1179         sve_size_sd2 iclass decode.
1180         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1181         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1182
1183 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1184
1185         * aarch64-asm-2.c: Regenerated.
1186         * aarch64-dis-2.c: Regenerated.
1187         * aarch64-opc-2.c: Regenerated.
1188         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1189         for SVE_ADDR_ZX.
1190         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1191         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1192
1193 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1194
1195         * aarch64-asm-2.c: Regenerated.
1196         * aarch64-dis-2.c: Regenerated.
1197         * aarch64-opc-2.c: Regenerated.
1198         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1199         for SVE_Zm3_11_INDEX.
1200         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1201         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1202         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1203         fields.
1204         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1205
1206 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1207
1208         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1209         sve_size_hsd2 iclass encode.
1210         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1211         sve_size_hsd2 iclass decode.
1212         * aarch64-opc.c (fields): Handle SVE_size field.
1213         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1214
1215 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1216
1217         * aarch64-asm-2.c: Regenerated.
1218         * aarch64-dis-2.c: Regenerated.
1219         * aarch64-opc-2.c: Regenerated.
1220         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1221         for SVE_IMM_ROT3.
1222         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1223         (fields): Handle SVE_rot3 field.
1224         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1225         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1226
1227 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1228
1229         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1230         instructions.
1231
1232 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1233
1234         * aarch64-tbl.h
1235         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1236         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1237         aarch64_feature_sve2bitperm): New feature sets.
1238         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1239         for feature set addresses.
1240         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1241         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1242
1243 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1244             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1245
1246         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1247         argument and set ASE_EVA_R6 appropriately.
1248         (set_default_mips_dis_options): Pass ISA to above.
1249         (parse_mips_dis_option): Likewise.
1250         * mips-opc.c (EVAR6): New macro.
1251         (mips_builtin_opcodes): Add llwpe, scwpe.
1252
1253 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1254
1255         * aarch64-asm-2.c: Regenerated.
1256         * aarch64-dis-2.c: Regenerated.
1257         * aarch64-opc-2.c: Regenerated.
1258         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1259         AARCH64_OPND_TME_UIMM16.
1260         (aarch64_print_operand): Likewise.
1261         * aarch64-tbl.h (QL_IMM_NIL): New.
1262         (TME): New.
1263         (_TME_INSN): New.
1264         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1265
1266 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1267
1268         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1269
1270 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1271             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1272
1273         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1274
1275 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1276
1277         * s12z-opc.h: Add extern "C" bracketing to help
1278         users who wish to use this interface in c++ code.
1279
1280 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1281
1282         * s12z-opc.c (bm_decode): Handle bit map operations with the
1283         "reserved0" mode.
1284
1285 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1286
1287         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1288         specifier.  Add entries for VLDR and VSTR of system registers.
1289         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1290         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1291         of %J and %K format specifier.
1292
1293 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1294
1295         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1296         Add new entries for VSCCLRM instruction.
1297         (print_insn_coprocessor): Handle new %C format control code.
1298
1299 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1300
1301         * arm-dis.c (enum isa): New enum.
1302         (struct sopcode32): New structure.
1303         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1304         set isa field of all current entries to ANY.
1305         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1306         Only match an entry if its isa field allows the current mode.
1307
1308 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1309
1310         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1311         CLRM.
1312         (print_insn_thumb32): Add logic to print %n CLRM register list.
1313
1314 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1315
1316         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1317         and %Q patterns.
1318
1319 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1320
1321         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1322         (print_insn_thumb32): Edit the switch case for %Z.
1323
1324 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1325
1326         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1327
1328 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1329
1330         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1331
1332 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1333
1334         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1335
1336 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1337
1338         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1339         Arm register with r13 and r15 unpredictable.
1340         (thumb32_opcodes): New instructions for bfx and bflx.
1341
1342 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1343
1344         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1345
1346 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1347
1348         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1349
1350 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1351
1352         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1353
1354 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1355
1356         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1357
1358 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1359
1360         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1361         "optr". ("operator" is a reserved word in c++).
1362
1363 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1364
1365         * aarch64-opc.c (aarch64_print_operand): Add case for
1366         AARCH64_OPND_Rt_SP.
1367         (verify_constraints): Likewise.
1368         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1369         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1370         to accept Rt|SP as first operand.
1371         (AARCH64_OPERANDS): Add new Rt_SP.
1372         * aarch64-asm-2.c: Regenerated.
1373         * aarch64-dis-2.c: Regenerated.
1374         * aarch64-opc-2.c: Regenerated.
1375
1376 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1377
1378         * aarch64-asm-2.c: Regenerated.
1379         * aarch64-dis-2.c: Likewise.
1380         * aarch64-opc-2.c: Likewise.
1381         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1382
1383 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1384
1385         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1386
1387 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1388
1389         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1390         * i386-init.h: Regenerated.
1391
1392 2019-04-07  Alan Modra  <amodra@gmail.com>
1393
1394         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1395         op_separator to control printing of spaces, comma and parens
1396         rather than need_comma, need_paren and spaces vars.
1397
1398 2019-04-07  Alan Modra  <amodra@gmail.com>
1399
1400         PR 24421
1401         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1402         (print_insn_neon, print_insn_arm): Likewise.
1403
1404 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1405
1406         * i386-dis-evex.h (evex_table): Updated to support BF16
1407         instructions.
1408         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1409         and EVEX_W_0F3872_P_3.
1410         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1411         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1412         * i386-opc.h (enum): Add CpuAVX512_BF16.
1413         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1414         * i386-opc.tbl: Add AVX512 BF16 instructions.
1415         * i386-init.h: Regenerated.
1416         * i386-tbl.h: Likewise.
1417
1418 2019-04-05  Alan Modra  <amodra@gmail.com>
1419
1420         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1421         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1422         to favour printing of "-" branch hint when using the "y" bit.
1423         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1424
1425 2019-04-05  Alan Modra  <amodra@gmail.com>
1426
1427         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1428         opcode until first operand is output.
1429
1430 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1431
1432         PR gas/24349
1433         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1434         (valid_bo_post_v2): Add support for 'at' branch hints.
1435         (insert_bo): Only error on branch on ctr.
1436         (get_bo_hint_mask): New function.
1437         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1438         for inserting 'at' branch hints.
1439         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1440         for extracting 'at' branch hints.
1441         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1442         (BOE): Delete operand.
1443         (BOM, BOP): New operands.
1444         (RM): Update value.
1445         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1446         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1447         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1448         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1449         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1450         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1451         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1452         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1453         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1454         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1455         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1456         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1457         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1458         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1459         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1460         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1461         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1462         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1463         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1464         bttarl+>: New extended mnemonics.
1465
1466 2019-03-28  Alan Modra  <amodra@gmail.com>
1467
1468         PR 24390
1469         * ppc-opc.c (BTF): Define.
1470         (powerpc_opcodes): Use for mtfsb*.
1471         * ppc-dis.c (print_insn_powerpc): Print fields with both
1472         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1473
1474 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1475
1476         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1477         (mapping_symbol_for_insn): Implement new algorithm.
1478         (print_insn): Remove duplicate code.
1479
1480 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1481
1482         * aarch64-dis.c (print_insn_aarch64):
1483         Implement override.
1484
1485 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1486
1487         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1488         order.
1489
1490 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1491
1492         * aarch64-dis.c (last_stop_offset): New.
1493         (print_insn_aarch64): Use stop_offset.
1494
1495 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1496
1497         PR gas/24359
1498         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1499         CPU_ANY_AVX2_FLAGS.
1500         * i386-init.h: Regenerated.
1501
1502 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1503
1504         PR gas/24348
1505         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1506         vmovdqu16, vmovdqu32 and vmovdqu64.
1507         * i386-tbl.h: Regenerated.
1508
1509 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1510
1511         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1512         from vstrszb, vstrszh, and vstrszf.
1513
1514 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1515
1516         * s390-opc.txt: Add instruction descriptions.
1517
1518 2019-02-08  Jim Wilson  <jimw@sifive.com>
1519
1520         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1521         <bne>: Likewise.
1522
1523 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1524
1525         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1526
1527 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1528
1529         PR binutils/23212
1530         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1531         * aarch64-opc.c (verify_elem_sd): New.
1532         (fields): Add FLD_sz entr.
1533         * aarch64-tbl.h (_SIMD_INSN): New.
1534         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1535         fmulx scalar and vector by element isns.
1536
1537 2019-02-07  Nick Clifton  <nickc@redhat.com>
1538
1539         * po/sv.po: Updated Swedish translation.
1540
1541 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1542
1543         * s390-mkopc.c (main): Accept arch13 as cpu string.
1544         * s390-opc.c: Add new instruction formats and instruction opcode
1545         masks.
1546         * s390-opc.txt: Add new arch13 instructions.
1547
1548 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1549
1550         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1551         (aarch64_opcode): Change encoding for stg, stzg
1552         st2g and st2zg.
1553         * aarch64-asm-2.c: Regenerated.
1554         * aarch64-dis-2.c: Regenerated.
1555         * aarch64-opc-2.c: Regenerated.
1556
1557 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1558
1559         * aarch64-asm-2.c: Regenerated.
1560         * aarch64-dis-2.c: Likewise.
1561         * aarch64-opc-2.c: Likewise.
1562         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1563
1564 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1565             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1566
1567         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1568         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1569         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1570         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1571         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1572         case for ldstgv_indexed.
1573         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1574         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1575         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1576         * aarch64-asm-2.c: Regenerated.
1577         * aarch64-dis-2.c: Regenerated.
1578         * aarch64-opc-2.c: Regenerated.
1579
1580 2019-01-23  Nick Clifton  <nickc@redhat.com>
1581
1582         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1583
1584 2019-01-21  Nick Clifton  <nickc@redhat.com>
1585
1586         * po/de.po: Updated German translation.
1587         * po/uk.po: Updated Ukranian translation.
1588
1589 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1590         * mips-dis.c (mips_arch_choices): Fix typo in
1591         gs464, gs464e and gs264e descriptors.
1592
1593 2019-01-19  Nick Clifton  <nickc@redhat.com>
1594
1595         * configure: Regenerate.
1596         * po/opcodes.pot: Regenerate.
1597
1598 2018-06-24  Nick Clifton  <nickc@redhat.com>
1599
1600         2.32 branch created.
1601
1602 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1603
1604         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1605         if it is null.
1606         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1607         zero.
1608
1609 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1610
1611         * configure: Regenerate.
1612
1613 2019-01-07  Alan Modra  <amodra@gmail.com>
1614
1615         * configure: Regenerate.
1616         * po/POTFILES.in: Regenerate.
1617
1618 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1619
1620         * s12z-opc.c: New file.
1621         * s12z-opc.h: New file.
1622         * s12z-dis.c: Removed all code not directly related to display
1623         of instructions.  Used the interface provided by the new files
1624         instead.
1625         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1626         * Makefile.in: Regenerate.
1627         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1628         * configure: Regenerate.
1629
1630 2019-01-01  Alan Modra  <amodra@gmail.com>
1631
1632         Update year range in copyright notice of all files.
1633
1634 For older changes see ChangeLog-2018
1635 \f
1636 Copyright (C) 2019 Free Software Foundation, Inc.
1637
1638 Copying and distribution of this file, with or without modification,
1639 are permitted in any medium without royalty provided the copyright
1640 notice and this notice are preserved.
1641
1642 Local Variables:
1643 mode: change-log
1644 left-margin: 8
1645 fill-column: 74
1646 version-control: never
1647 End: