opcodes/ChangeLog

   1 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
   2
   3         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
   4         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
   5         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
   6         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
   7         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
   8         (ldapur, ldapursw, stlur): New.
   9         * aarch64-dis-2.c: Regenerate.
  10
  11 2017-11-16  Jan Beulich  <jbeulich@suse.com>
  12
  13         (get_valid_dis386): Never flag bad opcode when
  14         vex.register_specifier is beyond 7. Always store all four
  15         bits of it. Move 16-/32-bit override in EVEX handling after
  16         all to be overridden bits have been set.
  17         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
  18         Use rex to determine GPR register set.
  19         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
  20         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
  21
  22 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
  25         determine GPR register set.
  26
  27 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  28
  29         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
  30         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
  31         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
  32         pass.
  33         (OP_REG_VexI4): Drop low 4 bits check.
  34
  35 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  36
  37         * i386-reg.tbl (axl): Remove Acc and Byte.
  38         * i386-tbl.h: Re-generate.
  39
  40 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  41
  42         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
  43         (vex_len_table): Use VPCOM.
  44
  45 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
  48         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
  49         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
  50         vpcmpw): Move up.
  51         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
  52         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
  53         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
  54         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
  55         vpcmpnltuw): New.
  56         * i386-tbl.h: Re-generate.
  57
  58 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  59
  60         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
  61         smov, ssca, stos, ssto, xlat): Drop Disp*.
  62         * i386-tbl.h: Re-generate.
  63
  64 2017-11-13  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
  67         xsaveopt64): Add No_qSuf.
  68         * i386-tbl.h: Re-generate.
  69
  70 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  71
  72         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
  73         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
  74         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
  75         sder32_el2, vncr_el2.
  76         (aarch64_sys_reg_supported_p): Likewise.
  77         (aarch64_pstatefields): Add dit register.
  78         (aarch64_pstatefield_supported_p): Likewise.
  79         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
  80         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
  81         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
  82         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
  83         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
  84         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
  85         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
  86
  87 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  88
  89         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
  90         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
  91         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
  92         (QL_STLW, QL_STLX): New.
  93
  94 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  95
  96         * aarch64-asm.h (ins_addr_offset): New.
  97         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
  98         (aarch64_ins_addr_offset): New.
  99         * aarch64-asm-2.c: Regenerate.
 100         * aarch64-dis.h (ext_addr_offset): New.
 101         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 102         (aarch64_ext_addr_offset): New.
 103         * aarch64-dis-2.c: Regenerate.
 104         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 105         FLD_imm4_2 and FLD_SM3_imm2.
 106         * aarch64-opc.c (fields): Add FLD_imm6_2,
 107         FLD_imm4_2 and FLD_SM3_imm2.
 108         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 109         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 110         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 111         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 112         * aarch64-tbl.h
 113         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 114
 115 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 116
 117         * aarch64-tbl.h
 118         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 119         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 120         (aarch64_feature_fp_16_v8_2): New.
 121         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 122         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 123         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 124
 125 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 126
 127         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 128         (aarch64_feature_sha2, aarch64_feature_aes): New.
 129         (SHA2, AES): New.
 130         (AES_INSN, SHA2_INSN): New.
 131         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 132         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 133          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 134         Change to SHA2_INS.
 135
 136 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 137             Tamar Christina <tamar.christina@arm.com>
 138
 139         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 140         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 141
 142 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 143
 144         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 145
 146 2017-11-07  Alan Modra  <amodra@gmail.com>
 147
 148         * opintl.h: Formatting, comment fixes.
 149         (gettext, ngettext): Redefine when ENABLE_NLS.
 150         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 151         (_): Define using gettext.
 152         (textdomain, bindtextdomain): Use safer "do nothing".
 153
 154 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 155
 156         * arc-dis.c (print_hex): New variable.
 157         (parse_option): Check for hex option.
 158         (print_insn_arc): Use hexadecimal representation for short
 159         immediate values when requested.
 160         (print_arc_disassembler_options): Add hex option to the list.
 161
 162 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 163
 164         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 165         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 166         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 167         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 168         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 169         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 170         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 171         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 172         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 173         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 174         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 175         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 176         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 177         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 178         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 179         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 180         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 181         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 182         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 183         Changed opcodes.
 184         (prealloc, prefetch*): Place them before ld instruction.
 185         * arc-opc.c (skip_this_opcode): Add ARITH class.
 186
 187 2017-10-25  Alan Modra  <amodra@gmail.com>
 188
 189         PR 22348
 190         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 191         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 192         (imm4flag, size_changed): Likewise.
 193         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 194         (words, allWords, processing_argument_number): Likewise.
 195         (cst4flag, size_changed): Likewise.
 196         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 197         (crx_cst4_maps): Rename from cst4_maps.
 198         (crx_no_op_insn): Rename from no_op_insn.
 199
 200 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 201
 202         * riscv-opc.c (match_c_addi16sp) : New function.
 203         (match_c_addi4spn): New function.
 204         (match_c_lui): Don't allow 0-immediate encodings.
 205         (riscv_opcodes) <addi>: Use the above functions.
 206         <add>: Likewise.
 207         <c.addi4spn>: Likewise.
 208         <c.addi16sp>: Likewise.
 209
 210 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 211
 212         * i386-init.h: Regenerate
 213         * i386-tbl.h: Likewise
 214
 215 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 216
 217         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 218         (enum): Add EVEX_W_0F3854_P_2.
 219         * i386-dis-evex.h (evex_table): Updated.
 220         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 221         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 222         (cpu_flags): Add CpuAVX512_BITALG.
 223         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 224         (i386_cpu_flags): Add cpuavx512_bitalg..
 225         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 226         * i386-init.h: Regenerate.
 227         * i386-tbl.h: Likewise.
 228
 229 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 230
 231         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 232         * i386-dis-evex.h (evex_table): Updated.
 233         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 234         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 235         (cpu_flags): Add CpuAVX512_VNNI.
 236         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 237         (i386_cpu_flags): Add cpuavx512_vnni.
 238         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 239         * i386-init.h: Regenerate.
 240         * i386-tbl.h: Likewise.
 241
 242 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 243
 244         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 245         (enum): Remove VEX_LEN_0F3A44_P_2.
 246         (vex_len_table): Ditto.
 247         (enum): Remove VEX_W_0F3A44_P_2.
 248         (vew_w_table): Ditto.
 249         (prefix_table): Adjust instructions (see prefixes above).
 250         * i386-dis-evex.h (evex_table):
 251         Add new instructions (see prefixes above).
 252         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 253         (bitfield_cpu_flags): Ditto.
 254         * i386-opc.h (enum): Ditto.
 255         (i386_cpu_flags): Ditto.
 256         (CpuUnused): Comment out to avoid zero-width field problem.
 257         * i386-opc.tbl (vpclmulqdq): New instruction.
 258         * i386-init.h: Regenerate.
 259         * i386-tbl.h: Ditto.
 260
 261 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 262
 263         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 264         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 265         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 266         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 267         (vex_len_table): Ditto.
 268         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 269         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 270         (vew_w_table): Ditto.
 271         (prefix_table): Adjust instructions (see prefixes above).
 272         * i386-dis-evex.h (evex_table):
 273         Add new instructions (see prefixes above).
 274         * i386-gen.c (cpu_flag_init): Add VAES.
 275         (bitfield_cpu_flags): Ditto.
 276         * i386-opc.h (enum): Ditto.
 277         (i386_cpu_flags): Ditto.
 278         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 279         * i386-init.h: Regenerate.
 280         * i386-tbl.h: Ditto.
 281
 282 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 283
 284         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 285         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 286         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 287         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 288         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 289         (prefix_table): Updated (see prefixes above).
 290         (three_byte_table): Likewise.
 291         (vex_w_table): Likewise.
 292         * i386-dis-evex.h: Likewise.
 293         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 294         (cpu_flags): Add CpuGFNI.
 295         * i386-opc.h (enum): Add CpuGFNI.
 296         (i386_cpu_flags): Add cpugfni.
 297         * i386-opc.tbl: Add Intel GFNI instructions.
 298         * i386-init.h: Regenerate.
 299         * i386-tbl.h: Likewise.
 300
 301 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 302
 303         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 304         Define EXbScalar and EXwScalar for OP_EX.
 305         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 306         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 307         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 308         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 309         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 310         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 311         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 312         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 313         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 314         (OP_E_memory): Likewise.
 315         * i386-dis-evex.h: Updated.
 316         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 317         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 318         (cpu_flags): Add CpuAVX512_VBMI2.
 319         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 320         (i386_cpu_flags): Add cpuavx512_vbmi2.
 321         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 322         * i386-init.h: Regenerate.
 323         * i386-tbl.h: Likewise.
 324
 325 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 326
 327         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 328
 329 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 330
 331         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 332         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 333         K15. Add jmpix pattern.
 334
 335 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 336
 337         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 338
 339 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 340
 341         * s390-opc.c (INSTR_SI_RD): New macro.
 342         (INSTR_S_RD): Adjust example instruction.
 343         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 344         SI_RD.
 345
 346 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 347
 348         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 349         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 350         VLE multimple load/store instructions. Old e_ldm* variants are
 351         kept as aliases.
 352         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 353
 354 2017-09-27  Nick Clifton  <nickc@redhat.com>
 355
 356         PR 22179
 357         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 358         names for the fmv.x.s and fmv.s.x instructions respectively.
 359
 360 2017-09-26  do  <do@nerilex.org>
 361
 362         PR 22123
 363         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 364         be used on CPUs that have emacs support.
 365
 366 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 367
 368         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 369
 370 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 371
 372         * nds32-asm.c: Rename __BIT() to N32_BIT().
 373         * nds32-asm.h: Likewise.
 374         * nds32-dis.c: Likewise.
 375
 376 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 377
 378         * i386-dis.c (last_active_prefix): Removed.
 379         (ckprefix): Don't set last_active_prefix.
 380         (NOTRACK_Fixup): Don't check last_active_prefix.
 381
 382 2017-08-31  Nick Clifton  <nickc@redhat.com>
 383
 384         * po/fr.po: Updated French translation.
 385
 386 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 387
 388         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 389         fields.
 390
 391 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 392             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 393
 394         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 395         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 396         New entries efs2 and spe2.
 397         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 398         (SPE2_OPCD_SEGS): New macro.
 399         (spe2_opcd_indices): New.
 400         (disassemble_init_powerpc): Handle SPE2 opcodes.
 401         (lookup_spe2): New function.
 402         (print_insn_powerpc): call lookup_spe2.
 403         * ppc-opc.c (insert_evuimm1_ex0): New function.
 404         (extract_evuimm1_ex0): Likewise.
 405         (insert_evuimm_lt8): Likewise.
 406         (extract_evuimm_lt8): Likewise.
 407         (insert_off_spe2): Likewise.
 408         (extract_off_spe2): Likewise.
 409         (insert_Ddd): Likewise.
 410         (extract_Ddd): Likewise.
 411         (DD): New operand.
 412         (EVUIMM_LT8): Likewise.
 413         (EVUIMM_LT16): Adjust.
 414         (MMMM): New operand.
 415         (EVUIMM_1): Likewise.
 416         (EVUIMM_1_EX0): Likewise.
 417         (EVUIMM_2): Adjust.
 418         (NNN): New operand.
 419         (VX_OFF_SPE2): Likewise.
 420         (BBB): Likewise.
 421         (DDD): Likewise.
 422         (VX_MASK_DDD): New mask.
 423         (HH): New operand.
 424         (VX_RA_CONST): New macro.
 425         (VX_RA_CONST_MASK): Likewise.
 426         (VX_RB_CONST): Likewise.
 427         (VX_RB_CONST_MASK): Likewise.
 428         (VX_OFF_SPE2_MASK): Likewise.
 429         (VX_SPE_CRFD): Likewise.
 430         (VX_SPE_CRFD_MASK VX): Likewise.
 431         (VX_SPE2_CLR): Likewise.
 432         (VX_SPE2_CLR_MASK): Likewise.
 433         (VX_SPE2_SPLATB): Likewise.
 434         (VX_SPE2_SPLATB_MASK): Likewise.
 435         (VX_SPE2_OCTET): Likewise.
 436         (VX_SPE2_OCTET_MASK): Likewise.
 437         (VX_SPE2_DDHH): Likewise.
 438         (VX_SPE2_DDHH_MASK): Likewise.
 439         (VX_SPE2_HH): Likewise.
 440         (VX_SPE2_HH_MASK): Likewise.
 441         (VX_SPE2_EVMAR): Likewise.
 442         (VX_SPE2_EVMAR_MASK): Likewise.
 443         (PPCSPE2): Likewise.
 444         (PPCEFS2): Likewise.
 445         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 446         (powerpc_macros): Map old SPE instructions have new names
 447         with the same opcodes. Add SPE2 instructions which just are
 448         mapped to SPE2.
 449         (spe2_opcodes): Add SPE2 opcodes.
 450
 451 2017-08-23  Alan Modra  <amodra@gmail.com>
 452
 453         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 454         extract functions earlier, deleting forward declarations.
 455         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 456         RA_MASK.
 457
 458 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 459
 460         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 461
 462 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 463             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 464
 465         * ppc-opc.c (insert_evuimm2_ex0): New function.
 466         (extract_evuimm2_ex0): Likewise.
 467         (insert_evuimm4_ex0): Likewise.
 468         (extract_evuimm4_ex0): Likewise.
 469         (insert_evuimm8_ex0): Likewise.
 470         (extract_evuimm8_ex0): Likewise.
 471         (insert_evuimm_lt16): Likewise.
 472         (extract_evuimm_lt16): Likewise.
 473         (insert_rD_rS_even): Likewise.
 474         (extract_rD_rS_even): Likewise.
 475         (insert_off_lsp): Likewise.
 476         (extract_off_lsp): Likewise.
 477         (RD_EVEN): New operand.
 478         (RS_EVEN): Likewise.
 479         (RSQ): Adjust.
 480         (EVUIMM_LT16): New operand.
 481         (HTM_SI): Adjust.
 482         (EVUIMM_2_EX0): New operand.
 483         (EVUIMM_4): Adjust.
 484         (EVUIMM_4_EX0): New operand.
 485         (EVUIMM_8): Adjust.
 486         (EVUIMM_8_EX0): New operand.
 487         (WS): Adjust.
 488         (VX_OFF): New operand.
 489         (VX_LSP): New macro.
 490         (VX_LSP_MASK): Likewise.
 491         (VX_LSP_OFF_MASK): Likewise.
 492         (PPC_OPCODE_LSP): Likewise.
 493         (vle_opcodes): Add LSP opcodes.
 494         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 495
 496 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 497
 498         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 499         register operands in CRC instructions.
 500         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 501         comments.
 502
 503 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 504
 505         * disassemble.c (disassembler): Mark big and mach with
 506         ATTRIBUTE_UNUSED.
 507
 508 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 509
 510         * disassemble.c (disassembler): Remove arch/mach/endian
 511         assertions.
 512
 513 2017-07-25  Nick Clifton  <nickc@redhat.com>
 514
 515         PR 21739
 516         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 517         message.
 518         (insert_r0): Likewise.
 519         (insert_r1): Likewise.
 520         (insert_r2): Likewise.
 521         (insert_r3): Likewise.
 522         (insert_sp): Likewise.
 523         (insert_gp): Likewise.
 524         (insert_pcl): Likewise.
 525         (insert_blink): Likewise.
 526         (insert_ilink1): Likewise.
 527         (insert_ilink2): Likewise.
 528         (insert_ras): Likewise.
 529         (insert_rbs): Likewise.
 530         (insert_rcs): Likewise.
 531         (insert_simm3s): Likewise.
 532         (insert_rrange): Likewise.
 533         (insert_r13el): Likewise.
 534         (insert_fpel): Likewise.
 535         (insert_blinkel): Likewise.
 536         (insert_pclel): Likewise.
 537         (insert_nps_bitop_size_2b): Likewise.
 538         (insert_nps_imm_offset): Likewise.
 539         (insert_nps_imm_entry): Likewise.
 540         (insert_nps_size_16bit): Likewise.
 541         (insert_nps_##NAME##_pos): Likewise.
 542         (insert_nps_##NAME): Likewise.
 543         (insert_nps_bitop_ins_ext): Likewise.
 544         (insert_nps_##NAME): Likewise.
 545         (insert_nps_min_hofs): Likewise.
 546         (insert_nps_##NAME): Likewise.
 547         (insert_nps_rbdouble_64): Likewise.
 548         (insert_nps_misc_imm_offset): Likewise.
 549         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 550         option description.
 551
 552 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 553             Jiong Wang  <jiong.wang@arm.com>
 554
 555         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 556         correct the print.
 557         * aarch64-dis-2.c: Regenerated.
 558
 559 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 560
 561         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 562         table.
 563
 564 2017-07-20  Nick Clifton  <nickc@redhat.com>
 565
 566         * po/de.po: Updated German translation.
 567
 568 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 569
 570         * arc-regs.h (sec_stat): New aux register.
 571         (aux_kernel_sp): Likewise.
 572         (aux_sec_u_sp): Likewise.
 573         (aux_sec_k_sp): Likewise.
 574         (sec_vecbase_build): Likewise.
 575         (nsc_table_top): Likewise.
 576         (nsc_table_base): Likewise.
 577         (ersec_stat): Likewise.
 578         (aux_sec_except): Likewise.
 579
 580 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 581
 582         * arc-opc.c (extract_uimm12_20): New function.
 583         (UIMM12_20): New operand.
 584         (SIMM3_5_S): Adjust.
 585         * arc-tbl.h (sjli): Add new instruction.
 586
 587 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 588             John Eric Martin  <John.Martin@emmicro-us.com>
 589
 590         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 591         (UIMM3_23): Adjust accordingly.
 592         * arc-regs.h: Add/correct jli_base register.
 593         * arc-tbl.h (jli_s): Likewise.
 594
 595 2017-07-18  Nick Clifton  <nickc@redhat.com>
 596
 597         PR 21775
 598         * aarch64-opc.c: Fix spelling typos.
 599         * i386-dis.c: Likewise.
 600
 601 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 602
 603         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 604         max_addr_offset and octets variables to size_t.
 605
 606 2017-07-12  Alan Modra  <amodra@gmail.com>
 607
 608         * po/da.po: Update from translationproject.org/latest/opcodes/.
 609         * po/de.po: Likewise.
 610         * po/es.po: Likewise.
 611         * po/fi.po: Likewise.
 612         * po/fr.po: Likewise.
 613         * po/id.po: Likewise.
 614         * po/it.po: Likewise.
 615         * po/nl.po: Likewise.
 616         * po/pt_BR.po: Likewise.
 617         * po/ro.po: Likewise.
 618         * po/sv.po: Likewise.
 619         * po/tr.po: Likewise.
 620         * po/uk.po: Likewise.
 621         * po/vi.po: Likewise.
 622         * po/zh_CN.po: Likewise.
 623
 624 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 625             Alan Modra  <amodra@gmail.com>
 626
 627         * cgen.sh: Mark generated files read-only.
 628         * epiphany-asm.c: Regenerate.
 629         * epiphany-desc.c: Regenerate.
 630         * epiphany-desc.h: Regenerate.
 631         * epiphany-dis.c: Regenerate.
 632         * epiphany-ibld.c: Regenerate.
 633         * epiphany-opc.c: Regenerate.
 634         * epiphany-opc.h: Regenerate.
 635         * fr30-asm.c: Regenerate.
 636         * fr30-desc.c: Regenerate.
 637         * fr30-desc.h: Regenerate.
 638         * fr30-dis.c: Regenerate.
 639         * fr30-ibld.c: Regenerate.
 640         * fr30-opc.c: Regenerate.
 641         * fr30-opc.h: Regenerate.
 642         * frv-asm.c: Regenerate.
 643         * frv-desc.c: Regenerate.
 644         * frv-desc.h: Regenerate.
 645         * frv-dis.c: Regenerate.
 646         * frv-ibld.c: Regenerate.
 647         * frv-opc.c: Regenerate.
 648         * frv-opc.h: Regenerate.
 649         * ip2k-asm.c: Regenerate.
 650         * ip2k-desc.c: Regenerate.
 651         * ip2k-desc.h: Regenerate.
 652         * ip2k-dis.c: Regenerate.
 653         * ip2k-ibld.c: Regenerate.
 654         * ip2k-opc.c: Regenerate.
 655         * ip2k-opc.h: Regenerate.
 656         * iq2000-asm.c: Regenerate.
 657         * iq2000-desc.c: Regenerate.
 658         * iq2000-desc.h: Regenerate.
 659         * iq2000-dis.c: Regenerate.
 660         * iq2000-ibld.c: Regenerate.
 661         * iq2000-opc.c: Regenerate.
 662         * iq2000-opc.h: Regenerate.
 663         * lm32-asm.c: Regenerate.
 664         * lm32-desc.c: Regenerate.
 665         * lm32-desc.h: Regenerate.
 666         * lm32-dis.c: Regenerate.
 667         * lm32-ibld.c: Regenerate.
 668         * lm32-opc.c: Regenerate.
 669         * lm32-opc.h: Regenerate.
 670         * lm32-opinst.c: Regenerate.
 671         * m32c-asm.c: Regenerate.
 672         * m32c-desc.c: Regenerate.
 673         * m32c-desc.h: Regenerate.
 674         * m32c-dis.c: Regenerate.
 675         * m32c-ibld.c: Regenerate.
 676         * m32c-opc.c: Regenerate.
 677         * m32c-opc.h: Regenerate.
 678         * m32r-asm.c: Regenerate.
 679         * m32r-desc.c: Regenerate.
 680         * m32r-desc.h: Regenerate.
 681         * m32r-dis.c: Regenerate.
 682         * m32r-ibld.c: Regenerate.
 683         * m32r-opc.c: Regenerate.
 684         * m32r-opc.h: Regenerate.
 685         * m32r-opinst.c: Regenerate.
 686         * mep-asm.c: Regenerate.
 687         * mep-desc.c: Regenerate.
 688         * mep-desc.h: Regenerate.
 689         * mep-dis.c: Regenerate.
 690         * mep-ibld.c: Regenerate.
 691         * mep-opc.c: Regenerate.
 692         * mep-opc.h: Regenerate.
 693         * mt-asm.c: Regenerate.
 694         * mt-desc.c: Regenerate.
 695         * mt-desc.h: Regenerate.
 696         * mt-dis.c: Regenerate.
 697         * mt-ibld.c: Regenerate.
 698         * mt-opc.c: Regenerate.
 699         * mt-opc.h: Regenerate.
 700         * or1k-asm.c: Regenerate.
 701         * or1k-desc.c: Regenerate.
 702         * or1k-desc.h: Regenerate.
 703         * or1k-dis.c: Regenerate.
 704         * or1k-ibld.c: Regenerate.
 705         * or1k-opc.c: Regenerate.
 706         * or1k-opc.h: Regenerate.
 707         * or1k-opinst.c: Regenerate.
 708         * xc16x-asm.c: Regenerate.
 709         * xc16x-desc.c: Regenerate.
 710         * xc16x-desc.h: Regenerate.
 711         * xc16x-dis.c: Regenerate.
 712         * xc16x-ibld.c: Regenerate.
 713         * xc16x-opc.c: Regenerate.
 714         * xc16x-opc.h: Regenerate.
 715         * xstormy16-asm.c: Regenerate.
 716         * xstormy16-desc.c: Regenerate.
 717         * xstormy16-desc.h: Regenerate.
 718         * xstormy16-dis.c: Regenerate.
 719         * xstormy16-ibld.c: Regenerate.
 720         * xstormy16-opc.c: Regenerate.
 721         * xstormy16-opc.h: Regenerate.
 722
 723 2017-07-07  Alan Modra  <amodra@gmail.com>
 724
 725         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 726         * m32c-dis.c: Regenerate.
 727         * mep-dis.c: Regenerate.
 728
 729 2017-07-05  Borislav Petkov  <bp@suse.de>
 730
 731         * i386-dis.c: Enable ModRM.reg /6 aliases.
 732
 733 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 734
 735         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 736         with vmrs and vmsr.
 737
 738 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 739
 740         * configure: Regenerate.
 741
 742 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 743
 744         * po/opcodes.pot: Regenerate.
 745
 746 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 747
 748         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 749         entries to the MSA ASE instruction block.
 750
 751 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 752             Maciej W. Rozycki  <macro@imgtec.com>
 753
 754         * micromips-opc.c (XPA, XPAVZ): New macros.
 755         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 756         "mthgc0".
 757
 758 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 759             Maciej W. Rozycki  <macro@imgtec.com>
 760
 761         * micromips-opc.c (I36): New macro.
 762         (micromips_opcodes): Add "eretnc".
 763
 764 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 765             Andrew Bennett  <andrew.bennett@imgtec.com>
 766
 767         * mips-dis.c (mips_calculate_combination_ases): Handle the
 768         ASE_XPA_VIRT flag.
 769         (parse_mips_ase_option): New function.
 770         (parse_mips_dis_option): Factor out ASE option handling to the
 771         new function.  Call `mips_calculate_combination_ases'.
 772         * mips-opc.c (XPAVZ): New macro.
 773         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 774         "mfhgc0", "mthc0" and "mthgc0".
 775
 776 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 777
 778         * mips-dis.c (mips_calculate_combination_ases): New function.
 779         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 780         calculation to the new function.
 781         (set_default_mips_dis_options): Call the new function.
 782
 783 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 784
 785         * arc-dis.c (parse_disassembler_options): Use
 786         FOR_EACH_DISASSEMBLER_OPTION.
 787
 788 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 789
 790         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 791         disassembler option strings.
 792         (parse_cpu_option): Likewise.
 793
 794 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 795
 796         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 797         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 798         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 799         (aarch64_feature_dotprod, DOT_INSN): New.
 800         (udot, sdot): New.
 801         * aarch64-dis-2.c: Regenerated.
 802
 803 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 804
 805         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 806
 807 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 808             Matthew Fortune  <matthew.fortune@imgtec.com>
 809             Andrew Bennett  <andrew.bennett@imgtec.com>
 810
 811         * mips-formats.h (INT_BIAS): New macro.
 812         (INT_ADJ): Redefine in INT_BIAS terms.
 813         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 814         (mips_print_save_restore): New function.
 815         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 816         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 817         call.
 818         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 819         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 820         OP_SAVE_RESTORE_LIST handling, factored out from here.
 821         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 822         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 823         (mips_builtin_opcodes): Add "restore" and "save" entries.
 824         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 825         (IAMR2): New macro.
 826         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 827
 828 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 829
 830         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 831         alias; do not mark SLTI instruction as an alias.
 832
 833 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 834
 835         * i386-dis.c (RM_0FAE_REG_5): Removed.
 836         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 837         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 838         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 839         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 840         PREFIX_MOD_3_0F01_REG_5_RM_0.
 841         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 842         PREFIX_MOD_3_0FAE_REG_5.
 843         (mod_table): Update MOD_0FAE_REG_5.
 844         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 845         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 846         * i386-tbl.h: Regenerated.
 847
 848 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 849
 850         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 851         * i386-opc.tbl: Likewise.
 852         * i386-tbl.h: Regenerated.
 853
 854 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 855
 856         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 857         and "jmp{&|}".
 858         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 859         prefix.
 860
 861 2017-06-19  Nick Clifton  <nickc@redhat.com>
 862
 863         PR binutils/21614
 864         * score-dis.c (score_opcodes): Add sentinel.
 865
 866 2017-06-16  Alan Modra  <amodra@gmail.com>
 867
 868         * rx-decode.c: Regenerate.
 869
 870 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         PR binutils/21594
 873         * i386-dis.c (OP_E_register): Check valid bnd register.
 874         (OP_G): Likewise.
 875
 876 2017-06-15  Nick Clifton  <nickc@redhat.com>
 877
 878         PR binutils/21595
 879         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 880         range value.
 881
 882 2017-06-15  Nick Clifton  <nickc@redhat.com>
 883
 884         PR binutils/21588
 885         * rl78-decode.opc (OP_BUF_LEN): Define.
 886         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 887         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 888         array.
 889         * rl78-decode.c: Regenerate.
 890
 891 2017-06-15  Nick Clifton  <nickc@redhat.com>
 892
 893         PR binutils/21586
 894         * bfin-dis.c (gregs): Clip index to prevent overflow.
 895         (regs): Likewise.
 896         (regs_lo): Likewise.
 897         (regs_hi): Likewise.
 898
 899 2017-06-14  Nick Clifton  <nickc@redhat.com>
 900
 901         PR binutils/21576
 902         * score7-dis.c (score_opcodes): Add sentinel.
 903
 904 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 905
 906         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 907         * arm-dis.c: Likewise.
 908         * ia64-dis.c: Likewise.
 909         * mips-dis.c: Likewise.
 910         * spu-dis.c: Likewise.
 911         * disassemble.h (print_insn_aarch64): New declaration, moved from
 912         include/dis-asm.h.
 913         (print_insn_big_arm, print_insn_big_mips): Likewise.
 914         (print_insn_i386, print_insn_ia64): Likewise.
 915         (print_insn_little_arm, print_insn_little_mips): Likewise.
 916
 917 2017-06-14  Nick Clifton  <nickc@redhat.com>
 918
 919         PR binutils/21587
 920         * rx-decode.opc: Include libiberty.h
 921         (GET_SCALE): New macro - validates access to SCALE array.
 922         (GET_PSCALE): New macro - validates access to PSCALE array.
 923         (DIs, SIs, S2Is, rx_disp): Use new macros.
 924         * rx-decode.c: Regenerate.
 925
 926 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 927
 928         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 929
 930 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 931
 932         * arc-dis.c (enforced_isa_mask): Declare.
 933         (cpu_types): Likewise.
 934         (parse_cpu_option): New function.
 935         (parse_disassembler_options): Use it.
 936         (print_insn_arc): Use enforced_isa_mask.
 937         (print_arc_disassembler_options): Document new options.
 938
 939 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 940
 941         * alpha-dis.c: Include disassemble.h, don't include
 942         dis-asm.h.
 943         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 944         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 945         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 946         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 947         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 948         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 949         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 950         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 951         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 952         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 953         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 954         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 955         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 956         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 957         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 958         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 959         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 960         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 961         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 962         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 963         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 964         * z80-dis.c, z8k-dis.c: Likewise.
 965         * disassemble.h: New file.
 966
 967 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 968
 969         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 970         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 971
 972 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 973
 974         * disassemble.c (disassembler): Add arguments a, big and mach.
 975         Use them.
 976
 977 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 978
 979         * i386-dis.c (NOTRACK_Fixup): New.
 980         (NOTRACK): Likewise.
 981         (NOTRACK_PREFIX): Likewise.
 982         (last_active_prefix): Likewise.
 983         (reg_table): Use NOTRACK on indirect call and jmp.
 984         (ckprefix): Set last_active_prefix.
 985         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 986         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 987         * i386-opc.h (NoTrackPrefixOk): New.
 988         (i386_opcode_modifier): Add notrackprefixok.
 989         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 990         Add notrack.
 991         * i386-tbl.h: Regenerated.
 992
 993 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 994
 995         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 996         (X_IMM2): Define.
 997         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 998         bfd_mach_sparc_v9m8.
 999         (print_insn_sparc): Handle new operand types.
1000         * sparc-opc.c (MASK_M8): Define.
1001         (v6): Add MASK_M8.
1002         (v6notlet): Likewise.
1003         (v7): Likewise.
1004         (v8): Likewise.
1005         (v9): Likewise.
1006         (v9a): Likewise.
1007         (v9b): Likewise.
1008         (v9c): Likewise.
1009         (v9d): Likewise.
1010         (v9e): Likewise.
1011         (v9v): Likewise.
1012         (v9m): Likewise.
1013         (v9andleon): Likewise.
1014         (m8): Define.
1015         (HWS_VM8): Define.
1016         (HWS2_VM8): Likewise.
1017         (sparc_opcode_archs): Add entry for "m8".
1018         (sparc_opcodes): Add OSA2017 and M8 instructions
1019         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1020         fpx{ll,ra,rl}64x,
1021         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1022         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1023         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1024         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1025         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1026         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1027         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1028         ASI_CORE_SELECT_COMMIT_NHT.
1029
1030 2017-05-18  Alan Modra  <amodra@gmail.com>
1031
1032         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1033         * aarch64-dis.c: Likewise.
1034         * aarch64-gen.c: Likewise.
1035         * aarch64-opc.c: Likewise.
1036
1037 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1038             Matthew Fortune  <matthew.fortune@imgtec.com>
1039
1040         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1041         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1042         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1043         (print_insn_arg) <OP_REG28>: Add handler.
1044         (validate_insn_args) <OP_REG28>: Handle.
1045         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1046         32-bit encoding and 9-bit immediates.
1047         (print_insn_mips16): Handle MIPS16 instructions that require
1048         32-bit encoding and MFC0/MTC0 operand decoding.
1049         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1050         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1051         (RD_C0, WR_C0, E2, E2MT): New macros.
1052         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1053         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1054         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1055         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1056         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1057         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1058         instructions, "swl", "swr", "sync" and its "sync_acquire",
1059         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1060         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1061         regular/extended entries for original MIPS16 ISA revision
1062         instructions whose extended forms are subdecoded in the MIPS16e2
1063         ISA revision: "li", "sll" and "srl".
1064
1065 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1066
1067         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1068         reference in CP0 move operand decoding.
1069
1070 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1071
1072         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1073         type to hexadecimal.
1074         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1075
1076 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1077
1078         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1079         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1080         "sync_rmb" and "sync_wmb" as aliases.
1081         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1082         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1083
1084 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1085
1086         * arc-dis.c (parse_option): Update quarkse_em option..
1087         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1088         QUARKSE1.
1089         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1090
1091 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1092
1093         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1094
1095 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1096
1097         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1098         register.
1099
1100 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1101
1102         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1103         and branches and not synthetic data instructions.
1104
1105 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1106
1107         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1108
1109 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1110
1111         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1112         * arc-opc.c (insert_r13el): New function.
1113         (R13_EL): Define.
1114         * arc-tbl.h: Add new enter/leave variants.
1115
1116 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1117
1118         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1119
1120 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1121
1122         * mips-dis.c (print_mips_disassembler_options): Add
1123         `no-aliases'.
1124
1125 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1126
1127         * mips16-opc.c (AL): New macro.
1128         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1129         of "ld" and "lw" as aliases.
1130
1131 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1132
1133         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1134         arguments.
1135
1136 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1137             Alan Modra  <amodra@gmail.com>
1138
1139         * ppc-opc.c (ELEV): Define.
1140         (vle_opcodes): Add se_rfgi and e_sc.
1141         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1142         for E200Z4.
1143
1144 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1145
1146         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1147
1148 2017-04-21  Nick Clifton  <nickc@redhat.com>
1149
1150         PR binutils/21380
1151         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1152         LD3R and LD4R.
1153
1154 2017-04-13  Alan Modra  <amodra@gmail.com>
1155
1156         * epiphany-desc.c: Regenerate.
1157         * fr30-desc.c: Regenerate.
1158         * frv-desc.c: Regenerate.
1159         * ip2k-desc.c: Regenerate.
1160         * iq2000-desc.c: Regenerate.
1161         * lm32-desc.c: Regenerate.
1162         * m32c-desc.c: Regenerate.
1163         * m32r-desc.c: Regenerate.
1164         * mep-desc.c: Regenerate.
1165         * mt-desc.c: Regenerate.
1166         * or1k-desc.c: Regenerate.
1167         * xc16x-desc.c: Regenerate.
1168         * xstormy16-desc.c: Regenerate.
1169
1170 2017-04-11  Alan Modra  <amodra@gmail.com>
1171
1172         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1173         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1174         PPC_OPCODE_TMR for e6500.
1175         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1176         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1177         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1178         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1179         (PPCHTM): Define as PPC_OPCODE_POWER8.
1180         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1181
1182 2017-04-10  Alan Modra  <amodra@gmail.com>
1183
1184         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1185         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1186         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1187         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1188
1189 2017-04-09  Pip Cet  <pipcet@gmail.com>
1190
1191         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1192         appropriate floating-point precision directly.
1193
1194 2017-04-07  Alan Modra  <amodra@gmail.com>
1195
1196         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1197         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1198         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1199         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1200         vector instructions with E6500 not PPCVEC2.
1201
1202 2017-04-06  Pip Cet  <pipcet@gmail.com>
1203
1204         * Makefile.am: Add wasm32-dis.c.
1205         * configure.ac: Add wasm32-dis.c to wasm32 target.
1206         * disassemble.c: Add wasm32 disassembler code.
1207         * wasm32-dis.c: New file.
1208         * Makefile.in: Regenerate.
1209         * configure: Regenerate.
1210         * po/POTFILES.in: Regenerate.
1211         * po/opcodes.pot: Regenerate.
1212
1213 2017-04-05  Pedro Alves  <palves@redhat.com>
1214
1215         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1216         * arm-dis.c (parse_arm_disassembler_options): Constify.
1217         * ppc-dis.c (powerpc_init_dialect): Constify local.
1218         * vax-dis.c (parse_disassembler_options): Constify.
1219
1220 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1221
1222         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1223         RISCV_GP_SYMBOL.
1224
1225 2017-03-30  Pip Cet  <pipcet@gmail.com>
1226
1227         * configure.ac: Add (empty) bfd_wasm32_arch target.
1228         * configure: Regenerate
1229         * po/opcodes.pot: Regenerate.
1230
1231 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1232
1233         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1234         OSA2015.
1235         * opcodes/sparc-opc.c (asi_table): New ASIs.
1236
1237 2017-03-29  Alan Modra  <amodra@gmail.com>
1238
1239         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1240         "raw" option.
1241         (lookup_powerpc): Don't special case -1 dialect.  Handle
1242         PPC_OPCODE_RAW.
1243         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1244         lookup_powerpc call, pass it on second.
1245
1246 2017-03-27  Alan Modra  <amodra@gmail.com>
1247
1248         PR 21303
1249         * ppc-dis.c (struct ppc_mopt): Comment.
1250         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1251
1252 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1253
1254         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1255         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1256         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1257         (insert_nps_misc_imm_offset): New function.
1258         (extract_nps_misc imm_offset): New function.
1259         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1260         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1261
1262 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1263
1264         * s390-mkopc.c (main): Remove vx2 check.
1265         * s390-opc.txt: Remove vx2 instruction flags.
1266
1267 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1268
1269         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1270         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1271         (insert_nps_imm_offset): New function.
1272         (extract_nps_imm_offset): New function.
1273         (insert_nps_imm_entry): New function.
1274         (extract_nps_imm_entry): New function.
1275
1276 2017-03-17  Alan Modra  <amodra@gmail.com>
1277
1278         PR 21248
1279         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1280         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1281         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1282
1283 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1284
1285         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1286         <c.andi>: Likewise.
1287         <c.addiw> Likewise.
1288
1289 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1290
1291         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1292
1293 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1294
1295         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1296         <srl> Likewise.
1297         <srai> Likewise.
1298         <sra> Likewise.
1299
1300 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1301
1302         * i386-gen.c (opcode_modifiers): Replace S with Load.
1303         * i386-opc.h (S): Removed.
1304         (Load): New.
1305         (i386_opcode_modifier): Replace s with load.
1306         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1307         and {evex}.  Replace S with Load.
1308         * i386-tbl.h: Regenerated.
1309
1310 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1311
1312         * i386-opc.tbl: Use CpuCET on rdsspq.
1313         * i386-tbl.h: Regenerated.
1314
1315 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1316
1317         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1318         <vsx>: Do not use PPC_OPCODE_VSX3;
1319
1320 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1321
1322         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1323
1324 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1325
1326         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1327         (MOD_0F1E_PREFIX_1): Likewise.
1328         (MOD_0F38F5_PREFIX_2): Likewise.
1329         (MOD_0F38F6_PREFIX_0): Likewise.
1330         (RM_0F1E_MOD_3_REG_7): Likewise.
1331         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1332         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1333         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1334         (PREFIX_0F1E): Likewise.
1335         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1336         (PREFIX_0F38F5): Likewise.
1337         (dis386_twobyte): Use PREFIX_0F1E.
1338         (reg_table): Add REG_0F1E_MOD_3.
1339         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1340         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1341         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1342         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1343         (three_byte_table): Use PREFIX_0F38F5.
1344         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1345         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1346         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1347         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1348         PREFIX_MOD_3_0F01_REG_5_RM_2.
1349         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1350         (cpu_flags): Add CpuCET.
1351         * i386-opc.h (CpuCET): New enum.
1352         (CpuUnused): Commented out.
1353         (i386_cpu_flags): Add cpucet.
1354         * i386-opc.tbl: Add Intel CET instructions.
1355         * i386-init.h: Regenerated.
1356         * i386-tbl.h: Likewise.
1357
1358 2017-03-06  Alan Modra  <amodra@gmail.com>
1359
1360         PR 21124
1361         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1362         (extract_raq, extract_ras, extract_rbx): New functions.
1363         (powerpc_operands): Use opposite corresponding insert function.
1364         (Q_MASK): Define.
1365         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1366         register restriction.
1367
1368 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1369
1370         * disassemble.c Include "safe-ctype.h".
1371         (disassemble_init_for_target): Handle s390 init.
1372         (remove_whitespace_and_extra_commas): New function.
1373         (disassembler_options_cmp): Likewise.
1374         * arm-dis.c: Include "libiberty.h".
1375         (NUM_ELEM): Delete.
1376         (regnames): Use long disassembler style names.
1377         Add force-thumb and no-force-thumb options.
1378         (NUM_ARM_REGNAMES): Rename from this...
1379         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1380         (get_arm_regname_num_options): Delete.
1381         (set_arm_regname_option): Likewise.
1382         (get_arm_regnames): Likewise.
1383         (parse_disassembler_options): Likewise.
1384         (parse_arm_disassembler_option): Rename from this...
1385         (parse_arm_disassembler_options): ...to this.  Make static.
1386         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1387         (print_insn): Use parse_arm_disassembler_options.
1388         (disassembler_options_arm): New function.
1389         (print_arm_disassembler_options): Handle updated regnames.
1390         * ppc-dis.c: Include "libiberty.h".
1391         (ppc_opts): Add "32" and "64" entries.
1392         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1393         (powerpc_init_dialect): Add break to switch statement.
1394         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1395         (disassembler_options_powerpc): New function.
1396         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1397         Remove printing of "32" and "64".
1398         * s390-dis.c: Include "libiberty.h".
1399         (init_flag): Remove unneeded variable.
1400         (struct s390_options_t): New structure type.
1401         (options): New structure.
1402         (init_disasm): Rename from this...
1403         (disassemble_init_s390): ...to this.  Add initializations for
1404         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1405         (print_insn_s390): Delete call to init_disasm.
1406         (disassembler_options_s390): New function.
1407         (print_s390_disassembler_options): Print using information from
1408         struct 'options'.
1409         * po/opcodes.pot: Regenerate.
1410
1411 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1412
1413         * i386-dis.c (PCMPESTR_Fixup): New.
1414         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1415         (prefix_table): Use PCMPESTR_Fixup.
1416         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1417         PCMPESTR_Fixup.
1418         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1419         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1420         Split 64-bit and non-64-bit variants.
1421         * opcodes/i386-tbl.h: Re-generate.
1422
1423 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1424
1425         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1426         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1427         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1428         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1429         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1430         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1431         (OP_SVE_V_HSD): New macros.
1432         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1433         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1434         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1435         (aarch64_opcode_table): Add new SVE instructions.
1436         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1437         for rotation operands.  Add new SVE operands.
1438         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1439         (ins_sve_quad_index): Likewise.
1440         (ins_imm_rotate): Split into...
1441         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1442         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1443         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1444         functions.
1445         (aarch64_ins_sve_addr_ri_s4): New function.
1446         (aarch64_ins_sve_quad_index): Likewise.
1447         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1448         * aarch64-asm-2.c: Regenerate.
1449         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1450         (ext_sve_quad_index): Likewise.
1451         (ext_imm_rotate): Split into...
1452         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1453         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1454         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1455         functions.
1456         (aarch64_ext_sve_addr_ri_s4): New function.
1457         (aarch64_ext_sve_quad_index): Likewise.
1458         (aarch64_ext_sve_index): Allow quad indices.
1459         (do_misc_decoding): Likewise.
1460         * aarch64-dis-2.c: Regenerate.
1461         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1462         aarch64_field_kinds.
1463         (OPD_F_OD_MASK): Widen by one bit.
1464         (OPD_F_NO_ZR): Bump accordingly.
1465         (get_operand_field_width): New function.
1466         * aarch64-opc.c (fields): Add new SVE fields.
1467         (operand_general_constraint_met_p): Handle new SVE operands.
1468         (aarch64_print_operand): Likewise.
1469         * aarch64-opc-2.c: Regenerate.
1470
1471 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1472
1473         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1474         (aarch64_feature_compnum): ...this.
1475         (SIMD_V8_3): Replace with...
1476         (COMPNUM): ...this.
1477         (CNUM_INSN): New macro.
1478         (aarch64_opcode_table): Use it for the complex number instructions.
1479
1480 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1481
1482         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1483
1484 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1485
1486         Add support for associating SPARC ASIs with an architecture level.
1487         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1488         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1489         decoding of SPARC ASIs.
1490
1491 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1492
1493         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1494         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1495
1496 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1497
1498         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1499         1 (instead of to itself). Correct typo.
1500
1501 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1502
1503         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1504         pseudoinstructions.
1505
1506 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1507
1508         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1509         (aarch64_sys_reg_supported_p): Handle them.
1510
1511 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1512
1513         * arc-opc.c (UIMM6_20R): Define.
1514         (SIMM12_20): Use above.
1515         (SIMM12_20R): Define.
1516         (SIMM3_5_S): Use above.
1517         (UIMM7_A32_11R_S): Define.
1518         (UIMM7_9_S): Use above.
1519         (UIMM3_13R_S): Define.
1520         (SIMM11_A32_7_S): Use above.
1521         (SIMM9_8R): Define.
1522         (UIMM10_A32_8_S): Use above.
1523         (UIMM8_8R_S): Define.
1524         (W6): Use above.
1525         (arc_relax_opcodes): Use all above defines.
1526
1527 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1528
1529         * arc-regs.h: Distinguish some of the registers different on
1530         ARC700 and HS38 cpus.
1531
1532 2017-02-14  Alan Modra  <amodra@gmail.com>
1533
1534         PR 21118
1535         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1536         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1537
1538 2017-02-11  Stafford Horne  <shorne@gmail.com>
1539             Alan Modra  <amodra@gmail.com>
1540
1541         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1542         Use insn_bytes_value and insn_int_value directly instead.  Don't
1543         free allocated memory until function exit.
1544
1545 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1546
1547         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1548
1549 2017-02-03  Nick Clifton  <nickc@redhat.com>
1550
1551         PR 21096
1552         * aarch64-opc.c (print_register_list): Ensure that the register
1553         list index will fir into the tb buffer.
1554         (print_register_offset_address): Likewise.
1555         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1556
1557 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1558
1559         PR 21056
1560         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1561         instructions when the previous fetch packet ends with a 32-bit
1562         instruction.
1563
1564 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1565
1566         * pru-opc.c: Remove vague reference to a future GDB port.
1567
1568 2017-01-20  Nick Clifton  <nickc@redhat.com>
1569
1570         * po/ga.po: Updated Irish translation.
1571
1572 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1573
1574         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1575
1576 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1577
1578         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1579         if FETCH_DATA returns 0.
1580         (m68k_scan_mask): Likewise.
1581         (print_insn_m68k): Update code to handle -1 return value.
1582
1583 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1584
1585         * m68k-dis.c (enum print_insn_arg_error): New.
1586         (NEXTBYTE): Replace -3 with
1587         PRINT_INSN_ARG_MEMORY_ERROR.
1588         (NEXTULONG): Likewise.
1589         (NEXTSINGLE): Likewise.
1590         (NEXTDOUBLE): Likewise.
1591         (NEXTDOUBLE): Likewise.
1592         (NEXTPACKED): Likewise.
1593         (FETCH_ARG): Likewise.
1594         (FETCH_DATA): Update comments.
1595         (print_insn_arg): Update comments. Replace magic numbers with
1596         enum.
1597         (match_insn_m68k): Likewise.
1598
1599 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1600
1601         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1602         * i386-dis-evex.h (evex_table): Updated.
1603         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1604         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1605         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1606         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1607         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1608         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1609         * i386-init.h: Regenerate.
1610         * i386-tbl.h: Ditto.
1611
1612 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1613
1614         * msp430-dis.c (msp430_singleoperand): Return -1 if
1615         msp430dis_opcode_signed returns false.
1616         (msp430_doubleoperand): Likewise.
1617         (msp430_branchinstr): Return -1 if
1618         msp430dis_opcode_unsigned returns false.
1619         (msp430x_calla_instr): Likewise.
1620         (print_insn_msp430): Likewise.
1621
1622 2017-01-05  Nick Clifton  <nickc@redhat.com>
1623
1624         PR 20946
1625         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1626         could not be matched.
1627         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1628         NULL.
1629
1630 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1631
1632         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1633         (aarch64_opcode_table): Use RCPC_INSN.
1634
1635 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1636
1637         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1638         extension.
1639         * riscv-opcodes/all-opcodes: Likewise.
1640
1641 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1642
1643         * riscv-dis.c (print_insn_args): Add fall through comment.
1644
1645 2017-01-03  Nick Clifton  <nickc@redhat.com>
1646
1647         * po/sr.po: New Serbian translation.
1648         * configure.ac (ALL_LINGUAS): Add sr.
1649         * configure: Regenerate.
1650
1651 2017-01-02  Alan Modra  <amodra@gmail.com>
1652
1653         * epiphany-desc.h: Regenerate.
1654         * epiphany-opc.h: Regenerate.
1655         * fr30-desc.h: Regenerate.
1656         * fr30-opc.h: Regenerate.
1657         * frv-desc.h: Regenerate.
1658         * frv-opc.h: Regenerate.
1659         * ip2k-desc.h: Regenerate.
1660         * ip2k-opc.h: Regenerate.
1661         * iq2000-desc.h: Regenerate.
1662         * iq2000-opc.h: Regenerate.
1663         * lm32-desc.h: Regenerate.
1664         * lm32-opc.h: Regenerate.
1665         * m32c-desc.h: Regenerate.
1666         * m32c-opc.h: Regenerate.
1667         * m32r-desc.h: Regenerate.
1668         * m32r-opc.h: Regenerate.
1669         * mep-desc.h: Regenerate.
1670         * mep-opc.h: Regenerate.
1671         * mt-desc.h: Regenerate.
1672         * mt-opc.h: Regenerate.
1673         * or1k-desc.h: Regenerate.
1674         * or1k-opc.h: Regenerate.
1675         * xc16x-desc.h: Regenerate.
1676         * xc16x-opc.h: Regenerate.
1677         * xstormy16-desc.h: Regenerate.
1678         * xstormy16-opc.h: Regenerate.
1679
1680 2017-01-02  Alan Modra  <amodra@gmail.com>
1681
1682         Update year range in copyright notice of all files.
1683
1684 For older changes see ChangeLog-2016
1685 \f
1686 Copyright (C) 2017 Free Software Foundation, Inc.
1687
1688 Copying and distribution of this file, with or without modification,
1689 are permitted in any medium without royalty provided the copyright
1690 notice and this notice are preserved.
1691
1692 Local Variables:
1693 mode: change-log
1694 left-margin: 8
1695 fill-column: 74
1696 version-control: never
1697 End: