opcodes/ChangeLog

   1 2020-03-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
   4         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
   5         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
   6         (ptwrite): Split into non-64-bit and 64-bit forms.
   7         * i386-tbl.h: Re-generate.
   8
   9 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
  12         template.
  13         * i386-tbl.h: Re-generate.
  14
  15 2020-03-04  Jan Beulich  <jbeulich@suse.com>
  16
  17         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
  18         (prefix_table): Move vmmcall here. Add vmgexit.
  19         (rm_table): Replace vmmcall entry by prefix_table[] escape.
  20         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
  21         (cpu_flags): Add CpuSEV_ES entry.
  22         * i386-opc.h (CpuSEV_ES): New.
  23         (union i386_cpu_flags): Add cpusev_es field.
  24         * i386-opc.tbl (vmgexit): New.
  25         * i386-init.h, i386-tbl.h: Re-generate.
  26
  27 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  28
  29         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
  30         with MnemonicSize.
  31         * i386-opc.h (IGNORESIZE): New.
  32         (DEFAULTSIZE): Likewise.
  33         (IgnoreSize): Removed.
  34         (DefaultSize): Likewise.
  35         (MnemonicSize): New.
  36         (i386_opcode_modifier): Replace ignoresize/defaultsize with
  37         mnemonicsize.
  38         * i386-opc.tbl (IgnoreSize): New.
  39         (DefaultSize): Likewise.
  40         * i386-tbl.h: Regenerated.
  41
  42 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
  43
  44         PR 25627
  45         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
  46         instructions.
  47
  48 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  49
  50         PR gas/25622
  51         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
  52         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
  53         * i386-tbl.h: Regenerated.
  54
  55 2020-02-26  Alan Modra  <amodra@gmail.com>
  56
  57         * aarch64-asm.c: Indent labels correctly.
  58         * aarch64-dis.c: Likewise.
  59         * aarch64-gen.c: Likewise.
  60         * aarch64-opc.c: Likewise.
  61         * alpha-dis.c: Likewise.
  62         * i386-dis.c: Likewise.
  63         * nds32-asm.c: Likewise.
  64         * nfp-dis.c: Likewise.
  65         * visium-dis.c: Likewise.
  66
  67 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
  68
  69         * arc-regs.h (int_vector_base): Make it available for all ARC
  70         CPUs.
  71
  72 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
  73
  74         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
  75         changed.
  76
  77 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
  78
  79         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
  80         c.mv/c.li if rs1 is zero.
  81
  82 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
  83
  84         * i386-gen.c (cpu_flag_init): Replace CpuABM with
  85         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
  86         CPU_POPCNT_FLAGS.
  87         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
  88         * i386-opc.h (CpuABM): Removed.
  89         (CpuPOPCNT): New.
  90         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
  91         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
  92         popcnt.  Remove CpuABM from lzcnt.
  93         * i386-init.h: Regenerated.
  94         * i386-tbl.h: Likewise.
  95
  96 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
  99         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 100         VexW1 instead of open-coding them.
 101         * i386-tbl.h: Re-generate.
 102
 103 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 104
 105         * i386-opc.tbl (AddrPrefixOpReg): Define.
 106         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 107         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 108         templates. Drop NoRex64.
 109         * i386-tbl.h: Re-generate.
 110
 111 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 112
 113         PR gas/6518
 114         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 115         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 116         into Intel syntax instance (with Unpsecified) and AT&T one
 117         (without).
 118         (vcvtneps2bf16): Likewise, along with folding the two so far
 119         separate ones.
 120         * i386-tbl.h: Re-generate.
 121
 122 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 123
 124         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 125         CPU_ANY_SSE4A_FLAGS.
 126
 127 2020-02-17  Alan Modra  <amodra@gmail.com>
 128
 129         * i386-gen.c (cpu_flag_init): Correct last change.
 130
 131 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 132
 133         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 134         CPU_ANY_SSE4_FLAGS.
 135
 136 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 137
 138         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 139         (movzx): Likewise.
 140
 141 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 142
 143         PR gas/25438
 144         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 145         destination for Cpu64-only variant.
 146         (movzx): Fold patterns.
 147         * i386-tbl.h: Re-generate.
 148
 149 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 150
 151         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 152         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 153         CPU_ANY_SSE4_FLAGS entry.
 154         * i386-init.h: Re-generate.
 155
 156 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 159         with Unspecified, making the present one AT&T syntax only.
 160         * i386-tbl.h: Re-generate.
 161
 162 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 165         * i386-tbl.h: Re-generate.
 166
 167 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 168
 169         PR gas/24546
 170         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 171         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 172         Amd64 and Intel64 templates.
 173         (call, jmp): Likewise for far indirect variants. Dro
 174         Unspecified.
 175         * i386-tbl.h: Re-generate.
 176
 177 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 178
 179         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 180         * i386-opc.h (ShortForm): Delete.
 181         (struct i386_opcode_modifier): Remove shortform field.
 182         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 183         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 184         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 185         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 186         Drop ShortForm.
 187         * i386-tbl.h: Re-generate.
 188
 189 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 192         fucompi): Drop ShortForm from operand-less templates.
 193         * i386-tbl.h: Re-generate.
 194
 195 2020-02-11  Alan Modra  <amodra@gmail.com>
 196
 197         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 198         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 199         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 200         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 201         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 202
 203 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 204
 205         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 206         (cde_opcodes): Add VCX* instructions.
 207
 208 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 209             Matthew Malcomson  <matthew.malcomson@arm.com>
 210
 211         * arm-dis.c (struct cdeopcode32): New.
 212         (CDE_OPCODE): New macro.
 213         (cde_opcodes): New disassembly table.
 214         (regnames): New option to table.
 215         (cde_coprocs): New global variable.
 216         (print_insn_cde): New
 217         (print_insn_thumb32): Use print_insn_cde.
 218         (parse_arm_disassembler_options): Parse coprocN args.
 219
 220 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 221
 222         PR gas/25516
 223         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 224         with ISA64.
 225         * i386-opc.h (AMD64): Removed.
 226         (Intel64): Likewose.
 227         (AMD64): New.
 228         (INTEL64): Likewise.
 229         (INTEL64ONLY): Likewise.
 230         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 231         * i386-opc.tbl (Amd64): New.
 232         (Intel64): Likewise.
 233         (Intel64Only): Likewise.
 234         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 235         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 236         * i386-tbl.h: Regenerated.
 237
 238 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 239
 240         PR 25469
 241         * z80-dis.c: Add support for GBZ80 opcodes.
 242
 243 2020-02-04  Alan Modra  <amodra@gmail.com>
 244
 245         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 246
 247 2020-02-03  Alan Modra  <amodra@gmail.com>
 248
 249         * m32c-ibld.c: Regenerate.
 250
 251 2020-02-01  Alan Modra  <amodra@gmail.com>
 252
 253         * frv-ibld.c: Regenerate.
 254
 255 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 256
 257         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 258         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 259         (OP_E_memory): Replace xmm_mdq_mode case label by
 260         vex_scalar_w_dq_mode one.
 261         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 262
 263 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 266         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 267         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 268         (intel_operand_size): Drop vex_w_dq_mode case label.
 269
 270 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 271
 272         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 273         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 274
 275 2020-01-30  Alan Modra  <amodra@gmail.com>
 276
 277         * m32c-ibld.c: Regenerate.
 278
 279 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 280
 281         * bpf-opc.c: Regenerate.
 282
 283 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 284
 285         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 286         (dis386): Use them to replace C2/C3 table entries.
 287         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 288         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 289         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 290         * i386-tbl.h: Re-generate.
 291
 292 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 295         forms.
 296         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 297         DefaultSize.
 298         * i386-tbl.h: Re-generate.
 299
 300 2020-01-30  Alan Modra  <amodra@gmail.com>
 301
 302         * tic4x-dis.c (tic4x_dp): Make unsigned.
 303
 304 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 305             Jan Beulich  <jbeulich@suse.com>
 306
 307         PR binutils/25445
 308         * i386-dis.c (MOVSXD_Fixup): New function.
 309         (movsxd_mode): New enum.
 310         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 311         (intel_operand_size): Handle movsxd_mode.
 312         (OP_E_register): Likewise.
 313         (OP_G): Likewise.
 314         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 315         register on movsxd.  Add movsxd with 16-bit destination register
 316         for AMD64 and Intel64 ISAs.
 317         * i386-tbl.h: Regenerated.
 318
 319 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 320
 321         PR 25403
 322         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 323         * aarch64-asm-2.c: Regenerate
 324         * aarch64-dis-2.c: Likewise.
 325         * aarch64-opc-2.c: Likewise.
 326
 327 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 328
 329         * i386-opc.tbl (sysret): Drop DefaultSize.
 330         * i386-tbl.h: Re-generate.
 331
 332 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 333
 334         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 335         Dword.
 336         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 337         * i386-tbl.h: Re-generate.
 338
 339 2020-01-20  Nick Clifton  <nickc@redhat.com>
 340
 341         * po/de.po: Updated German translation.
 342         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 343         * po/uk.po: Updated Ukranian translation.
 344
 345 2020-01-20  Alan Modra  <amodra@gmail.com>
 346
 347         * hppa-dis.c (fput_const): Remove useless cast.
 348
 349 2020-01-20  Alan Modra  <amodra@gmail.com>
 350
 351         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 352
 353 2020-01-18  Nick Clifton  <nickc@redhat.com>
 354
 355         * configure: Regenerate.
 356         * po/opcodes.pot: Regenerate.
 357
 358 2020-01-18  Nick Clifton  <nickc@redhat.com>
 359
 360         Binutils 2.34 branch created.
 361
 362 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 363
 364         * opintl.h: Fix spelling error (seperate).
 365
 366 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 367
 368         * i386-opc.tbl: Add {vex} pseudo prefix.
 369         * i386-tbl.h: Regenerated.
 370
 371 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 372
 373         PR 25376
 374         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 375         (neon_opcodes): Likewise.
 376         (select_arm_features): Make sure we enable MVE bits when selecting
 377         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 378         any architecture.
 379
 380 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-opc.tbl: Drop stale comment from XOP section.
 383
 384 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 385
 386         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 387         (extractps): Add VexWIG to SSE2AVX forms.
 388         * i386-tbl.h: Re-generate.
 389
 390 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 393         Size64 from and use VexW1 on SSE2AVX forms.
 394         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 395         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 396         * i386-tbl.h: Re-generate.
 397
 398 2020-01-15  Alan Modra  <amodra@gmail.com>
 399
 400         * tic4x-dis.c (tic4x_version): Make unsigned long.
 401         (optab, optab_special, registernames): New file scope vars.
 402         (tic4x_print_register): Set up registernames rather than
 403         malloc'd registertable.
 404         (tic4x_disassemble): Delete optable and optable_special.  Use
 405         optab and optab_special instead.  Throw away old optab,
 406         optab_special and registernames when info->mach changes.
 407
 408 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 409
 410         PR 25377
 411         * z80-dis.c (suffix): Use .db instruction to generate double
 412         prefix.
 413
 414 2020-01-14  Alan Modra  <amodra@gmail.com>
 415
 416         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 417         values to unsigned before shifting.
 418
 419 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 420
 421         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 422         flow instructions.
 423         (print_insn_thumb16, print_insn_thumb32): Likewise.
 424         (print_insn): Initialize the insn info.
 425         * i386-dis.c (print_insn): Initialize the insn info fields, and
 426         detect jumps.
 427
 428 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 429
 430         * arc-opc.c (C_NE): Make it required.
 431
 432 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 433
 434         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 435         reserved register name.
 436
 437 2020-01-13  Alan Modra  <amodra@gmail.com>
 438
 439         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 440         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 441
 442 2020-01-13  Alan Modra  <amodra@gmail.com>
 443
 444         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 445         result of wasm_read_leb128 in a uint64_t and check that bits
 446         are not lost when copying to other locals.  Use uint32_t for
 447         most locals.  Use PRId64 when printing int64_t.
 448
 449 2020-01-13  Alan Modra  <amodra@gmail.com>
 450
 451         * score-dis.c: Formatting.
 452         * score7-dis.c: Formatting.
 453
 454 2020-01-13  Alan Modra  <amodra@gmail.com>
 455
 456         * score-dis.c (print_insn_score48): Use unsigned variables for
 457         unsigned values.  Don't left shift negative values.
 458         (print_insn_score32): Likewise.
 459         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 460
 461 2020-01-13  Alan Modra  <amodra@gmail.com>
 462
 463         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 464
 465 2020-01-13  Alan Modra  <amodra@gmail.com>
 466
 467         * fr30-ibld.c: Regenerate.
 468
 469 2020-01-13  Alan Modra  <amodra@gmail.com>
 470
 471         * xgate-dis.c (print_insn): Don't left shift signed value.
 472         (ripBits): Formatting, use 1u.
 473
 474 2020-01-10  Alan Modra  <amodra@gmail.com>
 475
 476         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 477         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 478
 479 2020-01-10  Alan Modra  <amodra@gmail.com>
 480
 481         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 482         and XRREG value earlier to avoid a shift with negative exponent.
 483         * m10200-dis.c (disassemble): Similarly.
 484
 485 2020-01-09  Nick Clifton  <nickc@redhat.com>
 486
 487         PR 25224
 488         * z80-dis.c (ld_ii_ii): Use correct cast.
 489
 490 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 491
 492         PR 25224
 493         * z80-dis.c (ld_ii_ii): Use character constant when checking
 494         opcode byte value.
 495
 496 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 497
 498         * i386-dis.c (SEP_Fixup): New.
 499         (SEP): Define.
 500         (dis386_twobyte): Use it for sysenter/sysexit.
 501         (enum x86_64_isa): Change amd64 enumerator to value 1.
 502         (OP_J): Compare isa64 against intel64 instead of amd64.
 503         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 504         forms.
 505         * i386-tbl.h: Re-generate.
 506
 507 2020-01-08  Alan Modra  <amodra@gmail.com>
 508
 509         * z8k-dis.c: Include libiberty.h
 510         (instr_data_s): Make max_fetched unsigned.
 511         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 512         Don't exceed byte_info bounds.
 513         (output_instr): Make num_bytes unsigned.
 514         (unpack_instr): Likewise for nibl_count and loop.
 515         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 516         idx unsigned.
 517         * z8k-opc.h: Regenerate.
 518
 519 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 520
 521         * arc-tbl.h (llock): Use 'LLOCK' as class.
 522         (llockd): Likewise.
 523         (scond): Use 'SCOND' as class.
 524         (scondd): Likewise.
 525         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 526         (scondd): Likewise.
 527
 528 2020-01-06  Alan Modra  <amodra@gmail.com>
 529
 530         * m32c-ibld.c: Regenerate.
 531
 532 2020-01-06  Alan Modra  <amodra@gmail.com>
 533
 534         PR 25344
 535         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 536         Peek at next byte to prevent recursion on repeated prefix bytes.
 537         Ensure uninitialised "mybuf" is not accessed.
 538         (print_insn_z80): Don't zero n_fetch and n_used here,..
 539         (print_insn_z80_buf): ..do it here instead.
 540
 541 2020-01-04  Alan Modra  <amodra@gmail.com>
 542
 543         * m32r-ibld.c: Regenerate.
 544
 545 2020-01-04  Alan Modra  <amodra@gmail.com>
 546
 547         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 548
 549 2020-01-04  Alan Modra  <amodra@gmail.com>
 550
 551         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 552
 553 2020-01-04  Alan Modra  <amodra@gmail.com>
 554
 555         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 556
 557 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 558
 559         * aarch64-tbl.h (aarch64_opcode_table): Use
 560         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 561
 562 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 563
 564         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 565         forms of SUDOT and USDOT.
 566
 567 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 568
 569         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 570         uzip{1,2}.
 571         * opcodes/aarch64-dis-2.c: Re-generate.
 572
 573 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 574
 575         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 576         FMMLA encoding.
 577         * opcodes/aarch64-dis-2.c: Re-generate.
 578
 579 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 580
 581         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 582
 583 2020-01-01  Alan Modra  <amodra@gmail.com>
 584
 585         Update year range in copyright notice of all files.
 586
 587 For older changes see ChangeLog-2019
 588 \f
 589 Copyright (C) 2020 Free Software Foundation, Inc.
 590
 591 Copying and distribution of this file, with or without modification,
 592 are permitted in any medium without royalty provided the copyright
 593 notice and this notice are preserved.
 594
 595 Local Variables:
 596 mode: change-log
 597 left-margin: 8
 598 fill-column: 74
 599 version-control: never
 600 End: