opcodes/ChangeLog

   1 2012-11-30  Oleg Raikhman  <oleg@adapteva.com>
   2             Joern Rennecke  <joern.rennecke@embecosm.com>
   3
   4         * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
   5
   6 2012-11-29  Roland McGrath  <mcgrathr@google.com>
   7
   8         * s390-mkopc.c (file_header): Add const.
   9
  10 2012-11-29  David Holsgrove  <david.holsgrove@xilinx.com>
  11
  12         * microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to
  13         INST_TYPE_R1_R2_SPECIAL
  14         * microblaze-dis.c (print_insn_microblaze): Same.
  15
  16 2012-11-23  Alan Modra  <amodra@gmail.com>
  17
  18         * ppc-dis.c (ppc_parse_cpu): Add "sticky" param.  Track bits
  19         set from ppc_opts.sticky in it.  Delete "retain_mask".
  20         (powerpc_init_dialect): Choose default dialect from info->mach
  21         before parsing -M options.  Handle more bfd_mach_ppc variants.
  22         Update common default to power7.
  23
  24 2012-11-21  David Holsgrove  <david.holsgrove@xilinx.com>
  25
  26         * microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES.
  27         * microblaze-opcm.h (microblaze_instr): Likewise
  28
  29 2012-11-21  Edgar E. Iglesias <edgar.iglesias@gmail.com>
  30
  31         * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
  32         * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
  33
  34 2012-11-20  Kirill Yukhin  <kirill.yukhin@intel.com>
  35             H.J. Lu  <hongjiu.lu@intel.com>
  36
  37         PR gas/14859
  38         * i386-opc.tbl: Fix opcode for 64-bit jecxz.
  39         * i386-tbl.h: Regenerated.
  40
  41 2012-11-20  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  42
  43         * s390-opc.txt: Fix srstu and strag opcodes.
  44
  45 2012-11-14  David Holsgrove  <david.holsgrove@xilinx.com>
  46
  47         * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
  48         update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
  49         and increase MAX_OPCODES.
  50         (op_code_struct):  add mbar and sleep
  51         * microblaze-opcm.h (microblaze_instr): add mbar
  52         Define IMM_MBAR and IMM5_MBAR_MASK
  53         * microblaze-dis.c: Add get_field_imm5_mbar
  54         (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
  55
  56 2012-11-14  Edgar E. Iglesias <edgar.iglesias@gmail.com>
  57
  58         * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct):  add clz insn
  59         * microblaze-opcm.h (microblaze_instr): add clz
  60
  61 2012-11-14  Edgar E. Iglesias <edgar.iglesias@gmail.com>
  62
  63         * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct):  add lbur,
  64         lhur, lwr, sbr, shr, swr
  65         * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
  66         swr
  67
  68 2012-11-09  Nick Clifton  <nickc@redhat.com>
  69
  70         * configure.in: Add bfd_v850_rh850_arch.
  71         * configure: Regenerate.
  72         * disassemble.c (disassembler): Likewise.
  73
  74 2012-11-09  H.J. Lu  <hongjiu.lu@intel.com>
  75
  76         * aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
  77         * ia64-gen.c (fetch_insn_class): Likewise.
  78
  79 2012-11-08  Alan Modra  <amodra@gmail.com>
  80
  81         * po/POTFILES.in: Regenerate.
  82
  83 2012-11-05  Alan Modra  <amodra@gmail.com>
  84
  85         * configure.in: Apply 2012-09-10 change to config.in here.
  86
  87 2012-10-26  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  88
  89         * s390-mkopc.c: Accept empty lines in s390-opc.txt.
  90         * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
  91         and RRF_RMRR.
  92         * s390-opc.txt: Add new instructions.  New instruction type for lptea.
  93
  94 2012-10-26  Christian Groessler  <chris@groessler.org>
  95
  96         * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
  97         trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb).  Remove
  98         non-existing opcode trtrb.
  99         * z8k-opc.h: Regenerate.
 100
 101 2012-10-26  Alan Modra  <amodra@gmail.com>
 102
 103         * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
 104
 105 2012-10-24  Roland McGrath  <mcgrathr@google.com>
 106
 107         * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
 108         set rex_used to rex.
 109
 110 2012-10-22  Peter Bergner  <bergner@vnet.ibm.com>
 111
 112         * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
 113
 114 2012-10-18  Tom Tromey  <tromey@redhat.com>
 115
 116         * tic54x-dis.c (print_instruction): Don't use K&R style.
 117         (print_parallel_instruction, sprint_dual_address)
 118         (sprint_indirect_address, sprint_direct_address, sprint_mmr)
 119         (sprint_cc2, sprint_condition): Likewise.
 120
 121 2012-10-18  Kai Tietz  <ktietz@redhat.com>
 122
 123         * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
 124         value with a default.
 125         (do_special_encoding): Likewise.
 126         (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
 127         variables with default.
 128         * arc-dis.c (write_comments_): Don't use strncat due
 129         size of state->commentBuffer pointer isn't predictable.
 130
 131 2012-10-15  Yufeng Zhang  <yufeng.zhang@arm.com>
 132
 133         * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
 134         rmr_el3; remove daifset and daifclr.
 135
 136 2012-10-15  Yufeng Zhang  <yufeng.zhang@arm.com>
 137
 138         * aarch64-opc.c (operand_general_constraint_met_p): Change to check
 139         the alignment of addr.offset.imm instead of that of shifter.amount for
 140         operand type AARCH64_OPND_ADDR_UIMM12.
 141
 142 2012-10-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 143
 144         * arm-dis.c: Use preferred form of vrint instruction variants
 145         for disassembly.
 146
 147 2012-10-09  Nagajyothi Eggone  <nagajyothi.eggone@amd.com>
 148
 149         * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
 150         * i386-init.h: Regenerated.
 151
 152 2012-10-05  Peter Bergner  <bergner@vnet.ibm.com>
 153
 154         * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
 155         * ppc-opc.c (VBA): New define.
 156         (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
 157         mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
 158
 159 2012-10-04  Nick Clifton  <nickc@redhat.com>
 160
 161         * v850-dis.c (disassemble): Place square parentheses around second
 162         register operand of clr1, not1, set1 and tst1 instructions.
 163
 164 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 165
 166         * s390-mkopc.c: Support new option zEC12.
 167         * s390-opc.c: Add new instruction formats.
 168         * s390-opc.txt: Add new instructions for zEC12.
 169
 170 2012-09-27  Anthony Green  <green@moxielogic.com>
 171
 172         * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
 173         * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
 174
 175 2012-09-25  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 176
 177         * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
 178         CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
 179         and CPU_BTVER2_FLAGS.
 180         * i386-init.h: Regenerated.
 181
 182 2012-09-20  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 183
 184         * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
 185         CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
 186         CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
 187         CPU_BTVER2_FLAGS.  Add CPU_CX16_FLAGS.
 188         (cpu_flags): Add CpuCX16.
 189         * i386-opc.h (CpuCX16): New.
 190         (i386_cpu_flags): Add cpucx16.
 191         * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
 192         * i386-tbl.h: Regenerate.
 193         * i386-init.h: Likewise.
 194
 195 2012-09-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 196
 197         * arm-dis.c: Changed ldra and strl-form mnemonics
 198         to lda and stl-form.
 199
 200 2012-09-18  Chao-ying Fu  <fu@mips.com>
 201
 202         * micromips-opc.c (micromips_opcodes): Correct the encoding of
 203         the "swxc1" instruction.
 204
 205 2012-09-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 206
 207         * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
 208         the parameter 'inst'.
 209         (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
 210         (convert_mov_to_movewide): Change to assert (0) when
 211         aarch64_wide_constant_p returns FALSE.
 212
 213 2012-09-14  David Edelsohn  <dje.gcc@gmail.com>
 214
 215         * configure: Regenerate.
 216
 217 2012-09-14  Anthony Green  <green@moxielogic.com>
 218
 219         * moxie-dis.c (print_insn_moxie): Branch targets are relative to
 220         the address after the branch instruction.
 221
 222 2012-09-13  Anthony Green  <green@moxielogic.com>
 223
 224         * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
 225
 226 2012-09-10  Matthias Klose  <doko@ubuntu.com>
 227
 228         * config.in: Disable sanity check for kfreebsd.
 229
 230 2012-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 231
 232         * configure: Regenerated.
 233
 234 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 235
 236         * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
 237         * ia64-gen.c: Promote completer index type to longlong.
 238         (irf_operand): Add new register recognition.
 239         (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
 240         (lookup_specifier): Add new resource recognition.
 241         (insert_bit_table_ent): Relax abort condition according to the
 242         changed completer index type.
 243         (print_dis_table): Fix printf format for completer index.
 244         * ia64-ic.tbl: Add a new instruction class.
 245         * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
 246         * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
 247         * ia64-opc.h: Define short names for new operand types.
 248         * ia64-raw.tbl: Add new RAW resource for DAHR register.
 249         * ia64-waw.tbl: Add new WAW resource for DAHR register.
 250         * ia64-asmtab.c: Regenerate.
 251
 252 2012-08-29  Peter Bergner  <bergner@vnet.ibm.com>
 253
 254         * ppc-opc.c (VXASHB_MASK): New define.
 255         (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
 256
 257 2012-08-28  Peter Bergner  <bergner@vnet.ibm.com>
 258
 259         * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
 260         VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
 261         (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
 262         vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
 263         vupklsh>: Use VXVA_MASK.
 264         <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
 265         <mfvscr>: Use VXVAVB_MASK.
 266         <mtvscr>: Use VXVDVA_MASK.
 267         <vspltb>: Use VXUIMM4_MASK.
 268         <vsplth>: Use VXUIMM3_MASK.
 269         <vspltw>: Use VXUIMM2_MASK.
 270
 271 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 272
 273         * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
 274
 275 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 276
 277         * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
 278
 279 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 280
 281         * arm-dis.c (neon_opcodes): Handle VMULL.P64.
 282
 283 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 284
 285         * arm-dis.c (neon_opcodes): Add support for AES instructions.
 286
 287 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 288
 289         * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
 290         conversions.
 291
 292 2012-08-24  Matthew  Gretton-Dann  <matthew.gretton-dann@arm.com>
 293
 294         * arm-dis.c (coprocessor_opcodes): Add VRINT.
 295         (neon_opcodes): Likewise.
 296
 297 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 298
 299         * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
 300         variants.
 301         (neon_opcodes): Likewise.
 302
 303 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 304
 305         * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
 306         (neon_opcodes): Likewise.
 307
 308 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 309
 310         * arm-dis.c (coprocessor_opcodes): Add VSEL.
 311         (print_insn_coprocessor): Add new %<>c bitfield format
 312         specifier.
 313
 314 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 315
 316         * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
 317         (thumb32_opcodes): Likewise.
 318         (print_arm_insn): Add support for %<>T formatter.
 319
 320 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 321
 322         * arm-dis.c (arm_opcodes): Add HLT.
 323         (thumb_opcodes): Likewise.
 324
 325 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 326
 327         * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
 328
 329 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 330
 331         * arm-dis.c (arm_opcodes): Add SEVL.
 332         (thumb_opcodes): Likewise.
 333         (thumb32_opcodes): Likewise.
 334
 335 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 336
 337         * arm-dis.c (data_barrier_option): New function.
 338         (print_insn_arm): Use data_barrier_option.
 339         (print_insn_thumb32): Use data_barrier_option.
 340
 341 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com
 342
 343         * arm-dis.c (COND_UNCOND): New constant.
 344         (print_insn_coprocessor): Add support for %u format specifier.
 345         (print_insn_neon): Likewise.
 346
 347 2012-08-21  David S. Miller  <davem@davemloft.net>
 348
 349         * sparc-opc.c (4-argument crypto instructions): Fix encoding using
 350         F3F4 macro.
 351
 352 2012-08-20  Edmar Wienskoski  <edmar@freescale.com>
 353
 354         * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
 355         vabsduh, vabsduw, mviwsplt.
 356
 357 2012-08-17  Nagajyothi Eggone  <nagajyothi.eggone@amd.com>
 358
 359         * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
 360         CPU_BTVER2_FLAGS.
 361
 362         * i386-opc.h: Update CpuPRFCHW comment.
 363
 364         * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
 365         * i386-init.h: Regenerated.
 366         * i386-tbl.h: Likewise.
 367
 368 2012-08-17  Nick Clifton  <nickc@redhat.com>
 369
 370         * po/uk.po: New Ukranian translation.
 371         * configure.in (ALL_LINGUAS): Add uk.
 372         * configure: Regenerate.
 373
 374 2012-08-16  Peter Bergner  <bergner@vnet.ibm.com>
 375
 376         * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
 377         RBX for the third operand.
 378         <"lswi">: Use RAX for second and NBI for the third operand.
 379
 380 2012-08-15  DJ Delorie  <dj@redhat.com>
 381
 382         * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
 383         operands, so that data addresses can be corrected when not
 384         ES-overridden.
 385         * rl78-decode.c: Regenerate.
 386         * rl78-dis.c (print_insn_rl78): Make order of modifiers
 387         irrelevent.  When the 'e' specifier is used on an operand and no
 388         ES prefix is provided, adjust address to make it absolute.
 389
 390 2012-08-15  Peter Bergner  <bergner@vnet.ibm.com>
 391
 392         * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
 393
 394 2012-08-15  Peter Bergner  <bergner@vnet.ibm.com>
 395
 396         * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
 397
 398 2012-08-14  Maciej W. Rozycki  <macro@codesourcery.com>
 399
 400         * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
 401         macros, use local variables for info struct member accesses,
 402         update the type of the variable used to hold the instruction
 403         word.
 404         (print_insn_mips, print_mips16_insn_arg): Likewise.
 405         (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
 406         local variables for info struct member accesses.
 407         (print_insn_micromips): Add GET_OP_S local macro.
 408         (_print_insn_mips): Update the type of the variable used to hold
 409         the instruction word.
 410
 411 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 412             Laurent Desnogues  <laurent.desnogues@arm.com>
 413             Jim MacArthur  <jim.macarthur@arm.com>
 414             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 415             Nigel Stephens  <nigel.stephens@arm.com>
 416             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 417             Richard Earnshaw  <rearnsha@arm.com>
 418             Sofiane Naci  <sofiane.naci@arm.com>
 419             Tejas Belagod  <tejas.belagod@arm.com>
 420             Yufeng Zhang  <yufeng.zhang@arm.com>
 421
 422         * Makefile.am: Add AArch64.
 423         * Makefile.in: Regenerate.
 424         * aarch64-asm.c: New file.
 425         * aarch64-asm.h: New file.
 426         * aarch64-dis.c: New file.
 427         * aarch64-dis.h: New file.
 428         * aarch64-gen.c: New file.
 429         * aarch64-opc.c: New file.
 430         * aarch64-opc.h: New file.
 431         * aarch64-tbl.h: New file.
 432         * configure.in: Add AArch64.
 433         * configure: Regenerate.
 434         * disassemble.c: Add AArch64.
 435         * aarch64-asm-2.c: New file (automatically generated).
 436         * aarch64-dis-2.c: New file (automatically generated).
 437         * aarch64-opc-2.c: New file (automatically generated).
 438         * po/POTFILES.in: Regenerate.
 439
 440 2012-08-13  Maciej W. Rozycki  <macro@codesourcery.com>
 441
 442         * micromips-opc.c (micromips_opcodes): Update comment.
 443         * mips-opc.c (mips_builtin_opcodes): Likewise.  Mark coprocessor
 444         instructions for IOCT as appropriate.
 445         * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
 446         opcode_is_member.
 447         * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
 448         the result of a check for the -Wno-missing-field-initializers
 449         GCC option.
 450         * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
 451         (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
 452         compilation.
 453         (mips16-opc.lo): Likewise.
 454         (micromips-opc.lo): Likewise.
 455         * aclocal.m4: Regenerate.
 456         * configure: Regenerate.
 457         * Makefile.in: Regenerate.
 458
 459 2012-08-11  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 460
 461         PR gas/14423
 462         * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
 463         * i386-init.h: Regenerated.
 464
 465 2012-08-09  Nick Clifton  <nickc@redhat.com>
 466
 467         * po/vi.po: Updated Vietnamese translation.
 468
 469 2012-08-07  Roland McGrath  <mcgrathr@google.com>
 470
 471         * i386-dis.c (reg_table): Fill out REG_0F0D table with
 472         AMD-reserved cases as "prefetch".
 473         (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
 474         (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
 475         (reg_table): Use those under REG_0F18.
 476         (mod_table): Add those cases as "nop/reserved".
 477
 478 2012-08-07  Jan Beulich <jbeulich@suse.com>
 479
 480         * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
 481
 482 2012-08-06  Roland McGrath  <mcgrathr@google.com>
 483
 484         * i386-dis.c (print_insn): Print spaces between multiple excess
 485         prefixes.  Return actual number of excess prefixes consumed,
 486         not always one.
 487
 488         * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
 489
 490 2012-08-06  Roland McGrath  <mcgrathr@google.com>
 491             Victor Khimenko  <khim@google.com>
 492             H.J. Lu  <hongjiu.lu@intel.com>
 493
 494         * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
 495         (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
 496         (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
 497         (OP_E_register): Likewise.
 498         (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
 499
 500 2012-08-02  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
 501
 502         * configure.in: Formatting.
 503         * configure: Regenerate.
 504
 505 2012-08-01  Alan Modra  <amodra@gmail.com>
 506
 507         * h8300-dis.c: Fix printf arg warnings.
 508         * i960-dis.c: Likewise.
 509         * mips-dis.c: Likewise.
 510         * pdp11-dis.c: Likewise.
 511         * sh-dis.c: Likewise.
 512         * v850-dis.c: Likewise.
 513         * configure.in: Formatting.
 514         * configure: Regenerate.
 515         * rl78-decode.c: Regenerate.
 516         * po/POTFILES.in: Regenerate.
 517
 518 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 519             Catherine Moore  <clm@codesourcery.com>
 520             Maciej W. Rozycki  <macro@codesourcery.com>
 521
 522         * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
 523         (DSP_VOLA): Likewise.
 524         (D32, D33): Likewise.
 525         (micromips_opcodes): Add DSP ASE instructions.
 526         * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
 527         <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
 528
 529 2012-07-31  Jan Beulich <jbeulich@suse.com>
 530
 531         * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
 532         instruction group. Mark as requiring AVX2.
 533         * i386-tbl.h: Re-generate.
 534
 535 2012-07-30  Nick Clifton  <nickc@redhat.com>
 536
 537         * po/opcodes.pot: Updated template.
 538         * po/es.po: Updated Spanish translation.
 539         * po/fi.po: Updated Finnish translation.
 540
 541 2012-07-27  Mike Frysinger  <vapier@gentoo.org>
 542
 543         * configure.in (BFD_VERSION): Run bfd/configure --version and
 544         parse the output of that.
 545         * configure: Regenerate.
 546
 547 2012-07-25  James Lemke  <jwlemke@codesourcery.com>
 548
 549         * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
 550
 551 2012-07-24  Stephan McCamant  <smcc@cs.berkeley.edu>
 552             Dr David Alan Gilbert  <dave@treblig.org>
 553
 554         PR binutils/13135
 555         * arm-dis.c: Add necessary casts for printing integer values.
 556         Use %s when printing string values.
 557         * hppa-dis.c: Likewise.
 558         * m68k-dis.c: Likewise.
 559         * microblaze-dis.c: Likewise.
 560         * mips-dis.c: Likewise.
 561         * sparc-dis.c: Likewise.
 562
 563 2012-07-19  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 564
 565         PR binutils/14355
 566         * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
 567         (VEX_LEN_0FXOP_08_CD): Likewise.
 568         (VEX_LEN_0FXOP_08_CE): Likewise.
 569         (VEX_LEN_0FXOP_08_CF): Likewise.
 570         (VEX_LEN_0FXOP_08_EC): Likewise.
 571         (VEX_LEN_0FXOP_08_ED): Likewise.
 572         (VEX_LEN_0FXOP_08_EE): Likewise.
 573         (VEX_LEN_0FXOP_08_EF): Likewise.
 574         (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
 575         vpcomub, vpcomuw, vpcomud, vpcomuq.
 576         (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
 577         VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
 578         VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
 579         VEX_LEN_0FXOP_08_EF.
 580
 581 2012-07-16  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 582
 583         * i386-dis.c (PREFIX_0F38F6): New.
 584         (prefix_table): Add adcx, adox instructions.
 585         (three_byte_table): Use PREFIX_0F38F6.
 586         (mod_table): Add rdseed instruction.
 587         * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
 588         (cpu_flags): Likewise.
 589         * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
 590         (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
 591         * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
 592         prefetchw.
 593         * i386-tbl.h: Regenerate.
 594         * i386-init.h: Likewise.
 595
 596 2012-07-05  Thomas Schwinge  <thomas@codesourcery.com>
 597
 598         * mips-dis.c: Remove gratuitous newline.
 599
 600 2012-07-05  Sean Keys  <skeys@ipdatasys.com>
 601
 602         * xgate-dis.c: Removed an IF statement that will
 603         always be false due to overlapping operand masks.
 604         * xgate-opc.c: Corrected 'com' opcode entry and
 605         fixed spacing.
 606
 607 2012-07-02  Roland McGrath  <mcgrathr@google.com>
 608
 609         * i386-opc.tbl: Add RepPrefixOk to nop.
 610         * i386-tbl.h: Regenerate.
 611
 612 2012-06-28  Nick Clifton  <nickc@redhat.com>
 613
 614         * po/vi.po: Updated Vietnamese translation.
 615
 616 2012-06-22  Roland McGrath  <mcgrathr@google.com>
 617
 618         * i386-opc.tbl: Add RepPrefixOk to ret.
 619         * i386-tbl.h: Regenerate.
 620
 621         * i386-opc.h (RepPrefixOk): New enum constant.
 622         (i386_opcode_modifier): New bitfield 'repprefixok'.
 623         * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
 624         * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
 625         instructions that have IsString.
 626         * i386-tbl.h: Regenerate.
 627
 628 2012-06-11  Andreas Schwab  <schwab@linux-m68k.org>
 629
 630         * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
 631         (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
 632         (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
 633         (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
 634         (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
 635         (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
 636         (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
 637         (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
 638         (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
 639
 640 2012-05-19  Alan Modra  <amodra@gmail.com>
 641
 642         * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
 643         (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
 644
 645 2012-05-18  Alan Modra  <amodra@gmail.com>
 646
 647         * ia64-opc.c: Remove #include "ansidecl.h".
 648         * z8kgen.c: Include sysdep.h first.
 649
 650         * arc-dis.c: Include sysdep.h first, remove some redundant includes.
 651         * bfin-dis.c: Likewise.
 652         * i860-dis.c: Likewise.
 653         * ia64-dis.c: Likewise.
 654         * ia64-gen.c: Likewise.
 655         * m68hc11-dis.c: Likewise.
 656         * mmix-dis.c: Likewise.
 657         * msp430-dis.c: Likewise.
 658         * or32-dis.c: Likewise.
 659         * rl78-dis.c: Likewise.
 660         * rx-dis.c: Likewise.
 661         * tic4x-dis.c: Likewise.
 662         * tilegx-opc.c: Likewise.
 663         * tilepro-opc.c: Likewise.
 664         * rx-decode.c: Regenerate.
 665
 666 2012-05-17  James Lemke  <jwlemke@codesourcery.com>
 667
 668         * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
 669
 670 2012-05-17  James Lemke  <jwlemke@codesourcery.com>
 671
 672         * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
 673
 674 2012-05-17  Daniel Richard G.  <skunk@iskunk.org>
 675             Nick Clifton  <nickc@redhat.com>
 676
 677         PR 14072
 678         * configure.in: Add check that sysdep.h has been included before
 679         any system header files.
 680         * configure: Regenerate.
 681         * config.in: Regenerate.
 682         * sysdep.h: Generate an error if included before config.h.
 683         * alpha-opc.c: Include sysdep.h before any other header file.
 684         * alpha-dis.c: Likewise.
 685         * avr-dis.c: Likewise.
 686         * cgen-opc.c: Likewise.
 687         * cr16-dis.c: Likewise.
 688         * cris-dis.c: Likewise.
 689         * crx-dis.c: Likewise.
 690         * d10v-dis.c: Likewise.
 691         * d10v-opc.c: Likewise.
 692         * d30v-dis.c: Likewise.
 693         * d30v-opc.c: Likewise.
 694         * h8500-dis.c: Likewise.
 695         * i370-dis.c: Likewise.
 696         * i370-opc.c: Likewise.
 697         * m10200-dis.c: Likewise.
 698         * m10300-dis.c: Likewise.
 699         * micromips-opc.c: Likewise.
 700         * mips-opc.c: Likewise.
 701         * mips61-opc.c: Likewise.
 702         * moxie-dis.c: Likewise.
 703         * or32-opc.c: Likewise.
 704         * pj-dis.c: Likewise.
 705         * ppc-dis.c: Likewise.
 706         * ppc-opc.c: Likewise.
 707         * s390-dis.c: Likewise.
 708         * sh-dis.c: Likewise.
 709         * sh64-dis.c: Likewise.
 710         * sparc-dis.c: Likewise.
 711         * sparc-opc.c: Likewise.
 712         * spu-dis.c: Likewise.
 713         * tic30-dis.c: Likewise.
 714         * tic54x-dis.c: Likewise.
 715         * tic80-dis.c: Likewise.
 716         * tic80-opc.c: Likewise.
 717         * tilegx-dis.c: Likewise.
 718         * tilepro-dis.c: Likewise.
 719         * v850-dis.c: Likewise.
 720         * v850-opc.c: Likewise.
 721         * vax-dis.c: Likewise.
 722         * w65-dis.c: Likewise.
 723         * xgate-dis.c: Likewise.
 724         * xtensa-dis.c: Likewise.
 725         * rl78-decode.opc: Likewise.
 726         * rl78-decode.c: Regenerate.
 727         * rx-decode.opc: Likewise.
 728         * rx-decode.c: Regenerate.
 729
 730 2012-05-17  Alan Modra  <amodra@gmail.com>
 731
 732         * ppc_dis.c: Don't include elf/ppc.h.
 733
 734 2012-05-16  Meador Inge  <meadori@codesourcery.com>
 735
 736         * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
 737         to PUSH/POP {reg}.
 738
 739 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 740             Stephane Carrez <stcarrez@nerim.fr>
 741
 742         * configure.in: Add S12X and XGATE co-processor support to m68hc11
 743         target.
 744         * disassemble.c: Likewise.
 745         * configure: Regenerate.
 746         * m68hc11-dis.c: Make objdump output more consistent, use hex
 747         instead of decimal and use 0x prefix for hex.
 748         * m68hc11-opc.c: Add S12X and XGATE opcodes.
 749
 750 2012-05-14  James Lemke  <jwlemke@codesourcery.com>
 751
 752         * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
 753         (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
 754         (vle_opcd_indices): New array.
 755         (lookup_vle): New function.
 756         (disassemble_init_powerpc): Revise for second (VLE) opcode table.
 757         (print_insn_powerpc): Likewise.
 758         * ppc-opc.c: Likewise.
 759
 760 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 761             Maciej W. Rozycki  <macro@codesourcery.com>
 762             Rhonda Wittels  <rhonda@codesourcery.com>
 763             Nathan Froyd <froydnj@codesourcery.com>
 764
 765         * ppc-opc.c (insert_arx, extract_arx): New functions.
 766         (insert_ary, extract_ary): New functions.
 767         (insert_li20, extract_li20): New functions.
 768         (insert_rx, extract_rx): New functions.
 769         (insert_ry, extract_ry): New functions.
 770         (insert_sci8, extract_sci8): New functions.
 771         (insert_sci8n, extract_sci8n): New functions.
 772         (insert_sd4h, extract_sd4h): New functions.
 773         (insert_sd4w, extract_sd4w): New functions.
 774         (insert_vlesi, extract_vlesi): New functions.
 775         (insert_vlensi, extract_vlensi): New functions.
 776         (insert_vleui, extract_vleui): New functions.
 777         (insert_vleil, extract_vleil): New functions.
 778         (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
 779         (BI16, BI32, BO32, B8): New.
 780         (B15, B24, CRD32, CRS): New.
 781         (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
 782         (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
 783         (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
 784         (SH6_MASK): Use PPC_OPSHIFT_INV.
 785         (SI8, UI5, OIMM5, UI7, BO16): New.
 786         (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
 787         (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
 788         (ALLOW8_SPRG): New.
 789         (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
 790         (OPVUP, OPVUP_MASK OPVUP): New
 791         (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
 792         (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
 793         (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
 794         (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
 795         (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
 796         (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
 797         (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
 798         (SE_IM5, SE_IM5_MASK): New.
 799         (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
 800         (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
 801         (BO32DNZ, BO32DZ): New.
 802         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
 803         (PPCVLE): New.
 804         (powerpc_opcodes): Add new VLE instructions.  Update existing
 805         instruction to include PPCVLE if supported.
 806         * ppc-dis.c (ppc_opts): Add vle entry.
 807         (get_powerpc_dialect): New function.
 808         (powerpc_init_dialect): VLE support.
 809         (print_insn_big_powerpc): Call get_powerpc_dialect.
 810         (print_insn_little_powerpc): Likewise.
 811         (operand_value_powerpc): Handle negative shift counts.
 812         (print_insn_powerpc): Handle 2-byte instruction lengths.
 813
 814 2012-05-11  Daniel Richard G.  <skunk@iskunk.org>
 815
 816         PR binutils/14028
 817         * configure.in: Invoke ACX_HEADER_STRING.
 818         * configure: Regenerate.
 819         * config.in: Regenerate.
 820         * sysdep.h: If STRINGS_WITH_STRING is defined then include both
 821         string.h and strings.h.
 822
 823 2012-05-11  Nick Clifton  <nickc@redhat.com>
 824
 825         PR binutils/14006
 826         * arm-dis.c (print_insn): Fix detection of instruction mode in
 827         files containing multiple executable sections.
 828
 829 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 830
 831         * Makefile.in, configure: regenerate
 832         * disassemble.c (disassembler): Recognize ARCH_XGATE.
 833         * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
 834         New functions.
 835         * configure.in: Recognize xgate.
 836         * xgate-dis.c, xgate-opc.c: New files for support of xgate
 837         * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
 838         and opcode generation for xgate.
 839
 840 2012-04-30  DJ Delorie  <dj@redhat.com>
 841
 842         * rx-decode.opc (MOV): Do not sign-extend immediates which are
 843         already the maximum bit size.
 844         * rx-decode.c: Regenerate.
 845
 846 2012-04-27  David S. Miller  <davem@davemloft.net>
 847
 848         * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
 849         * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
 850
 851         * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
 852         * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
 853
 854         * sparc-opc.c (CBCOND): New define.
 855         (CBCOND_XCC): Likewise.
 856         (cbcond): New helper macro.
 857         (sparc_opcodes): Add compare-and-branch instructions.
 858
 859         * sparc-dis.c (print_insn_sparc): Handle ')'.
 860         * sparc-opc.c (sparc_opcodes): Add crypto instructions.
 861
 862         * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
 863         into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
 864
 865 2012-04-12  David S. Miller  <davem@davemloft.net>
 866
 867         * sparc-dis.c (X_DISP10): Define.
 868         (print_insn_sparc): Handle '='.
 869
 870 2012-04-01  Mike Frysinger  <vapier@gentoo.org>
 871
 872         * bfin-dis.c (fmtconst): Replace decimal handling with a single
 873         sprintf call and the '*' field width.
 874
 875 2012-03-23  Maxim Kuvyrkov  <maxim@codesourcery.com>
 876
 877         * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
 878
 879 2012-03-16  Alan Modra  <amodra@gmail.com>
 880
 881         * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
 882         (powerpc_opcd_indices): Bump array size.
 883         (disassemble_init_powerpc): Set powerpc_opcd_indices entries
 884         corresponding to unused opcodes to following entry.
 885         (lookup_powerpc): New function, extracted and optimised from..
 886         (print_insn_powerpc): ..here.
 887
 888 2012-03-15  Alan Modra  <amodra@gmail.com>
 889             James Lemke  <jwlemke@codesourcery.com>
 890
 891         * disassemble.c (disassemble_init_for_target): Handle ppc init.
 892         * ppc-dis.c (private): New var.
 893         (powerpc_init_dialect): Don't return calloc failure, instead use
 894         private.
 895         (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
 896         (powerpc_opcd_indices): New array.
 897         (disassemble_init_powerpc): New function.
 898         (print_insn_big_powerpc): Don't init dialect here.
 899         (print_insn_little_powerpc): Likewise.
 900         (print_insn_powerpc): Start search using powerpc_opcd_indices.
 901
 902 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 903
 904         * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
 905         * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
 906         (PPCVEC2, PPCTMR, E6500): New short names.
 907         (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
 908         mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
 909         lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
 910         lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
 911         lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
 912         optional operands on sync instruction for E6500 target.
 913
 914 2012-03-08  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 915
 916         * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
 917
 918 2012-02-27  Alan Modra  <amodra@gmail.com>
 919
 920         * mt-dis.c: Regenerate.
 921
 922 2012-02-27  Alan Modra  <amodra@gmail.com>
 923
 924         * v850-opc.c (extract_v8): Rearrange to make it obvious this
 925         is the inverse of corresponding insert function.
 926         (extract_d22, extract_u9, extract_r4): Likewise.
 927         (extract_d9): Correct sign extension.
 928         (extract_d16_15): Don't assume "long" is 32 bits, and don't
 929         rely on implementation defined behaviour for shift right of
 930         signed types.
 931         (extract_d16_16, extract_d17_16, extract_i9): Likewise.
 932         (extract_d23): Likewise, and correct mask.
 933
 934 2012-02-27  Alan Modra  <amodra@gmail.com>
 935
 936         * crx-dis.c (print_arg): Mask constant to 32 bits.
 937         * crx-opc.c (cst4_map): Use int array.
 938
 939 2012-02-27  Alan Modra  <amodra@gmail.com>
 940
 941         * arc-dis.c (BITS): Don't use shifts to mask off bits.
 942         (FIELDD): Sign extend with xor,sub.
 943
 944 2012-02-25  Walter Lee  <walt@tilera.com>
 945
 946         * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
 947         * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
 948         TILEPRO_OPC_LW_TLS_SN.
 949
 950 2012-02-21  H.J. Lu  <hongjiu.lu@intel.com>
 951
 952         * i386-opc.h (HLEPrefixNone): New.
 953         (HLEPrefixLock): Likewise.
 954         (HLEPrefixAny): Likewise.
 955         (HLEPrefixRelease): Likewise.
 956
 957 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 958
 959         * i386-dis.c (HLE_Fixup1): New.
 960         (HLE_Fixup2): Likewise.
 961         (HLE_Fixup3): Likewise.
 962         (Ebh1): Likewise.
 963         (Evh1): Likewise.
 964         (Ebh2): Likewise.
 965         (Evh2): Likewise.
 966         (Ebh3): Likewise.
 967         (Evh3): Likewise.
 968         (MOD_C6_REG_7): Likewise.
 969         (MOD_C7_REG_7): Likewise.
 970         (RM_C6_REG_7): Likewise.
 971         (RM_C7_REG_7): Likewise.
 972         (XACQUIRE_PREFIX): Likewise.
 973         (XRELEASE_PREFIX): Likewise.
 974         (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
 975         cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
 976         Ebh2/Evh2 on xchg.  Use Ebh3/Evh3 on mov.
 977         (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
 978         not, or, sbb, sub and xor.  Use Ebh3/Evh3 on mov.  Use
 979         MOD_C6_REG_7 and MOD_C7_REG_7.
 980         (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
 981         (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7.  Add xend and
 982         xtest.
 983         (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
 984         (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
 985
 986         * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
 987         CPU_RTM_FLAGS.
 988         (cpu_flags): Add CpuHLE and CpuRTM.
 989         (opcode_modifiers): Add HLEPrefixOk.
 990
 991         * i386-opc.h (CpuHLE): New.
 992         (CpuRTM): Likewise.
 993         (HLEPrefixOk): Likewise.
 994         (i386_cpu_flags): Add cpuhle and cpurtm.
 995         (i386_opcode_modifier): Add hleprefixok.
 996
 997         * i386-opc.tbl: Add HLEPrefixOk=3 to mov.  Add HLEPrefixOk to
 998         add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
 999         sbb, sub, xor and xadd.  Add HLEPrefixOk=2 to xchg with memory
1000         operand.  Add xacquire, xrelease, xabort, xbegin, xend and
1001         xtest.
1002         * i386-init.h: Regenerated.
1003         * i386-tbl.h: Likewise.
1004
1005 2012-01-24  DJ Delorie  <dj@redhat.com>
1006
1007         * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
1008         * rl78-decode.c: Regenerate.
1009
1010 2012-01-17  James Murray  <jsm@jsm-net.demon.co.uk>
1011
1012         PR binutils/10173
1013         * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
1014
1015 2012-01-17  Andreas Schwab  <schwab@linux-m68k.org>
1016
1017         * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
1018         register and move them after pmove with PSR/PCSR register.
1019
1020 2012-01-13  H.J. Lu  <hongjiu.lu@intel.com>
1021
1022         * i386-dis.c (mod_table): Add vmfunc.
1023
1024         * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
1025         (cpu_flags): CpuVMFUNC.
1026
1027         * i386-opc.h (CpuVMFUNC): New.
1028         (i386_cpu_flags): Add cpuvmfunc.
1029
1030         * i386-opc.tbl: Add vmfunc.
1031         * i386-init.h: Regenerated.
1032         * i386-tbl.h: Likewise.
1033
1034 For older changes see ChangeLog-2011
1035 \f
1036 Copyright (C) 2012 Free Software Foundation, Inc.
1037
1038 Copying and distribution of this file, with or without modification,
1039 are permitted in any medium without royalty provided the copyright
1040 notice and this notice are preserved.
1041
1042 Local Variables:
1043 mode: change-log
1044 left-margin: 8
1045 fill-column: 74
1046 version-control: never
1047 End: