opcodes/ChangeLog

   1 2019-09-23  Alan Modra  <amodra@gmail.com>
   2
   3         * m68k-dis.c: Include cpu-m68k.h
   4
   5 2019-09-23  Alan Modra  <amodra@gmail.com>
   6
   7         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
   8         "elf/mips.h" earlier.
   9
  10 2018-09-20  Jan Beulich  <jbeulich@suse.com>
  11
  12         PR gas/25012
  13         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
  14         with SReg operand.
  15         * i386-tbl.h: Re-generate.
  16
  17 2019-09-18  Alan Modra  <amodra@gmail.com>
  18
  19         * arc-ext.c: Update throughout for bfd section macro changes.
  20
  21 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
  22
  23         * Makefile.in: Re-generate.
  24         * configure: Re-generate.
  25
  26 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
  27
  28         * riscv-opc.c (riscv_opcodes): Change subset field
  29         to insn_class field for all instructions.
  30         (riscv_insn_types): Likewise.
  31
  32 2019-09-16  Phil Blundell  <pb@pbcl.net>
  33
  34         * configure: Regenerated.
  35
  36 2019-09-10  Miod Vallat  <miod@online.fr>
  37
  38         PR 24982
  39         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
  40
  41 2019-09-09  Phil Blundell  <pb@pbcl.net>
  42
  43         binutils 2.33 branch created.
  44
  45 2019-09-03  Nick Clifton  <nickc@redhat.com>
  46
  47         PR 24961
  48         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
  49         greater than zero before indexing via (bufcnt -1).
  50
  51 2019-09-03  Nick Clifton  <nickc@redhat.com>
  52
  53         PR 24958
  54         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
  55         (MAX_SPEC_REG_NAME_LEN): Define.
  56         (struct mmix_dis_info): Use defined constants for array lengths.
  57         (get_reg_name): New function.
  58         (get_sprec_reg_name): New function.
  59         (print_insn_mmix): Use new functions.
  60
  61 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  62
  63         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
  64         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
  65         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
  66
  67 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
  68
  69         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
  70         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
  71         (aarch64_sys_reg_supported_p): Update checks for the above.
  72
  73 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  74
  75         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
  76         cases MVE_SQRSHRL and MVE_UQRSHLL.
  77         (print_insn_mve): Add case for specifier 'k' to check
  78         specific bit of the instruction.
  79
  80 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
  81
  82         PR 24854
  83         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
  84         encountering an unknown machine type.
  85         (print_insn_arc): Handle arc_insn_length returning 0.  In error
  86         cases return -1 rather than calling abort.
  87
  88 2019-08-07  Jan Beulich  <jbeulich@suse.com>
  89
  90         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
  91         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
  92         IgnoreSize.
  93         * i386-tbl.h: Re-generate.
  94
  95 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
  96
  97         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
  98         instructions.
  99
 100 2019-07-30  Mel Chen <mel.chen@sifive.com>
 101
 102         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 103         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 104
 105         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 106         fscsr.
 107
 108 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 109
 110         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 111         and MPY class instructions.
 112         (parse_option): Add nps400 option.
 113         (print_arc_disassembler_options): Add nps400 info.
 114
 115 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 116
 117         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 118         (bspop): Likewise.
 119         (modapp): Likewise.
 120         * arc-opc.c (RAD_CHK): Add.
 121         * arc-tbl.h: Regenerate.
 122
 123 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 124
 125         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 126         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 127
 128 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 129
 130         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 131         instructions as UNPREDICTABLE.
 132
 133 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 134
 135         * bpf-desc.c: Regenerated.
 136
 137 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-gen.c (static_assert): Define.
 140         (main): Use it.
 141         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 142         (Opcode_Modifier_Num): ... this.
 143         (Mem): Delete.
 144
 145 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 146
 147         * i386-gen.c (operand_types): Move RegMem ...
 148         (opcode_modifiers): ... here.
 149         * i386-opc.h (RegMem): Move to opcode modifer enum.
 150         (union i386_operand_type): Move regmem field ...
 151         (struct i386_opcode_modifier): ... here.
 152         * i386-opc.tbl (RegMem): Define.
 153         (mov, movq): Move RegMem on segment, control, debug, and test
 154         register flavors.
 155         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 156         to non-SSE2AVX flavor.
 157         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 158         Move RegMem on register only flavors. Drop IgnoreSize from
 159         legacy encoding flavors.
 160         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 161         flavors.
 162         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 163         register only flavors.
 164         (vmovd): Move RegMem and drop IgnoreSize on register only
 165         flavor. Change opcode and operand order to store form.
 166         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 167
 168 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 171         entries.
 172         * i386-opc.h (SReg2, SReg3): Replace by ...
 173         (SReg): ... this.
 174         (union i386_operand_type): Replace sreg fields.
 175         * i386-opc.tbl (mov, ): Use SReg.
 176         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 177         register flavors.
 178         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 179         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 180
 181 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 182
 183         * bpf-desc.c: Regenerate.
 184         * bpf-opc.c: Likewise.
 185         * bpf-opc.h: Likewise.
 186
 187 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 188
 189         * bpf-desc.c: Regenerate.
 190         * bpf-opc.c: Likewise.
 191
 192 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 193
 194         * arm-dis.c (print_insn_coprocessor): Rename index to
 195         index_operand.
 196
 197 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 198
 199         * riscv-opc.c (riscv_insn_types): Add r4 type.
 200
 201         * riscv-opc.c (riscv_insn_types): Add b and j type.
 202
 203         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 204         format for sb type and correct s type.
 205
 206 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 207
 208         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 209         SVE FMOV alias of FCPY.
 210
 211 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 212
 213         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 214         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 215
 216 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 217
 218         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 219         registers in an instruction prefixed by MOVPRFX.
 220
 221 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 222
 223         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 224         sve_size_13 icode to account for variant behaviour of
 225         pmull{t,b}.
 226         * aarch64-dis-2.c: Regenerate.
 227         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 228         sve_size_13 icode to account for variant behaviour of
 229         pmull{t,b}.
 230         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 231         (OP_SVE_VVV_Q_D): Add new qualifier.
 232         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 233         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 234         AES and those not.
 235
 236 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 237
 238         * opcodes/i386-gen.c (operand_type_init): Remove
 239         OPERAND_TYPE_VEC_IMM4 entry.
 240         (operand_types): Remove Vec_Imm4.
 241         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 242         (union i386_operand_type): Remove vec_imm4.
 243         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 244         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 245
 246 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 249         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 250         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 251         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 252         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 253         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 254         * i386-tbl.h: Re-generate.
 255
 256 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 259         register operands.
 260         * i386-tbl.h: Re-generate.
 261
 262 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 263
 264         * i386-opc.tbl (C): New.
 265         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 266         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 267         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 268         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 269         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 270         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 271         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 272         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 273         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 274         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 275         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 276         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 277         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 278         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 279         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 280         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 281         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 282         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 283         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 284         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 285         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 286         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 287         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 288         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 289         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 290         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 291         flavors.
 292         * i386-tbl.h: Re-generate.
 293
 294 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 295
 296         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 297         register operands.
 298         * i386-tbl.h: Re-generate.
 299
 300 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 301
 302         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 303         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 304         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 305         * i386-tbl.h: Re-generate.
 306
 307 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 310         Disp8MemShift from register only templates.
 311         * i386-tbl.h: Re-generate.
 312
 313 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 314
 315         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 316         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 317         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 318         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 319         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 320         EVEX_W_0F11_P_3_M_1): Delete.
 321         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 322         EVEX_W_0F11_P_3): New.
 323         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 324         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 325         MOD_EVEX_0F11_PREFIX_3 table entries.
 326         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 327         PREFIX_EVEX_0F11 table entries.
 328         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 329         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 330         EVEX_W_0F11_P_3_M_{0,1} table entries.
 331
 332 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 333
 334         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 335         Delete.
 336
 337 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 338
 339         PR binutils/24719
 340         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 341         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 342         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 343         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 344         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 345         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 346         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 347         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 348         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 349         PREFIX_EVEX_0F38C6_REG_6 entries.
 350         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 351         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 352         EVEX_W_0F38C7_R_6_P_2 entries.
 353         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 354         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 355         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 356         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 357         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 358         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 359         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 360
 361 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 362
 363         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 364         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 365         VEX_LEN_0F2D_P_3): Delete.
 366         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 367         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 368         (prefix_table): ... here.
 369
 370 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 371
 372         * i386-dis.c (Iq): Delete.
 373         (Id): New.
 374         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 375         TBM insns.
 376         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 377         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 378         (OP_E_memory): Also honor needindex when deciding whether an
 379         address size prefix needs printing.
 380         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 381
 382 2019-06-26  Jim Wilson  <jimw@sifive.com>
 383
 384         PR binutils/24739
 385         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 386         Set info->display_endian to info->endian_code.
 387
 388 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 389
 390         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 391         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 392         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 393         OPERAND_TYPE_ACC64 entries.
 394         * i386-init.h: Re-generate.
 395
 396 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 397
 398         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 399         Delete.
 400         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 401         of dqa_mode.
 402         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 403         entries here.
 404         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 405         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 406
 407 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 410         variables.
 411
 412 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 413
 414         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 415         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 416         movnti.
 417         * i386-opc.tbl (movnti): Add IgnoreSize.
 418         * i386-tbl.h: Re-generate.
 419
 420 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 421
 422         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 423         * i386-tbl.h: Re-generate.
 424
 425 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 426
 427         * i386-dis-evex.h: Break into ...
 428         * i386-dis-evex-len.h: New file.
 429         * i386-dis-evex-mod.h: Likewise.
 430         * i386-dis-evex-prefix.h: Likewise.
 431         * i386-dis-evex-reg.h: Likewise.
 432         * i386-dis-evex-w.h: Likewise.
 433         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 434         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 435         i386-dis-evex-mod.h.
 436
 437 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         PR binutils/24700
 440         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 441         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 442         EVEX_W_0F385B_P_2.
 443         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 444         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 445         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 446         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 447         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 448         EVEX_LEN_0F385B_P_2_W_1.
 449         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 450         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 451         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 452         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 453         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 454         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 455         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 456         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 457         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 458         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 459
 460 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 461
 462         PR binutils/24691
 463         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 464         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 465         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 466         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 467         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 468         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 469         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 470         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 471         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 472         EVEX_LEN_0F3A43_P_2_W_1.
 473         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 474         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 475         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 476         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 477         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 478         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 479         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 480         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 481         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 482         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 483         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 484         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 485
 486 2019-06-14  Nick Clifton  <nickc@redhat.com>
 487
 488         * po/fr.po; Updated French translation.
 489
 490 2019-06-13  Stafford Horne  <shorne@gmail.com>
 491
 492         * or1k-asm.c: Regenerated.
 493         * or1k-desc.c: Regenerated.
 494         * or1k-desc.h: Regenerated.
 495         * or1k-dis.c: Regenerated.
 496         * or1k-ibld.c: Regenerated.
 497         * or1k-opc.c: Regenerated.
 498         * or1k-opc.h: Regenerated.
 499         * or1k-opinst.c: Regenerated.
 500
 501 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 502
 503         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 504
 505 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 506
 507         PR binutils/24633
 508         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 509         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 510         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 511         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 512         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 513         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 514         EVEX_LEN_0F3A1B_P_2_W_1.
 515         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 516         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 517         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 518         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 519         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 520         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 521         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 522         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 523
 524 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 525
 526         PR binutils/24626
 527         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 528         EVEX.vvvv when disassembling VEX and EVEX instructions.
 529         (OP_VEX): Set vex.register_specifier to 0 after readding
 530         vex.register_specifier.
 531         (OP_Vex_2src_1): Likewise.
 532         (OP_Vex_2src_2): Likewise.
 533         (OP_LWP_E): Likewise.
 534         (OP_EX_Vex): Don't check vex.register_specifier.
 535         (OP_XMM_Vex): Likewise.
 536
 537 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 538             Lili Cui  <lili.cui@intel.com>
 539
 540         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 541         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 542         instructions.
 543         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 544         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 545         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 546         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 547         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 548         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 549         * i386-init.h: Regenerated.
 550         * i386-tbl.h: Likewise.
 551
 552 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 553             Lili Cui  <lili.cui@intel.com>
 554
 555         * doc/c-i386.texi: Document enqcmd.
 556         * testsuite/gas/i386/enqcmd-intel.d: New file.
 557         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 558         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 559         * testsuite/gas/i386/enqcmd.d: Likewise.
 560         * testsuite/gas/i386/enqcmd.s: Likewise.
 561         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 562         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 563         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 564         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 565         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 566         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 567         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 568         and x86-64-enqcmd.
 569
 570 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 571
 572         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 573
 574 2019-06-03  Alan Modra  <amodra@gmail.com>
 575
 576         * ppc-dis.c (prefix_opcd_indices): Correct size.
 577
 578 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 579
 580         PR gas/24625
 581         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 582         Disp8ShiftVL.
 583         * i386-tbl.h: Regenerated.
 584
 585 2019-05-24  Alan Modra  <amodra@gmail.com>
 586
 587         * po/POTFILES.in: Regenerate.
 588
 589 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 590             Alan Modra  <amodra@gmail.com>
 591
 592         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 593         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 594         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 595         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 596         XTOP>): Define and add entries.
 597         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 598         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 599         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 600         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 601
 602 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 603             Alan Modra  <amodra@gmail.com>
 604
 605         * ppc-dis.c (ppc_opts): Add "future" entry.
 606         (PREFIX_OPCD_SEGS): Define.
 607         (prefix_opcd_indices): New array.
 608         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 609         (lookup_prefix): New function.
 610         (print_insn_powerpc): Handle 64-bit prefix instructions.
 611         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 612         (PMRR, POWERXX): Define.
 613         (prefix_opcodes): New instruction table.
 614         (prefix_num_opcodes): New constant.
 615
 616 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 617
 618         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 619         * configure: Regenerated.
 620         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 621         and cpu/bpf.opc.
 622         (HFILES): Add bpf-desc.h and bpf-opc.h.
 623         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 624         bpf-ibld.c and bpf-opc.c.
 625         (BPF_DEPS): Define.
 626         * Makefile.in: Regenerated.
 627         * disassemble.c (ARCH_bpf): Define.
 628         (disassembler): Add case for bfd_arch_bpf.
 629         (disassemble_init_for_target): Likewise.
 630         (enum epbf_isa_attr): Define.
 631         * disassemble.h: extern print_insn_bpf.
 632         * bpf-asm.c: Generated.
 633         * bpf-opc.h: Likewise.
 634         * bpf-opc.c: Likewise.
 635         * bpf-ibld.c: Likewise.
 636         * bpf-dis.c: Likewise.
 637         * bpf-desc.h: Likewise.
 638         * bpf-desc.c: Likewise.
 639
 640 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 641
 642         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 643         and VMSR with the new operands.
 644
 645 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 646
 647         * arm-dis.c (enum mve_instructions): New enum
 648         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 649         and cneg.
 650         (mve_opcodes): New instructions as above.
 651         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 652         csneg and csel.
 653         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 654
 655 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 656
 657         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 658         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 659         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 660         uqshl, urshrl and urshr.
 661         (is_mve_okay_in_it): Add new instructions to TRUE list.
 662         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 663         (print_insn_mve): Updated to accept new %j,
 664         %<bitfield>m and %<bitfield>n patterns.
 665
 666 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 667
 668         * mips-opc.c (mips_builtin_opcodes): Change source register
 669         constraint for DAUI.
 670
 671 2019-05-20  Nick Clifton  <nickc@redhat.com>
 672
 673         * po/fr.po: Updated French translation.
 674
 675 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 676             Michael Collison <michael.collison@arm.com>
 677
 678         * arm-dis.c (thumb32_opcodes): Add new instructions.
 679         (enum mve_instructions): Likewise.
 680         (enum mve_undefined): Add new reasons.
 681         (is_mve_encoding_conflict): Handle new instructions.
 682         (is_mve_undefined): Likewise.
 683         (is_mve_unpredictable): Likewise.
 684         (print_mve_undefined): Likewise.
 685         (print_mve_size): Likewise.
 686
 687 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 688             Michael Collison <michael.collison@arm.com>
 689
 690         * arm-dis.c (thumb32_opcodes): Add new instructions.
 691         (enum mve_instructions): Likewise.
 692         (is_mve_encoding_conflict): Handle new instructions.
 693         (is_mve_undefined): Likewise.
 694         (is_mve_unpredictable): Likewise.
 695         (print_mve_size): Likewise.
 696
 697 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 698             Michael Collison <michael.collison@arm.com>
 699
 700         * arm-dis.c (thumb32_opcodes): Add new instructions.
 701         (enum mve_instructions): Likewise.
 702         (is_mve_encoding_conflict): Likewise.
 703         (is_mve_unpredictable): Likewise.
 704         (print_mve_size): Likewise.
 705
 706 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 707             Michael Collison <michael.collison@arm.com>
 708
 709         * arm-dis.c (thumb32_opcodes): Add new instructions.
 710         (enum mve_instructions): Likewise.
 711         (is_mve_encoding_conflict): Handle new instructions.
 712         (is_mve_undefined): Likewise.
 713         (is_mve_unpredictable): Likewise.
 714         (print_mve_size): Likewise.
 715
 716 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 717             Michael Collison <michael.collison@arm.com>
 718
 719         * arm-dis.c (thumb32_opcodes): Add new instructions.
 720         (enum mve_instructions): Likewise.
 721         (is_mve_encoding_conflict): Handle new instructions.
 722         (is_mve_undefined): Likewise.
 723         (is_mve_unpredictable): Likewise.
 724         (print_mve_size): Likewise.
 725         (print_insn_mve): Likewise.
 726
 727 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 728             Michael Collison <michael.collison@arm.com>
 729
 730         * arm-dis.c (thumb32_opcodes): Add new instructions.
 731         (print_insn_thumb32): Handle new instructions.
 732
 733 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 734             Michael Collison <michael.collison@arm.com>
 735
 736         * arm-dis.c (enum mve_instructions): Add new instructions.
 737         (enum mve_undefined): Add new reasons.
 738         (is_mve_encoding_conflict): Handle new instructions.
 739         (is_mve_undefined): Likewise.
 740         (is_mve_unpredictable): Likewise.
 741         (print_mve_undefined): Likewise.
 742         (print_mve_size): Likewise.
 743         (print_mve_shift_n): Likewise.
 744         (print_insn_mve): Likewise.
 745
 746 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 747             Michael Collison <michael.collison@arm.com>
 748
 749         * arm-dis.c (enum mve_instructions): Add new instructions.
 750         (is_mve_encoding_conflict): Handle new instructions.
 751         (is_mve_unpredictable): Likewise.
 752         (print_mve_rotate): Likewise.
 753         (print_mve_size): Likewise.
 754         (print_insn_mve): Likewise.
 755
 756 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 757             Michael Collison <michael.collison@arm.com>
 758
 759         * arm-dis.c (enum mve_instructions): Add new instructions.
 760         (is_mve_encoding_conflict): Handle new instructions.
 761         (is_mve_unpredictable): Likewise.
 762         (print_mve_size): Likewise.
 763         (print_insn_mve): Likewise.
 764
 765 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 766             Michael Collison <michael.collison@arm.com>
 767
 768         * arm-dis.c (enum mve_instructions): Add new instructions.
 769         (enum mve_undefined): Add new reasons.
 770         (is_mve_encoding_conflict): Handle new instructions.
 771         (is_mve_undefined): Likewise.
 772         (is_mve_unpredictable): Likewise.
 773         (print_mve_undefined): Likewise.
 774         (print_mve_size): Likewise.
 775         (print_insn_mve): Likewise.
 776
 777 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 778             Michael Collison <michael.collison@arm.com>
 779
 780         * arm-dis.c (enum mve_instructions): Add new instructions.
 781         (is_mve_encoding_conflict): Handle new instructions.
 782         (is_mve_undefined): Likewise.
 783         (is_mve_unpredictable): Likewise.
 784         (print_mve_size): Likewise.
 785         (print_insn_mve): Likewise.
 786
 787 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 788             Michael Collison <michael.collison@arm.com>
 789
 790         * arm-dis.c (enum mve_instructions): Add new instructions.
 791         (enum mve_unpredictable): Add new reasons.
 792         (enum mve_undefined): Likewise.
 793         (is_mve_okay_in_it): Handle new isntructions.
 794         (is_mve_encoding_conflict): Likewise.
 795         (is_mve_undefined): Likewise.
 796         (is_mve_unpredictable): Likewise.
 797         (print_mve_vmov_index): Likewise.
 798         (print_simd_imm8): Likewise.
 799         (print_mve_undefined): Likewise.
 800         (print_mve_unpredictable): Likewise.
 801         (print_mve_size): Likewise.
 802         (print_insn_mve): Likewise.
 803
 804 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 805             Michael Collison <michael.collison@arm.com>
 806
 807         * arm-dis.c (enum mve_instructions): Add new instructions.
 808         (enum mve_unpredictable): Add new reasons.
 809         (enum mve_undefined): Likewise.
 810         (is_mve_encoding_conflict): Handle new instructions.
 811         (is_mve_undefined): Likewise.
 812         (is_mve_unpredictable): Likewise.
 813         (print_mve_undefined): Likewise.
 814         (print_mve_unpredictable): Likewise.
 815         (print_mve_rounding_mode): Likewise.
 816         (print_mve_vcvt_size): Likewise.
 817         (print_mve_size): Likewise.
 818         (print_insn_mve): Likewise.
 819
 820 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 821             Michael Collison <michael.collison@arm.com>
 822
 823         * arm-dis.c (enum mve_instructions): Add new instructions.
 824         (enum mve_unpredictable): Add new reasons.
 825         (enum mve_undefined): Likewise.
 826         (is_mve_undefined): Handle new instructions.
 827         (is_mve_unpredictable): Likewise.
 828         (print_mve_undefined): Likewise.
 829         (print_mve_unpredictable): Likewise.
 830         (print_mve_size): Likewise.
 831         (print_insn_mve): Likewise.
 832
 833 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 834             Michael Collison <michael.collison@arm.com>
 835
 836         * arm-dis.c (enum mve_instructions): Add new instructions.
 837         (enum mve_undefined): Add new reasons.
 838         (insns): Add new instructions.
 839         (is_mve_encoding_conflict):
 840         (print_mve_vld_str_addr): New print function.
 841         (is_mve_undefined): Handle new instructions.
 842         (is_mve_unpredictable): Likewise.
 843         (print_mve_undefined): Likewise.
 844         (print_mve_size): Likewise.
 845         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 846         (print_insn_mve):  Handle new operands.
 847
 848 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 849             Michael Collison <michael.collison@arm.com>
 850
 851         * arm-dis.c (enum mve_instructions): Add new instructions.
 852         (enum mve_unpredictable): Add new reasons.
 853         (is_mve_encoding_conflict): Handle new instructions.
 854         (is_mve_unpredictable): Likewise.
 855         (mve_opcodes): Add new instructions.
 856         (print_mve_unpredictable): Handle new reasons.
 857         (print_mve_register_blocks): New print function.
 858         (print_mve_size): Handle new instructions.
 859         (print_insn_mve): Likewise.
 860
 861 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 862             Michael Collison <michael.collison@arm.com>
 863
 864         * arm-dis.c (enum mve_instructions): Add new instructions.
 865         (enum mve_unpredictable): Add new reasons.
 866         (enum mve_undefined): Likewise.
 867         (is_mve_encoding_conflict): Handle new instructions.
 868         (is_mve_undefined): Likewise.
 869         (is_mve_unpredictable): Likewise.
 870         (coprocessor_opcodes): Move NEON VDUP from here...
 871         (neon_opcodes): ... to here.
 872         (mve_opcodes): Add new instructions.
 873         (print_mve_undefined):  Handle new reasons.
 874         (print_mve_unpredictable): Likewise.
 875         (print_mve_size): Handle new instructions.
 876         (print_insn_neon): Handle vdup.
 877         (print_insn_mve): Handle new operands.
 878
 879 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 880             Michael Collison <michael.collison@arm.com>
 881
 882         * arm-dis.c (enum mve_instructions): Add new instructions.
 883         (enum mve_unpredictable): Add new values.
 884         (mve_opcodes): Add new instructions.
 885         (vec_condnames): New array with vector conditions.
 886         (mve_predicatenames): New array with predicate suffixes.
 887         (mve_vec_sizename): New array with vector sizes.
 888         (enum vpt_pred_state): New enum with vector predication states.
 889         (struct vpt_block): New struct type for vpt blocks.
 890         (vpt_block_state): Global struct to keep track of state.
 891         (mve_extract_pred_mask): New helper function.
 892         (num_instructions_vpt_block): Likewise.
 893         (mark_outside_vpt_block): Likewise.
 894         (mark_inside_vpt_block): Likewise.
 895         (invert_next_predicate_state): Likewise.
 896         (update_next_predicate_state): Likewise.
 897         (update_vpt_block_state): Likewise.
 898         (is_vpt_instruction): Likewise.
 899         (is_mve_encoding_conflict): Add entries for new instructions.
 900         (is_mve_unpredictable): Likewise.
 901         (print_mve_unpredictable): Handle new cases.
 902         (print_instruction_predicate): Likewise.
 903         (print_mve_size): New function.
 904         (print_vec_condition): New function.
 905         (print_insn_mve): Handle vpt blocks and new print operands.
 906
 907 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 908
 909         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 910         8, 14 and 15 for Armv8.1-M Mainline.
 911
 912 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 913             Michael Collison <michael.collison@arm.com>
 914
 915         * arm-dis.c (enum mve_instructions): New enum.
 916         (enum mve_unpredictable): Likewise.
 917         (enum mve_undefined): Likewise.
 918         (struct mopcode32): New struct.
 919         (is_mve_okay_in_it): New function.
 920         (is_mve_architecture): Likewise.
 921         (arm_decode_field): Likewise.
 922         (arm_decode_field_multiple): Likewise.
 923         (is_mve_encoding_conflict): Likewise.
 924         (is_mve_undefined): Likewise.
 925         (is_mve_unpredictable): Likewise.
 926         (print_mve_undefined): Likewise.
 927         (print_mve_unpredictable): Likewise.
 928         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 929         (print_insn_mve): New function.
 930         (print_insn_thumb32): Handle MVE architecture.
 931         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 932
 933 2019-05-10  Nick Clifton  <nickc@redhat.com>
 934
 935         PR 24538
 936         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 937         end of the table prematurely.
 938
 939 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 940
 941         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 942         macros for R6.
 943
 944 2019-05-11  Alan Modra  <amodra@gmail.com>
 945
 946         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 947         when -Mraw is in effect.
 948
 949 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 950
 951         * aarch64-dis-2.c: Regenerate.
 952         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 953         (OP_SVE_BBB): New variant set.
 954         (OP_SVE_DDDD): New variant set.
 955         (OP_SVE_HHH): New variant set.
 956         (OP_SVE_HHHU): New variant set.
 957         (OP_SVE_SSS): New variant set.
 958         (OP_SVE_SSSU): New variant set.
 959         (OP_SVE_SHH): New variant set.
 960         (OP_SVE_SBBU): New variant set.
 961         (OP_SVE_DSS): New variant set.
 962         (OP_SVE_DHHU): New variant set.
 963         (OP_SVE_VMV_HSD_BHS): New variant set.
 964         (OP_SVE_VVU_HSD_BHS): New variant set.
 965         (OP_SVE_VVVU_SD_BH): New variant set.
 966         (OP_SVE_VVVU_BHSD): New variant set.
 967         (OP_SVE_VVV_QHD_DBS): New variant set.
 968         (OP_SVE_VVV_HSD_BHS): New variant set.
 969         (OP_SVE_VVV_HSD_BHS2): New variant set.
 970         (OP_SVE_VVV_BHS_HSD): New variant set.
 971         (OP_SVE_VV_BHS_HSD): New variant set.
 972         (OP_SVE_VVV_SD): New variant set.
 973         (OP_SVE_VVU_BHS_HSD): New variant set.
 974         (OP_SVE_VZVV_SD): New variant set.
 975         (OP_SVE_VZVV_BH): New variant set.
 976         (OP_SVE_VZV_SD): New variant set.
 977         (aarch64_opcode_table): Add sve2 instructions.
 978
 979 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 980
 981         * aarch64-asm-2.c: Regenerated.
 982         * aarch64-dis-2.c: Regenerated.
 983         * aarch64-opc-2.c: Regenerated.
 984         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 985         for SVE_SHLIMM_UNPRED_22.
 986         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 987         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 988         operand.
 989
 990 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 991
 992         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 993         sve_size_tsz_bhs iclass encode.
 994         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 995         sve_size_tsz_bhs iclass decode.
 996
 997 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 998
 999         * aarch64-asm-2.c: Regenerated.
1000         * aarch64-dis-2.c: Regenerated.
1001         * aarch64-opc-2.c: Regenerated.
1002         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1003         for SVE_Zm4_11_INDEX.
1004         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1005         (fields): Handle SVE_i2h field.
1006         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1007         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1008
1009 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1010
1011         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1012         sve_shift_tsz_bhsd iclass encode.
1013         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1014         sve_shift_tsz_bhsd iclass decode.
1015
1016 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1017
1018         * aarch64-asm-2.c: Regenerated.
1019         * aarch64-dis-2.c: Regenerated.
1020         * aarch64-opc-2.c: Regenerated.
1021         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1022         (aarch64_encode_variant_using_iclass): Handle
1023         sve_shift_tsz_hsd iclass encode.
1024         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1025         sve_shift_tsz_hsd iclass decode.
1026         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1027         for SVE_SHRIMM_UNPRED_22.
1028         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1029         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1030         operand.
1031
1032 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1033
1034         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1035         sve_size_013 iclass encode.
1036         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1037         sve_size_013 iclass decode.
1038
1039 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1040
1041         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1042         sve_size_bh iclass encode.
1043         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1044         sve_size_bh iclass decode.
1045
1046 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1047
1048         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1049         sve_size_sd2 iclass encode.
1050         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1051         sve_size_sd2 iclass decode.
1052         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1053         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1054
1055 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1056
1057         * aarch64-asm-2.c: Regenerated.
1058         * aarch64-dis-2.c: Regenerated.
1059         * aarch64-opc-2.c: Regenerated.
1060         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1061         for SVE_ADDR_ZX.
1062         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1063         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1064
1065 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1066
1067         * aarch64-asm-2.c: Regenerated.
1068         * aarch64-dis-2.c: Regenerated.
1069         * aarch64-opc-2.c: Regenerated.
1070         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1071         for SVE_Zm3_11_INDEX.
1072         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1073         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1074         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1075         fields.
1076         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1077
1078 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1079
1080         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1081         sve_size_hsd2 iclass encode.
1082         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1083         sve_size_hsd2 iclass decode.
1084         * aarch64-opc.c (fields): Handle SVE_size field.
1085         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1086
1087 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1088
1089         * aarch64-asm-2.c: Regenerated.
1090         * aarch64-dis-2.c: Regenerated.
1091         * aarch64-opc-2.c: Regenerated.
1092         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1093         for SVE_IMM_ROT3.
1094         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1095         (fields): Handle SVE_rot3 field.
1096         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1097         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1098
1099 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1100
1101         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1102         instructions.
1103
1104 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1105
1106         * aarch64-tbl.h
1107         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1108         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1109         aarch64_feature_sve2bitperm): New feature sets.
1110         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1111         for feature set addresses.
1112         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1113         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1114
1115 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1116             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1117
1118         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1119         argument and set ASE_EVA_R6 appropriately.
1120         (set_default_mips_dis_options): Pass ISA to above.
1121         (parse_mips_dis_option): Likewise.
1122         * mips-opc.c (EVAR6): New macro.
1123         (mips_builtin_opcodes): Add llwpe, scwpe.
1124
1125 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1126
1127         * aarch64-asm-2.c: Regenerated.
1128         * aarch64-dis-2.c: Regenerated.
1129         * aarch64-opc-2.c: Regenerated.
1130         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1131         AARCH64_OPND_TME_UIMM16.
1132         (aarch64_print_operand): Likewise.
1133         * aarch64-tbl.h (QL_IMM_NIL): New.
1134         (TME): New.
1135         (_TME_INSN): New.
1136         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1137
1138 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1139
1140         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1141
1142 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1143             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1144
1145         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1146
1147 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1148
1149         * s12z-opc.h: Add extern "C" bracketing to help
1150         users who wish to use this interface in c++ code.
1151
1152 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1153
1154         * s12z-opc.c (bm_decode): Handle bit map operations with the
1155         "reserved0" mode.
1156
1157 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1158
1159         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1160         specifier.  Add entries for VLDR and VSTR of system registers.
1161         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1162         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1163         of %J and %K format specifier.
1164
1165 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1166
1167         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1168         Add new entries for VSCCLRM instruction.
1169         (print_insn_coprocessor): Handle new %C format control code.
1170
1171 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1172
1173         * arm-dis.c (enum isa): New enum.
1174         (struct sopcode32): New structure.
1175         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1176         set isa field of all current entries to ANY.
1177         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1178         Only match an entry if its isa field allows the current mode.
1179
1180 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1181
1182         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1183         CLRM.
1184         (print_insn_thumb32): Add logic to print %n CLRM register list.
1185
1186 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1187
1188         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1189         and %Q patterns.
1190
1191 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1192
1193         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1194         (print_insn_thumb32): Edit the switch case for %Z.
1195
1196 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1197
1198         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1199
1200 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1201
1202         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1203
1204 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1205
1206         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1207
1208 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1209
1210         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1211         Arm register with r13 and r15 unpredictable.
1212         (thumb32_opcodes): New instructions for bfx and bflx.
1213
1214 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1215
1216         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1217
1218 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1219
1220         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1221
1222 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1223
1224         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1225
1226 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1227
1228         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1229
1230 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1231
1232         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1233         "optr". ("operator" is a reserved word in c++).
1234
1235 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1236
1237         * aarch64-opc.c (aarch64_print_operand): Add case for
1238         AARCH64_OPND_Rt_SP.
1239         (verify_constraints): Likewise.
1240         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1241         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1242         to accept Rt|SP as first operand.
1243         (AARCH64_OPERANDS): Add new Rt_SP.
1244         * aarch64-asm-2.c: Regenerated.
1245         * aarch64-dis-2.c: Regenerated.
1246         * aarch64-opc-2.c: Regenerated.
1247
1248 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1249
1250         * aarch64-asm-2.c: Regenerated.
1251         * aarch64-dis-2.c: Likewise.
1252         * aarch64-opc-2.c: Likewise.
1253         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1254
1255 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1256
1257         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1258
1259 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1260
1261         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1262         * i386-init.h: Regenerated.
1263
1264 2019-04-07  Alan Modra  <amodra@gmail.com>
1265
1266         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1267         op_separator to control printing of spaces, comma and parens
1268         rather than need_comma, need_paren and spaces vars.
1269
1270 2019-04-07  Alan Modra  <amodra@gmail.com>
1271
1272         PR 24421
1273         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1274         (print_insn_neon, print_insn_arm): Likewise.
1275
1276 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1277
1278         * i386-dis-evex.h (evex_table): Updated to support BF16
1279         instructions.
1280         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1281         and EVEX_W_0F3872_P_3.
1282         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1283         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1284         * i386-opc.h (enum): Add CpuAVX512_BF16.
1285         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1286         * i386-opc.tbl: Add AVX512 BF16 instructions.
1287         * i386-init.h: Regenerated.
1288         * i386-tbl.h: Likewise.
1289
1290 2019-04-05  Alan Modra  <amodra@gmail.com>
1291
1292         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1293         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1294         to favour printing of "-" branch hint when using the "y" bit.
1295         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1296
1297 2019-04-05  Alan Modra  <amodra@gmail.com>
1298
1299         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1300         opcode until first operand is output.
1301
1302 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1303
1304         PR gas/24349
1305         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1306         (valid_bo_post_v2): Add support for 'at' branch hints.
1307         (insert_bo): Only error on branch on ctr.
1308         (get_bo_hint_mask): New function.
1309         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1310         for inserting 'at' branch hints.
1311         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1312         for extracting 'at' branch hints.
1313         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1314         (BOE): Delete operand.
1315         (BOM, BOP): New operands.
1316         (RM): Update value.
1317         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1318         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1319         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1320         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1321         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1322         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1323         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1324         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1325         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1326         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1327         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1328         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1329         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1330         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1331         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1332         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1333         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1334         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1335         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1336         bttarl+>: New extended mnemonics.
1337
1338 2019-03-28  Alan Modra  <amodra@gmail.com>
1339
1340         PR 24390
1341         * ppc-opc.c (BTF): Define.
1342         (powerpc_opcodes): Use for mtfsb*.
1343         * ppc-dis.c (print_insn_powerpc): Print fields with both
1344         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1345
1346 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1347
1348         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1349         (mapping_symbol_for_insn): Implement new algorithm.
1350         (print_insn): Remove duplicate code.
1351
1352 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1353
1354         * aarch64-dis.c (print_insn_aarch64):
1355         Implement override.
1356
1357 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1358
1359         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1360         order.
1361
1362 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1363
1364         * aarch64-dis.c (last_stop_offset): New.
1365         (print_insn_aarch64): Use stop_offset.
1366
1367 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1368
1369         PR gas/24359
1370         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1371         CPU_ANY_AVX2_FLAGS.
1372         * i386-init.h: Regenerated.
1373
1374 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1375
1376         PR gas/24348
1377         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1378         vmovdqu16, vmovdqu32 and vmovdqu64.
1379         * i386-tbl.h: Regenerated.
1380
1381 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1382
1383         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1384         from vstrszb, vstrszh, and vstrszf.
1385
1386 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1387
1388         * s390-opc.txt: Add instruction descriptions.
1389
1390 2019-02-08  Jim Wilson  <jimw@sifive.com>
1391
1392         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1393         <bne>: Likewise.
1394
1395 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1396
1397         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1398
1399 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1400
1401         PR binutils/23212
1402         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1403         * aarch64-opc.c (verify_elem_sd): New.
1404         (fields): Add FLD_sz entr.
1405         * aarch64-tbl.h (_SIMD_INSN): New.
1406         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1407         fmulx scalar and vector by element isns.
1408
1409 2019-02-07  Nick Clifton  <nickc@redhat.com>
1410
1411         * po/sv.po: Updated Swedish translation.
1412
1413 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1414
1415         * s390-mkopc.c (main): Accept arch13 as cpu string.
1416         * s390-opc.c: Add new instruction formats and instruction opcode
1417         masks.
1418         * s390-opc.txt: Add new arch13 instructions.
1419
1420 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1421
1422         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1423         (aarch64_opcode): Change encoding for stg, stzg
1424         st2g and st2zg.
1425         * aarch64-asm-2.c: Regenerated.
1426         * aarch64-dis-2.c: Regenerated.
1427         * aarch64-opc-2.c: Regenerated.
1428
1429 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1430
1431         * aarch64-asm-2.c: Regenerated.
1432         * aarch64-dis-2.c: Likewise.
1433         * aarch64-opc-2.c: Likewise.
1434         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1435
1436 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1437             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1438
1439         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1440         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1441         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1442         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1443         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1444         case for ldstgv_indexed.
1445         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1446         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1447         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1448         * aarch64-asm-2.c: Regenerated.
1449         * aarch64-dis-2.c: Regenerated.
1450         * aarch64-opc-2.c: Regenerated.
1451
1452 2019-01-23  Nick Clifton  <nickc@redhat.com>
1453
1454         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1455
1456 2019-01-21  Nick Clifton  <nickc@redhat.com>
1457
1458         * po/de.po: Updated German translation.
1459         * po/uk.po: Updated Ukranian translation.
1460
1461 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1462         * mips-dis.c (mips_arch_choices): Fix typo in
1463         gs464, gs464e and gs264e descriptors.
1464
1465 2019-01-19  Nick Clifton  <nickc@redhat.com>
1466
1467         * configure: Regenerate.
1468         * po/opcodes.pot: Regenerate.
1469
1470 2018-06-24  Nick Clifton  <nickc@redhat.com>
1471
1472         2.32 branch created.
1473
1474 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1475
1476         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1477         if it is null.
1478         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1479         zero.
1480
1481 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1482
1483         * configure: Regenerate.
1484
1485 2019-01-07  Alan Modra  <amodra@gmail.com>
1486
1487         * configure: Regenerate.
1488         * po/POTFILES.in: Regenerate.
1489
1490 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1491
1492         * s12z-opc.c: New file.
1493         * s12z-opc.h: New file.
1494         * s12z-dis.c: Removed all code not directly related to display
1495         of instructions.  Used the interface provided by the new files
1496         instead.
1497         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1498         * Makefile.in: Regenerate.
1499         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1500         * configure: Regenerate.
1501
1502 2019-01-01  Alan Modra  <amodra@gmail.com>
1503
1504         Update year range in copyright notice of all files.
1505
1506 For older changes see ChangeLog-2018
1507 \f
1508 Copyright (C) 2019 Free Software Foundation, Inc.
1509
1510 Copying and distribution of this file, with or without modification,
1511 are permitted in any medium without royalty provided the copyright
1512 notice and this notice are preserved.
1513
1514 Local Variables:
1515 mode: change-log
1516 left-margin: 8
1517 fill-column: 74
1518 version-control: never
1519 End: