opcodes/ChangeLog

   1 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
   2
   3         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
   4         sve_size_sd2 iclass encode.
   5         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
   6         sve_size_sd2 iclass decode.
   7         * aarch64-opc.c (fields): Handle SVE_sz2 field.
   8         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
   9
  10 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  11
  12         * aarch64-asm-2.c: Regenerated.
  13         * aarch64-dis-2.c: Regenerated.
  14         * aarch64-opc-2.c: Regenerated.
  15         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  16         for SVE_ADDR_ZX.
  17         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
  18         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
  19
  20 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  21
  22         * aarch64-asm-2.c: Regenerated.
  23         * aarch64-dis-2.c: Regenerated.
  24         * aarch64-opc-2.c: Regenerated.
  25         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  26         for SVE_Zm3_11_INDEX.
  27         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
  28         (fields): Handle SVE_i3l and SVE_i3h2 fields.
  29         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
  30         fields.
  31         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
  32
  33 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  34
  35         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  36         sve_size_hsd2 iclass encode.
  37         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  38         sve_size_hsd2 iclass decode.
  39         * aarch64-opc.c (fields): Handle SVE_size field.
  40         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
  41
  42 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  43
  44         * aarch64-asm-2.c: Regenerated.
  45         * aarch64-dis-2.c: Regenerated.
  46         * aarch64-opc-2.c: Regenerated.
  47         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  48         for SVE_IMM_ROT3.
  49         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
  50         (fields): Handle SVE_rot3 field.
  51         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
  52         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
  53
  54 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  55
  56         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
  57         instructions.
  58
  59 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  60
  61         * aarch64-tbl.h
  62         (aarch64_feature_sve2, aarch64_feature_sve2aes,
  63         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
  64         aarch64_feature_sve2bitperm): New feature sets.
  65         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
  66         for feature set addresses.
  67         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
  68         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
  69
  70 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
  71             Faraz Shahbazker  <fshahbazker@wavecomp.com>
  72
  73         * mips-dis.c (mips_calculate_combination_ases): Add ISA
  74         argument and set ASE_EVA_R6 appropriately.
  75         (set_default_mips_dis_options): Pass ISA to above.
  76         (parse_mips_dis_option): Likewise.
  77         * mips-opc.c (EVAR6): New macro.
  78         (mips_builtin_opcodes): Add llwpe, scwpe.
  79
  80 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
  81
  82         * aarch64-asm-2.c: Regenerated.
  83         * aarch64-dis-2.c: Regenerated.
  84         * aarch64-opc-2.c: Regenerated.
  85         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
  86         AARCH64_OPND_TME_UIMM16.
  87         (aarch64_print_operand): Likewise.
  88         * aarch64-tbl.h (QL_IMM_NIL): New.
  89         (TME): New.
  90         (_TME_INSN): New.
  91         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
  92
  93 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
  94
  95         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
  96
  97 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
  98             Faraz Shahbazker  <fshahbazker@wavecomp.com>
  99
 100         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 101
 102 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 103
 104         * s12z-opc.h: Add extern "C" bracketing to help
 105         users who wish to use this interface in c++ code.
 106
 107 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 108
 109         * s12z-opc.c (bm_decode): Handle bit map operations with the
 110         "reserved0" mode.
 111
 112 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 113
 114         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 115         specifier.  Add entries for VLDR and VSTR of system registers.
 116         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 117         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 118         of %J and %K format specifier.
 119
 120 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 121
 122         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 123         Add new entries for VSCCLRM instruction.
 124         (print_insn_coprocessor): Handle new %C format control code.
 125
 126 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 127
 128         * arm-dis.c (enum isa): New enum.
 129         (struct sopcode32): New structure.
 130         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 131         set isa field of all current entries to ANY.
 132         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 133         Only match an entry if its isa field allows the current mode.
 134
 135 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 136
 137         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 138         CLRM.
 139         (print_insn_thumb32): Add logic to print %n CLRM register list.
 140
 141 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 142
 143         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 144         and %Q patterns.
 145
 146 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 147
 148         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 149         (print_insn_thumb32): Edit the switch case for %Z.
 150
 151 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 152
 153         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 154
 155 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 156
 157         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 158
 159 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 160
 161         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 162
 163 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 164
 165         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 166         Arm register with r13 and r15 unpredictable.
 167         (thumb32_opcodes): New instructions for bfx and bflx.
 168
 169 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 170
 171         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 172
 173 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 174
 175         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 176
 177 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 178
 179         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 180
 181 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 182
 183         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 184
 185 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 186
 187         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 188         "optr". ("operator" is a reserved word in c++).
 189
 190 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 191
 192         * aarch64-opc.c (aarch64_print_operand): Add case for
 193         AARCH64_OPND_Rt_SP.
 194         (verify_constraints): Likewise.
 195         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 196         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 197         to accept Rt|SP as first operand.
 198         (AARCH64_OPERANDS): Add new Rt_SP.
 199         * aarch64-asm-2.c: Regenerated.
 200         * aarch64-dis-2.c: Regenerated.
 201         * aarch64-opc-2.c: Regenerated.
 202
 203 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 204
 205         * aarch64-asm-2.c: Regenerated.
 206         * aarch64-dis-2.c: Likewise.
 207         * aarch64-opc-2.c: Likewise.
 208         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 209
 210 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 211
 212         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 213
 214 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 215
 216         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 217         * i386-init.h: Regenerated.
 218
 219 2019-04-07  Alan Modra  <amodra@gmail.com>
 220
 221         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 222         op_separator to control printing of spaces, comma and parens
 223         rather than need_comma, need_paren and spaces vars.
 224
 225 2019-04-07  Alan Modra  <amodra@gmail.com>
 226
 227         PR 24421
 228         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 229         (print_insn_neon, print_insn_arm): Likewise.
 230
 231 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 232
 233         * i386-dis-evex.h (evex_table): Updated to support BF16
 234         instructions.
 235         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 236         and EVEX_W_0F3872_P_3.
 237         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 238         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 239         * i386-opc.h (enum): Add CpuAVX512_BF16.
 240         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 241         * i386-opc.tbl: Add AVX512 BF16 instructions.
 242         * i386-init.h: Regenerated.
 243         * i386-tbl.h: Likewise.
 244
 245 2019-04-05  Alan Modra  <amodra@gmail.com>
 246
 247         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 248         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 249         to favour printing of "-" branch hint when using the "y" bit.
 250         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 251
 252 2019-04-05  Alan Modra  <amodra@gmail.com>
 253
 254         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 255         opcode until first operand is output.
 256
 257 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 258
 259         PR gas/24349
 260         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 261         (valid_bo_post_v2): Add support for 'at' branch hints.
 262         (insert_bo): Only error on branch on ctr.
 263         (get_bo_hint_mask): New function.
 264         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 265         for inserting 'at' branch hints.
 266         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 267         for extracting 'at' branch hints.
 268         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 269         (BOE): Delete operand.
 270         (BOM, BOP): New operands.
 271         (RM): Update value.
 272         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 273         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 274         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 275         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 276         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 277         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 278         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 279         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 280         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 281         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 282         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 283         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 284         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 285         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 286         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 287         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 288         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 289         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 290         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 291         bttarl+>: New extended mnemonics.
 292
 293 2019-03-28  Alan Modra  <amodra@gmail.com>
 294
 295         PR 24390
 296         * ppc-opc.c (BTF): Define.
 297         (powerpc_opcodes): Use for mtfsb*.
 298         * ppc-dis.c (print_insn_powerpc): Print fields with both
 299         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 300
 301 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 302
 303         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 304         (mapping_symbol_for_insn): Implement new algorithm.
 305         (print_insn): Remove duplicate code.
 306
 307 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 308
 309         * aarch64-dis.c (print_insn_aarch64):
 310         Implement override.
 311
 312 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 313
 314         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 315         order.
 316
 317 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 318
 319         * aarch64-dis.c (last_stop_offset): New.
 320         (print_insn_aarch64): Use stop_offset.
 321
 322 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 323
 324         PR gas/24359
 325         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 326         CPU_ANY_AVX2_FLAGS.
 327         * i386-init.h: Regenerated.
 328
 329 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 330
 331         PR gas/24348
 332         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 333         vmovdqu16, vmovdqu32 and vmovdqu64.
 334         * i386-tbl.h: Regenerated.
 335
 336 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 337
 338         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 339         from vstrszb, vstrszh, and vstrszf.
 340
 341 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 342
 343         * s390-opc.txt: Add instruction descriptions.
 344
 345 2019-02-08  Jim Wilson  <jimw@sifive.com>
 346
 347         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 348         <bne>: Likewise.
 349
 350 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 351
 352         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 353
 354 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 355
 356         PR binutils/23212
 357         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 358         * aarch64-opc.c (verify_elem_sd): New.
 359         (fields): Add FLD_sz entr.
 360         * aarch64-tbl.h (_SIMD_INSN): New.
 361         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 362         fmulx scalar and vector by element isns.
 363
 364 2019-02-07  Nick Clifton  <nickc@redhat.com>
 365
 366         * po/sv.po: Updated Swedish translation.
 367
 368 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 369
 370         * s390-mkopc.c (main): Accept arch13 as cpu string.
 371         * s390-opc.c: Add new instruction formats and instruction opcode
 372         masks.
 373         * s390-opc.txt: Add new arch13 instructions.
 374
 375 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 376
 377         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 378         (aarch64_opcode): Change encoding for stg, stzg
 379         st2g and st2zg.
 380         * aarch64-asm-2.c: Regenerated.
 381         * aarch64-dis-2.c: Regenerated.
 382         * aarch64-opc-2.c: Regenerated.
 383
 384 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 385
 386         * aarch64-asm-2.c: Regenerated.
 387         * aarch64-dis-2.c: Likewise.
 388         * aarch64-opc-2.c: Likewise.
 389         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 390
 391 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 392             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 393
 394         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 395         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 396         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 397         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 398         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 399         case for ldstgv_indexed.
 400         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 401         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 402         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 403         * aarch64-asm-2.c: Regenerated.
 404         * aarch64-dis-2.c: Regenerated.
 405         * aarch64-opc-2.c: Regenerated.
 406
 407 2019-01-23  Nick Clifton  <nickc@redhat.com>
 408
 409         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 410
 411 2019-01-21  Nick Clifton  <nickc@redhat.com>
 412
 413         * po/de.po: Updated German translation.
 414         * po/uk.po: Updated Ukranian translation.
 415
 416 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 417         * mips-dis.c (mips_arch_choices): Fix typo in
 418         gs464, gs464e and gs264e descriptors.
 419
 420 2019-01-19  Nick Clifton  <nickc@redhat.com>
 421
 422         * configure: Regenerate.
 423         * po/opcodes.pot: Regenerate.
 424
 425 2018-06-24  Nick Clifton  <nickc@redhat.com>
 426
 427         2.32 branch created.
 428
 429 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 430
 431         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 432         if it is null.
 433         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 434         zero.
 435
 436 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 437
 438         * configure: Regenerate.
 439
 440 2019-01-07  Alan Modra  <amodra@gmail.com>
 441
 442         * configure: Regenerate.
 443         * po/POTFILES.in: Regenerate.
 444
 445 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 446
 447         * s12z-opc.c: New file.
 448         * s12z-opc.h: New file.
 449         * s12z-dis.c: Removed all code not directly related to display
 450         of instructions.  Used the interface provided by the new files
 451         instead.
 452         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 453         * Makefile.in: Regenerate.
 454         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 455         * configure: Regenerate.
 456
 457 2019-01-01  Alan Modra  <amodra@gmail.com>
 458
 459         Update year range in copyright notice of all files.
 460
 461 For older changes see ChangeLog-2018
 462 \f
 463 Copyright (C) 2019 Free Software Foundation, Inc.
 464
 465 Copying and distribution of this file, with or without modification,
 466 are permitted in any medium without royalty provided the copyright
 467 notice and this notice are preserved.
 468
 469 Local Variables:
 470 mode: change-log
 471 left-margin: 8
 472 fill-column: 74
 473 version-control: never
 474 End: