opcodes/ChangeLog

   1 2020-03-09  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (struct template_arg, struct template_instance,
   4         struct template_param, struct template, templates,
   5         parse_template, expand_templates): New.
   6         (process_i386_opcodes): Various local variables moved to
   7         expand_templates. Call parse_template and expand_templates.
   8         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
   9         * i386-tbl.h: Re-generate.
  10
  11 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  12
  13         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
  14         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
  15         register and memory source templates. Replace VexW= by VexW*
  16         where applicable.
  17         * i386-tbl.h: Re-generate.
  18
  19 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  20
  21         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
  22         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
  23         * i386-tbl.h: Re-generate.
  24
  25 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
  28         * i386-tbl.h: Re-generate.
  29
  30 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
  33         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
  34         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
  35         VexW0 on SSE2AVX variants.
  36         (vmovq): Drop NoRex64 from XMM/XMM variants.
  37         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
  38         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
  39         applicable use VexW0.
  40         * i386-tbl.h: Re-generate.
  41
  42 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
  45         * i386-opc.h (Rex64): Delete.
  46         (struct i386_opcode_modifier): Remove rex64 field.
  47         * i386-opc.tbl (crc32): Drop Rex64.
  48         Replace Rex64 with Size64 everywhere else.
  49         * i386-tbl.h: Re-generate.
  50
  51 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-dis.c (OP_E_memory): Exclude recording of used address
  54         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
  55         addressed memory operands for MPX insns.
  56
  57 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  58
  59         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
  60         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
  61         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
  62         (ptwrite): Split into non-64-bit and 64-bit forms.
  63         * i386-tbl.h: Re-generate.
  64
  65 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  66
  67         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
  68         template.
  69         * i386-tbl.h: Re-generate.
  70
  71 2020-03-04  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
  74         (prefix_table): Move vmmcall here. Add vmgexit.
  75         (rm_table): Replace vmmcall entry by prefix_table[] escape.
  76         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
  77         (cpu_flags): Add CpuSEV_ES entry.
  78         * i386-opc.h (CpuSEV_ES): New.
  79         (union i386_cpu_flags): Add cpusev_es field.
  80         * i386-opc.tbl (vmgexit): New.
  81         * i386-init.h, i386-tbl.h: Re-generate.
  82
  83 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  84
  85         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
  86         with MnemonicSize.
  87         * i386-opc.h (IGNORESIZE): New.
  88         (DEFAULTSIZE): Likewise.
  89         (IgnoreSize): Removed.
  90         (DefaultSize): Likewise.
  91         (MnemonicSize): New.
  92         (i386_opcode_modifier): Replace ignoresize/defaultsize with
  93         mnemonicsize.
  94         * i386-opc.tbl (IgnoreSize): New.
  95         (DefaultSize): Likewise.
  96         * i386-tbl.h: Regenerated.
  97
  98 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
  99
 100         PR 25627
 101         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 102         instructions.
 103
 104 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 105
 106         PR gas/25622
 107         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 108         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 109         * i386-tbl.h: Regenerated.
 110
 111 2020-02-26  Alan Modra  <amodra@gmail.com>
 112
 113         * aarch64-asm.c: Indent labels correctly.
 114         * aarch64-dis.c: Likewise.
 115         * aarch64-gen.c: Likewise.
 116         * aarch64-opc.c: Likewise.
 117         * alpha-dis.c: Likewise.
 118         * i386-dis.c: Likewise.
 119         * nds32-asm.c: Likewise.
 120         * nfp-dis.c: Likewise.
 121         * visium-dis.c: Likewise.
 122
 123 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 124
 125         * arc-regs.h (int_vector_base): Make it available for all ARC
 126         CPUs.
 127
 128 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 129
 130         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 131         changed.
 132
 133 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 134
 135         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 136         c.mv/c.li if rs1 is zero.
 137
 138 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 139
 140         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 141         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 142         CPU_POPCNT_FLAGS.
 143         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 144         * i386-opc.h (CpuABM): Removed.
 145         (CpuPOPCNT): New.
 146         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 147         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 148         popcnt.  Remove CpuABM from lzcnt.
 149         * i386-init.h: Regenerated.
 150         * i386-tbl.h: Likewise.
 151
 152 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 155         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 156         VexW1 instead of open-coding them.
 157         * i386-tbl.h: Re-generate.
 158
 159 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 160
 161         * i386-opc.tbl (AddrPrefixOpReg): Define.
 162         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 163         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 164         templates. Drop NoRex64.
 165         * i386-tbl.h: Re-generate.
 166
 167 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 168
 169         PR gas/6518
 170         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 171         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 172         into Intel syntax instance (with Unpsecified) and AT&T one
 173         (without).
 174         (vcvtneps2bf16): Likewise, along with folding the two so far
 175         separate ones.
 176         * i386-tbl.h: Re-generate.
 177
 178 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 179
 180         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 181         CPU_ANY_SSE4A_FLAGS.
 182
 183 2020-02-17  Alan Modra  <amodra@gmail.com>
 184
 185         * i386-gen.c (cpu_flag_init): Correct last change.
 186
 187 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 188
 189         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 190         CPU_ANY_SSE4_FLAGS.
 191
 192 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 193
 194         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 195         (movzx): Likewise.
 196
 197 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 198
 199         PR gas/25438
 200         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 201         destination for Cpu64-only variant.
 202         (movzx): Fold patterns.
 203         * i386-tbl.h: Re-generate.
 204
 205 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 208         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 209         CPU_ANY_SSE4_FLAGS entry.
 210         * i386-init.h: Re-generate.
 211
 212 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 213
 214         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 215         with Unspecified, making the present one AT&T syntax only.
 216         * i386-tbl.h: Re-generate.
 217
 218 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 219
 220         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 221         * i386-tbl.h: Re-generate.
 222
 223 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 224
 225         PR gas/24546
 226         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 227         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 228         Amd64 and Intel64 templates.
 229         (call, jmp): Likewise for far indirect variants. Dro
 230         Unspecified.
 231         * i386-tbl.h: Re-generate.
 232
 233 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 236         * i386-opc.h (ShortForm): Delete.
 237         (struct i386_opcode_modifier): Remove shortform field.
 238         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 239         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 240         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 241         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 242         Drop ShortForm.
 243         * i386-tbl.h: Re-generate.
 244
 245 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 248         fucompi): Drop ShortForm from operand-less templates.
 249         * i386-tbl.h: Re-generate.
 250
 251 2020-02-11  Alan Modra  <amodra@gmail.com>
 252
 253         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 254         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 255         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 256         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 257         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 258
 259 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 260
 261         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 262         (cde_opcodes): Add VCX* instructions.
 263
 264 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 265             Matthew Malcomson  <matthew.malcomson@arm.com>
 266
 267         * arm-dis.c (struct cdeopcode32): New.
 268         (CDE_OPCODE): New macro.
 269         (cde_opcodes): New disassembly table.
 270         (regnames): New option to table.
 271         (cde_coprocs): New global variable.
 272         (print_insn_cde): New
 273         (print_insn_thumb32): Use print_insn_cde.
 274         (parse_arm_disassembler_options): Parse coprocN args.
 275
 276 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 277
 278         PR gas/25516
 279         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 280         with ISA64.
 281         * i386-opc.h (AMD64): Removed.
 282         (Intel64): Likewose.
 283         (AMD64): New.
 284         (INTEL64): Likewise.
 285         (INTEL64ONLY): Likewise.
 286         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 287         * i386-opc.tbl (Amd64): New.
 288         (Intel64): Likewise.
 289         (Intel64Only): Likewise.
 290         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 291         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 292         * i386-tbl.h: Regenerated.
 293
 294 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 295
 296         PR 25469
 297         * z80-dis.c: Add support for GBZ80 opcodes.
 298
 299 2020-02-04  Alan Modra  <amodra@gmail.com>
 300
 301         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 302
 303 2020-02-03  Alan Modra  <amodra@gmail.com>
 304
 305         * m32c-ibld.c: Regenerate.
 306
 307 2020-02-01  Alan Modra  <amodra@gmail.com>
 308
 309         * frv-ibld.c: Regenerate.
 310
 311 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 312
 313         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 314         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 315         (OP_E_memory): Replace xmm_mdq_mode case label by
 316         vex_scalar_w_dq_mode one.
 317         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 318
 319 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 322         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 323         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 324         (intel_operand_size): Drop vex_w_dq_mode case label.
 325
 326 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 327
 328         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 329         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 330
 331 2020-01-30  Alan Modra  <amodra@gmail.com>
 332
 333         * m32c-ibld.c: Regenerate.
 334
 335 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 336
 337         * bpf-opc.c: Regenerate.
 338
 339 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 340
 341         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 342         (dis386): Use them to replace C2/C3 table entries.
 343         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 344         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 345         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 346         * i386-tbl.h: Re-generate.
 347
 348 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 351         forms.
 352         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 353         DefaultSize.
 354         * i386-tbl.h: Re-generate.
 355
 356 2020-01-30  Alan Modra  <amodra@gmail.com>
 357
 358         * tic4x-dis.c (tic4x_dp): Make unsigned.
 359
 360 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 361             Jan Beulich  <jbeulich@suse.com>
 362
 363         PR binutils/25445
 364         * i386-dis.c (MOVSXD_Fixup): New function.
 365         (movsxd_mode): New enum.
 366         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 367         (intel_operand_size): Handle movsxd_mode.
 368         (OP_E_register): Likewise.
 369         (OP_G): Likewise.
 370         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 371         register on movsxd.  Add movsxd with 16-bit destination register
 372         for AMD64 and Intel64 ISAs.
 373         * i386-tbl.h: Regenerated.
 374
 375 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 376
 377         PR 25403
 378         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 379         * aarch64-asm-2.c: Regenerate
 380         * aarch64-dis-2.c: Likewise.
 381         * aarch64-opc-2.c: Likewise.
 382
 383 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 384
 385         * i386-opc.tbl (sysret): Drop DefaultSize.
 386         * i386-tbl.h: Re-generate.
 387
 388 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 389
 390         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 391         Dword.
 392         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 393         * i386-tbl.h: Re-generate.
 394
 395 2020-01-20  Nick Clifton  <nickc@redhat.com>
 396
 397         * po/de.po: Updated German translation.
 398         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 399         * po/uk.po: Updated Ukranian translation.
 400
 401 2020-01-20  Alan Modra  <amodra@gmail.com>
 402
 403         * hppa-dis.c (fput_const): Remove useless cast.
 404
 405 2020-01-20  Alan Modra  <amodra@gmail.com>
 406
 407         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 408
 409 2020-01-18  Nick Clifton  <nickc@redhat.com>
 410
 411         * configure: Regenerate.
 412         * po/opcodes.pot: Regenerate.
 413
 414 2020-01-18  Nick Clifton  <nickc@redhat.com>
 415
 416         Binutils 2.34 branch created.
 417
 418 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 419
 420         * opintl.h: Fix spelling error (seperate).
 421
 422 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 423
 424         * i386-opc.tbl: Add {vex} pseudo prefix.
 425         * i386-tbl.h: Regenerated.
 426
 427 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 428
 429         PR 25376
 430         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 431         (neon_opcodes): Likewise.
 432         (select_arm_features): Make sure we enable MVE bits when selecting
 433         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 434         any architecture.
 435
 436 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 437
 438         * i386-opc.tbl: Drop stale comment from XOP section.
 439
 440 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 441
 442         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 443         (extractps): Add VexWIG to SSE2AVX forms.
 444         * i386-tbl.h: Re-generate.
 445
 446 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 447
 448         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 449         Size64 from and use VexW1 on SSE2AVX forms.
 450         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 451         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 452         * i386-tbl.h: Re-generate.
 453
 454 2020-01-15  Alan Modra  <amodra@gmail.com>
 455
 456         * tic4x-dis.c (tic4x_version): Make unsigned long.
 457         (optab, optab_special, registernames): New file scope vars.
 458         (tic4x_print_register): Set up registernames rather than
 459         malloc'd registertable.
 460         (tic4x_disassemble): Delete optable and optable_special.  Use
 461         optab and optab_special instead.  Throw away old optab,
 462         optab_special and registernames when info->mach changes.
 463
 464 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 465
 466         PR 25377
 467         * z80-dis.c (suffix): Use .db instruction to generate double
 468         prefix.
 469
 470 2020-01-14  Alan Modra  <amodra@gmail.com>
 471
 472         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 473         values to unsigned before shifting.
 474
 475 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 476
 477         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 478         flow instructions.
 479         (print_insn_thumb16, print_insn_thumb32): Likewise.
 480         (print_insn): Initialize the insn info.
 481         * i386-dis.c (print_insn): Initialize the insn info fields, and
 482         detect jumps.
 483
 484 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 485
 486         * arc-opc.c (C_NE): Make it required.
 487
 488 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 489
 490         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 491         reserved register name.
 492
 493 2020-01-13  Alan Modra  <amodra@gmail.com>
 494
 495         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 496         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 497
 498 2020-01-13  Alan Modra  <amodra@gmail.com>
 499
 500         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 501         result of wasm_read_leb128 in a uint64_t and check that bits
 502         are not lost when copying to other locals.  Use uint32_t for
 503         most locals.  Use PRId64 when printing int64_t.
 504
 505 2020-01-13  Alan Modra  <amodra@gmail.com>
 506
 507         * score-dis.c: Formatting.
 508         * score7-dis.c: Formatting.
 509
 510 2020-01-13  Alan Modra  <amodra@gmail.com>
 511
 512         * score-dis.c (print_insn_score48): Use unsigned variables for
 513         unsigned values.  Don't left shift negative values.
 514         (print_insn_score32): Likewise.
 515         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 516
 517 2020-01-13  Alan Modra  <amodra@gmail.com>
 518
 519         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 520
 521 2020-01-13  Alan Modra  <amodra@gmail.com>
 522
 523         * fr30-ibld.c: Regenerate.
 524
 525 2020-01-13  Alan Modra  <amodra@gmail.com>
 526
 527         * xgate-dis.c (print_insn): Don't left shift signed value.
 528         (ripBits): Formatting, use 1u.
 529
 530 2020-01-10  Alan Modra  <amodra@gmail.com>
 531
 532         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 533         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 534
 535 2020-01-10  Alan Modra  <amodra@gmail.com>
 536
 537         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 538         and XRREG value earlier to avoid a shift with negative exponent.
 539         * m10200-dis.c (disassemble): Similarly.
 540
 541 2020-01-09  Nick Clifton  <nickc@redhat.com>
 542
 543         PR 25224
 544         * z80-dis.c (ld_ii_ii): Use correct cast.
 545
 546 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 547
 548         PR 25224
 549         * z80-dis.c (ld_ii_ii): Use character constant when checking
 550         opcode byte value.
 551
 552 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 553
 554         * i386-dis.c (SEP_Fixup): New.
 555         (SEP): Define.
 556         (dis386_twobyte): Use it for sysenter/sysexit.
 557         (enum x86_64_isa): Change amd64 enumerator to value 1.
 558         (OP_J): Compare isa64 against intel64 instead of amd64.
 559         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 560         forms.
 561         * i386-tbl.h: Re-generate.
 562
 563 2020-01-08  Alan Modra  <amodra@gmail.com>
 564
 565         * z8k-dis.c: Include libiberty.h
 566         (instr_data_s): Make max_fetched unsigned.
 567         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 568         Don't exceed byte_info bounds.
 569         (output_instr): Make num_bytes unsigned.
 570         (unpack_instr): Likewise for nibl_count and loop.
 571         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 572         idx unsigned.
 573         * z8k-opc.h: Regenerate.
 574
 575 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 576
 577         * arc-tbl.h (llock): Use 'LLOCK' as class.
 578         (llockd): Likewise.
 579         (scond): Use 'SCOND' as class.
 580         (scondd): Likewise.
 581         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 582         (scondd): Likewise.
 583
 584 2020-01-06  Alan Modra  <amodra@gmail.com>
 585
 586         * m32c-ibld.c: Regenerate.
 587
 588 2020-01-06  Alan Modra  <amodra@gmail.com>
 589
 590         PR 25344
 591         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 592         Peek at next byte to prevent recursion on repeated prefix bytes.
 593         Ensure uninitialised "mybuf" is not accessed.
 594         (print_insn_z80): Don't zero n_fetch and n_used here,..
 595         (print_insn_z80_buf): ..do it here instead.
 596
 597 2020-01-04  Alan Modra  <amodra@gmail.com>
 598
 599         * m32r-ibld.c: Regenerate.
 600
 601 2020-01-04  Alan Modra  <amodra@gmail.com>
 602
 603         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 604
 605 2020-01-04  Alan Modra  <amodra@gmail.com>
 606
 607         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 608
 609 2020-01-04  Alan Modra  <amodra@gmail.com>
 610
 611         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 612
 613 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 614
 615         * aarch64-tbl.h (aarch64_opcode_table): Use
 616         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 617
 618 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 619
 620         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 621         forms of SUDOT and USDOT.
 622
 623 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 624
 625         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 626         uzip{1,2}.
 627         * opcodes/aarch64-dis-2.c: Re-generate.
 628
 629 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 630
 631         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 632         FMMLA encoding.
 633         * opcodes/aarch64-dis-2.c: Re-generate.
 634
 635 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 636
 637         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 638
 639 2020-01-01  Alan Modra  <amodra@gmail.com>
 640
 641         Update year range in copyright notice of all files.
 642
 643 For older changes see ChangeLog-2019
 644 \f
 645 Copyright (C) 2020 Free Software Foundation, Inc.
 646
 647 Copying and distribution of this file, with or without modification,
 648 are permitted in any medium without royalty provided the copyright
 649 notice and this notice are preserved.
 650
 651 Local Variables:
 652 mode: change-log
 653 left-margin: 8
 654 fill-column: 74
 655 version-control: never
 656 End: