opcodes/ChangeLog

   1 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
   2             Wei-Cheng Wang  <cole945@gmail.com>
   3
   4         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c
   5         and nds32-dis.c.
   6         * Makefile.in: Regenerate.
   7         * configure.in: Add case for bfd_nds32_arch.
   8         * configure: Regenerate.
   9         * disassemble.c (ARCH_nds32): Define.
  10         * nds32-asm.c: New file for nds32.
  11         * nds32-asm.h: New file for nds32.
  12         * nds32-dis.c: New file for nds32.
  13         * nds32-opc.h: New file for nds32.
  14
  15 2013-12-05  Nick Clifton  <nickc@redhat.com>
  16
  17         * s390-mkopc.c (dumpTable): Provide a format string to printf so
  18         that compiling with -Werror=format-security does not produce an
  19         error.
  20
  21 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  22
  23         * aarch64-opc.c (aarch64_pstatefields): Update.
  24
  25 2013-11-19  Catherine Moore  <clm@codesourcery.com>
  26
  27         * micromips-opc.c (LM): Define.
  28         (micromips_opcodes): Add LM to load instructions.
  29         * mips-opc.c (prefe): Add LM attribute.
  30
  31 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
  32
  33         Revert
  34
  35         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  36
  37         * aarch64-opc.c (CPENT): New define.
  38         (F_READONLY, F_WRITEONLY): Likewise.
  39         (aarch64_sys_regs): Add trace unit registers.
  40         (aarch64_sys_reg_readonly_p): New function.
  41         (aarch64_sys_reg_writeonly_p): Ditto.
  42
  43 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  44
  45         * aarch64-opc.c (CPENT): New define.
  46         (F_READONLY, F_WRITEONLY): Likewise.
  47         (aarch64_sys_regs): Add trace unit registers.
  48         (aarch64_sys_reg_readonly_p): New function.
  49         (aarch64_sys_reg_writeonly_p): Ditto.
  50
  51 2013-11-15  Maciej W. Rozycki  <macro@codesourcery.com>
  52
  53         * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
  54         "mtcr".
  55
  56 2013-11-11  Catherine Moore  <clm@codesourcery.com>
  57
  58         * mips-dis.c (print_insn_mips): Use
  59         INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
  60         (print_insn_micromips): Likewise.
  61         * mips-opc.c (LDD): Remove.
  62         (CLD): Include INSN_LOAD_MEMORY.
  63         (LM): New.
  64         (mips_builtin_opcodes): Use LM instead of LDD.
  65         Add LM to load instructions.
  66
  67 2013-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  68
  69         PR gas/16140
  70         * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
  71         * i386-init.h: Regenerated.
  72
  73 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  74
  75         * aarch64-opc.c (F_DEPRECATED): New macro.
  76         (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
  77         F_DEPRECATED.
  78         (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
  79         AARCH64_OPND_SYSREG.
  80
  81 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  82
  83         * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
  84         (convert_from_csel): Likewise.
  85         * aarch64-opc.c (operand_general_constraint_met_p): Handle
  86         AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
  87         (aarch64_print_operand): Handle AARCH64_OPND_COND1.
  88         * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
  89         COND for cinc, cset, cinv, csetm and cneg.
  90         (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
  91         * aarch64-asm-2.c: Re-generated.
  92         * aarch64-dis-2.c: Ditto.
  93         * aarch64-opc-2.c: Ditto.
  94
  95 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  96
  97         * aarch64-opc.c (set_syntax_error): New function.
  98         (operand_general_constraint_met_p): Replace set_other_error
  99         with set_syntax_error.
 100
 101 2013-10-30  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 102
 103         * s390-dis.c (init_disasm): Default to full 'zarch' opcode
 104         availability even for 31-bit programs.
 105
 106 2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 107
 108         * arm-dis.c (neon_opcodes): Adjust print string for vshll.
 109
 110 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 111
 112         * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
 113         +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
 114         +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 115         (MSA): New define.
 116         (MSA64): New define.
 117         (micromips_opcodes): Add MSA instructions.
 118         * mips-dis.c (msa_control_names): New array.
 119         (mips_abi_choice): Add ASE_MSA to mips32r2.
 120         Remove ASE_MDMX from mips64r2.
 121         Add ASE_MSA and ASE_MSA64 to mips64r2.
 122         (parse_mips_dis_option): Handle -Mmsa.
 123         (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
 124         (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
 125         (print_mips_disassembler_options): Print -Mmsa.
 126         * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
 127         +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 128         (MSA): New define.
 129         (MSA64): New define.
 130         (mips_builtin_op): Add MSA instructions.
 131
 132 2013-10-13  Sandra Loosemore  <sandra@codesourcery.com>
 133
 134         * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
 135         as the primary name of r30.
 136
 137 2013-10-12  Jan Beulich <jbeulich@suse.com>
 138
 139         * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
 140         default case.
 141         (OP_E_register): Move v_bnd_mode alongside m_mode.
 142         * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
 143         Drop Reg16 and Disp16. Add NoRex64.
 144         (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
 145         * i386-tbl.h: Re-generate.
 146
 147 2013-10-10  Sean Keys <skeys@ipdatasys.com>
 148
 149         * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
 150         table.
 151         * xgate-dis.c (print_insn): Refactor to work with table change.
 152
 153 2013-10-10  Roland McGrath  <mcgrathr@google.com>
 154
 155         * i386-dis.c (oappend_maybe_intel): New function.
 156         (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
 157         (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
 158         (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
 159
 160         * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
 161         possible compiler warnings when the union's initializer is
 162         actually meant for the 'preg' enum typed member.
 163         * crx-opc.c (REG): Likewise.
 164
 165         * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
 166         Remove duplicate const qualifier.
 167
 168 2013-10-08  Jan Beulich <jbeulich@suse.com>
 169
 170         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
 171         (clflush): Use Anysize instead of Byte|Unspecified.
 172         (prefetch*): Likewise.
 173         * i386-tbl.h: Re-generate.
 174
 175 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 176
 177         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
 178
 179 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 180
 181         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
 182         * i386-init.h: Regenerated.
 183
 184 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 185
 186         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
 187         * i386-init.h: Regenerated.
 188
 189 2013-09-20  Alan Modra  <amodra@gmail.com>
 190
 191         * configure: Regenerate.
 192
 193 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 194
 195         * s390-opc.txt (clih): Make the immediate unsigned.
 196
 197 2013-09-04  Roland McGrath  <mcgrathr@google.com>
 198
 199         PR gas/15914
 200         * arm-dis.c (arm_opcodes): Add udf.
 201         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
 202         (thumb32_opcodes): Add udf.w.
 203         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
 204
 205 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 206
 207         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
 208         For the load fp integer instructions only the suppression flag was
 209         new with z196 version.
 210
 211 2013-08-28  Nick Clifton  <nickc@redhat.com>
 212
 213         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
 214         immediate is not suitable for the 32-bit ABI.
 215
 216 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
 217
 218         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
 219         replacing NODS.
 220
 221 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 222
 223         PR binutils/15834
 224         * aarch64-asm.c: Fix typos.
 225         * aarch64-dis.c: Likewise.
 226         * msp430-dis.c: Likewise.
 227
 228 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 229
 230         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
 231         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
 232         Use +H rather than +C for the real "dext".
 233         * mips-opc.c (mips_builtin_opcodes): Likewise.
 234
 235 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 236
 237         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
 238         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
 239         and OPTIONAL_MAPPED_REG.
 240         * mips-opc.c (decode_mips_operand): Likewise.
 241         * mips16-opc.c (decode_mips16_operand): Likewise.
 242         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
 243
 244 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
 245
 246         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
 247         (PREFIX_EVEX_0F3A3F): Likewise.
 248         * i386-dis-evex.h (evex_table): Updated.
 249
 250 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
 251
 252         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
 253         VCLIPW.
 254
 255 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
 256             Konrad Eisele  <konrad@gaisler.com>
 257
 258         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
 259         bfd_mach_sparc.
 260         * sparc-opc.c (MASK_LEON): Define.
 261         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
 262         (letandleon): New macro.
 263         (v9andleon): Likewise.
 264         (sparc_opc): Add leon.
 265         (umac): Enable for letandleon.
 266         (smac): Likewise.
 267         (casa): Enable for v9andleon.
 268         (cas): Likewise.
 269         (casl): Likewise.
 270
 271 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 272             Richard Sandiford  <rdsandiford@googlemail.com>
 273
 274         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 275         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 276         (print_vu0_channel): New function.
 277         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 278         (print_insn_args): Handle '#'.
 279         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 280         * mips-opc.c (mips_vu0_channel_mask): New constant.
 281         (decode_mips_operand): Handle new VU0 operand types.
 282         (VU0, VU0CH): New macros.
 283         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 284         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 285         Use "+6" rather than "G" for QMFC2 and QMTC2.
 286
 287 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 288
 289         * mips-formats.h (PCREL): Reorder parameters and update the definition
 290         to match new mips_pcrel_operand layout.
 291         (JUMP, JALX, BRANCH): Update accordingly.
 292         * mips16-opc.c (decode_mips16_operand): Likewise.
 293
 294 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 295
 296         * micromips-opc.c (WR_s): Delete.
 297
 298 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 299
 300         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 301         New macros.
 302         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 303         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 304         (mips_builtin_opcodes): Use the new position-based read-write flags
 305         instead of field-based ones.  Use UDI for "udi..." instructions.
 306         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 307         New macros.
 308         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 309         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 310         (WR_SP, RD_16): New macros.
 311         (RD_SP): Redefine as an INSN2_* flag.
 312         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 313         (mips16_opcodes): Use the new position-based read-write flags
 314         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 315         pinfo2 field.
 316         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 317         New macros.
 318         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 319         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 320         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 321         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 322         (micromips_opcodes): Use the new position-based read-write flags
 323         instead of field-based ones.
 324         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 325         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 326         of field-based flags.
 327
 328 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 329
 330         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 331         (WR_SP): Replace with...
 332         (MOD_SP): ...this.
 333         (mips16_opcodes): Update accordingly.
 334         * mips-dis.c (print_insn_mips16): Likewise.
 335
 336 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 337
 338         * mips16-opc.c (mips16_opcodes): Reformat.
 339
 340 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 341
 342         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 343         for operands that are hard-coded to $0.
 344         * micromips-opc.c (micromips_opcodes): Likewise.
 345
 346 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 347
 348         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 349         for the single-operand forms of JALR and JALR.HB.
 350         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 351         and JALRS.HB.
 352
 353 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 354
 355         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 356         instructions.  Fix them to use WR_MACC instead of WR_CC and
 357         add missing RD_MACCs.
 358
 359 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 360
 361         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 362
 363 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 364
 365         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 366
 367 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 368             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 369             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 370             Sergey Lega  <sergey.s.lega@intel.com>
 371             Anna Tikhonova  <anna.tikhonova@intel.com>
 372             Ilya Tocar  <ilya.tocar@intel.com>
 373             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 374             Ilya Verbin  <ilya.verbin@intel.com>
 375             Kirill Yukhin  <kirill.yukhin@intel.com>
 376             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 377
 378         * i386-dis-evex.h: New.
 379         * i386-dis.c (OP_Rounding): New.
 380         (VPCMP_Fixup): New.
 381         (OP_Mask): New.
 382         (Rdq): New.
 383         (XMxmmq): New.
 384         (EXdScalarS): New.
 385         (EXymm): New.
 386         (EXEvexHalfBcstXmmq): New.
 387         (EXxmm_mdq): New.
 388         (EXEvexXGscat): New.
 389         (EXEvexXNoBcst): New.
 390         (VPCMP): New.
 391         (EXxEVexR): New.
 392         (EXxEVexS): New.
 393         (XMask): New.
 394         (MaskG): New.
 395         (MaskE): New.
 396         (MaskR): New.
 397         (MaskVex): New.
 398         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 399         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 400         evex_rounding_mode, evex_sae_mode, mask_mode.
 401         (USE_EVEX_TABLE): New.
 402         (EVEX_TABLE): New.
 403         (EVEX enum): New.
 404         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 405         REG_EVEX_0F38C7.
 406         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 407         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 408         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 409         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 410         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 411         MOD_EVEX_0F38C7_REG_6.
 412         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 413         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 414         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 415         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 416         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 417         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 418         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 419         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 420         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 421         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 422         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 423         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 424         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 425         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 426         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 427         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 428         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 429         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 430         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 431         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 432         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 433         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 434         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 435         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 436         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 437         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 438         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 439         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 440         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 441         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 442         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 443         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 444         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 445         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 446         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 447         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 448         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 449         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 450         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 451         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 452         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 453         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 454         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 455         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 456         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 457         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 458         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 459         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 460         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 461         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 462         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 463         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 464         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 465         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 466         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 467         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 468         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 469         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 470         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 471         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 472         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 473         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 474         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 475         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 476         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 477         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 478         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 479         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 480         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 481         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 482         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 483         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 484         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 485         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 486         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 487         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 488         PREFIX_EVEX_0F3A55.
 489         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 490         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 491         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 492         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 493         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 494         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 495         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 496         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 497         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 498         VEX_W_0F3A32_P_2_LEN_0.
 499         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 500         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 501         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 502         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 503         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 504         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 505         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 506         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 507         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 508         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 509         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 510         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 511         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 512         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 513         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 514         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 515         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 516         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 517         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 518         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 519         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 520         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 521         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 522         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 523         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 524         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 525         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 526         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 527         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 528         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 529         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 530         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 531         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 532         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 533         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 534         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 535         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 536         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 537         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 538         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 539         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 540         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 541         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 542         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 543         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 544         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 545         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 546         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 547         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 548         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 549         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 550         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 551         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 552         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 553         (struct vex): Add fields evex, r, v, mask_register_specifier,
 554         zeroing, ll, b.
 555         (intel_names_xmm): Add upper 16 registers.
 556         (att_names_xmm): Ditto.
 557         (intel_names_ymm): Ditto.
 558         (att_names_ymm): Ditto.
 559         (names_zmm): New.
 560         (intel_names_zmm): Ditto.
 561         (att_names_zmm): Ditto.
 562         (names_mask): Ditto.
 563         (intel_names_mask): Ditto.
 564         (att_names_mask): Ditto.
 565         (names_rounding): Ditto.
 566         (names_broadcast): Ditto.
 567         (x86_64_table): Add escape to evex-table.
 568         (reg_table): Include reg_table evex-entries from
 569         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 570         (prefix_table): Add entries for new instructions.
 571         (vex_table): Ditto.
 572         (vex_len_table): Ditto.
 573         (vex_w_table): Ditto.
 574         (mod_table): Ditto.
 575         (get_valid_dis386): Properly handle new instructions.
 576         (print_insn): Handle zmm and mask registers, print mask operand.
 577         (intel_operand_size): Support EVEX, new modes and sizes.
 578         (OP_E_register): Handle new modes.
 579         (OP_E_memory): Ditto.
 580         (OP_G): Ditto.
 581         (OP_XMM): Ditto.
 582         (OP_EX): Ditto.
 583         (OP_VEX): Ditto.
 584         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 585         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 586         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 587         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 588         CpuAVX512PF and CpuVREX.
 589         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 590         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 591         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 592         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 593         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 594         * i386-init.h: Regenerate.
 595         * i386-opc.h (CpuAVX512F): New.
 596         (CpuAVX512CD): New.
 597         (CpuAVX512ER): New.
 598         (CpuAVX512PF): New.
 599         (CpuVREX): New.
 600         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 601         cpuavx512pf and cpuvrex fields.
 602         (VecSIB): Add VecSIB512.
 603         (EVex): New.
 604         (Masking): New.
 605         (VecESize): New.
 606         (Broadcast): New.
 607         (StaticRounding): New.
 608         (SAE): New.
 609         (Disp8MemShift): New.
 610         (NoDefMask): New.
 611         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 612         staticrounding, sae, disp8memshift and nodefmask.
 613         (RegZMM): New.
 614         (Zmmword): Ditto.
 615         (Vec_Disp8): Ditto.
 616         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 617         fields.
 618         (RegVRex): New.
 619         * i386-opc.tbl: Add AVX512 instructions.
 620         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 621         registers, mask registers.
 622         * i386-tbl.h: Regenerate.
 623
 624 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 625
 626         PR gas/15220
 627         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 628         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 629
 630 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 631
 632         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 633         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 634         PREFIX_0F3ACC.
 635         (prefix_table): Updated.
 636         (three_byte_table): Likewise.
 637         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 638         (cpu_flags): Add CpuSHA.
 639         (i386_cpu_flags): Add cpusha.
 640         * i386-init.h: Regenerate.
 641         * i386-opc.h (CpuSHA): New.
 642         (CpuUnused): Restored.
 643         (i386_cpu_flags): Add cpusha.
 644         * i386-opc.tbl: Add SHA instructions.
 645         * i386-tbl.h: Regenerate.
 646
 647 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 648             Kirill Yukhin  <kirill.yukhin@intel.com>
 649             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 650
 651         * i386-dis.c (BND_Fixup): New.
 652         (Ebnd): New.
 653         (Ev_bnd): New.
 654         (Gbnd): New.
 655         (BND): New.
 656         (v_bnd_mode): New.
 657         (bnd_mode): New.
 658         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 659         MOD_0F1B_PREFIX_1.
 660         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 661         (dis tables): Replace XX with BND for near branch and call
 662         instructions.
 663         (prefix_table): Add new entries.
 664         (mod_table): Likewise.
 665         (names_bnd): New.
 666         (intel_names_bnd): New.
 667         (att_names_bnd): New.
 668         (BND_PREFIX): New.
 669         (prefix_name): Handle BND_PREFIX.
 670         (print_insn): Initialize names_bnd.
 671         (intel_operand_size): Handle new modes.
 672         (OP_E_register): Likewise.
 673         (OP_E_memory): Likewise.
 674         (OP_G): Likewise.
 675         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 676         (cpu_flags): Add CpuMPX.
 677         (operand_type_init): Add RegBND.
 678         (opcode_modifiers): Add BNDPrefixOk.
 679         (operand_types): Add RegBND.
 680         * i386-init.h: Regenerate.
 681         * i386-opc.h (CpuMPX): New.
 682         (CpuUnused): Comment out.
 683         (i386_cpu_flags): Add cpumpx.
 684         (BNDPrefixOk): New.
 685         (i386_opcode_modifier): Add bndprefixok.
 686         (RegBND): New.
 687         (i386_operand_type): Add regbnd.
 688         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 689         Add MPX instructions and bnd prefix.
 690         * i386-reg.tbl: Add bnd0-bnd3 registers.
 691         * i386-tbl.h: Regenerate.
 692
 693 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 694
 695         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 696         ATTRIBUTE_UNUSED.
 697
 698 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 699
 700         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 701         special rules.
 702         * Makefile.in: Regenerate.
 703         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 704         all fields.  Reformat.
 705
 706 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 707
 708         * mips16-opc.c: Include mips-formats.h.
 709         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 710         static arrays.
 711         (decode_mips16_operand): New function.
 712         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 713         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 714         Abort for OP_SAVE_RESTORE_LIST.
 715         (print_mips16_insn_arg): Change interface.  Use mips_operand
 716         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 717         (print_insn_mips16): ...here.  Call init_print_arg_state.
 718         Update the call to print_mips16_insn_arg.
 719
 720 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 721
 722         * mips-formats.h: New file.
 723         * mips-opc.c: Include mips-formats.h.
 724         (reg_0_map): New static array.
 725         (decode_mips_operand): New function.
 726         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 727         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 728         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 729         (int_c_map): New static arrays.
 730         (decode_micromips_operand): New function.
 731         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 732         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 733         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 734         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 735         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 736         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 737         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 738         (print_reg): New function.
 739         (mips_print_arg_state): New structure.
 740         (init_print_arg_state, print_insn_arg): New functions.
 741         (print_insn_args): Change interface and use mips_operand structures.
 742         Delete GET_OP_S.  Move GET_OP definition to...
 743         (print_insn_mips): ...here.  Update the call to print_insn_args.
 744         (print_insn_micromips): Use print_insn_args.
 745
 746 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 747
 748         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 749         in macros.
 750
 751 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 752
 753         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 754         ADDA.S, MULA.S and SUBA.S.
 755
 756 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 757
 758         PR gas/13572
 759         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 760         * i386-tbl.h: Regenerated.
 761
 762 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 763
 764         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 765         and SD A(B) macros up.
 766         * micromips-opc.c (micromips_opcodes): Likewise.
 767
 768 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 769
 770         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 771         instructions.
 772
 773 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 774
 775         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 776         MDMX-like instructions.
 777         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 778         printing "Q" operands for INSN_5400 instructions.
 779
 780 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 781
 782         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 783         "+S" for "cins".
 784         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 785         Combine cases.
 786
 787 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 788
 789         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 790         "jalx".
 791         * mips16-opc.c (mips16_opcodes): Likewise.
 792         * micromips-opc.c (micromips_opcodes): Likewise.
 793         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 794         (print_insn_mips16): Handle "+i".
 795         (print_insn_micromips): Likewise.  Conditionally preserve the
 796         ISA bit for "a" but not for "+i".
 797
 798 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 799
 800         * micromips-opc.c (WR_mhi): Rename to..
 801         (WR_mh): ...this.
 802         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 803         "mh,mi" with "mh".
 804         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 805         (micromips_to_32_reg_h_map1): ...this.
 806         (micromips_to_32_reg_i_map): Rename to...
 807         (micromips_to_32_reg_h_map2): ...this.
 808         (print_micromips_insn): Remove "mi" case.  Print both registers
 809         in the pair for "mh".
 810
 811 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 812
 813         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 814         * micromips-opc.c (micromips_opcodes): Likewise.
 815         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 816         and "+T" handling.  Check for a "0" suffix when deciding whether to
 817         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 818
 819 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 820
 821         * s390-opc.c (J12_12, J24_24): New macros.
 822         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 823         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 824         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 825
 826 2013-07-04  Alan Modra  <amodra@gmail.com>
 827
 828         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 829
 830 2013-06-26  Nick Clifton  <nickc@redhat.com>
 831
 832         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 833         field when checking for type 2 nop.
 834         * rx-decode.c: Regenerate.
 835
 836 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 837
 838         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 839         and "movep" macros.
 840
 841 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 842
 843         * mips-dis.c (is_mips16_plt_tail): New function.
 844         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 845         word.
 846         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 847
 848 2013-06-21  DJ Delorie  <dj@redhat.com>
 849
 850         * msp430-decode.opc: New.
 851         * msp430-decode.c: New/generated.
 852         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 853         (MAINTAINER_CLEANFILES): Likewise.
 854         Add rule to build msp430-decode.c frommsp430decode.opc
 855         using the opc2c program.
 856         * Makefile.in: Regenerate.
 857         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 858         * configure: Regenerate.
 859
 860 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 861
 862         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 863         (SYMTAB_AVAILABLE): Removed.
 864         (#include "elf/aarch64.h): Ditto.
 865
 866 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 867             Maciej W. Rozycki  <macro@codesourcery.com>
 868             Chao-Ying Fu  <fu@mips.com>
 869
 870         * micromips-opc.c (EVA): Define.
 871         (TLBINV): Define.
 872         (micromips_opcodes): Add EVA opcodes.
 873         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 874         (print_insn_args): Handle EVA offsets.
 875         (print_insn_micromips): Likewise.
 876         * mips-opc.c (EVA): Define.
 877         (TLBINV): Define.
 878         (mips_builtin_opcodes): Add EVA opcodes.
 879
 880 2013-06-17  Alan Modra  <amodra@gmail.com>
 881
 882         * Makefile.am (mips-opc.lo): Add rules to create automatic
 883         dependency files.  Pass archdefs.
 884         (micromips-opc.lo, mips16-opc.lo): Likewise.
 885         * Makefile.in: Regenerate.
 886
 887 2013-06-14  DJ Delorie  <dj@redhat.com>
 888
 889         * rx-decode.opc (rx_decode_opcode): Bit operations on
 890         registers are 32-bit operations, not 8-bit operations.
 891         * rx-decode.c: Regenerate.
 892
 893 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 894
 895         * micromips-opc.c (IVIRT): New define.
 896         (IVIRT64): New define.
 897         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 898         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 899
 900         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 901         dmtgc0 to print cp0 names.
 902
 903 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 904
 905         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 906         argument.
 907
 908 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 909             Richard Sandiford  <rdsandiford@googlemail.com>
 910
 911         * micromips-opc.c (D32, D33, MC): Update definitions.
 912         (micromips_opcodes):  Initialize ase field.
 913         * mips-dis.c (mips_arch_choice): Add ase field.
 914         (mips_arch_choices): Initialize ase field.
 915         (set_default_mips_dis_options): Declare and setup mips_ase.
 916         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 917         MT32, MC): Update definitions.
 918         (mips_builtin_opcodes): Initialize ase field.
 919
 920 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 921
 922         * s390-opc.txt (flogr): Require a register pair destination.
 923
 924 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 925
 926         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 927         instruction format.
 928
 929 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 930
 931         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 932
 933 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 934
 935         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 936         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 937         XLS_MASK, PPCVSX2): New defines.
 938         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 939         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 940         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 941         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 942         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 943         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 944         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 945         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 946         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 947         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 948         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 949         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 950         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 951         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 952         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 953         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 954         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 955         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 956         <lxvx, stxvx>: New extended mnemonics.
 957
 958 2013-05-17  Alan Modra  <amodra@gmail.com>
 959
 960         * ia64-raw.tbl: Replace non-ASCII char.
 961         * ia64-waw.tbl: Likewise.
 962         * ia64-asmtab.c: Regenerate.
 963
 964 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 965
 966         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 967         * i386-init.h: Regenerated.
 968
 969 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 970
 971         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 972         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 973         check from [0, 255] to [-128, 255].
 974
 975 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 976
 977         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 978         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 979         (parse_mips_dis_option): Handle the virt option.
 980         (print_insn_args): Handle "+J".
 981         (print_mips_disassembler_options): Print out message about virt64.
 982         * mips-opc.c (IVIRT): New define.
 983         (IVIRT64): New define.
 984         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 985         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 986         Move rfe to the bottom as it conflicts with tlbgp.
 987
 988 2013-05-09  Alan Modra  <amodra@gmail.com>
 989
 990         * ppc-opc.c (extract_vlesi): Properly sign extend.
 991         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 992
 993 2013-05-02  Nick Clifton  <nickc@redhat.com>
 994
 995         * msp430-dis.c: Add support for MSP430X instructions.
 996
 997 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 998
 999         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
1000         to "eccinj".
1001
1002 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
1003
1004         PR binutils/15369
1005         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
1006         of CGEN_CPU_ENDIAN.
1007         (hash_insns_list): Likewise.
1008
1009 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
1010
1011         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
1012         warning workaround.
1013
1014 2013-04-08  Jan Beulich <jbeulich@suse.com>
1015
1016         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
1017         * i386-tbl.h: Re-generate.
1018
1019 2013-04-06  David S. Miller  <davem@davemloft.net>
1020
1021         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
1022         of an opcode, prefer the one with F_PREFERRED set.
1023         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
1024         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
1025         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
1026         mark existing mnenomics as aliases.  Add "cc" suffix to edge
1027         instructions generating condition codes, mark existing mnenomics
1028         as aliases.  Add "fp" prefix to VIS compare instructions, mark
1029         existing mnenomics as aliases.
1030
1031 2013-04-03  Nick Clifton  <nickc@redhat.com>
1032
1033         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
1034         destination address by subtracting the operand from the current
1035         address.
1036         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
1037         a positive value in the insn.
1038         (extract_u16_loop): Do not negate the returned value.
1039         (D16_LOOP): Add V850_INVERSE_PCREL flag.
1040
1041         (ceilf.sw): Remove duplicate entry.
1042         (cvtf.hs): New entry.
1043         (cvtf.sh): Likewise.
1044         (fmaf.s): Likewise.
1045         (fmsf.s): Likewise.
1046         (fnmaf.s): Likewise.
1047         (fnmsf.s): Likewise.
1048         (maddf.s): Restrict to E3V5 architectures.
1049         (msubf.s): Likewise.
1050         (nmaddf.s): Likewise.
1051         (nmsubf.s): Likewise.
1052
1053 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
1054
1055         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
1056         check address mode.
1057         (print_insn): Pass sizeflag to get_sib.
1058
1059 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
1060
1061         PR binutils/15068
1062         * tic6x-dis.c: Add support for displaying 16-bit insns.
1063
1064 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
1065
1066         PR gas/15095
1067         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1068         individual msb and lsb halves in src1 & src2 fields.  Discard the
1069         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1070         follow what Ti SDK does in that case as any value in the src1
1071         field yields the same output with SDK disassembler.
1072
1073 2013-03-12  Michael Eager <eager@eagercon.com>
1074
1075         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
1076
1077 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1078
1079         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1080
1081 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1082
1083         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1084
1085 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1086
1087         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1088
1089 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1090
1091         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1092         (thumb32_opcodes): Likewise.
1093         (print_insn_thumb32): Handle 'S' control char.
1094
1095 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
1096
1097         * lm32-desc.c: Regenerate.
1098
1099 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1100
1101         * i386-reg.tbl (riz): Add RegRex64.
1102         * i386-tbl.h: Regenerated.
1103
1104 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
1105
1106         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1107         (aarch64_feature_crc): New static.
1108         (CRC): New macro.
1109         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1110         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1111         * aarch64-asm-2.c: Re-generate.
1112         * aarch64-dis-2.c: Ditto.
1113         * aarch64-opc-2.c: Ditto.
1114
1115 2013-02-27  Alan Modra  <amodra@gmail.com>
1116
1117         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1118         * rl78-decode.c: Regenerate.
1119
1120 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
1121
1122         * rl78-decode.opc: Fix encoding of DIVWU insn.
1123         * rl78-decode.c: Regenerate.
1124
1125 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
1126
1127         PR gas/15159
1128         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1129
1130         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1131         (cpu_flags): Add CpuSMAP.
1132
1133         * i386-opc.h (CpuSMAP): New.
1134         (i386_cpu_flags): Add cpusmap.
1135
1136         * i386-opc.tbl: Add clac and stac.
1137
1138         * i386-init.h: Regenerated.
1139         * i386-tbl.h: Likewise.
1140
1141 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
1142
1143         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1144         which also makes the disassembler output be in little
1145         endian like it should be.
1146
1147 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
1148
1149         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1150         fields to NULL.
1151         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1152
1153 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
1154
1155         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1156         section disassembled.
1157
1158 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1159
1160         * arm-dis.c: Update strht pattern.
1161
1162 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
1163
1164         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1165         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
1166         trunc.w.s macro for EE.
1167
1168 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1169             Andrew Jenner <andrew@codesourcery.com>
1170
1171         Based on patches from Altera Corporation.
1172
1173         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1174         nios2-opc.c.
1175         * Makefile.in: Regenerated.
1176         * configure.in: Add case for bfd_nios2_arch.
1177         * configure: Regenerated.
1178         * disassemble.c (ARCH_nios2): Define.
1179         (disassembler): Add case for bfd_arch_nios2.
1180         * nios2-dis.c: New file.
1181         * nios2-opc.c: New file.
1182
1183 2013-02-04  Alan Modra  <amodra@gmail.com>
1184
1185         * po/POTFILES.in: Regenerate.
1186         * rl78-decode.c: Regenerate.
1187         * rx-decode.c: Regenerate.
1188
1189 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1190
1191         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1192         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1193         * aarch64-asm.c (convert_xtl_to_shll): New function.
1194         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1195         calling convert_xtl_to_shll.
1196         * aarch64-dis.c (convert_shll_to_xtl): New function.
1197         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1198         calling convert_shll_to_xtl.
1199         * aarch64-gen.c: Update copyright year.
1200         * aarch64-asm-2.c: Re-generate.
1201         * aarch64-dis-2.c: Re-generate.
1202         * aarch64-opc-2.c: Re-generate.
1203
1204 2013-01-24  Nick Clifton  <nickc@redhat.com>
1205
1206         * v850-dis.c: Add support for e3v5 architecture.
1207         * v850-opc.c: Likewise.
1208
1209 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1210
1211         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1212         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1213         * aarch64-opc.c (operand_general_constraint_met_p): For
1214         AARCH64_MOD_LSL, move the range check on the shift amount before the
1215         alignment check; change to call set_sft_amount_out_of_range_error
1216         instead of set_imm_out_of_range_error.
1217         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1218         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1219         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1220         SIMD_IMM_SFT.
1221
1222 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1223
1224         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1225
1226         * i386-init.h: Regenerated.
1227         * i386-tbl.h: Likewise.
1228
1229 2013-01-15  Nick Clifton  <nickc@redhat.com>
1230
1231         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1232         values.
1233         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1234
1235 2013-01-14  Will Newton <will.newton@imgtec.com>
1236
1237         * metag-dis.c (REG_WIDTH): Increase to 64.
1238
1239 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1240
1241         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1242         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1243         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1244         (SH6): Update.
1245         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1246         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1247         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1248         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1249
1250 2013-01-10  Will Newton <will.newton@imgtec.com>
1251
1252         * Makefile.am: Add Meta.
1253         * configure.in: Add Meta.
1254         * disassemble.c: Add Meta support.
1255         * metag-dis.c: New file.
1256         * Makefile.in: Regenerate.
1257         * configure: Regenerate.
1258
1259 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1260
1261         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1262         (match_opcode): Rename to cr16_match_opcode.
1263
1264 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1265
1266         * mips-dis.c: Add names for CP0 registers of r5900.
1267         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1268         instructions sq and lq.
1269         Add support for MIPS r5900 CPU.
1270         Add support for 128 bit MMI (Multimedia Instructions).
1271         Add support for EE instructions (Emotion Engine).
1272         Disable unsupported floating point instructions (64 bit and
1273         undefined compare operations).
1274         Enable instructions of MIPS ISA IV which are supported by r5900.
1275         Disable 64 bit co processor instructions.
1276         Disable 64 bit multiplication and division instructions.
1277         Disable instructions for co-processor 2 and 3, because these are
1278         not supported (preparation for later VU0 support (Vector Unit)).
1279         Disable cvt.w.s because this behaves like trunc.w.s and the
1280         correct execution can't be ensured on r5900.
1281         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1282         will confuse less developers and compilers.
1283
1284 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1285
1286         * aarch64-opc.c (aarch64_print_operand): Change to print
1287         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1288         in comment.
1289         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1290         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1291         OP_MOV_IMM_WIDE.
1292
1293 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1294
1295         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1296         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1297
1298 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1299
1300         * i386-gen.c (process_copyright): Update copyright year to 2013.
1301
1302 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1303
1304         * cr16-dis.c (match_opcode,make_instruction): Remove static
1305         declaration.
1306         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1307         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1308
1309 For older changes see ChangeLog-2012
1310 \f
1311 Copyright (C) 2013 Free Software Foundation, Inc.
1312
1313 Copying and distribution of this file, with or without modification,
1314 are permitted in any medium without royalty provided the copyright
1315 notice and this notice are preserved.
1316
1317 Local Variables:
1318 mode: change-log
1319 left-margin: 8
1320 fill-column: 74
1321 version-control: never
1322 End: