opcodes/ChangeLog

   1 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
   2
   3         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
   4
   5 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
   6
   7         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
   8
   9 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  10
  11         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
  12         loongson3a as an alias of gs464 for compatibility.
  13         * mips-opc.c (mips_opcodes): Change Comments.
  14
  15 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  16
  17         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
  18         option.
  19         (print_mips_disassembler_options): Document -M loongson-ext.
  20         * mips-opc.c (LEXT2): New macro.
  21         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
  22
  23 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  24
  25          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
  26          descriptors.
  27          (parse_mips_ase_option): Handle -M loongson-ext option.
  28          (print_mips_disassembler_options): Document -M loongson-ext.
  29          * mips-opc.c (IL3A): Delete.
  30          * mips-opc.c (LEXT): New macro.
  31          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
  32          instructions.
  33
  34 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  35
  36         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
  37         descriptors.
  38         (parse_mips_ase_option): Handle -M loongson-cam option.
  39         (print_mips_disassembler_options): Document -M loongson-cam.
  40         * mips-opc.c (LCAM): New macro.
  41         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
  42         instructions.
  43
  44 2018-08-21  Alan Modra  <amodra@gmail.com>
  45
  46         * ppc-dis.c (operand_value_powerpc): Init "invalid".
  47         (skip_optional_operands): Count optional operands, and update
  48         ppc_optional_operand_value call.
  49         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
  50         (extract_vlensi): Likewise.
  51         (extract_fxm): Return default value for missing optional operand.
  52         (extract_ls, extract_raq, extract_tbr): Likewise.
  53         (insert_sxl, extract_sxl): New functions.
  54         (insert_esync, extract_esync): Remove Power9 handling and simplify.
  55         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
  56         flag and extra entry.
  57         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
  58         extract_sxl.
  59
  60 2018-08-20  Alan Modra  <amodra@gmail.com>
  61
  62         * sh-opc.h (MASK): Simplify.
  63
  64 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
  65
  66         * s12z-dis.c (bm_decode): Deal with cases where the mode is
  67         BM_RESERVED0 or BM_RESERVED1
  68         (bm_rel_decode, bm_n_bytes): Ditto.
  69
  70 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
  71
  72         * s12z.h: Delete.
  73
  74 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
  75
  76         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
  77         address with the addr32 prefix and without base nor index
  78         registers.
  79
  80 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
  81
  82         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
  83         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
  84         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
  85         (cpu_flags): Add CpuCMOV and CpuFXSR.
  86         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
  87         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
  88         * i386-init.h: Regenerated.
  89         * i386-tbl.h: Likewise.
  90
  91 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
  92
  93         * arc-regs.h: Update auxiliary registers.
  94
  95 2018-08-06  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
  98         (RegIP, RegIZ): Define.
  99         * i386-reg.tbl: Adjust comments.
 100         (rip): Use Qword instead of BaseIndex. Use RegIP.
 101         (eip): Use Dword instead of BaseIndex. Use RegIP.
 102         (riz): Add Qword. Use RegIZ.
 103         (eiz): Add Dword. Use RegIZ.
 104         * i386-tbl.h: Re-generate.
 105
 106 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 107
 108         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 109         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 110         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 111         * i386-tbl.h: Re-generate.
 112
 113 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-gen.c (operand_types): Remove Mem field.
 116         * i386-opc.h (union i386_operand_type): Remove mem field.
 117         * i386-init.h, i386-tbl.h: Re-generate.
 118
 119 2018-08-01  Alan Modra  <amodra@gmail.com>
 120
 121         * po/POTFILES.in: Regenerate.
 122
 123 2018-07-31  Nick Clifton  <nickc@redhat.com>
 124
 125         * po/sv.po: Updated Swedish translation.
 126
 127 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 128
 129         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 130         * i386-init.h, i386-tbl.h: Re-generate.
 131
 132 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 133
 134         * i386-opc.h (ZEROING_MASKING) Rename to ...
 135         (DYNAMIC_MASKING): ... this. Adjust comment.
 136         * i386-opc.tbl (MaskingMorZ): Define.
 137         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 138         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 139         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 140         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 141         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 142         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 143         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 144         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 145         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 146
 147 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 148
 149         * i386-opc.tbl: Use element rather than vector size for AVX512*
 150         scatter/gather insns.
 151         * i386-tbl.h: Re-generate.
 152
 153 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 154
 155         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 156         (cpu_flags): Drop CpuVREX.
 157         * i386-opc.h (CpuVREX): Delete.
 158         (union i386_cpu_flags): Remove cpuvrex.
 159         * i386-init.h, i386-tbl.h: Re-generate.
 160
 161 2018-07-30  Jim Wilson  <jimw@sifive.com>
 162
 163         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 164         fields.
 165         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 166
 167 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 168
 169         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 170         * Makefile.in: Regenerated.
 171         * configure.ac: Add C-SKY.
 172         * configure: Regenerated.
 173         * csky-dis.c: New file.
 174         * csky-opc.h: New file.
 175         * disassemble.c (ARCH_csky): Define.
 176         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 177         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 178
 179 2018-07-27  Alan Modra  <amodra@gmail.com>
 180
 181         * ppc-opc.c (insert_sprbat): Correct function parameter and
 182         return type.
 183         (extract_sprbat): Likewise, variable too.
 184
 185 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 186             Alan Modra  <amodra@gmail.com>
 187
 188         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 189         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 190         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 191         support disjointed BAT.
 192         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 193         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 194         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 195
 196 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 197             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 198
 199         * i386-gen.c (adjust_broadcast_modifier): New function.
 200         (process_i386_opcode_modifier): Add an argument for operands.
 201         Adjust the Broadcast value based on operands.
 202         (output_i386_opcode): Pass operand_types to
 203         process_i386_opcode_modifier.
 204         (process_i386_opcodes): Pass NULL as operands to
 205         process_i386_opcode_modifier.
 206         * i386-opc.h (BYTE_BROADCAST): New.
 207         (WORD_BROADCAST): Likewise.
 208         (DWORD_BROADCAST): Likewise.
 209         (QWORD_BROADCAST): Likewise.
 210         (i386_opcode_modifier): Expand broadcast to 3 bits.
 211         * i386-tbl.h: Regenerated.
 212
 213 2018-07-24  Alan Modra  <amodra@gmail.com>
 214
 215         PR 23430
 216         * or1k-desc.h: Regenerate.
 217
 218 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 219
 220         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 221         vcvtusi2ss, and vcvtusi2sd.
 222         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 223         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 224         * i386-tbl.h: Re-generate.
 225
 226 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 227
 228         * arc-opc.c (extract_w6): Fix extending the sign.
 229
 230 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 231
 232         * arc-tbl.h (vewt): Allow it for ARC EM family.
 233
 234 2018-07-23  Alan Modra  <amodra@gmail.com>
 235
 236         PR 23419
 237         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 238         opcode variants for mtspr/mfspr encodings.
 239
 240 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 241             Maciej W. Rozycki  <macro@mips.com>
 242
 243         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 244         loongson3a descriptors.
 245         (parse_mips_ase_option): Handle -M loongson-mmi option.
 246         (print_mips_disassembler_options): Document -M loongson-mmi.
 247         * mips-opc.c (LMMI): New macro.
 248         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 249         instructions.
 250
 251 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 254         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 255         IgnoreSize and [XYZ]MMword where applicable.
 256         * i386-tbl.h: Re-generate.
 257
 258 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 261         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 262         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 263         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 264         * i386-tbl.h: Re-generate.
 265
 266 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 269         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 270         VPCLMULQDQ templates into their respective AVX512VL counterparts
 271         where possible, using Disp8ShiftVL and CheckRegSize instead of
 272         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 273         * i386-tbl.h: Re-generate.
 274
 275 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 276
 277         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 278         AVX512VL counterparts where possible, using Disp8ShiftVL and
 279         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 280         IgnoreSize) as appropriate.
 281         * i386-tbl.h: Re-generate.
 282
 283 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 284
 285         * i386-opc.tbl: Fold AVX512BW templates into their respective
 286         AVX512VL counterparts where possible, using Disp8ShiftVL and
 287         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 288         IgnoreSize) as appropriate.
 289         * i386-tbl.h: Re-generate.
 290
 291 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 292
 293         * i386-opc.tbl: Fold AVX512CD templates into their respective
 294         AVX512VL counterparts where possible, using Disp8ShiftVL and
 295         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 296         IgnoreSize) as appropriate.
 297         * i386-tbl.h: Re-generate.
 298
 299 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 300
 301         * i386-opc.h (DISP8_SHIFT_VL): New.
 302         * i386-opc.tbl (Disp8ShiftVL):  Define.
 303         (various): Fold AVX512VL templates into their respective
 304         AVX512F counterparts where possible, using Disp8ShiftVL and
 305         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 306         IgnoreSize) as appropriate.
 307         * i386-tbl.h: Re-generate.
 308
 309 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 310
 311         * Makefile.am: Change dependencies and rule for
 312         $(srcdir)/i386-init.h.
 313         * Makefile.in: Re-generate.
 314         * i386-gen.c (process_i386_opcodes): New local variable
 315         "marker". Drop opening of input file. Recognize marker and line
 316         number directives.
 317         * i386-opc.tbl (OPCODE_I386_H): Define.
 318         (i386-opc.h): Include it.
 319         (None): Undefine.
 320
 321 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 322
 323         PR gas/23418
 324         * i386-opc.h (Byte): Update comments.
 325         (Word): Likewise.
 326         (Dword): Likewise.
 327         (Fword): Likewise.
 328         (Qword): Likewise.
 329         (Tbyte): Likewise.
 330         (Xmmword): Likewise.
 331         (Ymmword): Likewise.
 332         (Zmmword): Likewise.
 333         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 334         vcvttps2uqq.
 335         * i386-tbl.h: Regenerated.
 336
 337 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 338
 339         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 340         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 341         * aarch64-asm-2.c: Regenerate.
 342         * aarch64-dis-2.c: Regenerate.
 343         * aarch64-opc-2.c: Regenerate.
 344
 345 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 346
 347         PR binutils/23192
 348         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 349         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 350         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 351         sqdmulh, sqrdmulh): Use Em16.
 352
 353 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 354
 355         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 356         csdb together with them.
 357         (thumb32_opcodes): Likewise.
 358
 359 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 360
 361         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 362         requiring 32-bit registers as operands 2 and 3. Improve
 363         comments.
 364         (mwait, mwaitx): Fold templates. Improve comments.
 365         OPERAND_TYPE_INOUTPORTREG.
 366         * i386-tbl.h: Re-generate.
 367
 368 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 369
 370         * i386-gen.c (operand_type_init): Remove
 371         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 372         OPERAND_TYPE_INOUTPORTREG.
 373         * i386-init.h: Re-generate.
 374
 375 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 376
 377         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 378         (wrssq, wrussq): Add Qword.
 379         * i386-tbl.h: Re-generate.
 380
 381 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 382
 383         * i386-opc.h: Rename OTMax to OTNum.
 384         (OTNumOfUints): Adjust calculation.
 385         (OTUnused): Directly alias to OTNum.
 386
 387 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 388
 389         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 390         `reg_xys'.
 391         (lea_reg_xys): Likewise.
 392         (print_insn_loop_primitive): Rename `reg' local variable to
 393         `reg_dxy'.
 394
 395 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 396
 397         PR binutils/23242
 398         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 399
 400 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 401
 402         PR binutils/23369
 403         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 404         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 405
 406 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 407
 408         PR tdep/8282
 409         * mips-dis.c (mips_option_arg_t): New enumeration.
 410         (mips_options): New variable.
 411         (disassembler_options_mips): New function.
 412         (print_mips_disassembler_options): Reimplement in terms of
 413         `disassembler_options_mips'.
 414         * arm-dis.c (disassembler_options_arm): Adapt to using the
 415         `disasm_options_and_args_t' structure.
 416         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 417         * s390-dis.c (disassembler_options_s390): Likewise.
 418
 419 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 420
 421         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 422         expected result.
 423         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 424         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 425         * testsuite/ld-arm/tls-longplt.d: Likewise.
 426
 427 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 428
 429         PR binutils/23192
 430         * aarch64-asm-2.c: Regenerate.
 431         * aarch64-dis-2.c: Likewise.
 432         * aarch64-opc-2.c: Likewise.
 433         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 434         * aarch64-opc.c (operand_general_constraint_met_p,
 435         aarch64_print_operand): Likewise.
 436         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 437         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 438         fmlal2, fmlsl2.
 439         (AARCH64_OPERANDS): Add Em2.
 440
 441 2018-06-26  Nick Clifton  <nickc@redhat.com>
 442
 443         * po/uk.po: Updated Ukranian translation.
 444         * po/de.po: Updated German translation.
 445         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 446
 447 2018-06-26  Nick Clifton  <nickc@redhat.com>
 448
 449         * nfp-dis.c: Fix spelling mistake.
 450
 451 2018-06-24  Nick Clifton  <nickc@redhat.com>
 452
 453         * configure: Regenerate.
 454         * po/opcodes.pot: Regenerate.
 455
 456 2018-06-24  Nick Clifton  <nickc@redhat.com>
 457
 458         2.31 branch created.
 459
 460 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 461
 462         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 463         * aarch64-asm-2.c: Regenerate.
 464         * aarch64-dis-2.c: Likewise.
 465
 466 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 467
 468         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 469         `-M ginv' option description.
 470
 471 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 472
 473         PR gas/23305
 474         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 475         la and lla.
 476
 477 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 478
 479         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 480         * configure.ac: Remove AC_PREREQ.
 481         * Makefile.in: Re-generate.
 482         * aclocal.m4: Re-generate.
 483         * configure: Re-generate.
 484
 485 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 486
 487         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 488         mips64r6 descriptors.
 489         (parse_mips_ase_option): Handle -Mginv option.
 490         (print_mips_disassembler_options): Document -Mginv.
 491         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 492         (GINV): New macro.
 493         (mips_opcodes): Define ginvi and ginvt.
 494
 495 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 496             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 497
 498         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 499         * mips-opc.c (CRC, CRC64): New macros.
 500         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 501         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 502         crc32cd for CRC64.
 503
 504 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 505
 506         PR 20319
 507         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 508         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 509
 510 2018-06-06  Alan Modra  <amodra@gmail.com>
 511
 512         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 513         setjmp.  Move init for some other vars later too.
 514
 515 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 516
 517         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 518         (dis_private): Add new fields for property section tracking.
 519         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 520         (xtensa_instruction_fits): New functions.
 521         (fetch_data): Bump minimal fetch size to 4.
 522         (print_insn_xtensa): Make struct dis_private static.
 523         Load and prepare property table on section change.
 524         Don't disassemble literals. Don't disassemble instructions that
 525         cross property table boundaries.
 526
 527 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         * configure: Regenerated.
 530
 531 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 532
 533         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 534         * i386-tbl.h: Re-generate.
 535
 536 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 537
 538         * i386-opc.tbl (sldt, str): Add NoRex64.
 539         * i386-tbl.h: Re-generate.
 540
 541 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 542
 543         * i386-opc.tbl (invpcid): Add Oword.
 544         * i386-tbl.h: Re-generate.
 545
 546 2018-06-01  Alan Modra  <amodra@gmail.com>
 547
 548         * sysdep.h (_bfd_error_handler): Don't declare.
 549         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 550         * rl78-decode.opc: Likewise.
 551         * msp430-decode.c: Regenerate.
 552         * rl78-decode.c: Regenerate.
 553
 554 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 555
 556         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 557         * i386-init.h : Regenerated.
 558
 559 2018-05-25  Alan Modra  <amodra@gmail.com>
 560
 561         * Makefile.in: Regenerate.
 562         * po/POTFILES.in: Regenerate.
 563
 564 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 565
 566         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 567         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 568         (insert_bab, extract_bab, insert_btab, extract_btab,
 569         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 570         (BAT, BBA VBA RBS XB6S): Delete macros.
 571         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 572         (BB, BD, RBX, XC6): Update for new macros.
 573         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 574         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 575         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 576         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 577
 578 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 579
 580         * Makefile.am: Add support for s12z architecture.
 581         * configure.ac: Likewise.
 582         * disassemble.c: Likewise.
 583         * disassemble.h: Likewise.
 584         * Makefile.in: Regenerate.
 585         * configure: Regenerate.
 586         * s12z-dis.c: New file.
 587         * s12z.h: New file.
 588
 589 2018-05-18  Alan Modra  <amodra@gmail.com>
 590
 591         * nfp-dis.c: Don't #include libbfd.h.
 592         (init_nfp3200_priv): Use bfd_get_section_contents.
 593         (nit_nfp6000_mecsr_sec): Likewise.
 594
 595 2018-05-17  Nick Clifton  <nickc@redhat.com>
 596
 597         * po/zh_CN.po: Updated simplified Chinese translation.
 598
 599 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 600
 601         PR binutils/23109
 602         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 603         * aarch64-dis-2.c: Regenerate.
 604
 605 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 606
 607         PR binutils/21446
 608         * aarch64-asm.c (opintl.h): Include.
 609         (aarch64_ins_sysreg): Enforce read/write constraints.
 610         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 611         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 612         (F_REG_READ, F_REG_WRITE): New.
 613         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 614         AARCH64_OPND_SYSREG.
 615         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 616         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 617         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 618         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 619         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 620         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 621         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 622         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 623         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 624         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 625         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 626         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 627         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 628         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 629         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 630         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 631         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 632
 633 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 634
 635         PR binutils/21446
 636         * aarch64-dis.c (no_notes: New.
 637         (parse_aarch64_dis_option): Support notes.
 638         (aarch64_decode_insn, print_operands): Likewise.
 639         (print_aarch64_disassembler_options): Document notes.
 640         * aarch64-opc.c (aarch64_print_operand): Support notes.
 641
 642 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 643
 644         PR binutils/21446
 645         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 646         and take error struct.
 647         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 648         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 649         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 650         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 651         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 652         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 653         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 654         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 655         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 656         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 657         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 658         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 659         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 660         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 661         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 662         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 663         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 664         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 665         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 666         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 667         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 668         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 669         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 670         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 671         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 672         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 673         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 674         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 675         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 676         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 677         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 678         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 679         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 680         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 681         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 682         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 683         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 684         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 685         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 686         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 687         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 688         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 689         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 690         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 691         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 692         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 693         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 694         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 695         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 696         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 697         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 698         (determine_disassembling_preference, aarch64_decode_insn,
 699         print_insn_aarch64_word, print_insn_data): Take errors struct.
 700         (print_insn_aarch64): Use errors.
 701         * aarch64-asm-2.c: Regenerate.
 702         * aarch64-dis-2.c: Regenerate.
 703         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 704         boolean in aarch64_insert_operan.
 705         (print_operand_extractor): Likewise.
 706         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 707
 708 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 709
 710         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 711
 712 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 713
 714         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 715
 716 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 717
 718         * cr16-opc.c (cr16_instruction): Comment typo fix.
 719         * hppa-dis.c (print_insn_hppa): Likewise.
 720
 721 2018-05-08  Jim Wilson  <jimw@sifive.com>
 722
 723         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 724         (match_c_slli64, match_srxi_as_c_srxi): New.
 725         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 726         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 727         <c.slli, c.srli, c.srai>: Use match_s_slli.
 728         <c.slli64, c.srli64, c.srai64>: New.
 729
 730 2018-05-08  Alan Modra  <amodra@gmail.com>
 731
 732         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 733         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 734         partition opcode space for index lookup.
 735
 736 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 737
 738         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 739         <insn_length>: ...with this.  Update usage.
 740         Remove duplicate call to *info->memory_error_func.
 741
 742 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 743             H.J. Lu  <hongjiu.lu@intel.com>
 744
 745         * i386-dis.c (Gva): New.
 746         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 747         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 748         (prefix_table): New instructions (see prefix above).
 749         (mod_table): New instructions (see prefix above).
 750         (OP_G): Handle va_mode.
 751         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 752         CPU_MOVDIR64B_FLAGS.
 753         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 754         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 755         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 756         * i386-opc.tbl: Add movidir{i,64b}.
 757         * i386-init.h: Regenerated.
 758         * i386-tbl.h: Likewise.
 759
 760 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 761
 762         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 763         AddrPrefixOpReg.
 764         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 765         (AddrPrefixOpReg): This.
 766         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 767         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 768
 769 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 770
 771         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 772         (vle_num_opcodes): Likewise.
 773         (spe2_num_opcodes): Likewise.
 774         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 775         initialization loop.
 776         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 777         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 778         only once.
 779
 780 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 781
 782         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 783
 784 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 785
 786         Makefile.am: Added nfp-dis.c.
 787         configure.ac: Added bfd_nfp_arch.
 788         disassemble.h: Added print_insn_nfp prototype.
 789         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 790         nfp-dis.c: New, for NFP support.
 791         po/POTFILES.in: Added nfp-dis.c to the list.
 792         Makefile.in: Regenerate.
 793         configure: Regenerate.
 794
 795 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 798         templates into their base ones.
 799         * i386-tlb.h: Re-generate.
 800
 801 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 802
 803         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 804         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 805         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 806         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 807         * i386-init.h: Re-generate.
 808
 809 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 810
 811         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 812         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 813         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 814         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 815         comment.
 816         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 817         and CpuRegMask.
 818         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 819         CpuRegMask: Delete.
 820         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 821         cpuregzmm, and cpuregmask.
 822         * i386-init.h: Re-generate.
 823         * i386-tbl.h: Re-generate.
 824
 825 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 826
 827         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 828         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 829         * i386-init.h: Re-generate.
 830
 831 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 832
 833         * i386-gen.c (VexImmExt): Delete.
 834         * i386-opc.h (VexImmExt, veximmext): Delete.
 835         * i386-opc.tbl: Drop all VexImmExt uses.
 836         * i386-tlb.h: Re-generate.
 837
 838 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 839
 840         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 841         register-only forms.
 842         * i386-tlb.h: Re-generate.
 843
 844 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 845
 846         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 847
 848 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 849
 850         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 851         PREFIX_0F1C.
 852         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 853         (cpu_flags): Add CpuCLDEMOTE.
 854         * i386-init.h: Regenerate.
 855         * i386-opc.h (enum): Add CpuCLDEMOTE,
 856         (i386_cpu_flags): Add cpucldemote.
 857         * i386-opc.tbl: Add cldemote.
 858         * i386-tbl.h: Regenerate.
 859
 860 2018-04-16  Alan Modra  <amodra@gmail.com>
 861
 862         * Makefile.am: Remove sh5 and sh64 support.
 863         * configure.ac: Likewise.
 864         * disassemble.c: Likewise.
 865         * disassemble.h: Likewise.
 866         * sh-dis.c: Likewise.
 867         * sh64-dis.c: Delete.
 868         * sh64-opc.c: Delete.
 869         * sh64-opc.h: Delete.
 870         * Makefile.in: Regenerate.
 871         * configure: Regenerate.
 872         * po/POTFILES.in: Regenerate.
 873
 874 2018-04-16  Alan Modra  <amodra@gmail.com>
 875
 876         * Makefile.am: Remove w65 support.
 877         * configure.ac: Likewise.
 878         * disassemble.c: Likewise.
 879         * disassemble.h: Likewise.
 880         * w65-dis.c: Delete.
 881         * w65-opc.h: Delete.
 882         * Makefile.in: Regenerate.
 883         * configure: Regenerate.
 884         * po/POTFILES.in: Regenerate.
 885
 886 2018-04-16  Alan Modra  <amodra@gmail.com>
 887
 888         * configure.ac: Remove we32k support.
 889         * configure: Regenerate.
 890
 891 2018-04-16  Alan Modra  <amodra@gmail.com>
 892
 893         * Makefile.am: Remove m88k support.
 894         * configure.ac: Likewise.
 895         * disassemble.c: Likewise.
 896         * disassemble.h: Likewise.
 897         * m88k-dis.c: Delete.
 898         * Makefile.in: Regenerate.
 899         * configure: Regenerate.
 900         * po/POTFILES.in: Regenerate.
 901
 902 2018-04-16  Alan Modra  <amodra@gmail.com>
 903
 904         * Makefile.am: Remove i370 support.
 905         * configure.ac: Likewise.
 906         * disassemble.c: Likewise.
 907         * disassemble.h: Likewise.
 908         * i370-dis.c: Delete.
 909         * i370-opc.c: Delete.
 910         * Makefile.in: Regenerate.
 911         * configure: Regenerate.
 912         * po/POTFILES.in: Regenerate.
 913
 914 2018-04-16  Alan Modra  <amodra@gmail.com>
 915
 916         * Makefile.am: Remove h8500 support.
 917         * configure.ac: Likewise.
 918         * disassemble.c: Likewise.
 919         * disassemble.h: Likewise.
 920         * h8500-dis.c: Delete.
 921         * h8500-opc.h: Delete.
 922         * Makefile.in: Regenerate.
 923         * configure: Regenerate.
 924         * po/POTFILES.in: Regenerate.
 925
 926 2018-04-16  Alan Modra  <amodra@gmail.com>
 927
 928         * configure.ac: Remove tahoe support.
 929         * configure: Regenerate.
 930
 931 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 932
 933         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 934         umwait.
 935         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 936         64-bit mode.
 937         * i386-tbl.h: Regenerated.
 938
 939 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 940
 941         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 942         PREFIX_MOD_1_0FAE_REG_6.
 943         (va_mode): New.
 944         (OP_E_register): Use va_mode.
 945         * i386-dis-evex.h (prefix_table):
 946         New instructions (see prefixes above).
 947         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 948         (cpu_flags): Likewise.
 949         * i386-opc.h (enum): Likewise.
 950         (i386_cpu_flags): Likewise.
 951         * i386-opc.tbl: Add umonitor, umwait, tpause.
 952         * i386-init.h: Regenerate.
 953         * i386-tbl.h: Likewise.
 954
 955 2018-04-11  Alan Modra  <amodra@gmail.com>
 956
 957         * opcodes/i860-dis.c: Delete.
 958         * opcodes/i960-dis.c: Delete.
 959         * Makefile.am: Remove i860 and i960 support.
 960         * configure.ac: Likewise.
 961         * disassemble.c: Likewise.
 962         * disassemble.h: Likewise.
 963         * Makefile.in: Regenerate.
 964         * configure: Regenerate.
 965         * po/POTFILES.in: Regenerate.
 966
 967 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 968
 969         PR binutils/23025
 970         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 971         to 0.
 972         (print_insn): Clear vex instead of vex.evex.
 973
 974 2018-04-04  Nick Clifton  <nickc@redhat.com>
 975
 976         * po/es.po: Updated Spanish translation.
 977
 978 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 979
 980         * i386-gen.c (opcode_modifiers): Delete VecESize.
 981         * i386-opc.h (VecESize): Delete.
 982         (struct i386_opcode_modifier): Delete vecesize.
 983         * i386-opc.tbl: Drop VecESize.
 984         * i386-tlb.h: Re-generate.
 985
 986 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 987
 988         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 989         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 990         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 991         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 992         * i386-tlb.h: Re-generate.
 993
 994 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 997         Fold AVX512 forms
 998         * i386-tlb.h: Re-generate.
 999
1000 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1001
1002         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1003         (vex_len_table): Drop Y for vcvt*2si.
1004         (putop): Replace plain 'Y' handling by abort().
1005
1006 2018-03-28  Nick Clifton  <nickc@redhat.com>
1007
1008         PR 22988
1009         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1010         instructions with only a base address register.
1011         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1012         handle AARHC64_OPND_SVE_ADDR_R.
1013         (aarch64_print_operand): Likewise.
1014         * aarch64-asm-2.c: Regenerate.
1015         * aarch64_dis-2.c: Regenerate.
1016         * aarch64-opc-2.c: Regenerate.
1017
1018 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1019
1020         * i386-opc.tbl: Drop VecESize from register only insn forms and
1021         memory forms not allowing broadcast.
1022         * i386-tlb.h: Re-generate.
1023
1024 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1025
1026         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1027         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1028         sha256*): Drop Disp<N>.
1029
1030 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1031
1032         * i386-dis.c (EbndS, bnd_swap_mode): New.
1033         (prefix_table): Use EbndS.
1034         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1035         * i386-opc.tbl (bndmov): Move misplaced Load.
1036         * i386-tlb.h: Re-generate.
1037
1038 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1039
1040         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1041         templates allowing memory operands and folded ones for register
1042         only flavors.
1043         * i386-tlb.h: Re-generate.
1044
1045 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1046
1047         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1048         256-bit templates. Drop redundant leftover Disp<N>.
1049         * i386-tlb.h: Re-generate.
1050
1051 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1052
1053         * riscv-opc.c (riscv_insn_types): New.
1054
1055 2018-03-13  Nick Clifton  <nickc@redhat.com>
1056
1057         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1058
1059 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1060
1061         * i386-opc.tbl: Add Optimize to clr.
1062         * i386-tbl.h: Regenerated.
1063
1064 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1065
1066         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1067         * i386-opc.h (OldGcc): Removed.
1068         (i386_opcode_modifier): Remove oldgcc.
1069         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1070         instructions for old (<= 2.8.1) versions of gcc.
1071         * i386-tbl.h: Regenerated.
1072
1073 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1074
1075         * i386-opc.h (EVEXDYN): New.
1076         * i386-opc.tbl: Fold various AVX512VL templates.
1077         * i386-tlb.h: Re-generate.
1078
1079 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1080
1081         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1082         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1083         vpexpandd, vpexpandq): Fold AFX512VF templates.
1084         * i386-tlb.h: Re-generate.
1085
1086 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1087
1088         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1089         Fold 128- and 256-bit VEX-encoded templates.
1090         * i386-tlb.h: Re-generate.
1091
1092 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1093
1094         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1095         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1096         vpexpandd, vpexpandq): Fold AVX512F templates.
1097         * i386-tlb.h: Re-generate.
1098
1099 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1100
1101         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1102         64-bit templates. Drop Disp<N>.
1103         * i386-tlb.h: Re-generate.
1104
1105 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1106
1107         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1108         and 256-bit templates.
1109         * i386-tlb.h: Re-generate.
1110
1111 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1112
1113         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1114         * i386-tlb.h: Re-generate.
1115
1116 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1117
1118         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1119         Drop NoAVX.
1120         * i386-tlb.h: Re-generate.
1121
1122 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1123
1124         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1125         * i386-tlb.h: Re-generate.
1126
1127 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1128
1129         * i386-gen.c (opcode_modifiers): Delete FloatD.
1130         * i386-opc.h (FloatD): Delete.
1131         (struct i386_opcode_modifier): Delete floatd.
1132         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1133         FloatD by D.
1134         * i386-tlb.h: Re-generate.
1135
1136 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1137
1138         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1139
1140 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1141
1142         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1143         * i386-tlb.h: Re-generate.
1144
1145 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1146
1147         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1148         forms.
1149         * i386-tlb.h: Re-generate.
1150
1151 2018-03-07  Alan Modra  <amodra@gmail.com>
1152
1153         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1154         bfd_arch_rs6000.
1155         * disassemble.h (print_insn_rs6000): Delete.
1156         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1157         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1158         (print_insn_rs6000): Delete.
1159
1160 2018-03-03  Alan Modra  <amodra@gmail.com>
1161
1162         * sysdep.h (opcodes_error_handler): Define.
1163         (_bfd_error_handler): Declare.
1164         * Makefile.am: Remove stray #.
1165         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1166         EDIT" comment.
1167         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1168         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1169         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1170         opcodes_error_handler to print errors.  Standardize error messages.
1171         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1172         and include opintl.h.
1173         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1174         * i386-gen.c: Standardize error messages.
1175         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1176         * Makefile.in: Regenerate.
1177         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1178         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1179         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1180         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1181         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1182         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1183         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1184         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1185         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1186         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1187         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1188         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1189         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1190
1191 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1192
1193         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1194         vpsub[bwdq] instructions.
1195         * i386-tbl.h: Regenerated.
1196
1197 2018-03-01  Alan Modra  <amodra@gmail.com>
1198
1199         * configure.ac (ALL_LINGUAS): Sort.
1200         * configure: Regenerate.
1201
1202 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1203
1204         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1205         macro by assignements.
1206
1207 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1208
1209         PR gas/22871
1210         * i386-gen.c (opcode_modifiers): Add Optimize.
1211         * i386-opc.h (Optimize): New enum.
1212         (i386_opcode_modifier): Add optimize.
1213         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1214         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1215         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1216         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1217         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1218         vpxord and vpxorq.
1219         * i386-tbl.h: Regenerated.
1220
1221 2018-02-26  Alan Modra  <amodra@gmail.com>
1222
1223         * crx-dis.c (getregliststring): Allocate a large enough buffer
1224         to silence false positive gcc8 warning.
1225
1226 2018-02-22  Shea Levy <shea@shealevy.com>
1227
1228         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1229
1230 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1231
1232         * i386-opc.tbl: Add {rex},
1233         * i386-tbl.h: Regenerated.
1234
1235 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1236
1237         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1238         (mips16_opcodes): Replace `M' with `m' for "restore".
1239
1240 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1241
1242         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1243
1244 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1245
1246         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1247         variable to `function_index'.
1248
1249 2018-02-13  Nick Clifton  <nickc@redhat.com>
1250
1251         PR 22823
1252         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1253         about truncation of printing.
1254
1255 2018-02-12  Henry Wong <henry@stuffedcow.net>
1256
1257         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1258
1259 2018-02-05  Nick Clifton  <nickc@redhat.com>
1260
1261         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1262
1263 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1264
1265         * i386-dis.c (enum): Add pconfig.
1266         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1267         (cpu_flags): Add CpuPCONFIG.
1268         * i386-opc.h (enum): Add CpuPCONFIG.
1269         (i386_cpu_flags): Add cpupconfig.
1270         * i386-opc.tbl: Add PCONFIG instruction.
1271         * i386-init.h: Regenerate.
1272         * i386-tbl.h: Likewise.
1273
1274 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1275
1276         * i386-dis.c (enum): Add PREFIX_0F09.
1277         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1278         (cpu_flags): Add CpuWBNOINVD.
1279         * i386-opc.h (enum): Add CpuWBNOINVD.
1280         (i386_cpu_flags): Add cpuwbnoinvd.
1281         * i386-opc.tbl: Add WBNOINVD instruction.
1282         * i386-init.h: Regenerate.
1283         * i386-tbl.h: Likewise.
1284
1285 2018-01-17  Jim Wilson  <jimw@sifive.com>
1286
1287         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1288
1289 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1290
1291         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1292         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1293         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1294         (cpu_flags): Add CpuIBT, CpuSHSTK.
1295         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1296         (i386_cpu_flags): Add cpuibt, cpushstk.
1297         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1298         * i386-init.h: Regenerate.
1299         * i386-tbl.h: Likewise.
1300
1301 2018-01-16  Nick Clifton  <nickc@redhat.com>
1302
1303         * po/pt_BR.po: Updated Brazilian Portugese translation.
1304         * po/de.po: Updated German translation.
1305
1306 2018-01-15  Jim Wilson  <jimw@sifive.com>
1307
1308         * riscv-opc.c (match_c_nop): New.
1309         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1310
1311 2018-01-15  Nick Clifton  <nickc@redhat.com>
1312
1313         * po/uk.po: Updated Ukranian translation.
1314
1315 2018-01-13  Nick Clifton  <nickc@redhat.com>
1316
1317         * po/opcodes.pot: Regenerated.
1318
1319 2018-01-13  Nick Clifton  <nickc@redhat.com>
1320
1321         * configure: Regenerate.
1322
1323 2018-01-13  Nick Clifton  <nickc@redhat.com>
1324
1325         2.30 branch created.
1326
1327 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1328
1329         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1330         * i386-tbl.h: Regenerate.
1331
1332 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1333
1334         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1335         * i386-tbl.h: Re-generate.
1336
1337 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1338
1339         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1340         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1341         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1342         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1343         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1344         Disp8MemShift of AVX512VL forms.
1345         * i386-tbl.h: Re-generate.
1346
1347 2018-01-09  Jim Wilson  <jimw@sifive.com>
1348
1349         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1350         then the hi_addr value is zero.
1351
1352 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1353
1354         * arm-dis.c (arm_opcodes): Add csdb.
1355         (thumb32_opcodes): Add csdb.
1356
1357 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1358
1359         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1360         * aarch64-asm-2.c: Regenerate.
1361         * aarch64-dis-2.c: Regenerate.
1362         * aarch64-opc-2.c: Regenerate.
1363
1364 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1365
1366         PR gas/22681
1367         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1368         Remove AVX512 vmovd with 64-bit operands.
1369         * i386-tbl.h: Regenerated.
1370
1371 2018-01-05  Jim Wilson  <jimw@sifive.com>
1372
1373         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1374         jalr.
1375
1376 2018-01-03  Alan Modra  <amodra@gmail.com>
1377
1378         Update year range in copyright notice of all files.
1379
1380 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1381
1382         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1383         and OPERAND_TYPE_REGZMM entries.
1384
1385 For older changes see ChangeLog-2017
1386 \f
1387 Copyright (C) 2018 Free Software Foundation, Inc.
1388
1389 Copying and distribution of this file, with or without modification,
1390 are permitted in any medium without royalty provided the copyright
1391 notice and this notice are preserved.
1392
1393 Local Variables:
1394 mode: change-log
1395 left-margin: 8
1396 fill-column: 74
1397 version-control: never
1398 End: