RISC-V: Add .insn support.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
2
3 * riscv-opc.c (riscv_insn_types): New.
4
5 2018-03-13 Nick Clifton <nickc@redhat.com>
6
7 * po/pt_BR.po: Updated Brazilian Portuguese translation.
8
9 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
10
11 * i386-opc.tbl: Add Optimize to clr.
12 * i386-tbl.h: Regenerated.
13
14 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
15
16 * i386-gen.c (opcode_modifiers): Remove OldGcc.
17 * i386-opc.h (OldGcc): Removed.
18 (i386_opcode_modifier): Remove oldgcc.
19 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
20 instructions for old (<= 2.8.1) versions of gcc.
21 * i386-tbl.h: Regenerated.
22
23 2018-03-08 Jan Beulich <jbeulich@suse.com>
24
25 * i386-opc.h (EVEXDYN): New.
26 * i386-opc.tbl: Fold various AVX512VL templates.
27 * i386-tlb.h: Re-generate.
28
29 2018-03-08 Jan Beulich <jbeulich@suse.com>
30
31 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
32 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
33 vpexpandd, vpexpandq): Fold AFX512VF templates.
34 * i386-tlb.h: Re-generate.
35
36 2018-03-08 Jan Beulich <jbeulich@suse.com>
37
38 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
39 Fold 128- and 256-bit VEX-encoded templates.
40 * i386-tlb.h: Re-generate.
41
42 2018-03-08 Jan Beulich <jbeulich@suse.com>
43
44 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
45 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
46 vpexpandd, vpexpandq): Fold AVX512F templates.
47 * i386-tlb.h: Re-generate.
48
49 2018-03-08 Jan Beulich <jbeulich@suse.com>
50
51 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
52 64-bit templates. Drop Disp<N>.
53 * i386-tlb.h: Re-generate.
54
55 2018-03-08 Jan Beulich <jbeulich@suse.com>
56
57 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
58 and 256-bit templates.
59 * i386-tlb.h: Re-generate.
60
61 2018-03-08 Jan Beulich <jbeulich@suse.com>
62
63 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
64 * i386-tlb.h: Re-generate.
65
66 2018-03-08 Jan Beulich <jbeulich@suse.com>
67
68 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
69 Drop NoAVX.
70 * i386-tlb.h: Re-generate.
71
72 2018-03-08 Jan Beulich <jbeulich@suse.com>
73
74 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
75 * i386-tlb.h: Re-generate.
76
77 2018-03-08 Jan Beulich <jbeulich@suse.com>
78
79 * i386-gen.c (opcode_modifiers): Delete FloatD.
80 * i386-opc.h (FloatD): Delete.
81 (struct i386_opcode_modifier): Delete floatd.
82 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
83 FloatD by D.
84 * i386-tlb.h: Re-generate.
85
86 2018-03-08 Jan Beulich <jbeulich@suse.com>
87
88 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
89
90 2018-03-08 Jan Beulich <jbeulich@suse.com>
91
92 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
93 * i386-tlb.h: Re-generate.
94
95 2018-03-08 Jan Beulich <jbeulich@suse.com>
96
97 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
98 forms.
99 * i386-tlb.h: Re-generate.
100
101 2018-03-07 Alan Modra <amodra@gmail.com>
102
103 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
104 bfd_arch_rs6000.
105 * disassemble.h (print_insn_rs6000): Delete.
106 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
107 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
108 (print_insn_rs6000): Delete.
109
110 2018-03-03 Alan Modra <amodra@gmail.com>
111
112 * sysdep.h (opcodes_error_handler): Define.
113 (_bfd_error_handler): Declare.
114 * Makefile.am: Remove stray #.
115 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
116 EDIT" comment.
117 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
118 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
119 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
120 opcodes_error_handler to print errors. Standardize error messages.
121 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
122 and include opintl.h.
123 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
124 * i386-gen.c: Standardize error messages.
125 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
126 * Makefile.in: Regenerate.
127 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
128 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
129 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
130 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
131 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
132 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
133 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
134 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
135 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
136 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
137 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
138 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
139 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
140
141 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
142
143 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
144 vpsub[bwdq] instructions.
145 * i386-tbl.h: Regenerated.
146
147 2018-03-01 Alan Modra <amodra@gmail.com>
148
149 * configure.ac (ALL_LINGUAS): Sort.
150 * configure: Regenerate.
151
152 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
153
154 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
155 macro by assignements.
156
157 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
158
159 PR gas/22871
160 * i386-gen.c (opcode_modifiers): Add Optimize.
161 * i386-opc.h (Optimize): New enum.
162 (i386_opcode_modifier): Add optimize.
163 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
164 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
165 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
166 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
167 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
168 vpxord and vpxorq.
169 * i386-tbl.h: Regenerated.
170
171 2018-02-26 Alan Modra <amodra@gmail.com>
172
173 * crx-dis.c (getregliststring): Allocate a large enough buffer
174 to silence false positive gcc8 warning.
175
176 2018-02-22 Shea Levy <shea@shealevy.com>
177
178 * disassemble.c (ARCH_riscv): Define if ARCH_all.
179
180 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
181
182 * i386-opc.tbl: Add {rex},
183 * i386-tbl.h: Regenerated.
184
185 2018-02-20 Maciej W. Rozycki <macro@mips.com>
186
187 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
188 (mips16_opcodes): Replace `M' with `m' for "restore".
189
190 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
191
192 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
193
194 2018-02-13 Maciej W. Rozycki <macro@mips.com>
195
196 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
197 variable to `function_index'.
198
199 2018-02-13 Nick Clifton <nickc@redhat.com>
200
201 PR 22823
202 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
203 about truncation of printing.
204
205 2018-02-12 Henry Wong <henry@stuffedcow.net>
206
207 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
208
209 2018-02-05 Nick Clifton <nickc@redhat.com>
210
211 * po/pt_BR.po: Updated Brazilian Portuguese translation.
212
213 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
214
215 * i386-dis.c (enum): Add pconfig.
216 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
217 (cpu_flags): Add CpuPCONFIG.
218 * i386-opc.h (enum): Add CpuPCONFIG.
219 (i386_cpu_flags): Add cpupconfig.
220 * i386-opc.tbl: Add PCONFIG instruction.
221 * i386-init.h: Regenerate.
222 * i386-tbl.h: Likewise.
223
224 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
225
226 * i386-dis.c (enum): Add PREFIX_0F09.
227 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
228 (cpu_flags): Add CpuWBNOINVD.
229 * i386-opc.h (enum): Add CpuWBNOINVD.
230 (i386_cpu_flags): Add cpuwbnoinvd.
231 * i386-opc.tbl: Add WBNOINVD instruction.
232 * i386-init.h: Regenerate.
233 * i386-tbl.h: Likewise.
234
235 2018-01-17 Jim Wilson <jimw@sifive.com>
236
237 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
238
239 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
240
241 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
242 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
243 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
244 (cpu_flags): Add CpuIBT, CpuSHSTK.
245 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
246 (i386_cpu_flags): Add cpuibt, cpushstk.
247 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
248 * i386-init.h: Regenerate.
249 * i386-tbl.h: Likewise.
250
251 2018-01-16 Nick Clifton <nickc@redhat.com>
252
253 * po/pt_BR.po: Updated Brazilian Portugese translation.
254 * po/de.po: Updated German translation.
255
256 2018-01-15 Jim Wilson <jimw@sifive.com>
257
258 * riscv-opc.c (match_c_nop): New.
259 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
260
261 2018-01-15 Nick Clifton <nickc@redhat.com>
262
263 * po/uk.po: Updated Ukranian translation.
264
265 2018-01-13 Nick Clifton <nickc@redhat.com>
266
267 * po/opcodes.pot: Regenerated.
268
269 2018-01-13 Nick Clifton <nickc@redhat.com>
270
271 * configure: Regenerate.
272
273 2018-01-13 Nick Clifton <nickc@redhat.com>
274
275 2.30 branch created.
276
277 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
278
279 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
280 * i386-tbl.h: Regenerate.
281
282 2018-01-10 Jan Beulich <jbeulich@suse.com>
283
284 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
285 * i386-tbl.h: Re-generate.
286
287 2018-01-10 Jan Beulich <jbeulich@suse.com>
288
289 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
290 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
291 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
292 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
293 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
294 Disp8MemShift of AVX512VL forms.
295 * i386-tbl.h: Re-generate.
296
297 2018-01-09 Jim Wilson <jimw@sifive.com>
298
299 * riscv-dis.c (maybe_print_address): If base_reg is zero,
300 then the hi_addr value is zero.
301
302 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
303
304 * arm-dis.c (arm_opcodes): Add csdb.
305 (thumb32_opcodes): Add csdb.
306
307 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
308
309 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
310 * aarch64-asm-2.c: Regenerate.
311 * aarch64-dis-2.c: Regenerate.
312 * aarch64-opc-2.c: Regenerate.
313
314 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
315
316 PR gas/22681
317 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
318 Remove AVX512 vmovd with 64-bit operands.
319 * i386-tbl.h: Regenerated.
320
321 2018-01-05 Jim Wilson <jimw@sifive.com>
322
323 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
324 jalr.
325
326 2018-01-03 Alan Modra <amodra@gmail.com>
327
328 Update year range in copyright notice of all files.
329
330 2018-01-02 Jan Beulich <jbeulich@suse.com>
331
332 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
333 and OPERAND_TYPE_REGZMM entries.
334
335 For older changes see ChangeLog-2017
336 \f
337 Copyright (C) 2018 Free Software Foundation, Inc.
338
339 Copying and distribution of this file, with or without modification,
340 are permitted in any medium without royalty provided the copyright
341 notice and this notice are preserved.
342
343 Local Variables:
344 mode: change-log
345 left-margin: 8
346 fill-column: 74
347 version-control: never
348 End:
This page took 0.045687 seconds and 4 git commands to generate.