opcodes/ChangeLog

   1 2019-06-25  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
   4         Delete.
   5         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
   6         of dqa_mode.
   7         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
   8         entries here.
   9         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
  10         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
  11
  12 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  13
  14         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
  15         variables.
  16
  17 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  18
  19         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
  20         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
  21         movnti.
  22         * i386-opc.tbl (movnti): Add IgnoreSize.
  23         * i386-tbl.h: Re-generate.
  24
  25 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-opc.tbl (and): Mark Imm8S form for optimization.
  28         * i386-tbl.h: Re-generate.
  29
  30 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  31
  32         * i386-dis-evex.h: Break into ...
  33         * i386-dis-evex-len.h: New file.
  34         * i386-dis-evex-mod.h: Likewise.
  35         * i386-dis-evex-prefix.h: Likewise.
  36         * i386-dis-evex-reg.h: Likewise.
  37         * i386-dis-evex-w.h: Likewise.
  38         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
  39         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
  40         i386-dis-evex-mod.h.
  41
  42 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
  43
  44         PR binutils/24700
  45         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
  46         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
  47         EVEX_W_0F385B_P_2.
  48         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
  49         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
  50         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
  51         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
  52         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
  53         EVEX_LEN_0F385B_P_2_W_1.
  54         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
  55         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
  56         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
  57         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
  58         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
  59         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
  60         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
  61         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
  62         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
  63         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
  64
  65 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         PR binutils/24691
  68         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
  69         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
  70         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
  71         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
  72         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
  73         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
  74         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
  75         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
  76         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
  77         EVEX_LEN_0F3A43_P_2_W_1.
  78         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
  79         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
  80         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
  81         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
  82         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
  83         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
  84         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
  85         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
  86         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
  87         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
  88         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
  89         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
  90
  91 2019-06-14  Nick Clifton  <nickc@redhat.com>
  92
  93         * po/fr.po; Updated French translation.
  94
  95 2019-06-13  Stafford Horne  <shorne@gmail.com>
  96
  97         * or1k-asm.c: Regenerated.
  98         * or1k-desc.c: Regenerated.
  99         * or1k-desc.h: Regenerated.
 100         * or1k-dis.c: Regenerated.
 101         * or1k-ibld.c: Regenerated.
 102         * or1k-opc.c: Regenerated.
 103         * or1k-opc.h: Regenerated.
 104         * or1k-opinst.c: Regenerated.
 105
 106 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 107
 108         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 109
 110 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 111
 112         PR binutils/24633
 113         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 114         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 115         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 116         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 117         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 118         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 119         EVEX_LEN_0F3A1B_P_2_W_1.
 120         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 121         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 122         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 123         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 124         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 125         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 126         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 127         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 128
 129 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 130
 131         PR binutils/24626
 132         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 133         EVEX.vvvv when disassembling VEX and EVEX instructions.
 134         (OP_VEX): Set vex.register_specifier to 0 after readding
 135         vex.register_specifier.
 136         (OP_Vex_2src_1): Likewise.
 137         (OP_Vex_2src_2): Likewise.
 138         (OP_LWP_E): Likewise.
 139         (OP_EX_Vex): Don't check vex.register_specifier.
 140         (OP_XMM_Vex): Likewise.
 141
 142 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 143             Lili Cui  <lili.cui@intel.com>
 144
 145         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 146         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 147         instructions.
 148         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 149         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 150         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 151         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 152         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 153         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 154         * i386-init.h: Regenerated.
 155         * i386-tbl.h: Likewise.
 156
 157 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 158             Lili Cui  <lili.cui@intel.com>
 159
 160         * doc/c-i386.texi: Document enqcmd.
 161         * testsuite/gas/i386/enqcmd-intel.d: New file.
 162         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 163         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 164         * testsuite/gas/i386/enqcmd.d: Likewise.
 165         * testsuite/gas/i386/enqcmd.s: Likewise.
 166         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 167         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 168         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 169         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 170         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 171         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 172         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 173         and x86-64-enqcmd.
 174
 175 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 176
 177         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 178
 179 2019-06-03  Alan Modra  <amodra@gmail.com>
 180
 181         * ppc-dis.c (prefix_opcd_indices): Correct size.
 182
 183 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 184
 185         PR gas/24625
 186         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 187         Disp8ShiftVL.
 188         * i386-tbl.h: Regenerated.
 189
 190 2019-05-24  Alan Modra  <amodra@gmail.com>
 191
 192         * po/POTFILES.in: Regenerate.
 193
 194 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 195             Alan Modra  <amodra@gmail.com>
 196
 197         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 198         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 199         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 200         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 201         XTOP>): Define and add entries.
 202         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 203         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 204         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 205         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 206
 207 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 208             Alan Modra  <amodra@gmail.com>
 209
 210         * ppc-dis.c (ppc_opts): Add "future" entry.
 211         (PREFIX_OPCD_SEGS): Define.
 212         (prefix_opcd_indices): New array.
 213         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 214         (lookup_prefix): New function.
 215         (print_insn_powerpc): Handle 64-bit prefix instructions.
 216         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 217         (PMRR, POWERXX): Define.
 218         (prefix_opcodes): New instruction table.
 219         (prefix_num_opcodes): New constant.
 220
 221 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 222
 223         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 224         * configure: Regenerated.
 225         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 226         and cpu/bpf.opc.
 227         (HFILES): Add bpf-desc.h and bpf-opc.h.
 228         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 229         bpf-ibld.c and bpf-opc.c.
 230         (BPF_DEPS): Define.
 231         * Makefile.in: Regenerated.
 232         * disassemble.c (ARCH_bpf): Define.
 233         (disassembler): Add case for bfd_arch_bpf.
 234         (disassemble_init_for_target): Likewise.
 235         (enum epbf_isa_attr): Define.
 236         * disassemble.h: extern print_insn_bpf.
 237         * bpf-asm.c: Generated.
 238         * bpf-opc.h: Likewise.
 239         * bpf-opc.c: Likewise.
 240         * bpf-ibld.c: Likewise.
 241         * bpf-dis.c: Likewise.
 242         * bpf-desc.h: Likewise.
 243         * bpf-desc.c: Likewise.
 244
 245 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 246
 247         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 248         and VMSR with the new operands.
 249
 250 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 251
 252         * arm-dis.c (enum mve_instructions): New enum
 253         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 254         and cneg.
 255         (mve_opcodes): New instructions as above.
 256         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 257         csneg and csel.
 258         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 259
 260 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 261
 262         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 263         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 264         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 265         uqshl, urshrl and urshr.
 266         (is_mve_okay_in_it): Add new instructions to TRUE list.
 267         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 268         (print_insn_mve): Updated to accept new %j,
 269         %<bitfield>m and %<bitfield>n patterns.
 270
 271 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 272
 273         * mips-opc.c (mips_builtin_opcodes): Change source register
 274         constraint for DAUI.
 275
 276 2019-05-20  Nick Clifton  <nickc@redhat.com>
 277
 278         * po/fr.po: Updated French translation.
 279
 280 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 281             Michael Collison <michael.collison@arm.com>
 282
 283         * arm-dis.c (thumb32_opcodes): Add new instructions.
 284         (enum mve_instructions): Likewise.
 285         (enum mve_undefined): Add new reasons.
 286         (is_mve_encoding_conflict): Handle new instructions.
 287         (is_mve_undefined): Likewise.
 288         (is_mve_unpredictable): Likewise.
 289         (print_mve_undefined): Likewise.
 290         (print_mve_size): Likewise.
 291
 292 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 293             Michael Collison <michael.collison@arm.com>
 294
 295         * arm-dis.c (thumb32_opcodes): Add new instructions.
 296         (enum mve_instructions): Likewise.
 297         (is_mve_encoding_conflict): Handle new instructions.
 298         (is_mve_undefined): Likewise.
 299         (is_mve_unpredictable): Likewise.
 300         (print_mve_size): Likewise.
 301
 302 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 303             Michael Collison <michael.collison@arm.com>
 304
 305         * arm-dis.c (thumb32_opcodes): Add new instructions.
 306         (enum mve_instructions): Likewise.
 307         (is_mve_encoding_conflict): Likewise.
 308         (is_mve_unpredictable): Likewise.
 309         (print_mve_size): Likewise.
 310
 311 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 312             Michael Collison <michael.collison@arm.com>
 313
 314         * arm-dis.c (thumb32_opcodes): Add new instructions.
 315         (enum mve_instructions): Likewise.
 316         (is_mve_encoding_conflict): Handle new instructions.
 317         (is_mve_undefined): Likewise.
 318         (is_mve_unpredictable): Likewise.
 319         (print_mve_size): Likewise.
 320
 321 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 322             Michael Collison <michael.collison@arm.com>
 323
 324         * arm-dis.c (thumb32_opcodes): Add new instructions.
 325         (enum mve_instructions): Likewise.
 326         (is_mve_encoding_conflict): Handle new instructions.
 327         (is_mve_undefined): Likewise.
 328         (is_mve_unpredictable): Likewise.
 329         (print_mve_size): Likewise.
 330         (print_insn_mve): Likewise.
 331
 332 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 333             Michael Collison <michael.collison@arm.com>
 334
 335         * arm-dis.c (thumb32_opcodes): Add new instructions.
 336         (print_insn_thumb32): Handle new instructions.
 337
 338 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 339             Michael Collison <michael.collison@arm.com>
 340
 341         * arm-dis.c (enum mve_instructions): Add new instructions.
 342         (enum mve_undefined): Add new reasons.
 343         (is_mve_encoding_conflict): Handle new instructions.
 344         (is_mve_undefined): Likewise.
 345         (is_mve_unpredictable): Likewise.
 346         (print_mve_undefined): Likewise.
 347         (print_mve_size): Likewise.
 348         (print_mve_shift_n): Likewise.
 349         (print_insn_mve): Likewise.
 350
 351 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 352             Michael Collison <michael.collison@arm.com>
 353
 354         * arm-dis.c (enum mve_instructions): Add new instructions.
 355         (is_mve_encoding_conflict): Handle new instructions.
 356         (is_mve_unpredictable): Likewise.
 357         (print_mve_rotate): Likewise.
 358         (print_mve_size): Likewise.
 359         (print_insn_mve): Likewise.
 360
 361 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 362             Michael Collison <michael.collison@arm.com>
 363
 364         * arm-dis.c (enum mve_instructions): Add new instructions.
 365         (is_mve_encoding_conflict): Handle new instructions.
 366         (is_mve_unpredictable): Likewise.
 367         (print_mve_size): Likewise.
 368         (print_insn_mve): Likewise.
 369
 370 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 371             Michael Collison <michael.collison@arm.com>
 372
 373         * arm-dis.c (enum mve_instructions): Add new instructions.
 374         (enum mve_undefined): Add new reasons.
 375         (is_mve_encoding_conflict): Handle new instructions.
 376         (is_mve_undefined): Likewise.
 377         (is_mve_unpredictable): Likewise.
 378         (print_mve_undefined): Likewise.
 379         (print_mve_size): Likewise.
 380         (print_insn_mve): Likewise.
 381
 382 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 383             Michael Collison <michael.collison@arm.com>
 384
 385         * arm-dis.c (enum mve_instructions): Add new instructions.
 386         (is_mve_encoding_conflict): Handle new instructions.
 387         (is_mve_undefined): Likewise.
 388         (is_mve_unpredictable): Likewise.
 389         (print_mve_size): Likewise.
 390         (print_insn_mve): Likewise.
 391
 392 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 393             Michael Collison <michael.collison@arm.com>
 394
 395         * arm-dis.c (enum mve_instructions): Add new instructions.
 396         (enum mve_unpredictable): Add new reasons.
 397         (enum mve_undefined): Likewise.
 398         (is_mve_okay_in_it): Handle new isntructions.
 399         (is_mve_encoding_conflict): Likewise.
 400         (is_mve_undefined): Likewise.
 401         (is_mve_unpredictable): Likewise.
 402         (print_mve_vmov_index): Likewise.
 403         (print_simd_imm8): Likewise.
 404         (print_mve_undefined): Likewise.
 405         (print_mve_unpredictable): Likewise.
 406         (print_mve_size): Likewise.
 407         (print_insn_mve): Likewise.
 408
 409 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 410             Michael Collison <michael.collison@arm.com>
 411
 412         * arm-dis.c (enum mve_instructions): Add new instructions.
 413         (enum mve_unpredictable): Add new reasons.
 414         (enum mve_undefined): Likewise.
 415         (is_mve_encoding_conflict): Handle new instructions.
 416         (is_mve_undefined): Likewise.
 417         (is_mve_unpredictable): Likewise.
 418         (print_mve_undefined): Likewise.
 419         (print_mve_unpredictable): Likewise.
 420         (print_mve_rounding_mode): Likewise.
 421         (print_mve_vcvt_size): Likewise.
 422         (print_mve_size): Likewise.
 423         (print_insn_mve): Likewise.
 424
 425 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 426             Michael Collison <michael.collison@arm.com>
 427
 428         * arm-dis.c (enum mve_instructions): Add new instructions.
 429         (enum mve_unpredictable): Add new reasons.
 430         (enum mve_undefined): Likewise.
 431         (is_mve_undefined): Handle new instructions.
 432         (is_mve_unpredictable): Likewise.
 433         (print_mve_undefined): Likewise.
 434         (print_mve_unpredictable): Likewise.
 435         (print_mve_size): Likewise.
 436         (print_insn_mve): Likewise.
 437
 438 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 439             Michael Collison <michael.collison@arm.com>
 440
 441         * arm-dis.c (enum mve_instructions): Add new instructions.
 442         (enum mve_undefined): Add new reasons.
 443         (insns): Add new instructions.
 444         (is_mve_encoding_conflict):
 445         (print_mve_vld_str_addr): New print function.
 446         (is_mve_undefined): Handle new instructions.
 447         (is_mve_unpredictable): Likewise.
 448         (print_mve_undefined): Likewise.
 449         (print_mve_size): Likewise.
 450         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 451         (print_insn_mve):  Handle new operands.
 452
 453 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 454             Michael Collison <michael.collison@arm.com>
 455
 456         * arm-dis.c (enum mve_instructions): Add new instructions.
 457         (enum mve_unpredictable): Add new reasons.
 458         (is_mve_encoding_conflict): Handle new instructions.
 459         (is_mve_unpredictable): Likewise.
 460         (mve_opcodes): Add new instructions.
 461         (print_mve_unpredictable): Handle new reasons.
 462         (print_mve_register_blocks): New print function.
 463         (print_mve_size): Handle new instructions.
 464         (print_insn_mve): Likewise.
 465
 466 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 467             Michael Collison <michael.collison@arm.com>
 468
 469         * arm-dis.c (enum mve_instructions): Add new instructions.
 470         (enum mve_unpredictable): Add new reasons.
 471         (enum mve_undefined): Likewise.
 472         (is_mve_encoding_conflict): Handle new instructions.
 473         (is_mve_undefined): Likewise.
 474         (is_mve_unpredictable): Likewise.
 475         (coprocessor_opcodes): Move NEON VDUP from here...
 476         (neon_opcodes): ... to here.
 477         (mve_opcodes): Add new instructions.
 478         (print_mve_undefined):  Handle new reasons.
 479         (print_mve_unpredictable): Likewise.
 480         (print_mve_size): Handle new instructions.
 481         (print_insn_neon): Handle vdup.
 482         (print_insn_mve): Handle new operands.
 483
 484 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 485             Michael Collison <michael.collison@arm.com>
 486
 487         * arm-dis.c (enum mve_instructions): Add new instructions.
 488         (enum mve_unpredictable): Add new values.
 489         (mve_opcodes): Add new instructions.
 490         (vec_condnames): New array with vector conditions.
 491         (mve_predicatenames): New array with predicate suffixes.
 492         (mve_vec_sizename): New array with vector sizes.
 493         (enum vpt_pred_state): New enum with vector predication states.
 494         (struct vpt_block): New struct type for vpt blocks.
 495         (vpt_block_state): Global struct to keep track of state.
 496         (mve_extract_pred_mask): New helper function.
 497         (num_instructions_vpt_block): Likewise.
 498         (mark_outside_vpt_block): Likewise.
 499         (mark_inside_vpt_block): Likewise.
 500         (invert_next_predicate_state): Likewise.
 501         (update_next_predicate_state): Likewise.
 502         (update_vpt_block_state): Likewise.
 503         (is_vpt_instruction): Likewise.
 504         (is_mve_encoding_conflict): Add entries for new instructions.
 505         (is_mve_unpredictable): Likewise.
 506         (print_mve_unpredictable): Handle new cases.
 507         (print_instruction_predicate): Likewise.
 508         (print_mve_size): New function.
 509         (print_vec_condition): New function.
 510         (print_insn_mve): Handle vpt blocks and new print operands.
 511
 512 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 513
 514         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 515         8, 14 and 15 for Armv8.1-M Mainline.
 516
 517 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 518             Michael Collison <michael.collison@arm.com>
 519
 520         * arm-dis.c (enum mve_instructions): New enum.
 521         (enum mve_unpredictable): Likewise.
 522         (enum mve_undefined): Likewise.
 523         (struct mopcode32): New struct.
 524         (is_mve_okay_in_it): New function.
 525         (is_mve_architecture): Likewise.
 526         (arm_decode_field): Likewise.
 527         (arm_decode_field_multiple): Likewise.
 528         (is_mve_encoding_conflict): Likewise.
 529         (is_mve_undefined): Likewise.
 530         (is_mve_unpredictable): Likewise.
 531         (print_mve_undefined): Likewise.
 532         (print_mve_unpredictable): Likewise.
 533         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 534         (print_insn_mve): New function.
 535         (print_insn_thumb32): Handle MVE architecture.
 536         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 537
 538 2019-05-10  Nick Clifton  <nickc@redhat.com>
 539
 540         PR 24538
 541         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 542         end of the table prematurely.
 543
 544 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 545
 546         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 547         macros for R6.
 548
 549 2019-05-11  Alan Modra  <amodra@gmail.com>
 550
 551         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 552         when -Mraw is in effect.
 553
 554 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 555
 556         * aarch64-dis-2.c: Regenerate.
 557         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 558         (OP_SVE_BBB): New variant set.
 559         (OP_SVE_DDDD): New variant set.
 560         (OP_SVE_HHH): New variant set.
 561         (OP_SVE_HHHU): New variant set.
 562         (OP_SVE_SSS): New variant set.
 563         (OP_SVE_SSSU): New variant set.
 564         (OP_SVE_SHH): New variant set.
 565         (OP_SVE_SBBU): New variant set.
 566         (OP_SVE_DSS): New variant set.
 567         (OP_SVE_DHHU): New variant set.
 568         (OP_SVE_VMV_HSD_BHS): New variant set.
 569         (OP_SVE_VVU_HSD_BHS): New variant set.
 570         (OP_SVE_VVVU_SD_BH): New variant set.
 571         (OP_SVE_VVVU_BHSD): New variant set.
 572         (OP_SVE_VVV_QHD_DBS): New variant set.
 573         (OP_SVE_VVV_HSD_BHS): New variant set.
 574         (OP_SVE_VVV_HSD_BHS2): New variant set.
 575         (OP_SVE_VVV_BHS_HSD): New variant set.
 576         (OP_SVE_VV_BHS_HSD): New variant set.
 577         (OP_SVE_VVV_SD): New variant set.
 578         (OP_SVE_VVU_BHS_HSD): New variant set.
 579         (OP_SVE_VZVV_SD): New variant set.
 580         (OP_SVE_VZVV_BH): New variant set.
 581         (OP_SVE_VZV_SD): New variant set.
 582         (aarch64_opcode_table): Add sve2 instructions.
 583
 584 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 585
 586         * aarch64-asm-2.c: Regenerated.
 587         * aarch64-dis-2.c: Regenerated.
 588         * aarch64-opc-2.c: Regenerated.
 589         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 590         for SVE_SHLIMM_UNPRED_22.
 591         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 592         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 593         operand.
 594
 595 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 596
 597         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 598         sve_size_tsz_bhs iclass encode.
 599         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 600         sve_size_tsz_bhs iclass decode.
 601
 602 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 603
 604         * aarch64-asm-2.c: Regenerated.
 605         * aarch64-dis-2.c: Regenerated.
 606         * aarch64-opc-2.c: Regenerated.
 607         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 608         for SVE_Zm4_11_INDEX.
 609         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 610         (fields): Handle SVE_i2h field.
 611         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 612         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 613
 614 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 615
 616         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 617         sve_shift_tsz_bhsd iclass encode.
 618         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 619         sve_shift_tsz_bhsd iclass decode.
 620
 621 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 622
 623         * aarch64-asm-2.c: Regenerated.
 624         * aarch64-dis-2.c: Regenerated.
 625         * aarch64-opc-2.c: Regenerated.
 626         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 627         (aarch64_encode_variant_using_iclass): Handle
 628         sve_shift_tsz_hsd iclass encode.
 629         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 630         sve_shift_tsz_hsd iclass decode.
 631         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 632         for SVE_SHRIMM_UNPRED_22.
 633         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 634         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 635         operand.
 636
 637 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 638
 639         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 640         sve_size_013 iclass encode.
 641         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 642         sve_size_013 iclass decode.
 643
 644 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 645
 646         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 647         sve_size_bh iclass encode.
 648         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 649         sve_size_bh iclass decode.
 650
 651 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 652
 653         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 654         sve_size_sd2 iclass encode.
 655         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 656         sve_size_sd2 iclass decode.
 657         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 658         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 659
 660 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 661
 662         * aarch64-asm-2.c: Regenerated.
 663         * aarch64-dis-2.c: Regenerated.
 664         * aarch64-opc-2.c: Regenerated.
 665         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 666         for SVE_ADDR_ZX.
 667         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 668         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 669
 670 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 671
 672         * aarch64-asm-2.c: Regenerated.
 673         * aarch64-dis-2.c: Regenerated.
 674         * aarch64-opc-2.c: Regenerated.
 675         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 676         for SVE_Zm3_11_INDEX.
 677         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 678         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 679         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 680         fields.
 681         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 682
 683 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 684
 685         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 686         sve_size_hsd2 iclass encode.
 687         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 688         sve_size_hsd2 iclass decode.
 689         * aarch64-opc.c (fields): Handle SVE_size field.
 690         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 691
 692 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 693
 694         * aarch64-asm-2.c: Regenerated.
 695         * aarch64-dis-2.c: Regenerated.
 696         * aarch64-opc-2.c: Regenerated.
 697         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 698         for SVE_IMM_ROT3.
 699         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 700         (fields): Handle SVE_rot3 field.
 701         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 702         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 703
 704 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 705
 706         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 707         instructions.
 708
 709 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 710
 711         * aarch64-tbl.h
 712         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 713         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 714         aarch64_feature_sve2bitperm): New feature sets.
 715         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 716         for feature set addresses.
 717         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 718         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 719
 720 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 721             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 722
 723         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 724         argument and set ASE_EVA_R6 appropriately.
 725         (set_default_mips_dis_options): Pass ISA to above.
 726         (parse_mips_dis_option): Likewise.
 727         * mips-opc.c (EVAR6): New macro.
 728         (mips_builtin_opcodes): Add llwpe, scwpe.
 729
 730 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 731
 732         * aarch64-asm-2.c: Regenerated.
 733         * aarch64-dis-2.c: Regenerated.
 734         * aarch64-opc-2.c: Regenerated.
 735         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 736         AARCH64_OPND_TME_UIMM16.
 737         (aarch64_print_operand): Likewise.
 738         * aarch64-tbl.h (QL_IMM_NIL): New.
 739         (TME): New.
 740         (_TME_INSN): New.
 741         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 742
 743 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 744
 745         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 746
 747 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 748             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 749
 750         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 751
 752 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 753
 754         * s12z-opc.h: Add extern "C" bracketing to help
 755         users who wish to use this interface in c++ code.
 756
 757 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 758
 759         * s12z-opc.c (bm_decode): Handle bit map operations with the
 760         "reserved0" mode.
 761
 762 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 763
 764         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 765         specifier.  Add entries for VLDR and VSTR of system registers.
 766         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 767         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 768         of %J and %K format specifier.
 769
 770 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 771
 772         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 773         Add new entries for VSCCLRM instruction.
 774         (print_insn_coprocessor): Handle new %C format control code.
 775
 776 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 777
 778         * arm-dis.c (enum isa): New enum.
 779         (struct sopcode32): New structure.
 780         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 781         set isa field of all current entries to ANY.
 782         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 783         Only match an entry if its isa field allows the current mode.
 784
 785 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 786
 787         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 788         CLRM.
 789         (print_insn_thumb32): Add logic to print %n CLRM register list.
 790
 791 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 792
 793         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 794         and %Q patterns.
 795
 796 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 797
 798         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 799         (print_insn_thumb32): Edit the switch case for %Z.
 800
 801 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 802
 803         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 804
 805 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 806
 807         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 808
 809 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 810
 811         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 812
 813 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 814
 815         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 816         Arm register with r13 and r15 unpredictable.
 817         (thumb32_opcodes): New instructions for bfx and bflx.
 818
 819 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 820
 821         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 822
 823 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 824
 825         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 826
 827 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 828
 829         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 830
 831 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 832
 833         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 834
 835 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 836
 837         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 838         "optr". ("operator" is a reserved word in c++).
 839
 840 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 841
 842         * aarch64-opc.c (aarch64_print_operand): Add case for
 843         AARCH64_OPND_Rt_SP.
 844         (verify_constraints): Likewise.
 845         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 846         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 847         to accept Rt|SP as first operand.
 848         (AARCH64_OPERANDS): Add new Rt_SP.
 849         * aarch64-asm-2.c: Regenerated.
 850         * aarch64-dis-2.c: Regenerated.
 851         * aarch64-opc-2.c: Regenerated.
 852
 853 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 854
 855         * aarch64-asm-2.c: Regenerated.
 856         * aarch64-dis-2.c: Likewise.
 857         * aarch64-opc-2.c: Likewise.
 858         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 859
 860 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 861
 862         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 863
 864 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 865
 866         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 867         * i386-init.h: Regenerated.
 868
 869 2019-04-07  Alan Modra  <amodra@gmail.com>
 870
 871         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 872         op_separator to control printing of spaces, comma and parens
 873         rather than need_comma, need_paren and spaces vars.
 874
 875 2019-04-07  Alan Modra  <amodra@gmail.com>
 876
 877         PR 24421
 878         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 879         (print_insn_neon, print_insn_arm): Likewise.
 880
 881 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 882
 883         * i386-dis-evex.h (evex_table): Updated to support BF16
 884         instructions.
 885         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 886         and EVEX_W_0F3872_P_3.
 887         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 888         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 889         * i386-opc.h (enum): Add CpuAVX512_BF16.
 890         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 891         * i386-opc.tbl: Add AVX512 BF16 instructions.
 892         * i386-init.h: Regenerated.
 893         * i386-tbl.h: Likewise.
 894
 895 2019-04-05  Alan Modra  <amodra@gmail.com>
 896
 897         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 898         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 899         to favour printing of "-" branch hint when using the "y" bit.
 900         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 901
 902 2019-04-05  Alan Modra  <amodra@gmail.com>
 903
 904         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 905         opcode until first operand is output.
 906
 907 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 908
 909         PR gas/24349
 910         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 911         (valid_bo_post_v2): Add support for 'at' branch hints.
 912         (insert_bo): Only error on branch on ctr.
 913         (get_bo_hint_mask): New function.
 914         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 915         for inserting 'at' branch hints.
 916         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 917         for extracting 'at' branch hints.
 918         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 919         (BOE): Delete operand.
 920         (BOM, BOP): New operands.
 921         (RM): Update value.
 922         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 923         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 924         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 925         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 926         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 927         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 928         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 929         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 930         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 931         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 932         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 933         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 934         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 935         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 936         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 937         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 938         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 939         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 940         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 941         bttarl+>: New extended mnemonics.
 942
 943 2019-03-28  Alan Modra  <amodra@gmail.com>
 944
 945         PR 24390
 946         * ppc-opc.c (BTF): Define.
 947         (powerpc_opcodes): Use for mtfsb*.
 948         * ppc-dis.c (print_insn_powerpc): Print fields with both
 949         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 950
 951 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 952
 953         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 954         (mapping_symbol_for_insn): Implement new algorithm.
 955         (print_insn): Remove duplicate code.
 956
 957 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 958
 959         * aarch64-dis.c (print_insn_aarch64):
 960         Implement override.
 961
 962 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 963
 964         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 965         order.
 966
 967 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 968
 969         * aarch64-dis.c (last_stop_offset): New.
 970         (print_insn_aarch64): Use stop_offset.
 971
 972 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 973
 974         PR gas/24359
 975         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 976         CPU_ANY_AVX2_FLAGS.
 977         * i386-init.h: Regenerated.
 978
 979 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 980
 981         PR gas/24348
 982         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 983         vmovdqu16, vmovdqu32 and vmovdqu64.
 984         * i386-tbl.h: Regenerated.
 985
 986 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 987
 988         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 989         from vstrszb, vstrszh, and vstrszf.
 990
 991 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 992
 993         * s390-opc.txt: Add instruction descriptions.
 994
 995 2019-02-08  Jim Wilson  <jimw@sifive.com>
 996
 997         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 998         <bne>: Likewise.
 999
1000 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1001
1002         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1003
1004 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1005
1006         PR binutils/23212
1007         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1008         * aarch64-opc.c (verify_elem_sd): New.
1009         (fields): Add FLD_sz entr.
1010         * aarch64-tbl.h (_SIMD_INSN): New.
1011         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1012         fmulx scalar and vector by element isns.
1013
1014 2019-02-07  Nick Clifton  <nickc@redhat.com>
1015
1016         * po/sv.po: Updated Swedish translation.
1017
1018 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1019
1020         * s390-mkopc.c (main): Accept arch13 as cpu string.
1021         * s390-opc.c: Add new instruction formats and instruction opcode
1022         masks.
1023         * s390-opc.txt: Add new arch13 instructions.
1024
1025 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1026
1027         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1028         (aarch64_opcode): Change encoding for stg, stzg
1029         st2g and st2zg.
1030         * aarch64-asm-2.c: Regenerated.
1031         * aarch64-dis-2.c: Regenerated.
1032         * aarch64-opc-2.c: Regenerated.
1033
1034 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1035
1036         * aarch64-asm-2.c: Regenerated.
1037         * aarch64-dis-2.c: Likewise.
1038         * aarch64-opc-2.c: Likewise.
1039         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1040
1041 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1042             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1043
1044         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1045         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1046         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1047         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1048         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1049         case for ldstgv_indexed.
1050         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1051         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1052         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1053         * aarch64-asm-2.c: Regenerated.
1054         * aarch64-dis-2.c: Regenerated.
1055         * aarch64-opc-2.c: Regenerated.
1056
1057 2019-01-23  Nick Clifton  <nickc@redhat.com>
1058
1059         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1060
1061 2019-01-21  Nick Clifton  <nickc@redhat.com>
1062
1063         * po/de.po: Updated German translation.
1064         * po/uk.po: Updated Ukranian translation.
1065
1066 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1067         * mips-dis.c (mips_arch_choices): Fix typo in
1068         gs464, gs464e and gs264e descriptors.
1069
1070 2019-01-19  Nick Clifton  <nickc@redhat.com>
1071
1072         * configure: Regenerate.
1073         * po/opcodes.pot: Regenerate.
1074
1075 2018-06-24  Nick Clifton  <nickc@redhat.com>
1076
1077         2.32 branch created.
1078
1079 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1080
1081         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1082         if it is null.
1083         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1084         zero.
1085
1086 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1087
1088         * configure: Regenerate.
1089
1090 2019-01-07  Alan Modra  <amodra@gmail.com>
1091
1092         * configure: Regenerate.
1093         * po/POTFILES.in: Regenerate.
1094
1095 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1096
1097         * s12z-opc.c: New file.
1098         * s12z-opc.h: New file.
1099         * s12z-dis.c: Removed all code not directly related to display
1100         of instructions.  Used the interface provided by the new files
1101         instead.
1102         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1103         * Makefile.in: Regenerate.
1104         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1105         * configure: Regenerate.
1106
1107 2019-01-01  Alan Modra  <amodra@gmail.com>
1108
1109         Update year range in copyright notice of all files.
1110
1111 For older changes see ChangeLog-2018
1112 \f
1113 Copyright (C) 2019 Free Software Foundation, Inc.
1114
1115 Copying and distribution of this file, with or without modification,
1116 are permitted in any medium without royalty provided the copyright
1117 notice and this notice are preserved.
1118
1119 Local Variables:
1120 mode: change-log
1121 left-margin: 8
1122 fill-column: 74
1123 version-control: never
1124 End: