opcodes/ChangeLog

   1 2021-07-03  Nick Clifton  <nickc@redhat.com>
   2
   3         * 2.37 release branch created.
   4
   5 2021-07-02  Alan Modra  <amodra@gmail.com>
   6
   7         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
   8         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
   9         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
  10         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
  11         (nds32_keyword_gpr): Move declarations to..
  12         * nds32-asm.h: ..here, constifying to match definitions.
  13
  14 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  15
  16         * Makefile.am (GUILE): New variable.
  17         (CGEN): Use $(GUILE).
  18         * Makefile.in: Regenerate.
  19
  20 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  21
  22         * mep-asm.c (macros): Mark static & const.
  23         (lookup_macro): Change return & m to const.
  24         (expand_macro): Change mac to const.
  25         (expand_string): Change pmacro to const.
  26
  27 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  28
  29         * nds32-asm.c (operand_fields): Rename to ...
  30         (nds32_operand_fields): ... this.
  31         (keyword_gpr): Rename to ...
  32         (nds32_keyword_gpr): ... this.
  33         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
  34         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
  35         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
  36         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
  37         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
  38         Mark static.
  39         (keywords): Rename to ...
  40         (nds32_keywords): ... this.
  41         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
  42         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
  43
  44 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  45
  46         * z80-dis.c (opc_ed): Make const.
  47         (pref_ed): Make p const.
  48
  49 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  50
  51         * microblaze-dis.c (get_field_special): Make op const.
  52         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
  53         microblaze_opcodes.
  54         (print_insn_microblaze): Make op & pop const.
  55         (get_insn_microblaze): Make op const.  Rename opcodes to
  56         microblaze_opcodes.
  57         (microblaze_get_target_address): Likewise.
  58         * microblaze-opc.h (struct op_code_struct): Make const.
  59         Rename opcodes to microblaze_opcodes.
  60
  61 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  62
  63         * aarch64-gen.c (aarch64_opcode_table): Add const.
  64         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
  65
  66 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
  67
  68         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
  69         available.
  70
  71 2021-06-22  Alan Modra  <amodra@gmail.com>
  72
  73         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
  74         print separator for pcrel insns.
  75
  76 2021-06-19  Alan Modra  <amodra@gmail.com>
  77
  78         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
  79
  80 2021-06-19  Alan Modra  <amodra@gmail.com>
  81
  82         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
  83         entire buffer.
  84
  85 2021-06-17  Alan Modra  <amodra@gmail.com>
  86
  87         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
  88         in table.
  89
  90 2021-06-03  Alan Modra  <amodra@gmail.com>
  91
  92         PR 1202
  93         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
  94         Use unsigned int for inst.
  95
  96 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
  97
  98         * arc-dis.c (arc_option_arg_t): New enumeration.
  99         (arc_options): New variable.
 100         (disassembler_options_arc): New function.
 101         (print_arc_disassembler_options): Reimplement in terms of
 102         "disassembler_options_arc".
 103
 104 2021-05-29  Alan Modra  <amodra@gmail.com>
 105
 106         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 107         Don't special case PPC_OPCODE_RAW.
 108         (lookup_prefix): Likewise.
 109         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 110         (print_insn_powerpc): ..update caller.
 111         * ppc-opc.c (EXT): Define.
 112         (powerpc_opcodes): Mark extended mnemonics with EXT.
 113         (prefix_opcodes, vle_opcodes): Likewise.
 114         (XISEL, XISEL_MASK): Add cr field and simplify.
 115         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 116         all isel variants to where the base mnemonic belongs.  Sort dstt,
 117         dststt and dssall.
 118
 119 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 120
 121         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 122         COP3 opcode instructions.
 123
 124 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 125
 126         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 127         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 128         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 129         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 130         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 131         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 132         "cop2", and "cop3" entries.
 133
 134 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 135
 136         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 137         entries and associated comments.
 138
 139 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 140
 141         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 142         of "c0".
 143
 144 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 145
 146         * mips-dis.c (mips_cp1_names_mips): New variable.
 147         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 148         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 149         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 150         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 151         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 152         "loongson2f".
 153
 154 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 155
 156         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 157         handling code over to...
 158         <OP_REG_CONTROL>: ... this new case.
 159         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 160         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 161         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 162         replacing the `G' operand code with `g'.  Update "cftc1" and
 163         "cftc2" entries replacing the `E' operand code with `y'.
 164         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 165         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 166         entries replacing the `G' operand code with `g'.
 167
 168 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 169
 170         * mips-dis.c (mips_cp0_names_r3900): New variable.
 171         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 172         for "r3900".
 173
 174 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 175
 176         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 177         and "mtthc2" to using the `G' rather than `g' operand code for
 178         the coprocessor control register referred.
 179
 180 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 181
 182         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 183         entries with each other.
 184
 185 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 186
 187         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 188
 189 2021-05-25  Alan Modra  <amodra@gmail.com>
 190
 191         * cris-desc.c: Regenerate.
 192         * cris-desc.h: Regenerate.
 193         * cris-opc.h: Regenerate.
 194         * po/POTFILES.in: Regenerate.
 195
 196 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 197
 198         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 199         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 200         (CGEN_CPUS): Add cris.
 201         (CRIS_DEPS): Define.
 202         (stamp-cris): New rule.
 203         * cgen.sh: Handle desc action.
 204         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 205         * Makefile.in, configure: Regenerate.
 206
 207 2021-05-18  Job Noorman  <mtvec@pm.me>
 208
 209         PR 27814
 210         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 211         the elf objects.
 212
 213 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 214
 215         * arm-dis.c (mve_opcodes): Fix disassembly of
 216         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 217         (is_mve_encoding_conflict): MVE vector loads should not match
 218         when P = W = 0.
 219         (is_mve_unpredictable): It's not unpredictable to use the same
 220         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 221
 222 2021-05-11  Nick Clifton  <nickc@redhat.com>
 223
 224         PR 27840
 225         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 226         the end of the code buffer.
 227
 228 2021-05-06  Stafford Horne  <shorne@gmail.com>
 229
 230         PR 21464
 231         * or1k-asm.c: Regenerate.
 232
 233 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 234
 235         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 236         info->insn_info_valid.
 237
 238 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-opc.tbl (lea): Add Optimize.
 241         * opcodes/i386-tbl.h: Re-generate.
 242
 243 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 244
 245         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 246         of l32r fetch and display referenced literal value.
 247
 248 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 249
 250         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 251         to 4 for literal disassembly.
 252
 253 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 254
 255         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 256         for TLBI instruction.
 257
 258 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 259
 260         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 261         DC instruction.
 262
 263 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 264
 265         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 266         "qualifier".
 267         (convert_mov_to_movewide): Add initializer for "value".
 268
 269 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 270
 271         * aarch64-opc.c: Add RME system registers.
 272
 273 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 274
 275         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 276         "addi d,CV,z" to "c.mv d,CV".
 277
 278 2021-04-12  Alan Modra  <amodra@gmail.com>
 279
 280         * configure.ac (--enable-checking): Add support.
 281         * config.in: Regenerate.
 282         * configure: Regenerate.
 283
 284 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 285
 286         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 287         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 288
 289 2021-04-09  Alan Modra  <amodra@gmail.com>
 290
 291         * ppc-dis.c (struct dis_private): Add "special".
 292         (POWERPC_DIALECT): Delete.  Replace uses with..
 293         (private_data): ..this.  New inline function.
 294         (disassemble_init_powerpc): Init "special" names.
 295         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 296         field of prefix instructions.
 297         (bsearch_reloc, print_got_plt): New functions.
 298         (print_insn_powerpc): For pcrel instructions, print target address
 299         and symbol if known, and decode plt and got loads too.
 300
 301 2021-04-08  Alan Modra  <amodra@gmail.com>
 302
 303         PR 27684
 304         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 305
 306 2021-04-08  Alan Modra  <amodra@gmail.com>
 307
 308         PR 27676
 309         * ppc-opc.c (DCBT_EO): Move earlier.
 310         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 311         (powerpc_operands): Add THCT and THDS entries.
 312         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 313
 314 2021-04-06  Alan Modra  <amodra@gmail.com>
 315
 316         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 317         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 318         symbol_at_address_func.
 319
 320 2021-04-05  Alan Modra  <amodra@gmail.com>
 321
 322         * configure.ac: Don't check for limits.h, string.h, strings.h or
 323         stdlib.h.
 324         (AC_ISC_POSIX): Don't invoke.
 325         * sysdep.h: Include stdlib.h and string.h unconditionally.
 326         * i386-opc.h: Include limits.h unconditionally.
 327         * wasm32-dis.c: Likewise.
 328         * cgen-opc.c: Don't include alloca-conf.h.
 329         * config.in: Regenerate.
 330         * configure: Regenerate.
 331
 332 2021-04-01  Martin Liska  <mliska@suse.cz>
 333
 334         * arm-dis.c (strneq): Remove strneq and use startswith.
 335         * cr16-dis.c (print_insn_cr16): Likewise.
 336         * score-dis.c (streq): Likewise.
 337         (strneq): Likewise.
 338         * score7-dis.c (strneq): Likewise.
 339
 340 2021-04-01  Alan Modra  <amodra@gmail.com>
 341
 342         PR 27675
 343         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 344
 345 2021-03-31  Alan Modra  <amodra@gmail.com>
 346
 347         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 348         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 349         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 350         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 351         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 352         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 353         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 354         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 355         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 356         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 357         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 358         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 359         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 360         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 361         and TRUE with true throughout.
 362
 363 2021-03-31  Alan Modra  <amodra@gmail.com>
 364
 365         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 366         * aarch64-dis.h: Likewise.
 367         * aarch64-opc.c: Likewise.
 368         * avr-dis.c: Likewise.
 369         * csky-dis.c: Likewise.
 370         * nds32-asm.c: Likewise.
 371         * nds32-dis.c: Likewise.
 372         * nfp-dis.c: Likewise.
 373         * riscv-dis.c: Likewise.
 374         * s12z-dis.c: Likewise.
 375         * wasm32-dis.c: Likewise.
 376
 377 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 378
 379         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 380         (i386_seg_prefixes): New.
 381         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 382         (i386_seg_prefixes): Declare.
 383
 384 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 385
 386         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 387
 388 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 389
 390         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 391         * i386-reg.tbl (st): Move down.
 392         (st(0)): Delete. Extend comment.
 393         * i386-tbl.h: Re-generate.
 394
 395 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 398         (cmpsd): Move next to cmps.
 399         (movsd): Move next to movs.
 400         (cmpxchg16b): Move to separate section.
 401         (fisttp, fisttpll): Likewise.
 402         (monitor, mwait): Likewise.
 403         * i386-tbl.h: Re-generate.
 404
 405 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 406
 407         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 408         (vpsadbw): Add C.
 409         * i386-tbl.h: Re-generate.
 410
 411 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 412
 413         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 414         pclmul, gfni): New templates. Use them wherever possible. Move
 415         SSE4.1 pextrw into respective section.
 416         * i386-tbl.h: Re-generate.
 417
 418 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 419
 420         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 421         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 422         "length".
 423         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 424         Convert all of their uses to representation in opcode.
 425
 426 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 427
 428         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 429         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 430         value of None. Shrink operands to 3 bits.
 431
 432 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 433
 434         * i386-gen.c (process_i386_opcode_modifier): New parameter
 435         "space".
 436         (output_i386_opcode): New local variable "space". Adjust
 437         process_i386_opcode_modifier() invocation.
 438         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 439         invocation.
 440         * i386-tbl.h: Re-generate.
 441
 442 2021-03-29  Alan Modra  <amodra@gmail.com>
 443
 444         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 445         (fp_qualifier_p, get_data_pattern): Likewise.
 446         (aarch64_get_operand_modifier_from_value): Likewise.
 447         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 448         (operand_variant_qualifier_p): Likewise.
 449         (qualifier_value_in_range_constraint_p): Likewise.
 450         (aarch64_get_qualifier_esize): Likewise.
 451         (aarch64_get_qualifier_nelem): Likewise.
 452         (aarch64_get_qualifier_standard_value): Likewise.
 453         (get_lower_bound, get_upper_bound): Likewise.
 454         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 455         (aarch64_print_operand): Likewise.
 456         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 457         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 458         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 459         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 460         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 461         (print_insn_tic6x): Likewise.
 462
 463 2021-03-29  Alan Modra  <amodra@gmail.com>
 464
 465         * arc-dis.c (extract_operand_value): Correct NULL cast.
 466         * frv-opc.h: Regenerate.
 467
 468 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 471         MMX form.
 472         * i386-tbl.h: Re-generate.
 473
 474 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 475
 476         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 477         immediate in br.n instruction.
 478
 479 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 480
 481         * i386-dis.c (XMGatherD, VexGatherD): New.
 482         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 483         (print_insn): Check masking for S/G insns.
 484         (OP_E_memory): New local variable check_gather. Extend mandatory
 485         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 486         Extend check for disallowed 16-bit addressing.
 487         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 488         if()s to switch(). Check register conflicts for (VEX-encoded)
 489         gathers. Drop no longer reachable cases.
 490         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 491         vgatherdp*.
 492
 493 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 494
 495         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 496         zeroing-masking without masking.
 497
 498 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 501         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 502         single-operand forms as deprecated.
 503         * i386-tbl.h: Re-generate.
 504
 505 2021-03-25  Alan Modra  <amodra@gmail.com>
 506
 507         PR 27647
 508         * ppc-opc.c (XLOCB_MASK): Delete.
 509         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 510         XLBH_MASK.
 511         (powerpc_opcodes): Accept a BH field on all extended forms of
 512         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 513
 514 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 515
 516         * i386-gen.c (output_i386_opcode): Drop processing of
 517         opcode_length. Calculate length from base_opcode. Adjust prefix
 518         encoding determination.
 519         (process_i386_opcodes): Drop output of fake opcode_length.
 520         * i386-opc.h (struct insn_template): Drop opcode_length field.
 521         * i386-opc.tbl: Drop opcode length field from all templates.
 522         * i386-tbl.h: Re-generate.
 523
 524 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 525
 526         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 527         parameter "prefix". Drop local variable "regular_encoding".
 528         Record prefix setting / check for consistency.
 529         (output_i386_opcode): Parse opcode_length and base_opcode
 530         earlier. Derive prefix encoding. Drop no longer applicable
 531         consistency checking. Adjust process_i386_opcode_modifier()
 532         invocation.
 533         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 534         invocation.
 535         * i386-tbl.h: Re-generate.
 536
 537 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 538
 539         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 540         check.
 541         * i386-opc.h (Prefix_*): Move #define-s.
 542         * i386-opc.tbl: Move pseudo prefix enumerator values to
 543         extension opcode field. Introduce pseudopfx template.
 544         * i386-tbl.h: Re-generate.
 545
 546 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 547
 548         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 549         comment.
 550         * i386-tbl.h: Re-generate.
 551
 552 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 553
 554         * i386-opc.h (struct insn_template): Move cpu_flags field past
 555         opcode_modifier one.
 556         * i386-tbl.h: Re-generate.
 557
 558 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 559
 560         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 561         * i386-opc.h (OpcodeSpace): New enumerator.
 562         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 563         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 564         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 565         (struct i386_opcode_modifier): New field opcodespace. Shrink
 566         opcodeprefix field.
 567         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 568         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 569         OpcodePrefix uses.
 570         * i386-tbl.h: Re-generate.
 571
 572 2021-03-22  Martin Liska  <mliska@suse.cz>
 573
 574         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 575         * arc-dis.c (parse_option): Likewise.
 576         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 577         * cris-dis.c (print_with_operands): Likewise.
 578         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 579         * i386-dis.c (print_insn): Likewise.
 580         * ia64-gen.c (fetch_insn_class): Likewise.
 581         (parse_resource_users): Likewise.
 582         (in_iclass): Likewise.
 583         (lookup_specifier): Likewise.
 584         (insert_opcode_dependencies): Likewise.
 585         * mips-dis.c (parse_mips_ase_option): Likewise.
 586         (parse_mips_dis_option): Likewise.
 587         * s390-dis.c (disassemble_init_s390): Likewise.
 588         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 589
 590 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 591
 592         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 593
 594 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 595
 596         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 597         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 598
 599 2021-03-12  Alan Modra  <amodra@gmail.com>
 600
 601         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 602
 603 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-dis.c (OP_XMM): Re-order checks.
 606
 607 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 608
 609         * i386-dis.c (putop): Drop need_vex check when also checking
 610         vex.evex.
 611         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 612         checking vex.b.
 613
 614 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 615
 616         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 617         checks. Move case label past broadcast check.
 618
 619 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 620
 621         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 622         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 623         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 624         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 625         EVEX_W_0F38C7_M_0_L_2): Delete.
 626         (REG_EVEX_0F38C7_M_0_L_2): New.
 627         (intel_operand_size): Handle VEX and EVEX the same for
 628         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 629         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 630         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 631         vex_vsib_q_w_d_mode uses.
 632         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 633         0F38A1, and 0F38A3 entries.
 634         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 635         entry.
 636         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 637         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 638         0F38A3 entries.
 639
 640 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 641
 642         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 643         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 644         MOD_VEX_0FXOP_09_12): Rename to ...
 645         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 646         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 647         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 648         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 649         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 650         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 651         (reg_table): Adjust comments.
 652         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 653         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 654         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 655         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 656         (vex_len_table): Adjust opcode 0A_12 entry.
 657         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 658         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 659         (rm_table): Move hreset entry.
 660
 661 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 662
 663         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 664         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 665         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 666         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 667         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 668         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 669         (get_valid_dis386): Also handle 512-bit vector length when
 670         vectoring into vex_len_table[].
 671         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 672         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 673         entries.
 674         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 675         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 676         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 677         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 678         entries.
 679
 680 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 681
 682         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 683         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 684         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 685         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 686         entries.
 687         * i386-dis-evex-len.h (evex_len_table): Likewise.
 688         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 689
 690 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 691
 692         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 693         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 694         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 695         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 696         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 697         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 698         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 699         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 700         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 701         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 702         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 703         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 704         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 705         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 706         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 707         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 708         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 709         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 710         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 711         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 712         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 713         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 714         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 715         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 716         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 717         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 718         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 719         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 720         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 721         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 722         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 723         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 724         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 725         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 726         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 727         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 728         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 729         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 730         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 731         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 732         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 733         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 734         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 735         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 736         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 737         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 738         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 739         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 740         EVEX_W_0F3A43_L_n): New.
 741         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 742         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 743         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 744         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 745         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 746         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 747         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 748         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 749         0F385B, 0F38C6, and 0F38C7 entries.
 750         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 751         0F38C6 and 0F38C7.
 752         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 753         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 754         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 755         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 756
 757 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 758
 759         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 760         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 761         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 762         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 763         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 764         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 765         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 766         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 767         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 768         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 769         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 770         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 771         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 772         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 773         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 774         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 775         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 776         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 777         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 778         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 779         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 780         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 781         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 782         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 783         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 784         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 785         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 786         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 787         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 788         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 789         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 790         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 791         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 792         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 793         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 794         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 795         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 796         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 797         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 798         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 799         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 800         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 801         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 802         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 803         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 804         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 805         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 806         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 807         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 808         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 809         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 810         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 811         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 812         VEX_W_0F99_P_2_LEN_0): Delete.
 813         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 814         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 815         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 816         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 817         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 818         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 819         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 820         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 821         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 822         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 823         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 824         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 825         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 826         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 827         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 828         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 829         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 830         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 831         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 832         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 833         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 834         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 835         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 836         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 837         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 838         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 839         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 840         (prefix_table): No longer link to vex_len_table[] for opcodes
 841         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 842         0F92, 0F93, 0F98, and 0F99.
 843         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 844         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 845         0F98, and 0F99.
 846         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 847         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 848         0F98, and 0F99.
 849         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 850         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 851         0F98, and 0F99.
 852         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 853         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 854         0F98, and 0F99.
 855
 856 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 857
 858         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 859         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 860         REG_VEX_0F73_M_0 respectively.
 861         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 862         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 863         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 864         MOD_VEX_0F73_REG_7): Delete.
 865         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 866         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 867         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 868         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 869         PREFIX_VEX_0F3AF0_L_0 respectively.
 870         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 871         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 872         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 873         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 874         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 875         VEX_LEN_0F38F7): New.
 876         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 877         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 878         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 879         0F38F3.
 880         (prefix_table): No longer link to vex_len_table[] for opcodes
 881         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 882         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 883         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 884         0F38F6, 0F38F7, and 0F3AF0.
 885         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 886         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 887         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 888         0F73.
 889
 890 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 891
 892         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 893         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 894         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 895         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 896         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 897         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 898         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 899         73.
 900         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 901         0F72, and 0F73.
 902         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 903         0F73.
 904
 905 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 906
 907         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 908         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 909         (reg_table): Don't link to mod_table[] where not needed. Add
 910         PREFIX_IGNORED to nop entries.
 911         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 912         (mod_table): Add nop entries next to prefetch ones. Drop
 913         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 914         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 915         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 916         PREFIX_OPCODE from endbr* entries.
 917         (get_valid_dis386): Also consider entry's name when zapping
 918         vindex.
 919         (print_insn): Handle PREFIX_IGNORED.
 920
 921 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 922
 923         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 924         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 925         element.
 926         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 927         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 928         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 929         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 930         (struct i386_opcode_modifier): Delete notrackprefixok,
 931         islockable, hleprefixok, and repprefixok fields. Add prefixok
 932         field.
 933         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 934         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 935         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 936         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 937         Replace HLEPrefixOk.
 938         * opcodes/i386-tbl.h: Re-generate.
 939
 940 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 941
 942         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 943         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 944         64-bit form.
 945         * opcodes/i386-tbl.h: Re-generate.
 946
 947 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 948
 949         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 950         for {} instead of {0}. Don't look for '0'.
 951         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 952         size specifiers.
 953
 954 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 955
 956         PR 27158
 957         * riscv-dis.c (print_insn_args): Updated encoding macros.
 958         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 959         (match_c_addi16sp): Updated encoding macros.
 960         (match_c_lui): Likewise.
 961         (match_c_lui_with_hint): Likewise.
 962         (match_c_addi4spn): Likewise.
 963         (match_c_slli): Likewise.
 964         (match_slli_as_c_slli): Likewise.
 965         (match_c_slli64): Likewise.
 966         (match_srxi_as_c_srxi): Likewise.
 967         (riscv_insn_types): Added .insn css/cl/cs.
 968
 969 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 970
 971         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 972         (default_priv_spec): Updated type to riscv_spec_class.
 973         (parse_riscv_dis_option): Updated.
 974         * riscv-opc.c: Moved stuff and make the file tidy.
 975
 976 2021-02-17  Alan Modra  <amodra@gmail.com>
 977
 978         * wasm32-dis.c: Include limits.h.
 979         (CHAR_BIT): Provide backup define.
 980         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 981         Correct signed overflow checking.
 982
 983 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 984
 985         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 986         * i386-tbl.h: Re-generate.
 987
 988 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 989
 990         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 991         Oword.
 992         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 993
 994 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 995
 996         * s390-mkopc.c (main): Accept arch14 as cpu string.
 997         * s390-opc.txt: Add new arch14 instructions.
 998
 999 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1000
1001         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1002         favour of LIBINTL.
1003         * configure: Regenerated.
1004
1005 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1006
1007         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1008         * tic54x-opc.c (regs): Rename to ...
1009         (tic54x_regs): ... this.
1010         (mmregs): Rename to ...
1011         (tic54x_mmregs): ... this.
1012         (condition_codes): Rename to ...
1013         (tic54x_condition_codes): ... this.
1014         (cc2_codes): Rename to ...
1015         (tic54x_cc2_codes): ... this.
1016         (cc3_codes): Rename to ...
1017         (tic54x_cc3_codes): ... this.
1018         (status_bits): Rename to ...
1019         (tic54x_status_bits): ... this.
1020         (misc_symbols): Rename to ...
1021         (tic54x_misc_symbols): ... this.
1022
1023 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1024
1025         * riscv-opc.c (MASK_RVB_IMM): Removed.
1026         (riscv_opcodes): Removed zb* instructions.
1027         (riscv_ext_version_table): Removed versions for zb*.
1028
1029 2021-01-26  Alan Modra  <amodra@gmail.com>
1030
1031         * i386-gen.c (parse_template): Ensure entire template_instance
1032         is initialised.
1033
1034 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1035
1036         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1037         (riscv_fpr_names_abi): Likewise.
1038         (riscv_opcodes): Likewise.
1039         (riscv_insn_types): Likewise.
1040
1041 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1042
1043         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1044
1045 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1046
1047         * riscv-dis.c: Comments tidy and improvement.
1048         * riscv-opc.c: Likewise.
1049
1050 2021-01-13  Alan Modra  <amodra@gmail.com>
1051
1052         * Makefile.in: Regenerate.
1053
1054 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1055
1056         PR binutils/26792
1057         * configure.ac: Use GNU_MAKE_JOBSERVER.
1058         * aclocal.m4: Regenerated.
1059         * configure: Likewise.
1060
1061 2021-01-12  Nick Clifton  <nickc@redhat.com>
1062
1063         * po/sr.po: Updated Serbian translation.
1064
1065 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1066
1067         PR ld/27173
1068         * configure: Regenerated.
1069
1070 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1071
1072         * aarch64-asm-2.c: Regenerate.
1073         * aarch64-dis-2.c: Likewise.
1074         * aarch64-opc-2.c: Likewise.
1075         * aarch64-opc.c (aarch64_print_operand):
1076         Delete handling of AARCH64_OPND_CSRE_CSR.
1077         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1078         (CSRE): Likewise.
1079         (_CSRE_INSN): Likewise.
1080         (aarch64_opcode_table): Delete csr.
1081
1082 2021-01-11  Nick Clifton  <nickc@redhat.com>
1083
1084         * po/de.po: Updated German translation.
1085         * po/fr.po: Updated French translation.
1086         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1087         * po/sv.po: Updated Swedish translation.
1088         * po/uk.po: Updated Ukranian translation.
1089
1090 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1091
1092         * configure: Regenerated.
1093
1094 2021-01-09  Nick Clifton  <nickc@redhat.com>
1095
1096         * configure: Regenerate.
1097         * po/opcodes.pot: Regenerate.
1098
1099 2021-01-09  Nick Clifton  <nickc@redhat.com>
1100
1101         * 2.36 release branch crated.
1102
1103 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1104
1105         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1106         (DW, (XRC_MASK): Define.
1107         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1108
1109 2021-01-09  Alan Modra  <amodra@gmail.com>
1110
1111         * configure: Regenerate.
1112
1113 2021-01-08  Nick Clifton  <nickc@redhat.com>
1114
1115         * po/sv.po: Updated Swedish translation.
1116
1117 2021-01-08  Nick Clifton  <nickc@redhat.com>
1118
1119         PR 27129
1120         * aarch64-dis.c (determine_disassembling_preference): Move call to
1121         aarch64_match_operands_constraint outside of the assertion.
1122         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1123         Replace with a return of FALSE.
1124
1125         PR 27139
1126         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1127         core system register.
1128
1129 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1130
1131         * configure: Regenerate.
1132
1133 2021-01-07  Nick Clifton  <nickc@redhat.com>
1134
1135         * po/fr.po: Updated French translation.
1136
1137 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1138
1139         * m68k-opc.c (chkl): Change minimum architecture requirement to
1140         m68020.
1141
1142 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1143
1144         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1145
1146 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1147             Jim Wilson  <jimw@sifive.com>
1148             Andrew Waterman  <andrew@sifive.com>
1149             Maxim Blinov  <maxim.blinov@embecosm.com>
1150             Kito Cheng  <kito.cheng@sifive.com>
1151             Nelson Chu  <nelson.chu@sifive.com>
1152
1153         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1154         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1155
1156 2021-01-01  Alan Modra  <amodra@gmail.com>
1157
1158         Update year range in copyright notice of all files.
1159
1160 For older changes see ChangeLog-2020
1161 \f
1162 Copyright (C) 2021 Free Software Foundation, Inc.
1163
1164 Copying and distribution of this file, with or without modification,
1165 are permitted in any medium without royalty provided the copyright
1166 notice and this notice are preserved.
1167
1168 Local Variables:
1169 mode: change-log
1170 left-margin: 8
1171 fill-column: 74
1172 version-control: never
1173 End: