opcodes/ChangeLog

   1 2019-12-11  Alan Modra  <amodra@gmail.com>
   2
   3         * m68k-dis.c (COERCE32): Cast value first.
   4         (NEXTLONG, NEXTULONG): Avoid signed overflow.
   5
   6 2019-12-11  Alan Modra  <amodra@gmail.com>
   7
   8         * h8300-dis.c (extract_immediate): Avoid signed overflow.
   9         (bfd_h8_disassemble): Likewise.
  10
  11 2019-12-11  Alan Modra  <amodra@gmail.com>
  12
  13         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
  14         past end of operands array.
  15
  16 2019-12-11  Alan Modra  <amodra@gmail.com>
  17
  18         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
  19         overflow when collecting bytes of a number.
  20
  21 2019-12-11  Alan Modra  <amodra@gmail.com>
  22
  23         * cris-dis.c (print_with_operands): Avoid signed integer
  24         overflow when collecting bytes of a 32-bit integer.
  25
  26 2019-12-11  Alan Modra  <amodra@gmail.com>
  27
  28         * cr16-dis.c (EXTRACT, SBM): Rewrite.
  29         (cr16_match_opcode): Delete duplicate bcond test.
  30
  31 2019-12-11  Alan Modra  <amodra@gmail.com>
  32
  33         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
  34         (SIGNBIT): New.
  35         (MASKBITS, SIGNEXTEND): Rewrite.
  36         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
  37         unsigned arithmetic, instead assign result of SIGNEXTEND back
  38         to x.
  39         (fmtconst_val): Use 1u in shift expression.
  40
  41 2019-12-11  Alan Modra  <amodra@gmail.com>
  42
  43         * arc-dis.c (find_format_from_table): Use ull constant when
  44         shifting by up to 32.
  45
  46 2019-12-11  Alan Modra  <amodra@gmail.com>
  47
  48         PR 25270
  49         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
  50         false when field is zero for sve_size_tsz_bhs.
  51
  52 2019-12-11  Alan Modra  <amodra@gmail.com>
  53
  54         * epiphany-ibld.c: Regenerate.
  55
  56 2019-12-10  Alan Modra  <amodra@gmail.com>
  57
  58         PR 24960
  59         * disassemble.c (disassemble_free_target): New function.
  60
  61 2019-12-10  Alan Modra  <amodra@gmail.com>
  62
  63         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
  64         * disassemble.c (disassemble_init_for_target): Likewise.
  65         * bpf-dis.c: Regenerate.
  66         * epiphany-dis.c: Regenerate.
  67         * fr30-dis.c: Regenerate.
  68         * frv-dis.c: Regenerate.
  69         * ip2k-dis.c: Regenerate.
  70         * iq2000-dis.c: Regenerate.
  71         * lm32-dis.c: Regenerate.
  72         * m32c-dis.c: Regenerate.
  73         * m32r-dis.c: Regenerate.
  74         * mep-dis.c: Regenerate.
  75         * mt-dis.c: Regenerate.
  76         * or1k-dis.c: Regenerate.
  77         * xc16x-dis.c: Regenerate.
  78         * xstormy16-dis.c: Regenerate.
  79
  80 2019-12-10  Alan Modra  <amodra@gmail.com>
  81
  82         * ppc-dis.c (private): Delete variable.
  83         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
  84         (powerpc_init_dialect): Don't use global private.
  85
  86 2019-12-10  Alan Modra  <amodra@gmail.com>
  87
  88         * s12z-opc.c: Formatting.
  89
  90 2019-12-08  Alan Modra  <amodra@gmail.com>
  91
  92         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
  93         registers.
  94
  95 2019-12-05  Jan Beulich  <jbeulich@suse.com>
  96
  97         * aarch64-tbl.h (aarch64_feature_crypto,
  98         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
  99         CRYPTO_V8_2_INSN): Delete.
 100
 101 2019-12-05  Alan Modra  <amodra@gmail.com>
 102
 103         PR 25249
 104         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 105         (struct string_buf): New.
 106         (strbuf): New function.
 107         (get_field): Use strbuf rather than strdup of local temp.
 108         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 109         (get_field_rfsl, get_field_imm15): Likewise.
 110         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 111         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 112         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 113         get_field functions.
 114
 115 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 118         * i386-tbl.h: Re-generate.
 119
 120 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 123
 124 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 125
 126         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 127         forms.
 128         (xbegin): Drop DefaultSize.
 129         * i386-tbl.h: Re-generate.
 130
 131 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 132
 133         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 134         Change the coproc CRC conditions to use the extension
 135         feature set, second word, base on ARM_EXT2_CRC.
 136
 137 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 140         * i386-tbl.h: Re-generate.
 141
 142 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 143
 144         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 145         JumpInterSegment, and JumpAbsolute entries.
 146         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 147         JUMP_ABSOLUTE): Define.
 148         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 149         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 150         fields.
 151         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 152         JumpInterSegment): Define.
 153         * i386-tbl.h: Re-generate.
 154
 155 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 156
 157         * i386-gen.c (operand_type_init): Remove
 158         OPERAND_TYPE_JUMPABSOLUTE entry.
 159         (opcode_modifiers): Add JumpAbsolute entry.
 160         (operand_types): Remove JumpAbsolute entry.
 161         * i386-opc.h (JumpAbsolute): Move between enums.
 162         (struct i386_opcode_modifier): Add jumpabsolute field.
 163         (union i386_operand_type): Remove jumpabsolute field.
 164         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 165         * i386-init.h, i386-tbl.h: Re-generate.
 166
 167 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 168
 169         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 170         (operand_types): Remove AnySize entry.
 171         * i386-opc.h (AnySize): Move between enums.
 172         (struct i386_opcode_modifier): Add anysize field.
 173         (OTUnused): Un-comment.
 174         (union i386_operand_type): Remove anysize field.
 175         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 176         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 177         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 178         AnySize.
 179         * i386-tbl.h: Re-generate.
 180
 181 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 182
 183         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 184         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 185         use the floating point register (FPR).
 186
 187 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 188
 189         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 190         cmode 1101.
 191         (is_mve_encoding_conflict): Update cmode conflict checks for
 192         MVE_VMVN_IMM.
 193
 194 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 195
 196         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 197         entry.
 198         (operand_types): Remove EsSeg entry.
 199         (main): Replace stale use of OTMax.
 200         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 201         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 202         (EsSeg): Delete.
 203         (OTUnused): Comment out.
 204         (union i386_operand_type): Remove esseg field.
 205         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 206         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 207         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 208         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 209         * i386-init.h, i386-tbl.h: Re-generate.
 210
 211 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 212
 213         * i386-gen.c (operand_instances): Add RegB entry.
 214         * i386-opc.h (enum operand_instance): Add RegB.
 215         * i386-opc.tbl (RegC, RegD, RegB): Define.
 216         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 217         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 218         monitorx, mwaitx): Drop ImmExt and convert encodings
 219         accordingly.
 220         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 221         (edx, rdx): Add Instance=RegD.
 222         (ebx, rbx): Add Instance=RegB.
 223         * i386-tbl.h: Re-generate.
 224
 225 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-gen.c (operand_type_init): Adjust
 228         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 229         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 230         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 231         (operand_instances): New.
 232         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 233         (output_operand_type): New parameter "instance". Process it.
 234         (process_i386_operand_type): New local variable "instance".
 235         (main): Adjust static assertions.
 236         * i386-opc.h (INSTANCE_WIDTH): Define.
 237         (enum operand_instance): New.
 238         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 239         (union i386_operand_type): Replace acc, inoutportreg, and
 240         shiftcount by instance.
 241         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 242         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 243         Add Instance=.
 244         * i386-init.h, i386-tbl.h: Re-generate.
 245
 246 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 247
 248         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 249         smaxp/sminp entries' "tied_operand" field to 2.
 250
 251 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 252
 253         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 254         "index" local variable by that of the already existing "num".
 255
 256 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 257
 258         PR gas/25167
 259         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 260         * i386-tbl.h: Regenerated.
 261
 262 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 263
 264         * i386-gen.c (operand_type_init): Add Class= to
 265         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 266         OPERAND_TYPE_REGBND entry.
 267         (operand_classes): Add RegMask and RegBND entries.
 268         (operand_types): Drop RegMask and RegBND entry.
 269         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 270         (RegMask, RegBND): Delete.
 271         (union i386_operand_type): Remove regmask and regbnd fields.
 272         * i386-opc.tbl (RegMask, RegBND): Define.
 273         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 274         Class=RegBND.
 275         * i386-init.h, i386-tbl.h: Re-generate.
 276
 277 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 278
 279         * i386-gen.c (operand_type_init): Add Class= to
 280         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 281         OPERAND_TYPE_REGZMM entries.
 282         (operand_classes): Add RegMMX and RegSIMD entries.
 283         (operand_types): Drop RegMMX and RegSIMD entries.
 284         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 285         (RegMMX, RegSIMD): Delete.
 286         (union i386_operand_type): Remove regmmx and regsimd fields.
 287         * i386-opc.tbl (RegMMX): Define.
 288         (RegXMM, RegYMM, RegZMM): Add Class=.
 289         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 290         Class=RegSIMD.
 291         * i386-init.h, i386-tbl.h: Re-generate.
 292
 293 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 294
 295         * i386-gen.c (operand_type_init): Add Class= to
 296         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 297         entries.
 298         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 299         (operand_types): Drop Control, Debug, and Test entries.
 300         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 301         (Control, Debug, Test): Delete.
 302         (union i386_operand_type): Remove control, debug, and test
 303         fields.
 304         * i386-opc.tbl (Control, Debug, Test): Define.
 305         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 306         Class=RegDR, and Test by Class=RegTR.
 307         * i386-init.h, i386-tbl.h: Re-generate.
 308
 309 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-gen.c (operand_type_init): Add Class= to
 312         OPERAND_TYPE_SREG entry.
 313         (operand_classes): Add SReg entry.
 314         (operand_types): Drop SReg entry.
 315         * i386-opc.h (enum operand_class): Add SReg.
 316         (SReg): Delete.
 317         (union i386_operand_type): Remove sreg field.
 318         * i386-opc.tbl (SReg): Define.
 319         * i386-reg.tbl: Replace SReg by Class=SReg.
 320         * i386-init.h, i386-tbl.h: Re-generate.
 321
 322 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 323
 324         * i386-gen.c (operand_type_init): Add Class=. New
 325         OPERAND_TYPE_ANYIMM entry.
 326         (operand_classes): New.
 327         (operand_types): Drop Reg entry.
 328         (output_operand_type): New parameter "class". Process it.
 329         (process_i386_operand_type): New local variable "class".
 330         (main): Adjust static assertions.
 331         * i386-opc.h (CLASS_WIDTH): Define.
 332         (enum operand_class): New.
 333         (Reg): Replace by Class. Adjust comment.
 334         (union i386_operand_type): Replace reg by class.
 335         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 336         Class=.
 337         * i386-reg.tbl: Replace Reg by Class=Reg.
 338         * i386-init.h: Re-generate.
 339
 340 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 341
 342         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 343         (aarch64_opcode_table): Add data gathering hint mnemonic.
 344         * opcodes/aarch64-dis-2.c: Account for new instruction.
 345
 346 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 347
 348         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 349
 350
 351 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 352
 353         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 354         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 355         aarch64_feature_f64mm): New feature sets.
 356         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 357         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 358         instructions.
 359         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 360         macros.
 361         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 362         (OP_SVE_QQQ): New qualifier.
 363         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 364         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 365         the movprfx constraint.
 366         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 367         (aarch64_opcode_table): Define new instructions smmla,
 368         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 369         uzip{1/2}, trn{1/2}.
 370         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 371         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 372         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 373         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 374         Account for new instructions.
 375         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 376         S4x32 operand.
 377         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 378
 379 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 380 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 381
 382         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 383         Armv8.6-A.
 384         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 385         (neon_opcodes): Add bfloat SIMD instructions.
 386         (print_insn_coprocessor): Add new control character %b to print
 387         condition code without checking cp_num.
 388         (print_insn_neon): Account for BFloat16 instructions that have no
 389         special top-byte handling.
 390
 391 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 392 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 393
 394         * arm-dis.c (print_insn_coprocessor,
 395         print_insn_generic_coprocessor): Create wrapper functions around
 396         the implementation of the print_insn_coprocessor control codes.
 397         (print_insn_coprocessor_1): Original print_insn_coprocessor
 398         function that now takes which array to look at as an argument.
 399         (print_insn_arm): Use both print_insn_coprocessor and
 400         print_insn_generic_coprocessor.
 401         (print_insn_thumb32): As above.
 402
 403 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 404 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 405
 406         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 407         in reglane special case.
 408         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 409         aarch64_find_next_opcode): Account for new instructions.
 410         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 411         in reglane special case.
 412         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 413         new AARCH64_OPND_QLF_S_2H qualifier.
 414         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 415         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 416         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 417         sets.
 418         (BFLOAT_SVE, BFLOAT): New feature set macros.
 419         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 420         instructions.
 421         (aarch64_opcode_table): Define new instructions bfdot,
 422         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 423         bfcvtn2, bfcvt.
 424
 425 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 426 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 427
 428         * aarch64-tbl.h (ARMV8_6): New macro.
 429
 430 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 431
 432         * i386-dis.c (prefix_table): Add mcommit.
 433         (rm_table): Add rdpru.
 434         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 435         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 436         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 437         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 438         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 439         * i386-opc.tbl (mcommit, rdpru): New.
 440         * i386-init.h, i386-tbl.h: Re-generate.
 441
 442 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 443
 444         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 445         "names32" instead.
 446         (OP_Monitor): Drop local variable "op1_names", re-purpose
 447         "names" for it instead, and replace former "names" uses by
 448         "names32" ones.
 449
 450 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 451
 452         PR/gas 25167
 453         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 454         operand-less forms.
 455         * opcodes/i386-tbl.h: Re-generate.
 456
 457 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 458
 459         * i386-dis.c (OP_Mwaitx): Delete.
 460         (prefix_table): Use OP_Mwait for mwaitx entry.
 461         (OP_Mwait): Also handle mwaitx.
 462
 463 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 464
 465         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 466         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 467         (prefix_table): Add respective entries.
 468         (rm_table): Link to those entries.
 469
 470 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 473         (REG_0F1C_P_0_MOD_0): ... this.
 474         (REG_0F1E_MOD_3): Rename to ...
 475         (REG_0F1E_P_1_MOD_3): ... this.
 476         (RM_0F01_REG_5): Rename to ...
 477         (RM_0F01_REG_5_MOD_3): ... this.
 478         (RM_0F01_REG_7): Rename to ...
 479         (RM_0F01_REG_7_MOD_3): ... this.
 480         (RM_0F1E_MOD_3_REG_7): Rename to ...
 481         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 482         (RM_0FAE_REG_6): Rename to ...
 483         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 484         (RM_0FAE_REG_7): Rename to ...
 485         (RM_0FAE_REG_7_MOD_3): ... this.
 486         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 487         (PREFIX_0F01_REG_5_MOD_0): ... this.
 488         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 489         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 490         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 491         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 492         (PREFIX_0FAE_REG_0): Rename to ...
 493         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 494         (PREFIX_0FAE_REG_1): Rename to ...
 495         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 496         (PREFIX_0FAE_REG_2): Rename to ...
 497         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 498         (PREFIX_0FAE_REG_3): Rename to ...
 499         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 500         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 501         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 502         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 503         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 504         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 505         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 506         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 507         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 508         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 509         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 510         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 511         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 512         (PREFIX_0FAE_REG_7): Rename to ...
 513         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 514         (PREFIX_MOD_0_0FC3): Rename to ...
 515         (PREFIX_0FC3_MOD_0): ... this.
 516         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 517         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 518         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 519         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 520         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 521         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 522         (reg_table, prefix_table, mod_table, rm_table): Adjust
 523         accordingly.
 524
 525 2019-11-04  Nick Clifton  <nickc@redhat.com>
 526
 527         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 528         of a v850 system register.  Move the v850_sreg_names array into
 529         this function.
 530         (get_v850_reg_name): Likewise for ordinary register names.
 531         (get_v850_vreg_name): Likewise for vector register names.
 532         (get_v850_cc_name): Likewise for condition codes.
 533         * get_v850_float_cc_name): Likewise for floating point condition
 534         codes.
 535         (get_v850_cacheop_name): Likewise for cache-ops.
 536         (get_v850_prefop_name): Likewise for pref-ops.
 537         (disassemble): Use the new accessor functions.
 538
 539 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 540
 541         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 542         immediate for the writeback form of ldraa/ldrab if it is 0.
 543         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 544         * aarch64-opc-2.c: Regenerated.
 545
 546 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 547
 548         * i386-gen.c (operand_type_shorthands): Delete.
 549         (operand_type_init): Expand previous shorthands.
 550         (set_bitfield_from_shorthand): Rename back to ...
 551         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 552         of operand_type_init[].
 553         (set_bitfield): Adjust call to the above function.
 554         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 555         RegXMM, RegYMM, RegZMM): Define.
 556         * i386-reg.tbl: Expand prior shorthands.
 557
 558 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 559
 560         * i386-gen.c (output_i386_opcode): Change order of fields
 561         emitted to output.
 562         * i386-opc.h (struct insn_template): Move operands field.
 563         Convert extension_opcode field to unsigned short.
 564         * i386-tbl.h: Re-generate.
 565
 566 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 567
 568         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 569         of W.
 570         * i386-opc.h (W): Extend comment.
 571         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 572         general purpose variants not allowing for byte operands.
 573         * i386-tbl.h: Re-generate.
 574
 575 2019-10-29  Nick Clifton  <nickc@redhat.com>
 576
 577         * tic30-dis.c (print_branch): Correct size of operand array.
 578
 579 2019-10-29  Nick Clifton  <nickc@redhat.com>
 580
 581         * d30v-dis.c (print_insn): Check that operand index is valid
 582         before attempting to access the operands array.
 583
 584 2019-10-29  Nick Clifton  <nickc@redhat.com>
 585
 586         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 587         locating the bit to be tested.
 588
 589 2019-10-29  Nick Clifton  <nickc@redhat.com>
 590
 591         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 592         values.
 593         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 594         (print_insn_s12z):  Check for illegal size values.
 595
 596 2019-10-28  Nick Clifton  <nickc@redhat.com>
 597
 598         * csky-dis.c (csky_chars_to_number): Check for a negative
 599         count. Use an unsigned integer to construct the return value.
 600
 601 2019-10-28  Nick Clifton  <nickc@redhat.com>
 602
 603         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 604         operand buffer.  Set value to 15 not 13.
 605         (get_register_operand): Use OPERAND_BUFFER_LEN.
 606         (get_indirect_operand): Likewise.
 607         (print_two_operand): Likewise.
 608         (print_three_operand): Likewise.
 609         (print_oar_insn): Likewise.
 610
 611 2019-10-28  Nick Clifton  <nickc@redhat.com>
 612
 613         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 614         (bit_extract_simple): Likewise.
 615         (bit_copy): Likewise.
 616         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 617         index_offset array are not accessed.
 618
 619 2019-10-28  Nick Clifton  <nickc@redhat.com>
 620
 621         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 622         operand.
 623
 624 2019-10-25  Nick Clifton  <nickc@redhat.com>
 625
 626         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 627         access to opcodes.op array element.
 628
 629 2019-10-23  Nick Clifton  <nickc@redhat.com>
 630
 631         * rx-dis.c (get_register_name): Fix spelling typo in error
 632         message.
 633         (get_condition_name, get_flag_name, get_double_register_name)
 634         (get_double_register_high_name, get_double_register_low_name)
 635         (get_double_control_register_name, get_double_condition_name)
 636         (get_opsize_name, get_size_name): Likewise.
 637
 638 2019-10-22  Nick Clifton  <nickc@redhat.com>
 639
 640         * rx-dis.c (get_size_name): New function.  Provides safe
 641         access to name array.
 642         (get_opsize_name): Likewise.
 643         (print_insn_rx): Use the accessor functions.
 644
 645 2019-10-16  Nick Clifton  <nickc@redhat.com>
 646
 647         * rx-dis.c (get_register_name): New function.  Provides safe
 648         access to name array.
 649         (get_condition_name, get_flag_name, get_double_register_name)
 650         (get_double_register_high_name, get_double_register_low_name)
 651         (get_double_control_register_name, get_double_condition_name):
 652         Likewise.
 653         (print_insn_rx): Use the accessor functions.
 654
 655 2019-10-09  Nick Clifton  <nickc@redhat.com>
 656
 657         PR 25041
 658         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 659         instructions.
 660
 661 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 662
 663         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 664         (cmpsd): Likewise. Move EsSeg to other operand.
 665         * opcodes/i386-tbl.h: Re-generate.
 666
 667 2019-09-23  Alan Modra  <amodra@gmail.com>
 668
 669         * m68k-dis.c: Include cpu-m68k.h
 670
 671 2019-09-23  Alan Modra  <amodra@gmail.com>
 672
 673         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 674         "elf/mips.h" earlier.
 675
 676 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 677
 678         PR gas/25012
 679         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 680         with SReg operand.
 681         * i386-tbl.h: Re-generate.
 682
 683 2019-09-18  Alan Modra  <amodra@gmail.com>
 684
 685         * arc-ext.c: Update throughout for bfd section macro changes.
 686
 687 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 688
 689         * Makefile.in: Re-generate.
 690         * configure: Re-generate.
 691
 692 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 693
 694         * riscv-opc.c (riscv_opcodes): Change subset field
 695         to insn_class field for all instructions.
 696         (riscv_insn_types): Likewise.
 697
 698 2019-09-16  Phil Blundell  <pb@pbcl.net>
 699
 700         * configure: Regenerated.
 701
 702 2019-09-10  Miod Vallat  <miod@online.fr>
 703
 704         PR 24982
 705         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 706
 707 2019-09-09  Phil Blundell  <pb@pbcl.net>
 708
 709         binutils 2.33 branch created.
 710
 711 2019-09-03  Nick Clifton  <nickc@redhat.com>
 712
 713         PR 24961
 714         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 715         greater than zero before indexing via (bufcnt -1).
 716
 717 2019-09-03  Nick Clifton  <nickc@redhat.com>
 718
 719         PR 24958
 720         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 721         (MAX_SPEC_REG_NAME_LEN): Define.
 722         (struct mmix_dis_info): Use defined constants for array lengths.
 723         (get_reg_name): New function.
 724         (get_sprec_reg_name): New function.
 725         (print_insn_mmix): Use new functions.
 726
 727 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 728
 729         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 730         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 731         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 732
 733 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 734
 735         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 736         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 737         (aarch64_sys_reg_supported_p): Update checks for the above.
 738
 739 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 740
 741         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 742         cases MVE_SQRSHRL and MVE_UQRSHLL.
 743         (print_insn_mve): Add case for specifier 'k' to check
 744         specific bit of the instruction.
 745
 746 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 747
 748         PR 24854
 749         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 750         encountering an unknown machine type.
 751         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 752         cases return -1 rather than calling abort.
 753
 754 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 755
 756         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 757         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 758         IgnoreSize.
 759         * i386-tbl.h: Re-generate.
 760
 761 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 762
 763         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 764         instructions.
 765
 766 2019-07-30  Mel Chen <mel.chen@sifive.com>
 767
 768         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 769         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 770
 771         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 772         fscsr.
 773
 774 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 775
 776         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 777         and MPY class instructions.
 778         (parse_option): Add nps400 option.
 779         (print_arc_disassembler_options): Add nps400 info.
 780
 781 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 782
 783         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 784         (bspop): Likewise.
 785         (modapp): Likewise.
 786         * arc-opc.c (RAD_CHK): Add.
 787         * arc-tbl.h: Regenerate.
 788
 789 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 790
 791         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 792         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 793
 794 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 795
 796         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 797         instructions as UNPREDICTABLE.
 798
 799 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 800
 801         * bpf-desc.c: Regenerated.
 802
 803 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 804
 805         * i386-gen.c (static_assert): Define.
 806         (main): Use it.
 807         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 808         (Opcode_Modifier_Num): ... this.
 809         (Mem): Delete.
 810
 811 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 812
 813         * i386-gen.c (operand_types): Move RegMem ...
 814         (opcode_modifiers): ... here.
 815         * i386-opc.h (RegMem): Move to opcode modifer enum.
 816         (union i386_operand_type): Move regmem field ...
 817         (struct i386_opcode_modifier): ... here.
 818         * i386-opc.tbl (RegMem): Define.
 819         (mov, movq): Move RegMem on segment, control, debug, and test
 820         register flavors.
 821         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 822         to non-SSE2AVX flavor.
 823         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 824         Move RegMem on register only flavors. Drop IgnoreSize from
 825         legacy encoding flavors.
 826         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 827         flavors.
 828         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 829         register only flavors.
 830         (vmovd): Move RegMem and drop IgnoreSize on register only
 831         flavor. Change opcode and operand order to store form.
 832         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 833
 834 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 835
 836         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 837         entries.
 838         * i386-opc.h (SReg2, SReg3): Replace by ...
 839         (SReg): ... this.
 840         (union i386_operand_type): Replace sreg fields.
 841         * i386-opc.tbl (mov, ): Use SReg.
 842         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 843         register flavors.
 844         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 845         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 846
 847 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 848
 849         * bpf-desc.c: Regenerate.
 850         * bpf-opc.c: Likewise.
 851         * bpf-opc.h: Likewise.
 852
 853 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 854
 855         * bpf-desc.c: Regenerate.
 856         * bpf-opc.c: Likewise.
 857
 858 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 859
 860         * arm-dis.c (print_insn_coprocessor): Rename index to
 861         index_operand.
 862
 863 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 864
 865         * riscv-opc.c (riscv_insn_types): Add r4 type.
 866
 867         * riscv-opc.c (riscv_insn_types): Add b and j type.
 868
 869         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 870         format for sb type and correct s type.
 871
 872 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 873
 874         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 875         SVE FMOV alias of FCPY.
 876
 877 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 878
 879         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 880         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 881
 882 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 883
 884         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 885         registers in an instruction prefixed by MOVPRFX.
 886
 887 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 888
 889         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 890         sve_size_13 icode to account for variant behaviour of
 891         pmull{t,b}.
 892         * aarch64-dis-2.c: Regenerate.
 893         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 894         sve_size_13 icode to account for variant behaviour of
 895         pmull{t,b}.
 896         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 897         (OP_SVE_VVV_Q_D): Add new qualifier.
 898         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 899         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 900         AES and those not.
 901
 902 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 903
 904         * opcodes/i386-gen.c (operand_type_init): Remove
 905         OPERAND_TYPE_VEC_IMM4 entry.
 906         (operand_types): Remove Vec_Imm4.
 907         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 908         (union i386_operand_type): Remove vec_imm4.
 909         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 910         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 911
 912 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 913
 914         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 915         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 916         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 917         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 918         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 919         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 920         * i386-tbl.h: Re-generate.
 921
 922 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 923
 924         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 925         register operands.
 926         * i386-tbl.h: Re-generate.
 927
 928 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 929
 930         * i386-opc.tbl (C): New.
 931         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 932         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 933         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 934         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 935         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 936         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 937         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 938         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 939         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 940         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 941         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 942         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 943         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 944         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 945         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 946         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 947         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 948         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 949         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 950         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 951         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 952         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 953         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 954         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 955         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 956         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 957         flavors.
 958         * i386-tbl.h: Re-generate.
 959
 960 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 961
 962         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 963         register operands.
 964         * i386-tbl.h: Re-generate.
 965
 966 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 967
 968         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 969         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 970         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 971         * i386-tbl.h: Re-generate.
 972
 973 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 974
 975         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 976         Disp8MemShift from register only templates.
 977         * i386-tbl.h: Re-generate.
 978
 979 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 980
 981         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 982         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 983         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 984         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 985         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 986         EVEX_W_0F11_P_3_M_1): Delete.
 987         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 988         EVEX_W_0F11_P_3): New.
 989         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 990         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 991         MOD_EVEX_0F11_PREFIX_3 table entries.
 992         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 993         PREFIX_EVEX_0F11 table entries.
 994         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 995         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 996         EVEX_W_0F11_P_3_M_{0,1} table entries.
 997
 998 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 999
1000         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1001         Delete.
1002
1003 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1004
1005         PR binutils/24719
1006         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1007         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1008         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1009         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1010         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1011         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1012         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1013         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1014         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1015         PREFIX_EVEX_0F38C6_REG_6 entries.
1016         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1017         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1018         EVEX_W_0F38C7_R_6_P_2 entries.
1019         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1020         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1021         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1022         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1023         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1024         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1025         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1026
1027 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1030         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1031         VEX_LEN_0F2D_P_3): Delete.
1032         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1033         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1034         (prefix_table): ... here.
1035
1036 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1037
1038         * i386-dis.c (Iq): Delete.
1039         (Id): New.
1040         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1041         TBM insns.
1042         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1043         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1044         (OP_E_memory): Also honor needindex when deciding whether an
1045         address size prefix needs printing.
1046         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1047
1048 2019-06-26  Jim Wilson  <jimw@sifive.com>
1049
1050         PR binutils/24739
1051         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1052         Set info->display_endian to info->endian_code.
1053
1054 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1057         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1058         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1059         OPERAND_TYPE_ACC64 entries.
1060         * i386-init.h: Re-generate.
1061
1062 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1063
1064         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1065         Delete.
1066         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1067         of dqa_mode.
1068         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1069         entries here.
1070         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1071         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1072
1073 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1074
1075         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1076         variables.
1077
1078 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1079
1080         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1081         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1082         movnti.
1083         * i386-opc.tbl (movnti): Add IgnoreSize.
1084         * i386-tbl.h: Re-generate.
1085
1086 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1087
1088         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1089         * i386-tbl.h: Re-generate.
1090
1091 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1092
1093         * i386-dis-evex.h: Break into ...
1094         * i386-dis-evex-len.h: New file.
1095         * i386-dis-evex-mod.h: Likewise.
1096         * i386-dis-evex-prefix.h: Likewise.
1097         * i386-dis-evex-reg.h: Likewise.
1098         * i386-dis-evex-w.h: Likewise.
1099         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1100         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1101         i386-dis-evex-mod.h.
1102
1103 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1104
1105         PR binutils/24700
1106         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1107         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1108         EVEX_W_0F385B_P_2.
1109         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1110         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1111         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1112         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1113         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1114         EVEX_LEN_0F385B_P_2_W_1.
1115         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1116         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1117         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1118         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1119         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1120         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1121         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1122         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1123         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1124         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1125
1126 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1127
1128         PR binutils/24691
1129         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1130         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1131         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1132         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1133         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1134         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1135         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1136         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1137         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1138         EVEX_LEN_0F3A43_P_2_W_1.
1139         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1140         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1141         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1142         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1143         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1144         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1145         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1146         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1147         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1148         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1149         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1150         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1151
1152 2019-06-14  Nick Clifton  <nickc@redhat.com>
1153
1154         * po/fr.po; Updated French translation.
1155
1156 2019-06-13  Stafford Horne  <shorne@gmail.com>
1157
1158         * or1k-asm.c: Regenerated.
1159         * or1k-desc.c: Regenerated.
1160         * or1k-desc.h: Regenerated.
1161         * or1k-dis.c: Regenerated.
1162         * or1k-ibld.c: Regenerated.
1163         * or1k-opc.c: Regenerated.
1164         * or1k-opc.h: Regenerated.
1165         * or1k-opinst.c: Regenerated.
1166
1167 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1168
1169         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1170
1171 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1172
1173         PR binutils/24633
1174         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1175         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1176         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1177         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1178         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1179         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1180         EVEX_LEN_0F3A1B_P_2_W_1.
1181         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1182         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1183         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1184         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1185         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1186         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1187         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1188         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1189
1190 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1191
1192         PR binutils/24626
1193         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1194         EVEX.vvvv when disassembling VEX and EVEX instructions.
1195         (OP_VEX): Set vex.register_specifier to 0 after readding
1196         vex.register_specifier.
1197         (OP_Vex_2src_1): Likewise.
1198         (OP_Vex_2src_2): Likewise.
1199         (OP_LWP_E): Likewise.
1200         (OP_EX_Vex): Don't check vex.register_specifier.
1201         (OP_XMM_Vex): Likewise.
1202
1203 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1204             Lili Cui  <lili.cui@intel.com>
1205
1206         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1207         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1208         instructions.
1209         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1210         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1211         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1212         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1213         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1214         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1215         * i386-init.h: Regenerated.
1216         * i386-tbl.h: Likewise.
1217
1218 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1219             Lili Cui  <lili.cui@intel.com>
1220
1221         * doc/c-i386.texi: Document enqcmd.
1222         * testsuite/gas/i386/enqcmd-intel.d: New file.
1223         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1224         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1225         * testsuite/gas/i386/enqcmd.d: Likewise.
1226         * testsuite/gas/i386/enqcmd.s: Likewise.
1227         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1228         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1229         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1230         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1231         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1232         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1233         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1234         and x86-64-enqcmd.
1235
1236 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1237
1238         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1239
1240 2019-06-03  Alan Modra  <amodra@gmail.com>
1241
1242         * ppc-dis.c (prefix_opcd_indices): Correct size.
1243
1244 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1245
1246         PR gas/24625
1247         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1248         Disp8ShiftVL.
1249         * i386-tbl.h: Regenerated.
1250
1251 2019-05-24  Alan Modra  <amodra@gmail.com>
1252
1253         * po/POTFILES.in: Regenerate.
1254
1255 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1256             Alan Modra  <amodra@gmail.com>
1257
1258         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1259         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1260         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1261         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1262         XTOP>): Define and add entries.
1263         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1264         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1265         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1266         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1267
1268 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1269             Alan Modra  <amodra@gmail.com>
1270
1271         * ppc-dis.c (ppc_opts): Add "future" entry.
1272         (PREFIX_OPCD_SEGS): Define.
1273         (prefix_opcd_indices): New array.
1274         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1275         (lookup_prefix): New function.
1276         (print_insn_powerpc): Handle 64-bit prefix instructions.
1277         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1278         (PMRR, POWERXX): Define.
1279         (prefix_opcodes): New instruction table.
1280         (prefix_num_opcodes): New constant.
1281
1282 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1283
1284         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1285         * configure: Regenerated.
1286         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1287         and cpu/bpf.opc.
1288         (HFILES): Add bpf-desc.h and bpf-opc.h.
1289         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1290         bpf-ibld.c and bpf-opc.c.
1291         (BPF_DEPS): Define.
1292         * Makefile.in: Regenerated.
1293         * disassemble.c (ARCH_bpf): Define.
1294         (disassembler): Add case for bfd_arch_bpf.
1295         (disassemble_init_for_target): Likewise.
1296         (enum epbf_isa_attr): Define.
1297         * disassemble.h: extern print_insn_bpf.
1298         * bpf-asm.c: Generated.
1299         * bpf-opc.h: Likewise.
1300         * bpf-opc.c: Likewise.
1301         * bpf-ibld.c: Likewise.
1302         * bpf-dis.c: Likewise.
1303         * bpf-desc.h: Likewise.
1304         * bpf-desc.c: Likewise.
1305
1306 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1307
1308         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1309         and VMSR with the new operands.
1310
1311 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1312
1313         * arm-dis.c (enum mve_instructions): New enum
1314         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1315         and cneg.
1316         (mve_opcodes): New instructions as above.
1317         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1318         csneg and csel.
1319         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1320
1321 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1322
1323         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1324         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1325         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1326         uqshl, urshrl and urshr.
1327         (is_mve_okay_in_it): Add new instructions to TRUE list.
1328         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1329         (print_insn_mve): Updated to accept new %j,
1330         %<bitfield>m and %<bitfield>n patterns.
1331
1332 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1333
1334         * mips-opc.c (mips_builtin_opcodes): Change source register
1335         constraint for DAUI.
1336
1337 2019-05-20  Nick Clifton  <nickc@redhat.com>
1338
1339         * po/fr.po: Updated French translation.
1340
1341 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1342             Michael Collison <michael.collison@arm.com>
1343
1344         * arm-dis.c (thumb32_opcodes): Add new instructions.
1345         (enum mve_instructions): Likewise.
1346         (enum mve_undefined): Add new reasons.
1347         (is_mve_encoding_conflict): Handle new instructions.
1348         (is_mve_undefined): Likewise.
1349         (is_mve_unpredictable): Likewise.
1350         (print_mve_undefined): Likewise.
1351         (print_mve_size): Likewise.
1352
1353 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1354             Michael Collison <michael.collison@arm.com>
1355
1356         * arm-dis.c (thumb32_opcodes): Add new instructions.
1357         (enum mve_instructions): Likewise.
1358         (is_mve_encoding_conflict): Handle new instructions.
1359         (is_mve_undefined): Likewise.
1360         (is_mve_unpredictable): Likewise.
1361         (print_mve_size): Likewise.
1362
1363 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1364             Michael Collison <michael.collison@arm.com>
1365
1366         * arm-dis.c (thumb32_opcodes): Add new instructions.
1367         (enum mve_instructions): Likewise.
1368         (is_mve_encoding_conflict): Likewise.
1369         (is_mve_unpredictable): Likewise.
1370         (print_mve_size): Likewise.
1371
1372 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1373             Michael Collison <michael.collison@arm.com>
1374
1375         * arm-dis.c (thumb32_opcodes): Add new instructions.
1376         (enum mve_instructions): Likewise.
1377         (is_mve_encoding_conflict): Handle new instructions.
1378         (is_mve_undefined): Likewise.
1379         (is_mve_unpredictable): Likewise.
1380         (print_mve_size): Likewise.
1381
1382 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1383             Michael Collison <michael.collison@arm.com>
1384
1385         * arm-dis.c (thumb32_opcodes): Add new instructions.
1386         (enum mve_instructions): Likewise.
1387         (is_mve_encoding_conflict): Handle new instructions.
1388         (is_mve_undefined): Likewise.
1389         (is_mve_unpredictable): Likewise.
1390         (print_mve_size): Likewise.
1391         (print_insn_mve): Likewise.
1392
1393 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1394             Michael Collison <michael.collison@arm.com>
1395
1396         * arm-dis.c (thumb32_opcodes): Add new instructions.
1397         (print_insn_thumb32): Handle new instructions.
1398
1399 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1400             Michael Collison <michael.collison@arm.com>
1401
1402         * arm-dis.c (enum mve_instructions): Add new instructions.
1403         (enum mve_undefined): Add new reasons.
1404         (is_mve_encoding_conflict): Handle new instructions.
1405         (is_mve_undefined): Likewise.
1406         (is_mve_unpredictable): Likewise.
1407         (print_mve_undefined): Likewise.
1408         (print_mve_size): Likewise.
1409         (print_mve_shift_n): Likewise.
1410         (print_insn_mve): Likewise.
1411
1412 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1413             Michael Collison <michael.collison@arm.com>
1414
1415         * arm-dis.c (enum mve_instructions): Add new instructions.
1416         (is_mve_encoding_conflict): Handle new instructions.
1417         (is_mve_unpredictable): Likewise.
1418         (print_mve_rotate): Likewise.
1419         (print_mve_size): Likewise.
1420         (print_insn_mve): Likewise.
1421
1422 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1423             Michael Collison <michael.collison@arm.com>
1424
1425         * arm-dis.c (enum mve_instructions): Add new instructions.
1426         (is_mve_encoding_conflict): Handle new instructions.
1427         (is_mve_unpredictable): Likewise.
1428         (print_mve_size): Likewise.
1429         (print_insn_mve): Likewise.
1430
1431 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1432             Michael Collison <michael.collison@arm.com>
1433
1434         * arm-dis.c (enum mve_instructions): Add new instructions.
1435         (enum mve_undefined): Add new reasons.
1436         (is_mve_encoding_conflict): Handle new instructions.
1437         (is_mve_undefined): Likewise.
1438         (is_mve_unpredictable): Likewise.
1439         (print_mve_undefined): Likewise.
1440         (print_mve_size): Likewise.
1441         (print_insn_mve): Likewise.
1442
1443 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1444             Michael Collison <michael.collison@arm.com>
1445
1446         * arm-dis.c (enum mve_instructions): Add new instructions.
1447         (is_mve_encoding_conflict): Handle new instructions.
1448         (is_mve_undefined): Likewise.
1449         (is_mve_unpredictable): Likewise.
1450         (print_mve_size): Likewise.
1451         (print_insn_mve): Likewise.
1452
1453 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1454             Michael Collison <michael.collison@arm.com>
1455
1456         * arm-dis.c (enum mve_instructions): Add new instructions.
1457         (enum mve_unpredictable): Add new reasons.
1458         (enum mve_undefined): Likewise.
1459         (is_mve_okay_in_it): Handle new isntructions.
1460         (is_mve_encoding_conflict): Likewise.
1461         (is_mve_undefined): Likewise.
1462         (is_mve_unpredictable): Likewise.
1463         (print_mve_vmov_index): Likewise.
1464         (print_simd_imm8): Likewise.
1465         (print_mve_undefined): Likewise.
1466         (print_mve_unpredictable): Likewise.
1467         (print_mve_size): Likewise.
1468         (print_insn_mve): Likewise.
1469
1470 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1471             Michael Collison <michael.collison@arm.com>
1472
1473         * arm-dis.c (enum mve_instructions): Add new instructions.
1474         (enum mve_unpredictable): Add new reasons.
1475         (enum mve_undefined): Likewise.
1476         (is_mve_encoding_conflict): Handle new instructions.
1477         (is_mve_undefined): Likewise.
1478         (is_mve_unpredictable): Likewise.
1479         (print_mve_undefined): Likewise.
1480         (print_mve_unpredictable): Likewise.
1481         (print_mve_rounding_mode): Likewise.
1482         (print_mve_vcvt_size): Likewise.
1483         (print_mve_size): Likewise.
1484         (print_insn_mve): Likewise.
1485
1486 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1487             Michael Collison <michael.collison@arm.com>
1488
1489         * arm-dis.c (enum mve_instructions): Add new instructions.
1490         (enum mve_unpredictable): Add new reasons.
1491         (enum mve_undefined): Likewise.
1492         (is_mve_undefined): Handle new instructions.
1493         (is_mve_unpredictable): Likewise.
1494         (print_mve_undefined): Likewise.
1495         (print_mve_unpredictable): Likewise.
1496         (print_mve_size): Likewise.
1497         (print_insn_mve): Likewise.
1498
1499 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1500             Michael Collison <michael.collison@arm.com>
1501
1502         * arm-dis.c (enum mve_instructions): Add new instructions.
1503         (enum mve_undefined): Add new reasons.
1504         (insns): Add new instructions.
1505         (is_mve_encoding_conflict):
1506         (print_mve_vld_str_addr): New print function.
1507         (is_mve_undefined): Handle new instructions.
1508         (is_mve_unpredictable): Likewise.
1509         (print_mve_undefined): Likewise.
1510         (print_mve_size): Likewise.
1511         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1512         (print_insn_mve):  Handle new operands.
1513
1514 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1515             Michael Collison <michael.collison@arm.com>
1516
1517         * arm-dis.c (enum mve_instructions): Add new instructions.
1518         (enum mve_unpredictable): Add new reasons.
1519         (is_mve_encoding_conflict): Handle new instructions.
1520         (is_mve_unpredictable): Likewise.
1521         (mve_opcodes): Add new instructions.
1522         (print_mve_unpredictable): Handle new reasons.
1523         (print_mve_register_blocks): New print function.
1524         (print_mve_size): Handle new instructions.
1525         (print_insn_mve): Likewise.
1526
1527 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1528             Michael Collison <michael.collison@arm.com>
1529
1530         * arm-dis.c (enum mve_instructions): Add new instructions.
1531         (enum mve_unpredictable): Add new reasons.
1532         (enum mve_undefined): Likewise.
1533         (is_mve_encoding_conflict): Handle new instructions.
1534         (is_mve_undefined): Likewise.
1535         (is_mve_unpredictable): Likewise.
1536         (coprocessor_opcodes): Move NEON VDUP from here...
1537         (neon_opcodes): ... to here.
1538         (mve_opcodes): Add new instructions.
1539         (print_mve_undefined):  Handle new reasons.
1540         (print_mve_unpredictable): Likewise.
1541         (print_mve_size): Handle new instructions.
1542         (print_insn_neon): Handle vdup.
1543         (print_insn_mve): Handle new operands.
1544
1545 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1546             Michael Collison <michael.collison@arm.com>
1547
1548         * arm-dis.c (enum mve_instructions): Add new instructions.
1549         (enum mve_unpredictable): Add new values.
1550         (mve_opcodes): Add new instructions.
1551         (vec_condnames): New array with vector conditions.
1552         (mve_predicatenames): New array with predicate suffixes.
1553         (mve_vec_sizename): New array with vector sizes.
1554         (enum vpt_pred_state): New enum with vector predication states.
1555         (struct vpt_block): New struct type for vpt blocks.
1556         (vpt_block_state): Global struct to keep track of state.
1557         (mve_extract_pred_mask): New helper function.
1558         (num_instructions_vpt_block): Likewise.
1559         (mark_outside_vpt_block): Likewise.
1560         (mark_inside_vpt_block): Likewise.
1561         (invert_next_predicate_state): Likewise.
1562         (update_next_predicate_state): Likewise.
1563         (update_vpt_block_state): Likewise.
1564         (is_vpt_instruction): Likewise.
1565         (is_mve_encoding_conflict): Add entries for new instructions.
1566         (is_mve_unpredictable): Likewise.
1567         (print_mve_unpredictable): Handle new cases.
1568         (print_instruction_predicate): Likewise.
1569         (print_mve_size): New function.
1570         (print_vec_condition): New function.
1571         (print_insn_mve): Handle vpt blocks and new print operands.
1572
1573 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1574
1575         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1576         8, 14 and 15 for Armv8.1-M Mainline.
1577
1578 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1579             Michael Collison <michael.collison@arm.com>
1580
1581         * arm-dis.c (enum mve_instructions): New enum.
1582         (enum mve_unpredictable): Likewise.
1583         (enum mve_undefined): Likewise.
1584         (struct mopcode32): New struct.
1585         (is_mve_okay_in_it): New function.
1586         (is_mve_architecture): Likewise.
1587         (arm_decode_field): Likewise.
1588         (arm_decode_field_multiple): Likewise.
1589         (is_mve_encoding_conflict): Likewise.
1590         (is_mve_undefined): Likewise.
1591         (is_mve_unpredictable): Likewise.
1592         (print_mve_undefined): Likewise.
1593         (print_mve_unpredictable): Likewise.
1594         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1595         (print_insn_mve): New function.
1596         (print_insn_thumb32): Handle MVE architecture.
1597         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1598
1599 2019-05-10  Nick Clifton  <nickc@redhat.com>
1600
1601         PR 24538
1602         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1603         end of the table prematurely.
1604
1605 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1606
1607         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1608         macros for R6.
1609
1610 2019-05-11  Alan Modra  <amodra@gmail.com>
1611
1612         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1613         when -Mraw is in effect.
1614
1615 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1616
1617         * aarch64-dis-2.c: Regenerate.
1618         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1619         (OP_SVE_BBB): New variant set.
1620         (OP_SVE_DDDD): New variant set.
1621         (OP_SVE_HHH): New variant set.
1622         (OP_SVE_HHHU): New variant set.
1623         (OP_SVE_SSS): New variant set.
1624         (OP_SVE_SSSU): New variant set.
1625         (OP_SVE_SHH): New variant set.
1626         (OP_SVE_SBBU): New variant set.
1627         (OP_SVE_DSS): New variant set.
1628         (OP_SVE_DHHU): New variant set.
1629         (OP_SVE_VMV_HSD_BHS): New variant set.
1630         (OP_SVE_VVU_HSD_BHS): New variant set.
1631         (OP_SVE_VVVU_SD_BH): New variant set.
1632         (OP_SVE_VVVU_BHSD): New variant set.
1633         (OP_SVE_VVV_QHD_DBS): New variant set.
1634         (OP_SVE_VVV_HSD_BHS): New variant set.
1635         (OP_SVE_VVV_HSD_BHS2): New variant set.
1636         (OP_SVE_VVV_BHS_HSD): New variant set.
1637         (OP_SVE_VV_BHS_HSD): New variant set.
1638         (OP_SVE_VVV_SD): New variant set.
1639         (OP_SVE_VVU_BHS_HSD): New variant set.
1640         (OP_SVE_VZVV_SD): New variant set.
1641         (OP_SVE_VZVV_BH): New variant set.
1642         (OP_SVE_VZV_SD): New variant set.
1643         (aarch64_opcode_table): Add sve2 instructions.
1644
1645 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1646
1647         * aarch64-asm-2.c: Regenerated.
1648         * aarch64-dis-2.c: Regenerated.
1649         * aarch64-opc-2.c: Regenerated.
1650         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1651         for SVE_SHLIMM_UNPRED_22.
1652         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1653         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1654         operand.
1655
1656 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1657
1658         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1659         sve_size_tsz_bhs iclass encode.
1660         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1661         sve_size_tsz_bhs iclass decode.
1662
1663 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1664
1665         * aarch64-asm-2.c: Regenerated.
1666         * aarch64-dis-2.c: Regenerated.
1667         * aarch64-opc-2.c: Regenerated.
1668         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1669         for SVE_Zm4_11_INDEX.
1670         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1671         (fields): Handle SVE_i2h field.
1672         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1673         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1674
1675 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1676
1677         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1678         sve_shift_tsz_bhsd iclass encode.
1679         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1680         sve_shift_tsz_bhsd iclass decode.
1681
1682 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1683
1684         * aarch64-asm-2.c: Regenerated.
1685         * aarch64-dis-2.c: Regenerated.
1686         * aarch64-opc-2.c: Regenerated.
1687         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1688         (aarch64_encode_variant_using_iclass): Handle
1689         sve_shift_tsz_hsd iclass encode.
1690         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1691         sve_shift_tsz_hsd iclass decode.
1692         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1693         for SVE_SHRIMM_UNPRED_22.
1694         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1695         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1696         operand.
1697
1698 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1699
1700         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1701         sve_size_013 iclass encode.
1702         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1703         sve_size_013 iclass decode.
1704
1705 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1706
1707         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1708         sve_size_bh iclass encode.
1709         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1710         sve_size_bh iclass decode.
1711
1712 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1713
1714         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1715         sve_size_sd2 iclass encode.
1716         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1717         sve_size_sd2 iclass decode.
1718         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1719         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1720
1721 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1722
1723         * aarch64-asm-2.c: Regenerated.
1724         * aarch64-dis-2.c: Regenerated.
1725         * aarch64-opc-2.c: Regenerated.
1726         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1727         for SVE_ADDR_ZX.
1728         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1729         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1730
1731 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1732
1733         * aarch64-asm-2.c: Regenerated.
1734         * aarch64-dis-2.c: Regenerated.
1735         * aarch64-opc-2.c: Regenerated.
1736         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1737         for SVE_Zm3_11_INDEX.
1738         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1739         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1740         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1741         fields.
1742         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1743
1744 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1745
1746         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1747         sve_size_hsd2 iclass encode.
1748         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1749         sve_size_hsd2 iclass decode.
1750         * aarch64-opc.c (fields): Handle SVE_size field.
1751         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1752
1753 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1754
1755         * aarch64-asm-2.c: Regenerated.
1756         * aarch64-dis-2.c: Regenerated.
1757         * aarch64-opc-2.c: Regenerated.
1758         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1759         for SVE_IMM_ROT3.
1760         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1761         (fields): Handle SVE_rot3 field.
1762         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1763         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1764
1765 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1766
1767         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1768         instructions.
1769
1770 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1771
1772         * aarch64-tbl.h
1773         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1774         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1775         aarch64_feature_sve2bitperm): New feature sets.
1776         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1777         for feature set addresses.
1778         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1779         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1780
1781 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1782             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1783
1784         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1785         argument and set ASE_EVA_R6 appropriately.
1786         (set_default_mips_dis_options): Pass ISA to above.
1787         (parse_mips_dis_option): Likewise.
1788         * mips-opc.c (EVAR6): New macro.
1789         (mips_builtin_opcodes): Add llwpe, scwpe.
1790
1791 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1792
1793         * aarch64-asm-2.c: Regenerated.
1794         * aarch64-dis-2.c: Regenerated.
1795         * aarch64-opc-2.c: Regenerated.
1796         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1797         AARCH64_OPND_TME_UIMM16.
1798         (aarch64_print_operand): Likewise.
1799         * aarch64-tbl.h (QL_IMM_NIL): New.
1800         (TME): New.
1801         (_TME_INSN): New.
1802         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1803
1804 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1805
1806         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1807
1808 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1809             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1810
1811         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1812
1813 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1814
1815         * s12z-opc.h: Add extern "C" bracketing to help
1816         users who wish to use this interface in c++ code.
1817
1818 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1819
1820         * s12z-opc.c (bm_decode): Handle bit map operations with the
1821         "reserved0" mode.
1822
1823 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1824
1825         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1826         specifier.  Add entries for VLDR and VSTR of system registers.
1827         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1828         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1829         of %J and %K format specifier.
1830
1831 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1832
1833         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1834         Add new entries for VSCCLRM instruction.
1835         (print_insn_coprocessor): Handle new %C format control code.
1836
1837 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1838
1839         * arm-dis.c (enum isa): New enum.
1840         (struct sopcode32): New structure.
1841         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1842         set isa field of all current entries to ANY.
1843         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1844         Only match an entry if its isa field allows the current mode.
1845
1846 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1847
1848         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1849         CLRM.
1850         (print_insn_thumb32): Add logic to print %n CLRM register list.
1851
1852 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1853
1854         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1855         and %Q patterns.
1856
1857 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1858
1859         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1860         (print_insn_thumb32): Edit the switch case for %Z.
1861
1862 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1863
1864         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1865
1866 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1867
1868         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1869
1870 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1871
1872         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1873
1874 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1875
1876         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1877         Arm register with r13 and r15 unpredictable.
1878         (thumb32_opcodes): New instructions for bfx and bflx.
1879
1880 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1881
1882         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1883
1884 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1885
1886         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1887
1888 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1889
1890         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1891
1892 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1893
1894         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1895
1896 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1897
1898         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1899         "optr". ("operator" is a reserved word in c++).
1900
1901 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1902
1903         * aarch64-opc.c (aarch64_print_operand): Add case for
1904         AARCH64_OPND_Rt_SP.
1905         (verify_constraints): Likewise.
1906         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1907         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1908         to accept Rt|SP as first operand.
1909         (AARCH64_OPERANDS): Add new Rt_SP.
1910         * aarch64-asm-2.c: Regenerated.
1911         * aarch64-dis-2.c: Regenerated.
1912         * aarch64-opc-2.c: Regenerated.
1913
1914 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1915
1916         * aarch64-asm-2.c: Regenerated.
1917         * aarch64-dis-2.c: Likewise.
1918         * aarch64-opc-2.c: Likewise.
1919         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1920
1921 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1922
1923         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1924
1925 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1926
1927         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1928         * i386-init.h: Regenerated.
1929
1930 2019-04-07  Alan Modra  <amodra@gmail.com>
1931
1932         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1933         op_separator to control printing of spaces, comma and parens
1934         rather than need_comma, need_paren and spaces vars.
1935
1936 2019-04-07  Alan Modra  <amodra@gmail.com>
1937
1938         PR 24421
1939         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1940         (print_insn_neon, print_insn_arm): Likewise.
1941
1942 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1943
1944         * i386-dis-evex.h (evex_table): Updated to support BF16
1945         instructions.
1946         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1947         and EVEX_W_0F3872_P_3.
1948         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1949         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1950         * i386-opc.h (enum): Add CpuAVX512_BF16.
1951         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1952         * i386-opc.tbl: Add AVX512 BF16 instructions.
1953         * i386-init.h: Regenerated.
1954         * i386-tbl.h: Likewise.
1955
1956 2019-04-05  Alan Modra  <amodra@gmail.com>
1957
1958         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1959         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1960         to favour printing of "-" branch hint when using the "y" bit.
1961         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1962
1963 2019-04-05  Alan Modra  <amodra@gmail.com>
1964
1965         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1966         opcode until first operand is output.
1967
1968 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1969
1970         PR gas/24349
1971         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1972         (valid_bo_post_v2): Add support for 'at' branch hints.
1973         (insert_bo): Only error on branch on ctr.
1974         (get_bo_hint_mask): New function.
1975         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1976         for inserting 'at' branch hints.
1977         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1978         for extracting 'at' branch hints.
1979         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1980         (BOE): Delete operand.
1981         (BOM, BOP): New operands.
1982         (RM): Update value.
1983         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1984         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1985         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1986         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1987         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1988         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1989         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1990         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1991         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1992         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1993         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1994         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1995         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1996         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1997         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1998         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1999         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2000         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2001         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2002         bttarl+>: New extended mnemonics.
2003
2004 2019-03-28  Alan Modra  <amodra@gmail.com>
2005
2006         PR 24390
2007         * ppc-opc.c (BTF): Define.
2008         (powerpc_opcodes): Use for mtfsb*.
2009         * ppc-dis.c (print_insn_powerpc): Print fields with both
2010         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2011
2012 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2013
2014         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2015         (mapping_symbol_for_insn): Implement new algorithm.
2016         (print_insn): Remove duplicate code.
2017
2018 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2019
2020         * aarch64-dis.c (print_insn_aarch64):
2021         Implement override.
2022
2023 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2024
2025         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2026         order.
2027
2028 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2029
2030         * aarch64-dis.c (last_stop_offset): New.
2031         (print_insn_aarch64): Use stop_offset.
2032
2033 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2034
2035         PR gas/24359
2036         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2037         CPU_ANY_AVX2_FLAGS.
2038         * i386-init.h: Regenerated.
2039
2040 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2041
2042         PR gas/24348
2043         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2044         vmovdqu16, vmovdqu32 and vmovdqu64.
2045         * i386-tbl.h: Regenerated.
2046
2047 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2048
2049         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2050         from vstrszb, vstrszh, and vstrszf.
2051
2052 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2053
2054         * s390-opc.txt: Add instruction descriptions.
2055
2056 2019-02-08  Jim Wilson  <jimw@sifive.com>
2057
2058         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2059         <bne>: Likewise.
2060
2061 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2062
2063         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2064
2065 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2066
2067         PR binutils/23212
2068         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2069         * aarch64-opc.c (verify_elem_sd): New.
2070         (fields): Add FLD_sz entr.
2071         * aarch64-tbl.h (_SIMD_INSN): New.
2072         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2073         fmulx scalar and vector by element isns.
2074
2075 2019-02-07  Nick Clifton  <nickc@redhat.com>
2076
2077         * po/sv.po: Updated Swedish translation.
2078
2079 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2080
2081         * s390-mkopc.c (main): Accept arch13 as cpu string.
2082         * s390-opc.c: Add new instruction formats and instruction opcode
2083         masks.
2084         * s390-opc.txt: Add new arch13 instructions.
2085
2086 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2087
2088         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2089         (aarch64_opcode): Change encoding for stg, stzg
2090         st2g and st2zg.
2091         * aarch64-asm-2.c: Regenerated.
2092         * aarch64-dis-2.c: Regenerated.
2093         * aarch64-opc-2.c: Regenerated.
2094
2095 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2096
2097         * aarch64-asm-2.c: Regenerated.
2098         * aarch64-dis-2.c: Likewise.
2099         * aarch64-opc-2.c: Likewise.
2100         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2101
2102 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2103             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2104
2105         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2106         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2107         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2108         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2109         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2110         case for ldstgv_indexed.
2111         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2112         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2113         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2114         * aarch64-asm-2.c: Regenerated.
2115         * aarch64-dis-2.c: Regenerated.
2116         * aarch64-opc-2.c: Regenerated.
2117
2118 2019-01-23  Nick Clifton  <nickc@redhat.com>
2119
2120         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2121
2122 2019-01-21  Nick Clifton  <nickc@redhat.com>
2123
2124         * po/de.po: Updated German translation.
2125         * po/uk.po: Updated Ukranian translation.
2126
2127 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2128         * mips-dis.c (mips_arch_choices): Fix typo in
2129         gs464, gs464e and gs264e descriptors.
2130
2131 2019-01-19  Nick Clifton  <nickc@redhat.com>
2132
2133         * configure: Regenerate.
2134         * po/opcodes.pot: Regenerate.
2135
2136 2018-06-24  Nick Clifton  <nickc@redhat.com>
2137
2138         2.32 branch created.
2139
2140 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2141
2142         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2143         if it is null.
2144         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2145         zero.
2146
2147 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2148
2149         * configure: Regenerate.
2150
2151 2019-01-07  Alan Modra  <amodra@gmail.com>
2152
2153         * configure: Regenerate.
2154         * po/POTFILES.in: Regenerate.
2155
2156 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2157
2158         * s12z-opc.c: New file.
2159         * s12z-opc.h: New file.
2160         * s12z-dis.c: Removed all code not directly related to display
2161         of instructions.  Used the interface provided by the new files
2162         instead.
2163         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2164         * Makefile.in: Regenerate.
2165         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2166         * configure: Regenerate.
2167
2168 2019-01-01  Alan Modra  <amodra@gmail.com>
2169
2170         Update year range in copyright notice of all files.
2171
2172 For older changes see ChangeLog-2018
2173 \f
2174 Copyright (C) 2019 Free Software Foundation, Inc.
2175
2176 Copying and distribution of this file, with or without modification,
2177 are permitted in any medium without royalty provided the copyright
2178 notice and this notice are preserved.
2179
2180 Local Variables:
2181 mode: change-log
2182 left-margin: 8
2183 fill-column: 74
2184 version-control: never
2185 End: