opcodes/ChangeLog

   1 2016-12-20  Andrew Waterman  <andrew@sifive.com>
   2
   3         * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
   4         INSN_ALIAS.
   5
   6 2016-12-20  Andrew Waterman  <andrew@sifive.com>
   7
   8         * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
   9         format.
  10
  11 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  12
  13         * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
  14         XLEN when none is provided.
  15
  16 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  17
  18         * riscv-opc.c: Formatting fixes.
  19
  20 2016-12-20  Alan Modra  <amodra@gmail.com>
  21
  22         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
  23         * Makefile.in: Regenerate.
  24         * po/POTFILES.in: Regenerate.
  25
  26 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
  27
  28         * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
  29         Only examine ELF file structures here.
  30
  31 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
  32
  33         * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
  34         `bfd_mips_elf_get_abiflags' here.
  35
  36 2016-12-16  Nick Clifton  <nickc@redhat.com>
  37
  38         * arm-dis.c (print_insn_thumb32): Fix compile time warning
  39         computing value_in_comment.
  40
  41 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  42
  43         * mips-dis.c (mips_convert_abiflags_ases): New function.
  44         (set_default_mips_dis_options): Also infer ASE flags from ELF
  45         file structures.
  46
  47 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  48
  49         * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
  50         header flag interpretation code.
  51
  52 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  53
  54         * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
  55         `pinfo2' with SP-relative "sd" entries.
  56
  57 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  58
  59         * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
  60         compact jumps.
  61
  62 2016-12-13 Renlin Li <renlin.li@arm.com>
  63
  64         * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
  65         qualifier.
  66         (operand_general_constraint_met_p): Remove case for CP_REG.
  67         (aarch64_print_operand): Print CRn, CRm operand using imm field.
  68         * aarch64-tbl.h (QL_SYS): Use CR qualifier.
  69         (QL_SYSL): Likewise.
  70         (aarch64_opcode_table): Change CRn, CRm operand class and type.
  71         * aarch64-opc-2.c : Regenerate.
  72         * aarch64-asm-2.c : Likewise.
  73         * aarch64-dis-2.c : Likewise.
  74
  75 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  76
  77         * rx-dis.c: Include <setjmp.h>
  78         (struct private): New.
  79         (rx_get_byte): Check return value of read_memory_func, and
  80         call memory_error_func and OPCODES_SIGLONGJMP on error.
  81         (print_insn_rx): Call OPCODES_SIGSETJMP.
  82
  83 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  84
  85         * rl78-dis.c: Include <setjmp.h>.
  86         (struct private): New.
  87         (rl78_get_byte): Check return value of read_memory_func, and
  88         call memory_error_func and OPCODES_SIGLONGJMP on error.
  89         (print_insn_rl78_common): Call OPCODES_SIGJMP.
  90
  91 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  92
  93         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
  94
  95 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  96
  97         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
  98         than UINT.
  99
 100 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 101
 102         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
 103         to separate `extend' and its uninterpreted argument output.
 104         Separate hexadecimal halves of undecoded extended instructions
 105         output.
 106
 107 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 108
 109         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
 110         indentation space across.
 111
 112 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 113
 114         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
 115         adjustment for PC-relative operations following MIPS16e compact
 116         jumps or undefined RR/J(AL)R(C) encodings.
 117
 118 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 119
 120         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
 121         variable to `reglane_index'.
 122
 123 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
 124
 125         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
 126
 127 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 128
 129         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
 130
 131 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 132
 133         * mips16-opc.c (mips16_opcodes): Update comment naming structure
 134         members.
 135
 136 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 137
 138         * mips-dis.c (print_mips_disassembler_options): Reformat output.
 139
 140 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 141
 142         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
 143         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
 144
 145 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 146
 147         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
 148
 149 2016-12-01  Nick Clifton  <nickc@redhat.com>
 150
 151         PR binutils/20893
 152         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
 153         opcode designator.
 154
 155 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 156
 157         * arc-opc.c (insert_ra_chk): New function.
 158         (insert_rb_chk): Likewise.
 159         (insert_rad): Update text error message.
 160         (insert_rcd): Likewise.
 161         (insert_rhv2): Likewise.
 162         (insert_r0): Likewise.
 163         (insert_r1): Likewise.
 164         (insert_r2): Likewise.
 165         (insert_r3): Likewise.
 166         (insert_sp): Likewise.
 167         (insert_gp): Likewise.
 168         (insert_pcl): Likewise.
 169         (insert_blink): Likewise.
 170         (insert_ilink1): Likewise.
 171         (insert_ilink2): Likewise.
 172         (insert_ras): Likewise.
 173         (insert_rbs): Likewise.
 174         (insert_rcs): Likewise.
 175         (insert_simm3s): Likewise.
 176         (insert_rrange): Likewise.
 177         (insert_fpel): Likewise.
 178         (insert_blinkel): Likewise.
 179         (insert_pcel): Likewise.
 180         (insert_nps_3bit_dst): Likewise.
 181         (insert_nps_3bit_dst_short): Likewise.
 182         (insert_nps_3bit_src2_short): Likewise.
 183         (insert_nps_bitop_size_2b): Likewise.
 184         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 185         (RA_CHK): Define.
 186         (RB): Adjust.
 187         (RB_CHK): Define.
 188         (RC): Adjust.
 189         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 190         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 191         Change first insn argument to check for LP_COUNT usage.
 192         (rem): Likewise.
 193         (ld, ldd): All instructions are LOAD class.  Change first insn
 194         argument to check for LP_COUNT usage.
 195         (st, std): All instructions are STORE class.
 196         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 197         Change first insn argument to check for LP_COUNT usage.
 198         (mov): All instructions are MOVE class.  Change first insn
 199         argument to check for LP_COUNT usage.
 200
 201 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 202
 203         * arc-dis.c (is_compatible_p): Remove function.
 204         (skip_this_opcode): Don't add any decoding class to decode list.
 205         Remove warning.
 206         (find_format_from_table): Go through all opcodes, and warn if we
 207         use a guessed mnemonic.
 208
 209 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 210             Amit Pawar  <amit.pawar@amd.com>
 211
 212         PR binutils/20637
 213         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 214         instructions.
 215
 216 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 217
 218         * configure: Regenerate.
 219
 220 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 221
 222         * sparc-opc.c (HWS_V8): Definition moved from
 223         gas/config/tc-sparc.c.
 224         (HWS_V9): Likewise.
 225         (HWS_VA): Likewise.
 226         (HWS_VB): Likewise.
 227         (HWS_VC): Likewise.
 228         (HWS_VD): Likewise.
 229         (HWS_VE): Likewise.
 230         (HWS_VV): Likewise.
 231         (HWS_VM): Likewise.
 232         (HWS2_VM): Likewise.
 233         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 234         existing entries.
 235
 236 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 237
 238         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 239         instructions.
 240
 241 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 242
 243         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 244         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 245         (aarch64_opcode_table): Add fcmla and fcadd.
 246         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 247         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 248         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 249         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 250         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 251         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 252         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 253         (operand_general_constraint_met_p): Rotate and index range check.
 254         (aarch64_print_operand): Handle rotate operand.
 255         * aarch64-asm-2.c: Regenerate.
 256         * aarch64-dis-2.c: Likewise.
 257         * aarch64-opc-2.c: Likewise.
 258
 259 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 260
 261         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 262         * aarch64-asm-2.c: Regenerate.
 263         * aarch64-dis-2.c: Regenerate.
 264         * aarch64-opc-2.c: Regenerate.
 265
 266 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 267
 268         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 269         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 270         * aarch64-asm-2.c: Regenerate.
 271         * aarch64-dis-2.c: Regenerate.
 272         * aarch64-opc-2.c: Regenerate.
 273
 274 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 275
 276         * aarch64-tbl.h (QL_X1NIL): New.
 277         (arch64_opcode_table): Add ldraa, ldrab.
 278         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 279         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 280         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 281         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 282         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 283         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 284         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 285         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 286         (aarch64_print_operand): Likewise.
 287         * aarch64-asm-2.c: Regenerate.
 288         * aarch64-dis-2.c: Regenerate.
 289         * aarch64-opc-2.c: Regenerate.
 290
 291 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 292
 293         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 294         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 295         * aarch64-asm-2.c: Regenerate.
 296         * aarch64-dis-2.c: Regenerate.
 297         * aarch64-opc-2.c: Regenerate.
 298
 299 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 300
 301         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 302         (AARCH64_OPERANDS): Add Rm_SP.
 303         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 304         * aarch64-asm-2.c: Regenerate.
 305         * aarch64-dis-2.c: Regenerate.
 306         * aarch64-opc-2.c: Regenerate.
 307
 308 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 309
 310         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 311         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 312         autdzb, xpaci, xpacd.
 313         * aarch64-asm-2.c: Regenerate.
 314         * aarch64-dis-2.c: Regenerate.
 315         * aarch64-opc-2.c: Regenerate.
 316
 317 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 318
 319         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 320         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 321         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 322         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 323
 324 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 325
 326         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 327         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 328         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 329         autibsp.
 330         * aarch64-asm-2.c: Regenerate.
 331         * aarch64-dis-2.c: Regenerate.
 332
 333 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 334
 335         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 336
 337 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 338
 339         PR binutils/20799
 340         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 341         * i386-dis.c (EdqwS): Removed.
 342         (dqw_swap_mode): Likewise.
 343         (intel_operand_size): Don't check dqw_swap_mode.
 344         (OP_E_register): Likewise.
 345         (OP_E_memory): Likewise.
 346         (OP_G): Likewise.
 347         (OP_EX): Likewise.
 348         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 349         * i386-tbl.h: Regerated.
 350
 351 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 352
 353         * i386-opc.tbl: Merge AVX512F vmovq.
 354         * i386-tbl.h: Regerated.
 355
 356 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 357
 358         PR binutils/20701
 359         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 360         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 361         (three_byte_table): Remove THREE_BYTE_0F7A.
 362
 363 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 364
 365         PR binutils/20775
 366         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 367         (FGRPd9_4): Replace 1 with 2.
 368         (FGRPd9_5): Replace 2 with 3.
 369         (FGRPd9_6): Replace 3 with 4.
 370         (FGRPd9_7): Replace 4 with 5.
 371         (FGRPda_5): Replace 5 with 6.
 372         (FGRPdb_4): Replace 6 with 7.
 373         (FGRPde_3): Replace 7 with 8.
 374         (FGRPdf_4): Replace 8 with 9.
 375         (fgrps): Add an entry for Bad_Opcode.
 376
 377 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 378
 379         * arc-opc.c (arc_flag_operands): Add F_DI14.
 380         (arc_flag_classes): Add C_DI14.
 381         * arc-nps400-tbl.h: Add new exc instructions.
 382
 383 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 384
 385         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 386         major opcode 0xa.
 387         * arc-nps-400-tbl.h: Add dcmac instruction.
 388         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 389         (insert_nps_rbdouble_64): Added.
 390         (extract_nps_rbdouble_64): Added.
 391         (insert_nps_proto_size): Added.
 392         (extract_nps_proto_size): Added.
 393
 394 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 395
 396         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 397         relating to long instruction processing, add new limm field.
 398         (OPCODE): Rename to...
 399         (OPCODE_32BIT_INSN): ...this.
 400         (OPCODE_AC): Delete.
 401         (skip_this_opcode): Handle different instruction lengths, update
 402         macro name.
 403         (special_flag_p): Update parameter type.
 404         (find_format_from_table): Update for more instruction lengths.
 405         (find_format_long_instructions): Delete.
 406         (find_format): Update for more instruction lengths.
 407         (arc_insn_length): Likewise.
 408         (extract_operand_value): Update for more instruction lengths.
 409         (operand_iterator_next): Remove code relating to long
 410         instructions.
 411         (arc_opcode_to_insn_type): New function.
 412         (print_insn_arc):Update for more instructions lengths.
 413         * arc-ext.c (extInstruction_t): Change argument type.
 414         * arc-ext.h (extInstruction_t): Change argument type.
 415         * arc-fxi.h: Change type unsigned to unsigned long long
 416         extensively throughout.
 417         * arc-nps400-tbl.h: Add long instructions taken from
 418         arc_long_opcodes table in arc-opc.c.
 419         * arc-opc.c: Update parameter types on insert/extract handlers.
 420         (arc_long_opcodes): Delete.
 421         (arc_num_long_opcodes): Delete.
 422         (arc_opcode_len): Update for more instruction lengths.
 423
 424 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 425
 426         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 427
 428 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 429
 430         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 431         with arc_opcode_len.
 432         (find_format_long_instructions): Likewise.
 433         * arc-opc.c (arc_opcode_len): New function.
 434
 435 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 436
 437         * arc-nps400-tbl.h: Fix some instruction masks.
 438
 439 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 440
 441         * i386-dis.c (REG_82): Removed.
 442         (X86_64_82_REG_0): Likewise.
 443         (X86_64_82_REG_1): Likewise.
 444         (X86_64_82_REG_2): Likewise.
 445         (X86_64_82_REG_3): Likewise.
 446         (X86_64_82_REG_4): Likewise.
 447         (X86_64_82_REG_5): Likewise.
 448         (X86_64_82_REG_6): Likewise.
 449         (X86_64_82_REG_7): Likewise.
 450         (X86_64_82): New.
 451         (dis386): Use X86_64_82 instead of REG_82.
 452         (reg_table): Remove REG_82.
 453         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 454         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 455         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 456         X86_64_82_REG_7.
 457
 458 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 459
 460         PR binutils/20754
 461         * i386-dis.c (REG_82): New.
 462         (X86_64_82_REG_0): Likewise.
 463         (X86_64_82_REG_1): Likewise.
 464         (X86_64_82_REG_2): Likewise.
 465         (X86_64_82_REG_3): Likewise.
 466         (X86_64_82_REG_4): Likewise.
 467         (X86_64_82_REG_5): Likewise.
 468         (X86_64_82_REG_6): Likewise.
 469         (X86_64_82_REG_7): Likewise.
 470         (dis386): Use REG_82.
 471         (reg_table): Add REG_82.
 472         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 473         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 474         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 475
 476 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 477
 478         * i386-dis.c (REG_82): Renamed to ...
 479         (REG_83): This.
 480         (dis386): Updated.
 481         (reg_table): Likewise.
 482
 483 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 484
 485         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 486         * i386-dis-evex.h (evex_table): Updated.
 487         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 488         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 489         (cpu_flags): Add CpuAVX512_4VNNIW.
 490         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 491         (i386_cpu_flags): Add cpuavx512_4vnniw.
 492         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 493         * i386-init.h: Regenerate.
 494         * i386-tbl.h: Ditto.
 495
 496 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 497
 498         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 499         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 500         * i386-dis-evex.h (evex_table): Updated.
 501         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 502         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 503         (cpu_flags): Add CpuAVX512_4FMAPS.
 504         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 505         * i386-opc.h (AVX512_4FMAP): New.
 506         (i386_cpu_flags): Add cpuavx512_4fmaps.
 507         (ImplicitQuadGroup): New.
 508         (i386_opcode_modifier): Add implicitquadgroup.
 509         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 510         * i386-init.h: Regenerate.
 511         * i386-tbl.h: Ditto.
 512
 513 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 514             Andrew Waterman <andrew@sifive.com>
 515
 516         Add support for RISC-V architecture.
 517         * configure.ac: Add entry for bfd_riscv_arch.
 518         * configure: Regenerate.
 519         * disassemble.c (disassembler): Add support for riscv.
 520         (disassembler_usage): Likewise.
 521         * riscv-dis.c: New file.
 522         * riscv-opc.c: New file.
 523
 524 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 525
 526         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 527         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 528         (rm_table): Update the RM_0FAE_REG_7 entry.
 529         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 530         (cpu_flags): Remove CpuPCOMMIT.
 531         * i386-opc.h (CpuPCOMMIT): Removed.
 532         (i386_cpu_flags): Remove cpupcommit.
 533         * i386-opc.tbl: Remove pcommit.
 534         * i386-init.h: Regenerated.
 535         * i386-tbl.h: Likewise.
 536
 537 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 538
 539         PR binutis/20705
 540         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 541         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 542         32-bit mode.  Don't check vex.register_specifier in 32-bit
 543         mode.
 544         (OP_VEX): Check for invalid mask registers.
 545
 546 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 547
 548         PR binutis/20699
 549         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 550         sizeflag.
 551
 552 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 553
 554         PR binutis/20704
 555         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 556
 557 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 558
 559         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 560         local variable to `index_regno'.
 561
 562 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 563
 564         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 565
 566 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 567
 568         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 569         usage on ISA basis.
 570
 571 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 572
 573         PR target/20666
 574         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 575
 576 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 577
 578         PR target/20667
 579         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 580         available.
 581
 582 2016-10-07  Alan Modra  <amodra@gmail.com>
 583
 584         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 585
 586 2016-10-06  Alan Modra  <amodra@gmail.com>
 587
 588         * aarch64-opc.c: Spell fall through comments consistently.
 589         * i386-dis.c: Likewise.
 590         * aarch64-dis.c: Add missing fall through comments.
 591         * aarch64-opc.c: Likewise.
 592         * arc-dis.c: Likewise.
 593         * arm-dis.c: Likewise.
 594         * i386-dis.c: Likewise.
 595         * m68k-dis.c: Likewise.
 596         * mep-asm.c: Likewise.
 597         * ns32k-dis.c: Likewise.
 598         * sh-dis.c: Likewise.
 599         * tic4x-dis.c: Likewise.
 600         * tic6x-dis.c: Likewise.
 601         * vax-dis.c: Likewise.
 602
 603 2016-10-06  Alan Modra  <amodra@gmail.com>
 604
 605         * arc-ext.c (create_map): Add missing break.
 606         * msp430-decode.opc (encode_as): Likewise.
 607         * msp430-decode.c: Regenerate.
 608
 609 2016-10-06  Alan Modra  <amodra@gmail.com>
 610
 611         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 612         * crx-dis.c (print_insn_crx): Likewise.
 613
 614 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 615
 616         PR binutils/20657
 617         * i386-dis.c (putop): Don't assign alt twice.
 618
 619 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 620
 621         PR target/20553
 622         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 623
 624 2016-09-29  Alan Modra  <amodra@gmail.com>
 625
 626         * ppc-opc.c (L): Make compulsory.
 627         (LOPT): New, optional form of L.
 628         (HTM_R): Define as LOPT.
 629         (L0, L1): Delete.
 630         (L32OPT): New, optional for 32-bit L.
 631         (L2OPT): New, 2-bit L for dcbf.
 632         (SVC_LEC): Update.
 633         (L2): Define.
 634         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 635         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 636         <dcbf>: Use L2OPT.
 637         <tlbiel, tlbie>: Use LOPT.
 638         <wclr, wclrall>: Use L2.
 639
 640 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 641
 642         * Makefile.in: Regenerate.
 643         * configure: Likewise.
 644
 645 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 646
 647         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 648         (EXTINSN2OP): Use EXTINSN2OPF.
 649         (bspeekm, bspop, modapp): New extension instructions.
 650         * arc-opc.c (F_DNZ_ND): Define.
 651         (F_DNZ_D): Likewise.
 652         (F_SIZEB1): Changed.
 653         (C_DNZ_D): Define.
 654         (C_HARD): Changed.
 655         * arc-tbl.h (dbnz): New instruction.
 656         (prealloc): Allow it for ARC EM.
 657         (xbfu): Likewise.
 658
 659 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 660
 661         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 662         after commas in addresses.
 663         (aarch64_print_operand): Likewise.
 664
 665 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 666
 667         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 668         rather than "should be" or "expected to be" in error messages.
 669
 670 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 671
 672         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 673         (print_mnemonic_name): ...here.
 674         (print_comment): New function.
 675         (print_aarch64_insn): Call it.
 676         * aarch64-opc.c (aarch64_conds): Add SVE names.
 677         (aarch64_print_operand): Print alternative condition names in
 678         a comment.
 679
 680 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 681
 682         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 683         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 684         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 685         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 686         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 687         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 688         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 689         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 690         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 691         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 692         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 693         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 694         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 695         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 696         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 697         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 698         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 699         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 700         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 701         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 702         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 703         (aarch64_feature_sve): New variable.
 704         (SVE): New macro.
 705         (_SVE_INSN): Likewise.
 706         (aarch64_opcode_table): Add SVE instructions.
 707         * aarch64-opc.h (extract_fields): Declare.
 708         * aarch64-opc-2.c: Regenerate.
 709         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 710         * aarch64-asm-2.c: Regenerate.
 711         * aarch64-dis.c (extract_fields): Make global.
 712         (do_misc_decoding): Handle the new SVE aarch64_ops.
 713         * aarch64-dis-2.c: Regenerate.
 714
 715 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 716
 717         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 718         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 719         aarch64_field_kinds.
 720         * aarch64-opc.c (fields): Add corresponding entries.
 721         * aarch64-asm.c (aarch64_get_variant): New function.
 722         (aarch64_encode_variant_using_iclass): Likewise.
 723         (aarch64_opcode_encode): Call it.
 724         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 725         (aarch64_opcode_decode): Call it.
 726
 727 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 728
 729         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 730         and FP register operands.
 731         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 732         (FLD_SVE_Vn): New aarch64_field_kinds.
 733         * aarch64-opc.c (fields): Add corresponding entries.
 734         (aarch64_print_operand): Handle the new SVE core and FP register
 735         operands.
 736         * aarch64-opc-2.c: Regenerate.
 737         * aarch64-asm-2.c: Likewise.
 738         * aarch64-dis-2.c: Likewise.
 739
 740 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 741
 742         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 743         immediate operands.
 744         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 745         * aarch64-opc.c (fields): Add corresponding entry.
 746         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 747         operands.
 748         (aarch64_print_operand): Likewise.
 749         * aarch64-opc-2.c: Regenerate.
 750         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 751         (ins_sve_float_zero_one): New inserters.
 752         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 753         (aarch64_ins_sve_float_half_two): Likewise.
 754         (aarch64_ins_sve_float_zero_one): Likewise.
 755         * aarch64-asm-2.c: Regenerate.
 756         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 757         (ext_sve_float_zero_one): New extractors.
 758         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 759         (aarch64_ext_sve_float_half_two): Likewise.
 760         (aarch64_ext_sve_float_zero_one): Likewise.
 761         * aarch64-dis-2.c: Regenerate.
 762
 763 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 764
 765         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 766         integer immediate operands.
 767         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 768         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 769         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 770         * aarch64-opc.c (fields): Add corresponding entries.
 771         (operand_general_constraint_met_p): Handle the new SVE integer
 772         immediate operands.
 773         (aarch64_print_operand): Likewise.
 774         (aarch64_sve_dupm_mov_immediate_p): New function.
 775         * aarch64-opc-2.c: Regenerate.
 776         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 777         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 778         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 779         (aarch64_ins_limm): ...here.
 780         (aarch64_ins_inv_limm): New function.
 781         (aarch64_ins_sve_aimm): Likewise.
 782         (aarch64_ins_sve_asimm): Likewise.
 783         (aarch64_ins_sve_limm_mov): Likewise.
 784         (aarch64_ins_sve_shlimm): Likewise.
 785         (aarch64_ins_sve_shrimm): Likewise.
 786         * aarch64-asm-2.c: Regenerate.
 787         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 788         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 789         * aarch64-dis.c (decode_limm): New function, split out from...
 790         (aarch64_ext_limm): ...here.
 791         (aarch64_ext_inv_limm): New function.
 792         (decode_sve_aimm): Likewise.
 793         (aarch64_ext_sve_aimm): Likewise.
 794         (aarch64_ext_sve_asimm): Likewise.
 795         (aarch64_ext_sve_limm_mov): Likewise.
 796         (aarch64_top_bit): Likewise.
 797         (aarch64_ext_sve_shlimm): Likewise.
 798         (aarch64_ext_sve_shrimm): Likewise.
 799         * aarch64-dis-2.c: Regenerate.
 800
 801 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 802
 803         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 804         operands.
 805         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 806         the AARCH64_MOD_MUL_VL entry.
 807         (value_aligned_p): Cope with non-power-of-two alignments.
 808         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 809         (print_immediate_offset_address): Likewise.
 810         (aarch64_print_operand): Likewise.
 811         * aarch64-opc-2.c: Regenerate.
 812         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 813         (ins_sve_addr_ri_s9xvl): New inserters.
 814         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 815         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 816         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 817         * aarch64-asm-2.c: Regenerate.
 818         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 819         (ext_sve_addr_ri_s9xvl): New extractors.
 820         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 821         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 822         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 823         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 824         * aarch64-dis-2.c: Regenerate.
 825
 826 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 827
 828         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 829         address operands.
 830         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 831         (FLD_SVE_xs_22): New aarch64_field_kinds.
 832         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 833         (get_operand_specific_data): New function.
 834         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 835         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 836         (operand_general_constraint_met_p): Handle the new SVE address
 837         operands.
 838         (sve_reg): New array.
 839         (get_addr_sve_reg_name): New function.
 840         (aarch64_print_operand): Handle the new SVE address operands.
 841         * aarch64-opc-2.c: Regenerate.
 842         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 843         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 844         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 845         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 846         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 847         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 848         (aarch64_ins_sve_addr_zi_u5): Likewise.
 849         (aarch64_ins_sve_addr_zz): Likewise.
 850         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 851         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 852         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 853         * aarch64-asm-2.c: Regenerate.
 854         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 855         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 856         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 857         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 858         (aarch64_ext_sve_addr_ri_u6): Likewise.
 859         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 860         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 861         (aarch64_ext_sve_addr_zi_u5): Likewise.
 862         (aarch64_ext_sve_addr_zz): Likewise.
 863         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 864         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 865         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 866         * aarch64-dis-2.c: Regenerate.
 867
 868 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 869
 870         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 871         AARCH64_OPND_SVE_PATTERN_SCALED.
 872         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 873         * aarch64-opc.c (fields): Add a corresponding entry.
 874         (set_multiplier_out_of_range_error): New function.
 875         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 876         (operand_general_constraint_met_p): Handle
 877         AARCH64_OPND_SVE_PATTERN_SCALED.
 878         (print_register_offset_address): Use PRIi64 to print the
 879         shift amount.
 880         (aarch64_print_operand): Likewise.  Handle
 881         AARCH64_OPND_SVE_PATTERN_SCALED.
 882         * aarch64-opc-2.c: Regenerate.
 883         * aarch64-asm.h (ins_sve_scale): New inserter.
 884         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 885         * aarch64-asm-2.c: Regenerate.
 886         * aarch64-dis.h (ext_sve_scale): New inserter.
 887         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 888         * aarch64-dis-2.c: Regenerate.
 889
 890 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 891
 892         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 893         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 894         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 895         (FLD_SVE_prfop): Likewise.
 896         * aarch64-opc.c: Include libiberty.h.
 897         (aarch64_sve_pattern_array): New variable.
 898         (aarch64_sve_prfop_array): Likewise.
 899         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 900         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 901         AARCH64_OPND_SVE_PRFOP.
 902         * aarch64-asm-2.c: Regenerate.
 903         * aarch64-dis-2.c: Likewise.
 904         * aarch64-opc-2.c: Likewise.
 905
 906 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 907
 908         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 909         AARCH64_OPND_QLF_P_[ZM].
 910         (aarch64_print_operand): Print /z and /m where appropriate.
 911
 912 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 913
 914         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 915         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 916         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 917         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 918         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 919         * aarch64-opc.c (fields): Add corresponding entries here.
 920         (operand_general_constraint_met_p): Check that SVE register lists
 921         have the correct length.  Check the ranges of SVE index registers.
 922         Check for cases where p8-p15 are used in 3-bit predicate fields.
 923         (aarch64_print_operand): Handle the new SVE operands.
 924         * aarch64-opc-2.c: Regenerate.
 925         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 926         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 927         (aarch64_ins_sve_reglist): Likewise.
 928         * aarch64-asm-2.c: Regenerate.
 929         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 930         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 931         (aarch64_ext_sve_reglist): Likewise.
 932         * aarch64-dis-2.c: Regenerate.
 933
 934 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 935
 936         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 937         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 938         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 939         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 940         tied operands.
 941
 942 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 943
 944         * aarch64-opc.c (get_offset_int_reg_name): New function.
 945         (print_immediate_offset_address): Likewise.
 946         (print_register_offset_address): Take the base and offset
 947         registers as parameters.
 948         (aarch64_print_operand): Update caller accordingly.  Use
 949         print_immediate_offset_address.
 950
 951 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 952
 953         * aarch64-opc.c (BANK): New macro.
 954         (R32, R64): Take a register number as argument
 955         (int_reg): Use BANK.
 956
 957 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 958
 959         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 960         (aarch64_print_operand): Update accordingly.
 961
 962 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 963
 964         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 965         for FPIMM.
 966         * aarch64-asm.h (ins_fpimm): New inserter.
 967         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 968         * aarch64-asm-2.c: Regenerate.
 969         * aarch64-dis.h (ext_fpimm): New extractor.
 970         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 971         (aarch64_ext_fpimm): New function.
 972         * aarch64-dis-2.c: Regenerate.
 973
 974 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 975
 976         * aarch64-asm.c: Include libiberty.h.
 977         (insert_fields): New function.
 978         (aarch64_ins_imm): Use it.
 979         * aarch64-dis.c (extract_fields): New function.
 980         (aarch64_ext_imm): Use it.
 981
 982 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 983
 984         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 985         with an esize parameter.
 986         (operand_general_constraint_met_p): Update accordingly.
 987         Fix misindented code.
 988         * aarch64-asm.c (aarch64_ins_limm): Update call to
 989         aarch64_logical_immediate_p.
 990
 991 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 992
 993         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 994
 995 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 996
 997         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 998
 999 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
1000
1001         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1002
1003 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
1004
1005         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1006         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1007         xor3>: Delete mnemonics.
1008         <cp_abort>: Rename mnemonic from ...
1009         <cpabort>: ...to this.
1010         <setb>: Change to a X form instruction.
1011         <sync>: Change to 1 operand form.
1012         <copy>: Delete mnemonic.
1013         <copy_first>: Rename mnemonic from ...
1014         <copy>: ...to this.
1015         <paste, paste.>: Delete mnemonics.
1016         <paste_last>: Rename mnemonic from ...
1017         <paste.>: ...to this.
1018
1019 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1020
1021         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1022
1023 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1024
1025         * s390-mkopc.c (main): Support alternate arch strings.
1026
1027 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
1028
1029         * s390-opc.txt: Fix kmctr instruction type.
1030
1031 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
1032
1033         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1034         * i386-init.h: Regenerated.
1035
1036 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
1037
1038         * opcodes/arc-dis.c (print_insn_arc): Changed.
1039
1040 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
1041
1042         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1043         camellia_fl.
1044
1045 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1046
1047         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
1048         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1049         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1050
1051 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
1052
1053         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1054         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1055         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1056         PREFIX_MOD_3_0FAE_REG_4.
1057         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1058         PREFIX_MOD_3_0FAE_REG_4.
1059         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1060         (cpu_flags): Add CpuPTWRITE.
1061         * i386-opc.h (CpuPTWRITE): New.
1062         (i386_cpu_flags): Add cpuptwrite.
1063         * i386-opc.tbl: Add ptwrite instruction.
1064         * i386-init.h: Regenerated.
1065         * i386-tbl.h: Likewise.
1066
1067 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1068
1069         * arc-dis.h: Wrap around in extern "C".
1070
1071 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1072
1073         * aarch64-tbl.h (V8_2_INSN): New macro.
1074         (aarch64_opcode_table): Use it.
1075
1076 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1077
1078         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1079         CORE_INSN, __FP_INSN and SIMD_INSN.
1080
1081 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1082
1083         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1084         (aarch64_opcode_table): Update uses accordingly.
1085
1086 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1087         Kwok Cheung Yeung  <kcy@codesourcery.com>
1088
1089         opcodes/
1090         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1091         'e_cmplwi' to 'e_cmpli' instead.
1092         (OPVUPRT, OPVUPRT_MASK): Define.
1093         (powerpc_opcodes): Add E200Z4 insns.
1094         (vle_opcodes): Add context save/restore insns.
1095
1096 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1097
1098         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1099         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1100         "j".
1101
1102 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1103
1104         * arc-nps400-tbl.h: Change block comments to GNU format.
1105         * arc-dis.c: Add new globals addrtypenames,
1106         addrtypenames_max, and addtypeunknown.
1107         (get_addrtype): New function.
1108         (print_insn_arc): Print colons and address types when
1109         required.
1110         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1111         define insert and extract functions for all address types.
1112         (arc_operands): Add operands for colon and all address
1113         types.
1114         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1115         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1116         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1117         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1118         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1119         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1120
1121 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1122
1123         * configure: Regenerated.
1124
1125 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1126
1127         * arc-dis.c (skipclass): New structure.
1128         (decodelist): New variable.
1129         (is_compatible_p): New function.
1130         (new_element): Likewise.
1131         (skip_class_p): Likewise.
1132         (find_format_from_table): Use skip_class_p function.
1133         (find_format): Decode first the extension instructions.
1134         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1135         e_flags.
1136         (parse_option): New function.
1137         (parse_disassembler_options): Likewise.
1138         (print_arc_disassembler_options): Likewise.
1139         (print_insn_arc): Use parse_disassembler_options function.  Proper
1140         select ARCv2 cpu variant.
1141         * disassemble.c (disassembler_usage): Add ARC disassembler
1142         options.
1143
1144 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1145
1146         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1147         annotation from the "nal" entry and reorder it beyond "bltzal".
1148
1149 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1150
1151         * sparc-opc.c (ldtxa): New macro.
1152         (sparc_opcodes): Use the macro defined above to add entries for
1153         the LDTXA instructions.
1154         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1155         instruction.
1156
1157 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1158
1159         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1160         and "jmpc".
1161
1162 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1163
1164         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1165         (movzb): Adjust to cover all permitted suffixes.
1166         (movzw): New.
1167         * i386-tbl.h: Re-generate.
1168
1169 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1170
1171         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1172         (lgdt): Remove Tbyte from non-64-bit variant.
1173         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1174         xsaves64, xsavec64): Remove Disp16.
1175         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1176         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1177         64-bit variants.
1178         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1179         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1180         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1181         64-bit variants.
1182         * i386-tbl.h: Re-generate.
1183
1184 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1185
1186         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1187         * i386-tbl.h: Re-generate.
1188
1189 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1190
1191         * arm-dis.c (print_insn): Fix typo in comment.
1192
1193 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1194
1195         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1196         range of ldst_elemlist operands.
1197         (print_register_list): Use PRIi64 to print the index.
1198         (aarch64_print_operand): Likewise.
1199
1200 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1201
1202         * mcore-opc.h: Remove sentinal.
1203         * mcore-dis.c (print_insn_mcore): Adjust.
1204
1205 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1206
1207         * arc-opc.c: Correct description of availability of NPS400
1208         features.
1209
1210 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1211
1212         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1213         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1214         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1215         xor3>: New mnemonics.
1216         <setb>: Change to a VX form instruction.
1217         (insert_sh6): Add support for rldixor.
1218         (extract_sh6): Likewise.
1219
1220 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1221
1222         * arc-ext.h: Wrap in extern C.
1223
1224 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1225
1226         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1227         Use same method for determining instruction length on ARC700 and
1228         NPS-400.
1229         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1230         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1231         with the NPS400 subclass.
1232         * arc-opc.c: Likewise.
1233
1234 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1235
1236         * sparc-opc.c (rdasr): New macro.
1237         (wrasr): Likewise.
1238         (rdpr): Likewise.
1239         (wrpr): Likewise.
1240         (rdhpr): Likewise.
1241         (wrhpr): Likewise.
1242         (sparc_opcodes): Use the macros above to fix and expand the
1243         definition of read/write instructions from/to
1244         asr/privileged/hyperprivileged instructions.
1245         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1246         %hva_mask_nz.  Prefer softint_set and softint_clear over
1247         set_softint and clear_softint.
1248         (print_insn_sparc): Support %ver in Rd.
1249
1250 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1251
1252         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1253         architecture according to the hardware capabilities they require.
1254
1255 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1256
1257         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1258         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1259         bfd_mach_sparc_v9{c,d,e,v,m}.
1260         * sparc-opc.c (MASK_V9C): Define.
1261         (MASK_V9D): Likewise.
1262         (MASK_V9E): Likewise.
1263         (MASK_V9V): Likewise.
1264         (MASK_V9M): Likewise.
1265         (v6): Add MASK_V9{C,D,E,V,M}.
1266         (v6notlet): Likewise.
1267         (v7): Likewise.
1268         (v8): Likewise.
1269         (v9): Likewise.
1270         (v9andleon): Likewise.
1271         (v9a): Likewise.
1272         (v9b): Likewise.
1273         (v9c): Define.
1274         (v9d): Likewise.
1275         (v9e): Likewise.
1276         (v9v): Likewise.
1277         (v9m): Likewise.
1278         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1279
1280 2016-06-15  Nick Clifton  <nickc@redhat.com>
1281
1282         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1283         constants to match expected behaviour.
1284         (nds32_parse_opcode): Likewise.  Also for whitespace.
1285
1286 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1287
1288         * arc-opc.c (extract_rhv1): Extract value from insn.
1289
1290 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1291
1292         * arc-nps400-tbl.h: Add ldbit instruction.
1293         * arc-opc.c: Add flag classes required for ldbit.
1294
1295 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1296
1297         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1298         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1299         support the above instructions.
1300
1301 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1302
1303         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1304         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1305         csma, cbba, zncv, and hofs.
1306         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1307         support the above instructions.
1308
1309 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1310
1311         * arc-nps400-tbl.h: Add andab and orab instructions.
1312
1313 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1314
1315         * arc-nps400-tbl.h: Add addl-like instructions.
1316
1317 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1318
1319         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1320
1321 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1322
1323         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1324         instructions.
1325
1326 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1327
1328         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1329         variable.
1330         (init_disasm): Handle new command line option "insnlength".
1331         (print_s390_disassembler_options): Mention new option in help
1332         output.
1333         (print_insn_s390): Use the encoded insn length when dumping
1334         unknown instructions.
1335
1336 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1337
1338         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1339          to the address and set as symbol address for LDS/ STS immediate operands.
1340
1341 2016-06-07  Alan Modra  <amodra@gmail.com>
1342
1343         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1344         cpu for "vle" to e500.
1345         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1346         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1347         (PPCNONE): Delete, substitute throughout.
1348         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1349         except for major opcode 4 and 31.
1350         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1351
1352 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1353
1354         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1355         ARM_EXT_RAS in relevant entries.
1356
1357 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1358
1359         PR binutils/20196
1360         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1361         opcodes for E6500.
1362
1363 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1364
1365         PR binutis/18386
1366         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1367         (indir_v_mode): New.
1368         Add comments for '&'.
1369         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1370         (putop): Handle '&'.
1371         (intel_operand_size): Handle indir_v_mode.
1372         (OP_E_register): Likewise.
1373         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1374         64-bit indirect call/jmp for AMD64.
1375         * i386-tbl.h: Regenerated
1376
1377 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1378
1379         * arc-dis.c (struct arc_operand_iterator): New structure.
1380         (find_format_from_table): All the old content from find_format,
1381         with some minor adjustments, and parameter renaming.
1382         (find_format_long_instructions): New function.
1383         (find_format): Rewritten.
1384         (arc_insn_length): Add LSB parameter.
1385         (extract_operand_value): New function.
1386         (operand_iterator_next): New function.
1387         (print_insn_arc): Use new functions to find opcode, and iterator
1388         over operands.
1389         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1390         (extract_nps_3bit_dst_short): New function.
1391         (insert_nps_3bit_src2_short): New function.
1392         (extract_nps_3bit_src2_short): New function.
1393         (insert_nps_bitop1_size): New function.
1394         (extract_nps_bitop1_size): New function.
1395         (insert_nps_bitop2_size): New function.
1396         (extract_nps_bitop2_size): New function.
1397         (insert_nps_bitop_mod4_msb): New function.
1398         (extract_nps_bitop_mod4_msb): New function.
1399         (insert_nps_bitop_mod4_lsb): New function.
1400         (extract_nps_bitop_mod4_lsb): New function.
1401         (insert_nps_bitop_dst_pos3_pos4): New function.
1402         (extract_nps_bitop_dst_pos3_pos4): New function.
1403         (insert_nps_bitop_ins_ext): New function.
1404         (extract_nps_bitop_ins_ext): New function.
1405         (arc_operands): Add new operands.
1406         (arc_long_opcodes): New global array.
1407         (arc_num_long_opcodes): New global.
1408         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1409
1410 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1411
1412         * nds32-asm.h: Add extern "C".
1413         * sh-opc.h: Likewise.
1414
1415 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1416
1417         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1418         0,b,limm to the rflt instruction.
1419
1420 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1421
1422         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1423         constant.
1424
1425 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1426
1427         PR gas/20145
1428         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1429         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1430         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1431         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1432         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1433         * i386-init.h: Regenerated.
1434
1435 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1436
1437         PR gas/20145
1438         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1439         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1440         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1441         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1442         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1443         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1444         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1445         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1446         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1447         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1448         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1449         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1450         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1451         CpuRegMask for AVX512.
1452         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1453         and CpuRegMask.
1454         (set_bitfield_from_cpu_flag_init): New function.
1455         (set_bitfield): Remove const on f.  Call
1456         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1457         * i386-opc.h (CpuRegMMX): New.
1458         (CpuRegXMM): Likewise.
1459         (CpuRegYMM): Likewise.
1460         (CpuRegZMM): Likewise.
1461         (CpuRegMask): Likewise.
1462         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1463         and cpuregmask.
1464         * i386-init.h: Regenerated.
1465         * i386-tbl.h: Likewise.
1466
1467 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1468
1469         PR gas/20154
1470         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1471         (opcode_modifiers): Add AMD64 and Intel64.
1472         (main): Properly verify CpuMax.
1473         * i386-opc.h (CpuAMD64): Removed.
1474         (CpuIntel64): Likewise.
1475         (CpuMax): Set to CpuNo64.
1476         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1477         (AMD64): New.
1478         (Intel64): Likewise.
1479         (i386_opcode_modifier): Add amd64 and intel64.
1480         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1481         on call and jmp.
1482         * i386-init.h: Regenerated.
1483         * i386-tbl.h: Likewise.
1484
1485 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1486
1487         PR gas/20154
1488         * i386-gen.c (main): Fail if CpuMax is incorrect.
1489         * i386-opc.h (CpuMax): Set to CpuIntel64.
1490         * i386-tbl.h: Regenerated.
1491
1492 2016-05-27  Nick Clifton  <nickc@redhat.com>
1493
1494         PR target/20150
1495         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1496         (msp430dis_opcode_unsigned): New function.
1497         (msp430dis_opcode_signed): New function.
1498         (msp430_singleoperand): Use the new opcode reading functions.
1499         Only disassenmble bytes if they were successfully read.
1500         (msp430_doubleoperand): Likewise.
1501         (msp430_branchinstr): Likewise.
1502         (msp430x_callx_instr): Likewise.
1503         (print_insn_msp430): Check that it is safe to read bytes before
1504         attempting disassembly.  Use the new opcode reading functions.
1505
1506 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1507
1508         * ppc-opc.c (CY): New define.  Document it.
1509         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1510
1511 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1512
1513         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1514         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1515         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1516         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1517         CPU_ANY_AVX_FLAGS.
1518         * i386-init.h: Regenerated.
1519
1520 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1521
1522         PR gas/20141
1523         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1524         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1525         * i386-init.h: Regenerated.
1526
1527 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1528
1529         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1530         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1531         * i386-init.h: Regenerated.
1532
1533 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1534
1535         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1536         information.
1537         (print_insn_arc): Set insn_type information.
1538         * arc-opc.c (C_CC): Add F_CLASS_COND.
1539         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1540         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1541         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1542         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1543         (brne, brne_s, jeq_s, jne_s): Likewise.
1544
1545 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1546
1547         * arc-tbl.h (neg): New instruction variant.
1548
1549 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1550
1551         * arc-dis.c (find_format, find_format, get_auxreg)
1552         (print_insn_arc): Changed.
1553         * arc-ext.h (INSERT_XOP): Likewise.
1554
1555 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1556
1557         * tic54x-dis.c (sprint_mmr): Adjust.
1558         * tic54x-opc.c: Likewise.
1559
1560 2016-05-19  Alan Modra  <amodra@gmail.com>
1561
1562         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1563
1564 2016-05-19  Alan Modra  <amodra@gmail.com>
1565
1566         * ppc-opc.c: Formatting.
1567         (NSISIGNOPT): Define.
1568         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1569
1570 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1571
1572         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1573         replacing references to `micromips_ase' throughout.
1574         (_print_insn_mips): Don't use file-level microMIPS annotation to
1575         determine the disassembly mode with the symbol table.
1576
1577 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1578
1579         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1580
1581 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1582
1583         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1584         mips64r6.
1585         * mips-opc.c (D34): New macro.
1586         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1587
1588 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1589
1590         * i386-dis.c (prefix_table): Add RDPID instruction.
1591         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1592         (cpu_flags): Add RDPID bitfield.
1593         * i386-opc.h (enum): Add RDPID element.
1594         (i386_cpu_flags): Add RDPID field.
1595         * i386-opc.tbl: Add RDPID instruction.
1596         * i386-init.h: Regenerate.
1597         * i386-tbl.h: Regenerate.
1598
1599 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1600
1601         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1602         branch type of a symbol.
1603         (print_insn): Likewise.
1604
1605 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1606
1607         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1608         Mainline Security Extensions instructions.
1609         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1610         Extensions instructions.
1611         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1612         instructions.
1613         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1614         special registers.
1615
1616 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1617
1618         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1619
1620 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1621
1622         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1623         (arcExtMap_genOpcode): Likewise.
1624         * arc-opc.c (arg_32bit_rc): Define new variable.
1625         (arg_32bit_u6): Likewise.
1626         (arg_32bit_limm): Likewise.
1627
1628 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1629
1630         * aarch64-gen.c (VERIFIER): Define.
1631         * aarch64-opc.c (VERIFIER): Define.
1632         (verify_ldpsw): Use static linkage.
1633         * aarch64-opc.h (verify_ldpsw): Remove.
1634         * aarch64-tbl.h: Use VERIFIER for verifiers.
1635
1636 2016-04-28  Nick Clifton  <nickc@redhat.com>
1637
1638         PR target/19722
1639         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1640         * aarch64-opc.c (verify_ldpsw): New function.
1641         * aarch64-opc.h (verify_ldpsw): New prototype.
1642         * aarch64-tbl.h: Add initialiser for verifier field.
1643         (LDPSW): Set verifier to verify_ldpsw.
1644
1645 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1646
1647         PR binutils/19983
1648         PR binutils/19984
1649         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1650         smaller than address size.
1651
1652 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1653
1654         * alpha-dis.c: Regenerate.
1655         * crx-dis.c: Likewise.
1656         * disassemble.c: Likewise.
1657         * epiphany-opc.c: Likewise.
1658         * fr30-opc.c: Likewise.
1659         * frv-opc.c: Likewise.
1660         * ip2k-opc.c: Likewise.
1661         * iq2000-opc.c: Likewise.
1662         * lm32-opc.c: Likewise.
1663         * lm32-opinst.c: Likewise.
1664         * m32c-opc.c: Likewise.
1665         * m32r-opc.c: Likewise.
1666         * m32r-opinst.c: Likewise.
1667         * mep-opc.c: Likewise.
1668         * mt-opc.c: Likewise.
1669         * or1k-opc.c: Likewise.
1670         * or1k-opinst.c: Likewise.
1671         * tic80-opc.c: Likewise.
1672         * xc16x-opc.c: Likewise.
1673         * xstormy16-opc.c: Likewise.
1674
1675 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1676
1677         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1678         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1679         calcsd, and calcxd instructions.
1680         * arc-opc.c (insert_nps_bitop_size): Delete.
1681         (extract_nps_bitop_size): Delete.
1682         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1683         (extract_nps_qcmp_m3): Define.
1684         (extract_nps_qcmp_m2): Define.
1685         (extract_nps_qcmp_m1): Define.
1686         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1687         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1688         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1689         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1690         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1691         NPS_QCMP_M3.
1692
1693 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1694
1695         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1696
1697 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1698
1699         * Makefile.in: Regenerated with automake 1.11.6.
1700         * aclocal.m4: Likewise.
1701
1702 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1703
1704         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1705         instructions.
1706         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1707         (extract_nps_cmem_uimm16): New function.
1708         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1709
1710 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1711
1712         * arc-dis.c (arc_insn_length): New function.
1713         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1714         (find_format): Change insnLen parameter to unsigned.
1715
1716 2016-04-13  Nick Clifton  <nickc@redhat.com>
1717
1718         PR target/19937
1719         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1720         the LD.B and LD.BU instructions.
1721
1722 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1723
1724         * arc-dis.c (find_format): Check for extension flags.
1725         (print_flags): New function.
1726         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1727         .extAuxRegister.
1728         * arc-ext.c (arcExtMap_coreRegName): Use
1729         LAST_EXTENSION_CORE_REGISTER.
1730         (arcExtMap_coreReadWrite): Likewise.
1731         (dump_ARC_extmap): Update printing.
1732         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1733         (arc_aux_regs): Add cpu field.
1734         * arc-regs.h: Add cpu field, lower case name aux registers.
1735
1736 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1737
1738         * arc-tbl.h: Add rtsc, sleep with no arguments.
1739
1740 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1741
1742         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1743         Initialize.
1744         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1745         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1746         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1747         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1748         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1749         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1750         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1751         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1752         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1753         (arc_opcode arc_opcodes): Null terminate the array.
1754         (arc_num_opcodes): Remove.
1755         * arc-ext.h (INSERT_XOP): Define.
1756         (extInstruction_t): Likewise.
1757         (arcExtMap_instName): Delete.
1758         (arcExtMap_insn): New function.
1759         (arcExtMap_genOpcode): Likewise.
1760         * arc-ext.c (ExtInstruction): Remove.
1761         (create_map): Zero initialize instruction fields.
1762         (arcExtMap_instName): Remove.
1763         (arcExtMap_insn): New function.
1764         (dump_ARC_extmap): More info while debuging.
1765         (arcExtMap_genOpcode): New function.
1766         * arc-dis.c (find_format): New function.
1767         (print_insn_arc): Use find_format.
1768         (arc_get_disassembler): Enable dump_ARC_extmap only when
1769         debugging.
1770
1771 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1772
1773         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1774         instruction bits out.
1775
1776 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1777
1778         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1779         * arc-opc.c (arc_flag_operands): Add new flags.
1780         (arc_flag_classes): Add new classes.
1781
1782 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1783
1784         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1785
1786 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1787
1788         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1789         encode1, rflt, crc16, and crc32 instructions.
1790         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1791         (arc_flag_classes): Add C_NPS_R.
1792         (insert_nps_bitop_size_2b): New function.
1793         (extract_nps_bitop_size_2b): Likewise.
1794         (insert_nps_bitop_uimm8): Likewise.
1795         (extract_nps_bitop_uimm8): Likewise.
1796         (arc_operands): Add new operand entries.
1797
1798 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1799
1800         * arc-regs.h: Add a new subclass field.  Add double assist
1801         accumulator register values.
1802         * arc-tbl.h: Use DPA subclass to mark the double assist
1803         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1804         * arc-opc.c (RSP): Define instead of SP.
1805         (arc_aux_regs): Add the subclass field.
1806
1807 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1808
1809         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1810
1811 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1812
1813         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1814         NPS_R_SRC1.
1815
1816 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1817
1818         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1819         issues.  No functional changes.
1820
1821 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1822
1823         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1824         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1825         (RTT): Remove duplicate.
1826         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1827         (PCT_CONFIG*): Remove.
1828         (D1L, D1H, D2H, D2L): Define.
1829
1830 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1831
1832         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1833
1834 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1835
1836         * arc-tbl.h (invld07): Remove.
1837         * arc-ext-tbl.h: New file.
1838         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1839         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1840
1841 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1842
1843         Fix -Wstack-usage warnings.
1844         * aarch64-dis.c (print_operands): Substitute size.
1845         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1846
1847 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1848
1849         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1850         to get a proper diagnostic when an invalid ASR register is used.
1851
1852 2016-03-22  Nick Clifton  <nickc@redhat.com>
1853
1854         * configure: Regenerate.
1855
1856 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1857
1858         * arc-nps400-tbl.h: New file.
1859         * arc-opc.c: Add top level comment.
1860         (insert_nps_3bit_dst): New function.
1861         (extract_nps_3bit_dst): New function.
1862         (insert_nps_3bit_src2): New function.
1863         (extract_nps_3bit_src2): New function.
1864         (insert_nps_bitop_size): New function.
1865         (extract_nps_bitop_size): New function.
1866         (arc_flag_operands): Add nps400 entries.
1867         (arc_flag_classes): Add nps400 entries.
1868         (arc_operands): Add nps400 entries.
1869         (arc_opcodes): Add nps400 include.
1870
1871 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1872
1873         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1874         the new class enum values.
1875
1876 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1877
1878         * arc-dis.c (print_insn_arc): Handle nps400.
1879
1880 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1881
1882         * arc-opc.c (BASE): Delete.
1883
1884 2016-03-18  Nick Clifton  <nickc@redhat.com>
1885
1886         PR target/19721
1887         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1888         of MOV insn that aliases an ORR insn.
1889
1890 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1891
1892         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1893
1894 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1895
1896         * mcore-opc.h: Add const qualifiers.
1897         * microblaze-opc.h (struct op_code_struct): Likewise.
1898         * sh-opc.h: Likewise.
1899         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1900         (tic4x_print_op): Likewise.
1901
1902 2016-03-02  Alan Modra  <amodra@gmail.com>
1903
1904         * or1k-desc.h: Regenerate.
1905         * fr30-ibld.c: Regenerate.
1906         * rl78-decode.c: Regenerate.
1907
1908 2016-03-01  Nick Clifton  <nickc@redhat.com>
1909
1910         PR target/19747
1911         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1912
1913 2016-02-24  Renlin Li  <renlin.li@arm.com>
1914
1915         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1916         (print_insn_coprocessor): Support fp16 instructions.
1917
1918 2016-02-24  Renlin Li  <renlin.li@arm.com>
1919
1920         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1921         vminnm, vrint(mpna).
1922
1923 2016-02-24  Renlin Li  <renlin.li@arm.com>
1924
1925         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1926         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1927
1928 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1929
1930         * i386-dis.c (print_insn): Parenthesize expression to prevent
1931         truncated addresses.
1932         (OP_J): Likewise.
1933
1934 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1935             Janek van Oirschot  <jvanoirs@synopsys.com>
1936
1937         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1938         variable.
1939
1940 2016-02-04  Nick Clifton  <nickc@redhat.com>
1941
1942         PR target/19561
1943         * msp430-dis.c (print_insn_msp430): Add a special case for
1944         decoding an RRC instruction with the ZC bit set in the extension
1945         word.
1946
1947 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1948
1949         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1950         * epiphany-ibld.c: Regenerate.
1951         * fr30-ibld.c: Regenerate.
1952         * frv-ibld.c: Regenerate.
1953         * ip2k-ibld.c: Regenerate.
1954         * iq2000-ibld.c: Regenerate.
1955         * lm32-ibld.c: Regenerate.
1956         * m32c-ibld.c: Regenerate.
1957         * m32r-ibld.c: Regenerate.
1958         * mep-ibld.c: Regenerate.
1959         * mt-ibld.c: Regenerate.
1960         * or1k-ibld.c: Regenerate.
1961         * xc16x-ibld.c: Regenerate.
1962         * xstormy16-ibld.c: Regenerate.
1963
1964 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1965
1966         * epiphany-dis.c: Regenerated from latest cpu files.
1967
1968 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1969
1970         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1971         test bit.
1972
1973 2016-01-25  Renlin Li  <renlin.li@arm.com>
1974
1975         * arm-dis.c (mapping_symbol_for_insn): New function.
1976         (find_ifthen_state): Call mapping_symbol_for_insn().
1977
1978 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1979
1980         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1981         of MSR UAO immediate operand.
1982
1983 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1984
1985         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1986         instruction support.
1987
1988 2016-01-17  Alan Modra  <amodra@gmail.com>
1989
1990         * configure: Regenerate.
1991
1992 2016-01-14  Nick Clifton  <nickc@redhat.com>
1993
1994         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1995         instructions that can support stack pointer operations.
1996         * rl78-decode.c: Regenerate.
1997         * rl78-dis.c: Fix display of stack pointer in MOVW based
1998         instructions.
1999
2000 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
2001
2002         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2003         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
2004         erxtatus_el1 and erxaddr_el1.
2005
2006 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
2007
2008         * arm-dis.c (arm_opcodes): Add "esb".
2009         (thumb_opcodes): Likewise.
2010
2011 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
2012
2013         * ppc-opc.c <xscmpnedp>: Delete.
2014         <xvcmpnedp>: Likewise.
2015         <xvcmpnedp.>: Likewise.
2016         <xvcmpnesp>: Likewise.
2017         <xvcmpnesp.>: Likewise.
2018
2019 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
2020
2021         PR gas/13050
2022         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2023         addition to ISA_A.
2024
2025 2016-01-01  Alan Modra  <amodra@gmail.com>
2026
2027         Update year range in copyright notice of all files.
2028
2029 For older changes see ChangeLog-2015
2030 \f
2031 Copyright (C) 2016 Free Software Foundation, Inc.
2032
2033 Copying and distribution of this file, with or without modification,
2034 are permitted in any medium without royalty provided the copyright
2035 notice and this notice are preserved.
2036
2037 Local Variables:
2038 mode: change-log
2039 left-margin: 8
2040 fill-column: 74
2041 version-control: never
2042 End: