opcodes/ChangeLog

   1 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
   4         and FP register operands.
   5         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
   6         (FLD_SVE_Vn): New aarch64_field_kinds.
   7         * aarch64-opc.c (fields): Add corresponding entries.
   8         (aarch64_print_operand): Handle the new SVE core and FP register
   9         operands.
  10         * aarch64-opc-2.c: Regenerate.
  11         * aarch64-asm-2.c: Likewise.
  12         * aarch64-dis-2.c: Likewise.
  13
  14 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  15
  16         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
  17         immediate operands.
  18         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
  19         * aarch64-opc.c (fields): Add corresponding entry.
  20         (operand_general_constraint_met_p): Handle the new SVE FP immediate
  21         operands.
  22         (aarch64_print_operand): Likewise.
  23         * aarch64-opc-2.c: Regenerate.
  24         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
  25         (ins_sve_float_zero_one): New inserters.
  26         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
  27         (aarch64_ins_sve_float_half_two): Likewise.
  28         (aarch64_ins_sve_float_zero_one): Likewise.
  29         * aarch64-asm-2.c: Regenerate.
  30         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
  31         (ext_sve_float_zero_one): New extractors.
  32         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
  33         (aarch64_ext_sve_float_half_two): Likewise.
  34         (aarch64_ext_sve_float_zero_one): Likewise.
  35         * aarch64-dis-2.c: Regenerate.
  36
  37 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  38
  39         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
  40         integer immediate operands.
  41         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
  42         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
  43         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
  44         * aarch64-opc.c (fields): Add corresponding entries.
  45         (operand_general_constraint_met_p): Handle the new SVE integer
  46         immediate operands.
  47         (aarch64_print_operand): Likewise.
  48         (aarch64_sve_dupm_mov_immediate_p): New function.
  49         * aarch64-opc-2.c: Regenerate.
  50         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
  51         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
  52         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
  53         (aarch64_ins_limm): ...here.
  54         (aarch64_ins_inv_limm): New function.
  55         (aarch64_ins_sve_aimm): Likewise.
  56         (aarch64_ins_sve_asimm): Likewise.
  57         (aarch64_ins_sve_limm_mov): Likewise.
  58         (aarch64_ins_sve_shlimm): Likewise.
  59         (aarch64_ins_sve_shrimm): Likewise.
  60         * aarch64-asm-2.c: Regenerate.
  61         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
  62         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
  63         * aarch64-dis.c (decode_limm): New function, split out from...
  64         (aarch64_ext_limm): ...here.
  65         (aarch64_ext_inv_limm): New function.
  66         (decode_sve_aimm): Likewise.
  67         (aarch64_ext_sve_aimm): Likewise.
  68         (aarch64_ext_sve_asimm): Likewise.
  69         (aarch64_ext_sve_limm_mov): Likewise.
  70         (aarch64_top_bit): Likewise.
  71         (aarch64_ext_sve_shlimm): Likewise.
  72         (aarch64_ext_sve_shrimm): Likewise.
  73         * aarch64-dis-2.c: Regenerate.
  74
  75 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  76
  77         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
  78         operands.
  79         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
  80         the AARCH64_MOD_MUL_VL entry.
  81         (value_aligned_p): Cope with non-power-of-two alignments.
  82         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
  83         (print_immediate_offset_address): Likewise.
  84         (aarch64_print_operand): Likewise.
  85         * aarch64-opc-2.c: Regenerate.
  86         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
  87         (ins_sve_addr_ri_s9xvl): New inserters.
  88         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
  89         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
  90         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
  91         * aarch64-asm-2.c: Regenerate.
  92         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
  93         (ext_sve_addr_ri_s9xvl): New extractors.
  94         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
  95         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
  96         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
  97         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
  98         * aarch64-dis-2.c: Regenerate.
  99
 100 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 101
 102         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 103         address operands.
 104         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 105         (FLD_SVE_xs_22): New aarch64_field_kinds.
 106         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 107         (get_operand_specific_data): New function.
 108         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 109         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 110         (operand_general_constraint_met_p): Handle the new SVE address
 111         operands.
 112         (sve_reg): New array.
 113         (get_addr_sve_reg_name): New function.
 114         (aarch64_print_operand): Handle the new SVE address operands.
 115         * aarch64-opc-2.c: Regenerate.
 116         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 117         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 118         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 119         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 120         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 121         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 122         (aarch64_ins_sve_addr_zi_u5): Likewise.
 123         (aarch64_ins_sve_addr_zz): Likewise.
 124         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 125         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 126         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 127         * aarch64-asm-2.c: Regenerate.
 128         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 129         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 130         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 131         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 132         (aarch64_ext_sve_addr_ri_u6): Likewise.
 133         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 134         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 135         (aarch64_ext_sve_addr_zi_u5): Likewise.
 136         (aarch64_ext_sve_addr_zz): Likewise.
 137         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 138         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 139         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 140         * aarch64-dis-2.c: Regenerate.
 141
 142 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 143
 144         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 145         AARCH64_OPND_SVE_PATTERN_SCALED.
 146         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 147         * aarch64-opc.c (fields): Add a corresponding entry.
 148         (set_multiplier_out_of_range_error): New function.
 149         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 150         (operand_general_constraint_met_p): Handle
 151         AARCH64_OPND_SVE_PATTERN_SCALED.
 152         (print_register_offset_address): Use PRIi64 to print the
 153         shift amount.
 154         (aarch64_print_operand): Likewise.  Handle
 155         AARCH64_OPND_SVE_PATTERN_SCALED.
 156         * aarch64-opc-2.c: Regenerate.
 157         * aarch64-asm.h (ins_sve_scale): New inserter.
 158         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 159         * aarch64-asm-2.c: Regenerate.
 160         * aarch64-dis.h (ext_sve_scale): New inserter.
 161         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 162         * aarch64-dis-2.c: Regenerate.
 163
 164 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 165
 166         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 167         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 168         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 169         (FLD_SVE_prfop): Likewise.
 170         * aarch64-opc.c: Include libiberty.h.
 171         (aarch64_sve_pattern_array): New variable.
 172         (aarch64_sve_prfop_array): Likewise.
 173         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 174         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 175         AARCH64_OPND_SVE_PRFOP.
 176         * aarch64-asm-2.c: Regenerate.
 177         * aarch64-dis-2.c: Likewise.
 178         * aarch64-opc-2.c: Likewise.
 179
 180 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 181
 182         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 183         AARCH64_OPND_QLF_P_[ZM].
 184         (aarch64_print_operand): Print /z and /m where appropriate.
 185
 186 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 187
 188         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 189         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 190         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 191         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 192         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 193         * aarch64-opc.c (fields): Add corresponding entries here.
 194         (operand_general_constraint_met_p): Check that SVE register lists
 195         have the correct length.  Check the ranges of SVE index registers.
 196         Check for cases where p8-p15 are used in 3-bit predicate fields.
 197         (aarch64_print_operand): Handle the new SVE operands.
 198         * aarch64-opc-2.c: Regenerate.
 199         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 200         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 201         (aarch64_ins_sve_reglist): Likewise.
 202         * aarch64-asm-2.c: Regenerate.
 203         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 204         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 205         (aarch64_ext_sve_reglist): Likewise.
 206         * aarch64-dis-2.c: Regenerate.
 207
 208 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 209
 210         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 211         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 212         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 213         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 214         tied operands.
 215
 216 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 217
 218         * aarch64-opc.c (get_offset_int_reg_name): New function.
 219         (print_immediate_offset_address): Likewise.
 220         (print_register_offset_address): Take the base and offset
 221         registers as parameters.
 222         (aarch64_print_operand): Update caller accordingly.  Use
 223         print_immediate_offset_address.
 224
 225 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 226
 227         * aarch64-opc.c (BANK): New macro.
 228         (R32, R64): Take a register number as argument
 229         (int_reg): Use BANK.
 230
 231 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 232
 233         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 234         (aarch64_print_operand): Update accordingly.
 235
 236 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 237
 238         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 239         for FPIMM.
 240         * aarch64-asm.h (ins_fpimm): New inserter.
 241         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 242         * aarch64-asm-2.c: Regenerate.
 243         * aarch64-dis.h (ext_fpimm): New extractor.
 244         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 245         (aarch64_ext_fpimm): New function.
 246         * aarch64-dis-2.c: Regenerate.
 247
 248 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 249
 250         * aarch64-asm.c: Include libiberty.h.
 251         (insert_fields): New function.
 252         (aarch64_ins_imm): Use it.
 253         * aarch64-dis.c (extract_fields): New function.
 254         (aarch64_ext_imm): Use it.
 255
 256 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 257
 258         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 259         with an esize parameter.
 260         (operand_general_constraint_met_p): Update accordingly.
 261         Fix misindented code.
 262         * aarch64-asm.c (aarch64_ins_limm): Update call to
 263         aarch64_logical_immediate_p.
 264
 265 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 266
 267         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 268
 269 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 270
 271         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 272
 273 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 274
 275         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 276
 277 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 278
 279         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 280         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 281         xor3>: Delete mnemonics.
 282         <cp_abort>: Rename mnemonic from ...
 283         <cpabort>: ...to this.
 284         <setb>: Change to a X form instruction.
 285         <sync>: Change to 1 operand form.
 286         <copy>: Delete mnemonic.
 287         <copy_first>: Rename mnemonic from ...
 288         <copy>: ...to this.
 289         <paste, paste.>: Delete mnemonics.
 290         <paste_last>: Rename mnemonic from ...
 291         <paste.>: ...to this.
 292
 293 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 294
 295         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 296
 297 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 298
 299         * s390-mkopc.c (main): Support alternate arch strings.
 300
 301 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 302
 303         * s390-opc.txt: Fix kmctr instruction type.
 304
 305 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 306
 307         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 308         * i386-init.h: Regenerated.
 309
 310 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 311
 312         * opcodes/arc-dis.c (print_insn_arc): Changed.
 313
 314 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 315
 316         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 317         camellia_fl.
 318
 319 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 320
 321         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 322         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 323         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 324
 325 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 326
 327         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 328         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 329         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 330         PREFIX_MOD_3_0FAE_REG_4.
 331         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 332         PREFIX_MOD_3_0FAE_REG_4.
 333         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 334         (cpu_flags): Add CpuPTWRITE.
 335         * i386-opc.h (CpuPTWRITE): New.
 336         (i386_cpu_flags): Add cpuptwrite.
 337         * i386-opc.tbl: Add ptwrite instruction.
 338         * i386-init.h: Regenerated.
 339         * i386-tbl.h: Likewise.
 340
 341 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 342
 343         * arc-dis.h: Wrap around in extern "C".
 344
 345 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 346
 347         * aarch64-tbl.h (V8_2_INSN): New macro.
 348         (aarch64_opcode_table): Use it.
 349
 350 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 351
 352         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 353         CORE_INSN, __FP_INSN and SIMD_INSN.
 354
 355 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 356
 357         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 358         (aarch64_opcode_table): Update uses accordingly.
 359
 360 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 361         Kwok Cheung Yeung  <kcy@codesourcery.com>
 362
 363         opcodes/
 364         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 365         'e_cmplwi' to 'e_cmpli' instead.
 366         (OPVUPRT, OPVUPRT_MASK): Define.
 367         (powerpc_opcodes): Add E200Z4 insns.
 368         (vle_opcodes): Add context save/restore insns.
 369
 370 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 371
 372         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 373         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 374         "j".
 375
 376 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 377
 378         * arc-nps400-tbl.h: Change block comments to GNU format.
 379         * arc-dis.c: Add new globals addrtypenames,
 380         addrtypenames_max, and addtypeunknown.
 381         (get_addrtype): New function.
 382         (print_insn_arc): Print colons and address types when
 383         required.
 384         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 385         define insert and extract functions for all address types.
 386         (arc_operands): Add operands for colon and all address
 387         types.
 388         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 389         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 390         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 391         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 392         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 393         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 394
 395 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 396
 397         * configure: Regenerated.
 398
 399 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 400
 401         * arc-dis.c (skipclass): New structure.
 402         (decodelist): New variable.
 403         (is_compatible_p): New function.
 404         (new_element): Likewise.
 405         (skip_class_p): Likewise.
 406         (find_format_from_table): Use skip_class_p function.
 407         (find_format): Decode first the extension instructions.
 408         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 409         e_flags.
 410         (parse_option): New function.
 411         (parse_disassembler_options): Likewise.
 412         (print_arc_disassembler_options): Likewise.
 413         (print_insn_arc): Use parse_disassembler_options function.  Proper
 414         select ARCv2 cpu variant.
 415         * disassemble.c (disassembler_usage): Add ARC disassembler
 416         options.
 417
 418 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 419
 420         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 421         annotation from the "nal" entry and reorder it beyond "bltzal".
 422
 423 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 424
 425         * sparc-opc.c (ldtxa): New macro.
 426         (sparc_opcodes): Use the macro defined above to add entries for
 427         the LDTXA instructions.
 428         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 429         instruction.
 430
 431 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 432
 433         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 434         and "jmpc".
 435
 436 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 437
 438         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 439         (movzb): Adjust to cover all permitted suffixes.
 440         (movzw): New.
 441         * i386-tbl.h: Re-generate.
 442
 443 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 444
 445         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 446         (lgdt): Remove Tbyte from non-64-bit variant.
 447         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 448         xsaves64, xsavec64): Remove Disp16.
 449         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 450         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 451         64-bit variants.
 452         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 453         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 454         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 455         64-bit variants.
 456         * i386-tbl.h: Re-generate.
 457
 458 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 459
 460         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 461         * i386-tbl.h: Re-generate.
 462
 463 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 464
 465         * arm-dis.c (print_insn): Fix typo in comment.
 466
 467 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 468
 469         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 470         range of ldst_elemlist operands.
 471         (print_register_list): Use PRIi64 to print the index.
 472         (aarch64_print_operand): Likewise.
 473
 474 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 475
 476         * mcore-opc.h: Remove sentinal.
 477         * mcore-dis.c (print_insn_mcore): Adjust.
 478
 479 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 480
 481         * arc-opc.c: Correct description of availability of NPS400
 482         features.
 483
 484 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 485
 486         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 487         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 488         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 489         xor3>: New mnemonics.
 490         <setb>: Change to a VX form instruction.
 491         (insert_sh6): Add support for rldixor.
 492         (extract_sh6): Likewise.
 493
 494 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 495
 496         * arc-ext.h: Wrap in extern C.
 497
 498 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 499
 500         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 501         Use same method for determining instruction length on ARC700 and
 502         NPS-400.
 503         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 504         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 505         with the NPS400 subclass.
 506         * arc-opc.c: Likewise.
 507
 508 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 509
 510         * sparc-opc.c (rdasr): New macro.
 511         (wrasr): Likewise.
 512         (rdpr): Likewise.
 513         (wrpr): Likewise.
 514         (rdhpr): Likewise.
 515         (wrhpr): Likewise.
 516         (sparc_opcodes): Use the macros above to fix and expand the
 517         definition of read/write instructions from/to
 518         asr/privileged/hyperprivileged instructions.
 519         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 520         %hva_mask_nz.  Prefer softint_set and softint_clear over
 521         set_softint and clear_softint.
 522         (print_insn_sparc): Support %ver in Rd.
 523
 524 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 525
 526         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 527         architecture according to the hardware capabilities they require.
 528
 529 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 530
 531         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 532         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 533         bfd_mach_sparc_v9{c,d,e,v,m}.
 534         * sparc-opc.c (MASK_V9C): Define.
 535         (MASK_V9D): Likewise.
 536         (MASK_V9E): Likewise.
 537         (MASK_V9V): Likewise.
 538         (MASK_V9M): Likewise.
 539         (v6): Add MASK_V9{C,D,E,V,M}.
 540         (v6notlet): Likewise.
 541         (v7): Likewise.
 542         (v8): Likewise.
 543         (v9): Likewise.
 544         (v9andleon): Likewise.
 545         (v9a): Likewise.
 546         (v9b): Likewise.
 547         (v9c): Define.
 548         (v9d): Likewise.
 549         (v9e): Likewise.
 550         (v9v): Likewise.
 551         (v9m): Likewise.
 552         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 553
 554 2016-06-15  Nick Clifton  <nickc@redhat.com>
 555
 556         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 557         constants to match expected behaviour.
 558         (nds32_parse_opcode): Likewise.  Also for whitespace.
 559
 560 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 561
 562         * arc-opc.c (extract_rhv1): Extract value from insn.
 563
 564 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 565
 566         * arc-nps400-tbl.h: Add ldbit instruction.
 567         * arc-opc.c: Add flag classes required for ldbit.
 568
 569 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 570
 571         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 572         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 573         support the above instructions.
 574
 575 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 576
 577         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 578         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 579         csma, cbba, zncv, and hofs.
 580         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 581         support the above instructions.
 582
 583 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 584
 585         * arc-nps400-tbl.h: Add andab and orab instructions.
 586
 587 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 588
 589         * arc-nps400-tbl.h: Add addl-like instructions.
 590
 591 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 592
 593         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 594
 595 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 596
 597         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 598         instructions.
 599
 600 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 601
 602         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 603         variable.
 604         (init_disasm): Handle new command line option "insnlength".
 605         (print_s390_disassembler_options): Mention new option in help
 606         output.
 607         (print_insn_s390): Use the encoded insn length when dumping
 608         unknown instructions.
 609
 610 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 611
 612         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 613          to the address and set as symbol address for LDS/ STS immediate operands.
 614
 615 2016-06-07  Alan Modra  <amodra@gmail.com>
 616
 617         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 618         cpu for "vle" to e500.
 619         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 620         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 621         (PPCNONE): Delete, substitute throughout.
 622         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 623         except for major opcode 4 and 31.
 624         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 625
 626 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 627
 628         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 629         ARM_EXT_RAS in relevant entries.
 630
 631 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 632
 633         PR binutils/20196
 634         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 635         opcodes for E6500.
 636
 637 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 638
 639         PR binutis/18386
 640         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 641         (indir_v_mode): New.
 642         Add comments for '&'.
 643         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 644         (putop): Handle '&'.
 645         (intel_operand_size): Handle indir_v_mode.
 646         (OP_E_register): Likewise.
 647         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 648         64-bit indirect call/jmp for AMD64.
 649         * i386-tbl.h: Regenerated
 650
 651 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 652
 653         * arc-dis.c (struct arc_operand_iterator): New structure.
 654         (find_format_from_table): All the old content from find_format,
 655         with some minor adjustments, and parameter renaming.
 656         (find_format_long_instructions): New function.
 657         (find_format): Rewritten.
 658         (arc_insn_length): Add LSB parameter.
 659         (extract_operand_value): New function.
 660         (operand_iterator_next): New function.
 661         (print_insn_arc): Use new functions to find opcode, and iterator
 662         over operands.
 663         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 664         (extract_nps_3bit_dst_short): New function.
 665         (insert_nps_3bit_src2_short): New function.
 666         (extract_nps_3bit_src2_short): New function.
 667         (insert_nps_bitop1_size): New function.
 668         (extract_nps_bitop1_size): New function.
 669         (insert_nps_bitop2_size): New function.
 670         (extract_nps_bitop2_size): New function.
 671         (insert_nps_bitop_mod4_msb): New function.
 672         (extract_nps_bitop_mod4_msb): New function.
 673         (insert_nps_bitop_mod4_lsb): New function.
 674         (extract_nps_bitop_mod4_lsb): New function.
 675         (insert_nps_bitop_dst_pos3_pos4): New function.
 676         (extract_nps_bitop_dst_pos3_pos4): New function.
 677         (insert_nps_bitop_ins_ext): New function.
 678         (extract_nps_bitop_ins_ext): New function.
 679         (arc_operands): Add new operands.
 680         (arc_long_opcodes): New global array.
 681         (arc_num_long_opcodes): New global.
 682         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 683
 684 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 685
 686         * nds32-asm.h: Add extern "C".
 687         * sh-opc.h: Likewise.
 688
 689 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 690
 691         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 692         0,b,limm to the rflt instruction.
 693
 694 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 695
 696         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 697         constant.
 698
 699 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 700
 701         PR gas/20145
 702         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 703         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 704         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 705         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 706         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 707         * i386-init.h: Regenerated.
 708
 709 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 710
 711         PR gas/20145
 712         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 713         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 714         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 715         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 716         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 717         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 718         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 719         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 720         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 721         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 722         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 723         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 724         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 725         CpuRegMask for AVX512.
 726         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 727         and CpuRegMask.
 728         (set_bitfield_from_cpu_flag_init): New function.
 729         (set_bitfield): Remove const on f.  Call
 730         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 731         * i386-opc.h (CpuRegMMX): New.
 732         (CpuRegXMM): Likewise.
 733         (CpuRegYMM): Likewise.
 734         (CpuRegZMM): Likewise.
 735         (CpuRegMask): Likewise.
 736         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 737         and cpuregmask.
 738         * i386-init.h: Regenerated.
 739         * i386-tbl.h: Likewise.
 740
 741 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 742
 743         PR gas/20154
 744         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 745         (opcode_modifiers): Add AMD64 and Intel64.
 746         (main): Properly verify CpuMax.
 747         * i386-opc.h (CpuAMD64): Removed.
 748         (CpuIntel64): Likewise.
 749         (CpuMax): Set to CpuNo64.
 750         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 751         (AMD64): New.
 752         (Intel64): Likewise.
 753         (i386_opcode_modifier): Add amd64 and intel64.
 754         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 755         on call and jmp.
 756         * i386-init.h: Regenerated.
 757         * i386-tbl.h: Likewise.
 758
 759 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 760
 761         PR gas/20154
 762         * i386-gen.c (main): Fail if CpuMax is incorrect.
 763         * i386-opc.h (CpuMax): Set to CpuIntel64.
 764         * i386-tbl.h: Regenerated.
 765
 766 2016-05-27  Nick Clifton  <nickc@redhat.com>
 767
 768         PR target/20150
 769         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 770         (msp430dis_opcode_unsigned): New function.
 771         (msp430dis_opcode_signed): New function.
 772         (msp430_singleoperand): Use the new opcode reading functions.
 773         Only disassenmble bytes if they were successfully read.
 774         (msp430_doubleoperand): Likewise.
 775         (msp430_branchinstr): Likewise.
 776         (msp430x_callx_instr): Likewise.
 777         (print_insn_msp430): Check that it is safe to read bytes before
 778         attempting disassembly.  Use the new opcode reading functions.
 779
 780 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 781
 782         * ppc-opc.c (CY): New define.  Document it.
 783         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 784
 785 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 786
 787         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 788         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 789         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 790         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 791         CPU_ANY_AVX_FLAGS.
 792         * i386-init.h: Regenerated.
 793
 794 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 795
 796         PR gas/20141
 797         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 798         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 799         * i386-init.h: Regenerated.
 800
 801 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 802
 803         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 804         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 805         * i386-init.h: Regenerated.
 806
 807 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 808
 809         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 810         information.
 811         (print_insn_arc): Set insn_type information.
 812         * arc-opc.c (C_CC): Add F_CLASS_COND.
 813         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 814         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 815         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 816         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 817         (brne, brne_s, jeq_s, jne_s): Likewise.
 818
 819 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 820
 821         * arc-tbl.h (neg): New instruction variant.
 822
 823 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 824
 825         * arc-dis.c (find_format, find_format, get_auxreg)
 826         (print_insn_arc): Changed.
 827         * arc-ext.h (INSERT_XOP): Likewise.
 828
 829 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 830
 831         * tic54x-dis.c (sprint_mmr): Adjust.
 832         * tic54x-opc.c: Likewise.
 833
 834 2016-05-19  Alan Modra  <amodra@gmail.com>
 835
 836         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 837
 838 2016-05-19  Alan Modra  <amodra@gmail.com>
 839
 840         * ppc-opc.c: Formatting.
 841         (NSISIGNOPT): Define.
 842         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 843
 844 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 845
 846         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 847         replacing references to `micromips_ase' throughout.
 848         (_print_insn_mips): Don't use file-level microMIPS annotation to
 849         determine the disassembly mode with the symbol table.
 850
 851 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 852
 853         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 854
 855 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 856
 857         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 858         mips64r6.
 859         * mips-opc.c (D34): New macro.
 860         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 861
 862 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 863
 864         * i386-dis.c (prefix_table): Add RDPID instruction.
 865         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 866         (cpu_flags): Add RDPID bitfield.
 867         * i386-opc.h (enum): Add RDPID element.
 868         (i386_cpu_flags): Add RDPID field.
 869         * i386-opc.tbl: Add RDPID instruction.
 870         * i386-init.h: Regenerate.
 871         * i386-tbl.h: Regenerate.
 872
 873 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 874
 875         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 876         branch type of a symbol.
 877         (print_insn): Likewise.
 878
 879 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 880
 881         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 882         Mainline Security Extensions instructions.
 883         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 884         Extensions instructions.
 885         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 886         instructions.
 887         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 888         special registers.
 889
 890 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 891
 892         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 893
 894 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 895
 896         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 897         (arcExtMap_genOpcode): Likewise.
 898         * arc-opc.c (arg_32bit_rc): Define new variable.
 899         (arg_32bit_u6): Likewise.
 900         (arg_32bit_limm): Likewise.
 901
 902 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 903
 904         * aarch64-gen.c (VERIFIER): Define.
 905         * aarch64-opc.c (VERIFIER): Define.
 906         (verify_ldpsw): Use static linkage.
 907         * aarch64-opc.h (verify_ldpsw): Remove.
 908         * aarch64-tbl.h: Use VERIFIER for verifiers.
 909
 910 2016-04-28  Nick Clifton  <nickc@redhat.com>
 911
 912         PR target/19722
 913         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 914         * aarch64-opc.c (verify_ldpsw): New function.
 915         * aarch64-opc.h (verify_ldpsw): New prototype.
 916         * aarch64-tbl.h: Add initialiser for verifier field.
 917         (LDPSW): Set verifier to verify_ldpsw.
 918
 919 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 920
 921         PR binutils/19983
 922         PR binutils/19984
 923         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 924         smaller than address size.
 925
 926 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 927
 928         * alpha-dis.c: Regenerate.
 929         * crx-dis.c: Likewise.
 930         * disassemble.c: Likewise.
 931         * epiphany-opc.c: Likewise.
 932         * fr30-opc.c: Likewise.
 933         * frv-opc.c: Likewise.
 934         * ip2k-opc.c: Likewise.
 935         * iq2000-opc.c: Likewise.
 936         * lm32-opc.c: Likewise.
 937         * lm32-opinst.c: Likewise.
 938         * m32c-opc.c: Likewise.
 939         * m32r-opc.c: Likewise.
 940         * m32r-opinst.c: Likewise.
 941         * mep-opc.c: Likewise.
 942         * mt-opc.c: Likewise.
 943         * or1k-opc.c: Likewise.
 944         * or1k-opinst.c: Likewise.
 945         * tic80-opc.c: Likewise.
 946         * xc16x-opc.c: Likewise.
 947         * xstormy16-opc.c: Likewise.
 948
 949 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 950
 951         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 952         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 953         calcsd, and calcxd instructions.
 954         * arc-opc.c (insert_nps_bitop_size): Delete.
 955         (extract_nps_bitop_size): Delete.
 956         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 957         (extract_nps_qcmp_m3): Define.
 958         (extract_nps_qcmp_m2): Define.
 959         (extract_nps_qcmp_m1): Define.
 960         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 961         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 962         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 963         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 964         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 965         NPS_QCMP_M3.
 966
 967 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 968
 969         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 970
 971 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 972
 973         * Makefile.in: Regenerated with automake 1.11.6.
 974         * aclocal.m4: Likewise.
 975
 976 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 977
 978         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 979         instructions.
 980         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 981         (extract_nps_cmem_uimm16): New function.
 982         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 983
 984 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 985
 986         * arc-dis.c (arc_insn_length): New function.
 987         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 988         (find_format): Change insnLen parameter to unsigned.
 989
 990 2016-04-13  Nick Clifton  <nickc@redhat.com>
 991
 992         PR target/19937
 993         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 994         the LD.B and LD.BU instructions.
 995
 996 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 997
 998         * arc-dis.c (find_format): Check for extension flags.
 999         (print_flags): New function.
1000         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1001         .extAuxRegister.
1002         * arc-ext.c (arcExtMap_coreRegName): Use
1003         LAST_EXTENSION_CORE_REGISTER.
1004         (arcExtMap_coreReadWrite): Likewise.
1005         (dump_ARC_extmap): Update printing.
1006         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1007         (arc_aux_regs): Add cpu field.
1008         * arc-regs.h: Add cpu field, lower case name aux registers.
1009
1010 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1011
1012         * arc-tbl.h: Add rtsc, sleep with no arguments.
1013
1014 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1015
1016         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1017         Initialize.
1018         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1019         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1020         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1021         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1022         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1023         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1024         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1025         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1026         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1027         (arc_opcode arc_opcodes): Null terminate the array.
1028         (arc_num_opcodes): Remove.
1029         * arc-ext.h (INSERT_XOP): Define.
1030         (extInstruction_t): Likewise.
1031         (arcExtMap_instName): Delete.
1032         (arcExtMap_insn): New function.
1033         (arcExtMap_genOpcode): Likewise.
1034         * arc-ext.c (ExtInstruction): Remove.
1035         (create_map): Zero initialize instruction fields.
1036         (arcExtMap_instName): Remove.
1037         (arcExtMap_insn): New function.
1038         (dump_ARC_extmap): More info while debuging.
1039         (arcExtMap_genOpcode): New function.
1040         * arc-dis.c (find_format): New function.
1041         (print_insn_arc): Use find_format.
1042         (arc_get_disassembler): Enable dump_ARC_extmap only when
1043         debugging.
1044
1045 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1046
1047         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1048         instruction bits out.
1049
1050 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1051
1052         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1053         * arc-opc.c (arc_flag_operands): Add new flags.
1054         (arc_flag_classes): Add new classes.
1055
1056 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1057
1058         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1059
1060 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1061
1062         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1063         encode1, rflt, crc16, and crc32 instructions.
1064         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1065         (arc_flag_classes): Add C_NPS_R.
1066         (insert_nps_bitop_size_2b): New function.
1067         (extract_nps_bitop_size_2b): Likewise.
1068         (insert_nps_bitop_uimm8): Likewise.
1069         (extract_nps_bitop_uimm8): Likewise.
1070         (arc_operands): Add new operand entries.
1071
1072 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1073
1074         * arc-regs.h: Add a new subclass field.  Add double assist
1075         accumulator register values.
1076         * arc-tbl.h: Use DPA subclass to mark the double assist
1077         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1078         * arc-opc.c (RSP): Define instead of SP.
1079         (arc_aux_regs): Add the subclass field.
1080
1081 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1082
1083         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1084
1085 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1086
1087         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1088         NPS_R_SRC1.
1089
1090 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1091
1092         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1093         issues.  No functional changes.
1094
1095 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1096
1097         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1098         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1099         (RTT): Remove duplicate.
1100         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1101         (PCT_CONFIG*): Remove.
1102         (D1L, D1H, D2H, D2L): Define.
1103
1104 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1105
1106         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1107
1108 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1109
1110         * arc-tbl.h (invld07): Remove.
1111         * arc-ext-tbl.h: New file.
1112         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1113         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1114
1115 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1116
1117         Fix -Wstack-usage warnings.
1118         * aarch64-dis.c (print_operands): Substitute size.
1119         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1120
1121 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1122
1123         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1124         to get a proper diagnostic when an invalid ASR register is used.
1125
1126 2016-03-22  Nick Clifton  <nickc@redhat.com>
1127
1128         * configure: Regenerate.
1129
1130 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1131
1132         * arc-nps400-tbl.h: New file.
1133         * arc-opc.c: Add top level comment.
1134         (insert_nps_3bit_dst): New function.
1135         (extract_nps_3bit_dst): New function.
1136         (insert_nps_3bit_src2): New function.
1137         (extract_nps_3bit_src2): New function.
1138         (insert_nps_bitop_size): New function.
1139         (extract_nps_bitop_size): New function.
1140         (arc_flag_operands): Add nps400 entries.
1141         (arc_flag_classes): Add nps400 entries.
1142         (arc_operands): Add nps400 entries.
1143         (arc_opcodes): Add nps400 include.
1144
1145 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1146
1147         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1148         the new class enum values.
1149
1150 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1151
1152         * arc-dis.c (print_insn_arc): Handle nps400.
1153
1154 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1155
1156         * arc-opc.c (BASE): Delete.
1157
1158 2016-03-18  Nick Clifton  <nickc@redhat.com>
1159
1160         PR target/19721
1161         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1162         of MOV insn that aliases an ORR insn.
1163
1164 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1165
1166         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1167
1168 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1169
1170         * mcore-opc.h: Add const qualifiers.
1171         * microblaze-opc.h (struct op_code_struct): Likewise.
1172         * sh-opc.h: Likewise.
1173         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1174         (tic4x_print_op): Likewise.
1175
1176 2016-03-02  Alan Modra  <amodra@gmail.com>
1177
1178         * or1k-desc.h: Regenerate.
1179         * fr30-ibld.c: Regenerate.
1180         * rl78-decode.c: Regenerate.
1181
1182 2016-03-01  Nick Clifton  <nickc@redhat.com>
1183
1184         PR target/19747
1185         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1186
1187 2016-02-24  Renlin Li  <renlin.li@arm.com>
1188
1189         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1190         (print_insn_coprocessor): Support fp16 instructions.
1191
1192 2016-02-24  Renlin Li  <renlin.li@arm.com>
1193
1194         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1195         vminnm, vrint(mpna).
1196
1197 2016-02-24  Renlin Li  <renlin.li@arm.com>
1198
1199         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1200         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1201
1202 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1203
1204         * i386-dis.c (print_insn): Parenthesize expression to prevent
1205         truncated addresses.
1206         (OP_J): Likewise.
1207
1208 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1209             Janek van Oirschot  <jvanoirs@synopsys.com>
1210
1211         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1212         variable.
1213
1214 2016-02-04  Nick Clifton  <nickc@redhat.com>
1215
1216         PR target/19561
1217         * msp430-dis.c (print_insn_msp430): Add a special case for
1218         decoding an RRC instruction with the ZC bit set in the extension
1219         word.
1220
1221 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1222
1223         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1224         * epiphany-ibld.c: Regenerate.
1225         * fr30-ibld.c: Regenerate.
1226         * frv-ibld.c: Regenerate.
1227         * ip2k-ibld.c: Regenerate.
1228         * iq2000-ibld.c: Regenerate.
1229         * lm32-ibld.c: Regenerate.
1230         * m32c-ibld.c: Regenerate.
1231         * m32r-ibld.c: Regenerate.
1232         * mep-ibld.c: Regenerate.
1233         * mt-ibld.c: Regenerate.
1234         * or1k-ibld.c: Regenerate.
1235         * xc16x-ibld.c: Regenerate.
1236         * xstormy16-ibld.c: Regenerate.
1237
1238 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1239
1240         * epiphany-dis.c: Regenerated from latest cpu files.
1241
1242 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1243
1244         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1245         test bit.
1246
1247 2016-01-25  Renlin Li  <renlin.li@arm.com>
1248
1249         * arm-dis.c (mapping_symbol_for_insn): New function.
1250         (find_ifthen_state): Call mapping_symbol_for_insn().
1251
1252 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1253
1254         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1255         of MSR UAO immediate operand.
1256
1257 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1258
1259         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1260         instruction support.
1261
1262 2016-01-17  Alan Modra  <amodra@gmail.com>
1263
1264         * configure: Regenerate.
1265
1266 2016-01-14  Nick Clifton  <nickc@redhat.com>
1267
1268         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1269         instructions that can support stack pointer operations.
1270         * rl78-decode.c: Regenerate.
1271         * rl78-dis.c: Fix display of stack pointer in MOVW based
1272         instructions.
1273
1274 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1275
1276         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1277         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1278         erxtatus_el1 and erxaddr_el1.
1279
1280 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1281
1282         * arm-dis.c (arm_opcodes): Add "esb".
1283         (thumb_opcodes): Likewise.
1284
1285 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1286
1287         * ppc-opc.c <xscmpnedp>: Delete.
1288         <xvcmpnedp>: Likewise.
1289         <xvcmpnedp.>: Likewise.
1290         <xvcmpnesp>: Likewise.
1291         <xvcmpnesp.>: Likewise.
1292
1293 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1294
1295         PR gas/13050
1296         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1297         addition to ISA_A.
1298
1299 2016-01-01  Alan Modra  <amodra@gmail.com>
1300
1301         Update year range in copyright notice of all files.
1302
1303 For older changes see ChangeLog-2015
1304 \f
1305 Copyright (C) 2016 Free Software Foundation, Inc.
1306
1307 Copying and distribution of this file, with or without modification,
1308 are permitted in any medium without royalty provided the copyright
1309 notice and this notice are preserved.
1310
1311 Local Variables:
1312 mode: change-log
1313 left-margin: 8
1314 fill-column: 74
1315 version-control: never
1316 End: