opcodes/ChangeLog

   1 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR gas/23670
   4         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
   5         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
   6         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
   7         (EVEX_LEN_0F7E_P_1): Likewise.
   8         (EVEX_LEN_0F7E_P_2): Likewise.
   9         (EVEX_LEN_0FD6_P_2): Likewise.
  10         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
  11         (EVEX_LEN_TABLE): Likewise.
  12         (EVEX_LEN_0F6E_P_2): New enum.
  13         (EVEX_LEN_0F7E_P_1): Likewise.
  14         (EVEX_LEN_0F7E_P_2): Likewise.
  15         (EVEX_LEN_0FD6_P_2): Likewise.
  16         (evex_len_table): New.
  17         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
  18         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
  19         * i386-tbl.h: Regenerated.
  20
  21 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         PR gas/23665
  24         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
  25         VEX_LEN_0F7E_P_2 entries.
  26         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
  27         * i386-tbl.h: Regenerated.
  28
  29 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
  30
  31         * i386-dis.c (VZERO_Fixup): Removed.
  32         (VZERO): Likewise.
  33         (VEX_LEN_0F10_P_1): Likewise.
  34         (VEX_LEN_0F10_P_3): Likewise.
  35         (VEX_LEN_0F11_P_1): Likewise.
  36         (VEX_LEN_0F11_P_3): Likewise.
  37         (VEX_LEN_0F2E_P_0): Likewise.
  38         (VEX_LEN_0F2E_P_2): Likewise.
  39         (VEX_LEN_0F2F_P_0): Likewise.
  40         (VEX_LEN_0F2F_P_2): Likewise.
  41         (VEX_LEN_0F51_P_1): Likewise.
  42         (VEX_LEN_0F51_P_3): Likewise.
  43         (VEX_LEN_0F52_P_1): Likewise.
  44         (VEX_LEN_0F53_P_1): Likewise.
  45         (VEX_LEN_0F58_P_1): Likewise.
  46         (VEX_LEN_0F58_P_3): Likewise.
  47         (VEX_LEN_0F59_P_1): Likewise.
  48         (VEX_LEN_0F59_P_3): Likewise.
  49         (VEX_LEN_0F5A_P_1): Likewise.
  50         (VEX_LEN_0F5A_P_3): Likewise.
  51         (VEX_LEN_0F5C_P_1): Likewise.
  52         (VEX_LEN_0F5C_P_3): Likewise.
  53         (VEX_LEN_0F5D_P_1): Likewise.
  54         (VEX_LEN_0F5D_P_3): Likewise.
  55         (VEX_LEN_0F5E_P_1): Likewise.
  56         (VEX_LEN_0F5E_P_3): Likewise.
  57         (VEX_LEN_0F5F_P_1): Likewise.
  58         (VEX_LEN_0F5F_P_3): Likewise.
  59         (VEX_LEN_0FC2_P_1): Likewise.
  60         (VEX_LEN_0FC2_P_3): Likewise.
  61         (VEX_LEN_0F3A0A_P_2): Likewise.
  62         (VEX_LEN_0F3A0B_P_2): Likewise.
  63         (VEX_W_0F10_P_0): Likewise.
  64         (VEX_W_0F10_P_1): Likewise.
  65         (VEX_W_0F10_P_2): Likewise.
  66         (VEX_W_0F10_P_3): Likewise.
  67         (VEX_W_0F11_P_0): Likewise.
  68         (VEX_W_0F11_P_1): Likewise.
  69         (VEX_W_0F11_P_2): Likewise.
  70         (VEX_W_0F11_P_3): Likewise.
  71         (VEX_W_0F12_P_0_M_0): Likewise.
  72         (VEX_W_0F12_P_0_M_1): Likewise.
  73         (VEX_W_0F12_P_1): Likewise.
  74         (VEX_W_0F12_P_2): Likewise.
  75         (VEX_W_0F12_P_3): Likewise.
  76         (VEX_W_0F13_M_0): Likewise.
  77         (VEX_W_0F14): Likewise.
  78         (VEX_W_0F15): Likewise.
  79         (VEX_W_0F16_P_0_M_0): Likewise.
  80         (VEX_W_0F16_P_0_M_1): Likewise.
  81         (VEX_W_0F16_P_1): Likewise.
  82         (VEX_W_0F16_P_2): Likewise.
  83         (VEX_W_0F17_M_0): Likewise.
  84         (VEX_W_0F28): Likewise.
  85         (VEX_W_0F29): Likewise.
  86         (VEX_W_0F2B_M_0): Likewise.
  87         (VEX_W_0F2E_P_0): Likewise.
  88         (VEX_W_0F2E_P_2): Likewise.
  89         (VEX_W_0F2F_P_0): Likewise.
  90         (VEX_W_0F2F_P_2): Likewise.
  91         (VEX_W_0F50_M_0): Likewise.
  92         (VEX_W_0F51_P_0): Likewise.
  93         (VEX_W_0F51_P_1): Likewise.
  94         (VEX_W_0F51_P_2): Likewise.
  95         (VEX_W_0F51_P_3): Likewise.
  96         (VEX_W_0F52_P_0): Likewise.
  97         (VEX_W_0F52_P_1): Likewise.
  98         (VEX_W_0F53_P_0): Likewise.
  99         (VEX_W_0F53_P_1): Likewise.
 100         (VEX_W_0F58_P_0): Likewise.
 101         (VEX_W_0F58_P_1): Likewise.
 102         (VEX_W_0F58_P_2): Likewise.
 103         (VEX_W_0F58_P_3): Likewise.
 104         (VEX_W_0F59_P_0): Likewise.
 105         (VEX_W_0F59_P_1): Likewise.
 106         (VEX_W_0F59_P_2): Likewise.
 107         (VEX_W_0F59_P_3): Likewise.
 108         (VEX_W_0F5A_P_0): Likewise.
 109         (VEX_W_0F5A_P_1): Likewise.
 110         (VEX_W_0F5A_P_3): Likewise.
 111         (VEX_W_0F5B_P_0): Likewise.
 112         (VEX_W_0F5B_P_1): Likewise.
 113         (VEX_W_0F5B_P_2): Likewise.
 114         (VEX_W_0F5C_P_0): Likewise.
 115         (VEX_W_0F5C_P_1): Likewise.
 116         (VEX_W_0F5C_P_2): Likewise.
 117         (VEX_W_0F5C_P_3): Likewise.
 118         (VEX_W_0F5D_P_0): Likewise.
 119         (VEX_W_0F5D_P_1): Likewise.
 120         (VEX_W_0F5D_P_2): Likewise.
 121         (VEX_W_0F5D_P_3): Likewise.
 122         (VEX_W_0F5E_P_0): Likewise.
 123         (VEX_W_0F5E_P_1): Likewise.
 124         (VEX_W_0F5E_P_2): Likewise.
 125         (VEX_W_0F5E_P_3): Likewise.
 126         (VEX_W_0F5F_P_0): Likewise.
 127         (VEX_W_0F5F_P_1): Likewise.
 128         (VEX_W_0F5F_P_2): Likewise.
 129         (VEX_W_0F5F_P_3): Likewise.
 130         (VEX_W_0F60_P_2): Likewise.
 131         (VEX_W_0F61_P_2): Likewise.
 132         (VEX_W_0F62_P_2): Likewise.
 133         (VEX_W_0F63_P_2): Likewise.
 134         (VEX_W_0F64_P_2): Likewise.
 135         (VEX_W_0F65_P_2): Likewise.
 136         (VEX_W_0F66_P_2): Likewise.
 137         (VEX_W_0F67_P_2): Likewise.
 138         (VEX_W_0F68_P_2): Likewise.
 139         (VEX_W_0F69_P_2): Likewise.
 140         (VEX_W_0F6A_P_2): Likewise.
 141         (VEX_W_0F6B_P_2): Likewise.
 142         (VEX_W_0F6C_P_2): Likewise.
 143         (VEX_W_0F6D_P_2): Likewise.
 144         (VEX_W_0F6F_P_1): Likewise.
 145         (VEX_W_0F6F_P_2): Likewise.
 146         (VEX_W_0F70_P_1): Likewise.
 147         (VEX_W_0F70_P_2): Likewise.
 148         (VEX_W_0F70_P_3): Likewise.
 149         (VEX_W_0F71_R_2_P_2): Likewise.
 150         (VEX_W_0F71_R_4_P_2): Likewise.
 151         (VEX_W_0F71_R_6_P_2): Likewise.
 152         (VEX_W_0F72_R_2_P_2): Likewise.
 153         (VEX_W_0F72_R_4_P_2): Likewise.
 154         (VEX_W_0F72_R_6_P_2): Likewise.
 155         (VEX_W_0F73_R_2_P_2): Likewise.
 156         (VEX_W_0F73_R_3_P_2): Likewise.
 157         (VEX_W_0F73_R_6_P_2): Likewise.
 158         (VEX_W_0F73_R_7_P_2): Likewise.
 159         (VEX_W_0F74_P_2): Likewise.
 160         (VEX_W_0F75_P_2): Likewise.
 161         (VEX_W_0F76_P_2): Likewise.
 162         (VEX_W_0F77_P_0): Likewise.
 163         (VEX_W_0F7C_P_2): Likewise.
 164         (VEX_W_0F7C_P_3): Likewise.
 165         (VEX_W_0F7D_P_2): Likewise.
 166         (VEX_W_0F7D_P_3): Likewise.
 167         (VEX_W_0F7E_P_1): Likewise.
 168         (VEX_W_0F7F_P_1): Likewise.
 169         (VEX_W_0F7F_P_2): Likewise.
 170         (VEX_W_0FAE_R_2_M_0): Likewise.
 171         (VEX_W_0FAE_R_3_M_0): Likewise.
 172         (VEX_W_0FC2_P_0): Likewise.
 173         (VEX_W_0FC2_P_1): Likewise.
 174         (VEX_W_0FC2_P_2): Likewise.
 175         (VEX_W_0FC2_P_3): Likewise.
 176         (VEX_W_0FD0_P_2): Likewise.
 177         (VEX_W_0FD0_P_3): Likewise.
 178         (VEX_W_0FD1_P_2): Likewise.
 179         (VEX_W_0FD2_P_2): Likewise.
 180         (VEX_W_0FD3_P_2): Likewise.
 181         (VEX_W_0FD4_P_2): Likewise.
 182         (VEX_W_0FD5_P_2): Likewise.
 183         (VEX_W_0FD6_P_2): Likewise.
 184         (VEX_W_0FD7_P_2_M_1): Likewise.
 185         (VEX_W_0FD8_P_2): Likewise.
 186         (VEX_W_0FD9_P_2): Likewise.
 187         (VEX_W_0FDA_P_2): Likewise.
 188         (VEX_W_0FDB_P_2): Likewise.
 189         (VEX_W_0FDC_P_2): Likewise.
 190         (VEX_W_0FDD_P_2): Likewise.
 191         (VEX_W_0FDE_P_2): Likewise.
 192         (VEX_W_0FDF_P_2): Likewise.
 193         (VEX_W_0FE0_P_2): Likewise.
 194         (VEX_W_0FE1_P_2): Likewise.
 195         (VEX_W_0FE2_P_2): Likewise.
 196         (VEX_W_0FE3_P_2): Likewise.
 197         (VEX_W_0FE4_P_2): Likewise.
 198         (VEX_W_0FE5_P_2): Likewise.
 199         (VEX_W_0FE6_P_1): Likewise.
 200         (VEX_W_0FE6_P_2): Likewise.
 201         (VEX_W_0FE6_P_3): Likewise.
 202         (VEX_W_0FE7_P_2_M_0): Likewise.
 203         (VEX_W_0FE8_P_2): Likewise.
 204         (VEX_W_0FE9_P_2): Likewise.
 205         (VEX_W_0FEA_P_2): Likewise.
 206         (VEX_W_0FEB_P_2): Likewise.
 207         (VEX_W_0FEC_P_2): Likewise.
 208         (VEX_W_0FED_P_2): Likewise.
 209         (VEX_W_0FEE_P_2): Likewise.
 210         (VEX_W_0FEF_P_2): Likewise.
 211         (VEX_W_0FF0_P_3_M_0): Likewise.
 212         (VEX_W_0FF1_P_2): Likewise.
 213         (VEX_W_0FF2_P_2): Likewise.
 214         (VEX_W_0FF3_P_2): Likewise.
 215         (VEX_W_0FF4_P_2): Likewise.
 216         (VEX_W_0FF5_P_2): Likewise.
 217         (VEX_W_0FF6_P_2): Likewise.
 218         (VEX_W_0FF7_P_2): Likewise.
 219         (VEX_W_0FF8_P_2): Likewise.
 220         (VEX_W_0FF9_P_2): Likewise.
 221         (VEX_W_0FFA_P_2): Likewise.
 222         (VEX_W_0FFB_P_2): Likewise.
 223         (VEX_W_0FFC_P_2): Likewise.
 224         (VEX_W_0FFD_P_2): Likewise.
 225         (VEX_W_0FFE_P_2): Likewise.
 226         (VEX_W_0F3800_P_2): Likewise.
 227         (VEX_W_0F3801_P_2): Likewise.
 228         (VEX_W_0F3802_P_2): Likewise.
 229         (VEX_W_0F3803_P_2): Likewise.
 230         (VEX_W_0F3804_P_2): Likewise.
 231         (VEX_W_0F3805_P_2): Likewise.
 232         (VEX_W_0F3806_P_2): Likewise.
 233         (VEX_W_0F3807_P_2): Likewise.
 234         (VEX_W_0F3808_P_2): Likewise.
 235         (VEX_W_0F3809_P_2): Likewise.
 236         (VEX_W_0F380A_P_2): Likewise.
 237         (VEX_W_0F380B_P_2): Likewise.
 238         (VEX_W_0F3817_P_2): Likewise.
 239         (VEX_W_0F381C_P_2): Likewise.
 240         (VEX_W_0F381D_P_2): Likewise.
 241         (VEX_W_0F381E_P_2): Likewise.
 242         (VEX_W_0F3820_P_2): Likewise.
 243         (VEX_W_0F3821_P_2): Likewise.
 244         (VEX_W_0F3822_P_2): Likewise.
 245         (VEX_W_0F3823_P_2): Likewise.
 246         (VEX_W_0F3824_P_2): Likewise.
 247         (VEX_W_0F3825_P_2): Likewise.
 248         (VEX_W_0F3828_P_2): Likewise.
 249         (VEX_W_0F3829_P_2): Likewise.
 250         (VEX_W_0F382A_P_2_M_0): Likewise.
 251         (VEX_W_0F382B_P_2): Likewise.
 252         (VEX_W_0F3830_P_2): Likewise.
 253         (VEX_W_0F3831_P_2): Likewise.
 254         (VEX_W_0F3832_P_2): Likewise.
 255         (VEX_W_0F3833_P_2): Likewise.
 256         (VEX_W_0F3834_P_2): Likewise.
 257         (VEX_W_0F3835_P_2): Likewise.
 258         (VEX_W_0F3837_P_2): Likewise.
 259         (VEX_W_0F3838_P_2): Likewise.
 260         (VEX_W_0F3839_P_2): Likewise.
 261         (VEX_W_0F383A_P_2): Likewise.
 262         (VEX_W_0F383B_P_2): Likewise.
 263         (VEX_W_0F383C_P_2): Likewise.
 264         (VEX_W_0F383D_P_2): Likewise.
 265         (VEX_W_0F383E_P_2): Likewise.
 266         (VEX_W_0F383F_P_2): Likewise.
 267         (VEX_W_0F3840_P_2): Likewise.
 268         (VEX_W_0F3841_P_2): Likewise.
 269         (VEX_W_0F38DB_P_2): Likewise.
 270         (VEX_W_0F3A08_P_2): Likewise.
 271         (VEX_W_0F3A09_P_2): Likewise.
 272         (VEX_W_0F3A0A_P_2): Likewise.
 273         (VEX_W_0F3A0B_P_2): Likewise.
 274         (VEX_W_0F3A0C_P_2): Likewise.
 275         (VEX_W_0F3A0D_P_2): Likewise.
 276         (VEX_W_0F3A0E_P_2): Likewise.
 277         (VEX_W_0F3A0F_P_2): Likewise.
 278         (VEX_W_0F3A21_P_2): Likewise.
 279         (VEX_W_0F3A40_P_2): Likewise.
 280         (VEX_W_0F3A41_P_2): Likewise.
 281         (VEX_W_0F3A42_P_2): Likewise.
 282         (VEX_W_0F3A62_P_2): Likewise.
 283         (VEX_W_0F3A63_P_2): Likewise.
 284         (VEX_W_0F3ADF_P_2): Likewise.
 285         (VEX_LEN_0F77_P_0): New.
 286         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 287         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 288         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 289         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 290         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 291         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 292         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 293         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 294         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 295         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 296         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 297         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 298         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 299         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 300         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 301         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 302         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 303         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 304         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 305         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 306         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 307         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 308         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 309         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 310         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 311         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 312         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 313         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 314         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 315         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 316         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 317         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 318         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 319         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 320         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 321         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 322         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 323         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 324         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 325         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 326         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 327         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 328         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 329         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 330         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 331         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 332         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 333         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 334         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 335         (vex_table): Update VEX 0F28 and 0F29 entries.
 336         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 337         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 338         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 339         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 340         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 341         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 342         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 343         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 344         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 345         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 346         VEX_LEN_0F3A0B_P_2 entries.
 347         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 348         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 349         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 350         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 351         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 352         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 353         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 354         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 355         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 356         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 357         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 358         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 359         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 360         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 361         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 362         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 363         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 364         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 365         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 366         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 367         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 368         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 369         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 370         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 371         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 372         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 373         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 374         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 375         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 376         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 377         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 378         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 379         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 380         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 381         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 382         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 383         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 384         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 385         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 386         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 387         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 388         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 389         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 390         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 391         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 392         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 393         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 394         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 395         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 396         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 397         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 398         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 399         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 400         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 401         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 402         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 403         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 404         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 405         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 406         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 407         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 408         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 409         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 410         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 411         VEX_W_0F3ADF_P_2 entries.
 412         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 413         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 414         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 415
 416 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 417
 418         * i386-opc.tbl (VexWIG): New.
 419         Replace VexW=3 with VexWIG.
 420
 421 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 422
 423         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 424         * i386-tbl.h: Regenerated.
 425
 426 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 427
 428         PR gas/23665
 429         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 430         VEX_LEN_0FD6_P_2 entries.
 431         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 432         * i386-tbl.h: Regenerated.
 433
 434 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 435
 436         PR gas/23642
 437         * i386-opc.h (VEXWIG): New.
 438         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 439         * i386-tbl.h: Regenerated.
 440
 441 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 442
 443         PR binutils/23655
 444         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 445         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 446         * i386-dis.c (EXxEVexR64): New.
 447         (evex_rounding_64_mode): Likewise.
 448         (OP_Rounding): Handle evex_rounding_64_mode.
 449
 450 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         PR binutils/23655
 453         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 454         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 455         * i386-dis.c (Edqa): New.
 456         (dqa_mode): Likewise.
 457         (intel_operand_size): Handle dqa_mode as m_mode.
 458         (OP_E_register): Handle dqa_mode as dq_mode.
 459         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 460
 461 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 462
 463         * i386-dis.c (OP_E_memory): Reformat.
 464
 465 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 466
 467         * i386-opc.tbl (crc32): Fold byte and word forms.
 468         * i386-tbl.h: Re-generate.
 469
 470 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 471
 472         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 473         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 474         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 475         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 476         * i386-tbl.h: Regenerated.
 477
 478 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 479
 480         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 481         meaningless.
 482         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 483         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 484         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 485         * i386-tbl.h: Re-generate.
 486
 487 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 488
 489         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 490         AVX512_4VNNIW insns.
 491         * i386-tbl.h: Re-generate.
 492
 493 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 494
 495         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 496         meaningless.
 497         * i386-tbl.h: Re-generate.
 498
 499 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 500
 501         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 502         meaningless.
 503         * i386-tbl.h: Re-generate.
 504
 505 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 506
 507         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 508         meaningless.
 509         * i386-tbl.h: Re-generate.
 510
 511 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 512
 513         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 514         meaningless.
 515         * i386-tbl.h: Re-generate.
 516
 517 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 520         meaningless.
 521         * i386-tbl.h: Re-generate.
 522
 523 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 524
 525         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 526         * i386-tbl.h: Re-generate.
 527
 528 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 529
 530         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 531         * i386-tbl.h: Re-generate.
 532
 533 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 534
 535         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 536         meaningless.
 537         * i386-tbl.h: Re-generate.
 538
 539 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 540
 541         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 542         meaningless.
 543         * i386-tbl.h: Re-generate.
 544
 545 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 546
 547         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 548         * i386-tbl.h: Re-generate.
 549
 550 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 551
 552         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 553         * i386-tbl.h: Re-generate.
 554
 555 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 556
 557         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 558         * i386-tbl.h: Re-generate.
 559
 560 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 561
 562         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 563         meaningless.
 564         * i386-tbl.h: Re-generate.
 565
 566 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 567
 568         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 569         meaningless.
 570         * i386-tbl.h: Re-generate.
 571
 572 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 573
 574         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 575         meaningless.
 576         * i386-tbl.h: Re-generate.
 577
 578 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 581         * i386-tbl.h: Re-generate.
 582
 583 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 584
 585         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 586         * i386-tbl.h: Re-generate.
 587
 588 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 589
 590         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 591         * i386-tbl.h: Re-generate.
 592
 593 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 594
 595         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 596         (vpbroadcastw, rdpid): Drop NoRex64.
 597         * i386-tbl.h: Re-generate.
 598
 599 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 600
 601         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 602         store templates, adding D.
 603         * i386-tbl.h: Re-generate.
 604
 605 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 606
 607         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 608         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 609         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 610         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 611         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 612         Fold load and store templates where possible, adding D. Drop
 613         IgnoreSize where it was pointlessly present. Drop redundant
 614         *word.
 615         * i386-tbl.h: Re-generate.
 616
 617 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 618
 619         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 620         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 621         (intel_operand_size): Handle v_bndmk_mode.
 622         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 623
 624 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 625
 626         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 627
 628 2018-08-31  Kito Cheng  <kito@andestech.com>
 629
 630         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 631         compressed floating point instructions.
 632
 633 2018-08-30  Kito Cheng  <kito@andestech.com>
 634
 635         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 636         riscv_opcode.xlen_requirement.
 637         * riscv-opc.c (riscv_opcodes): Update for struct change.
 638
 639 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 640
 641         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 642         psr (PWRPSR) instruction.
 643
 644 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 645
 646         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 647
 648 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 649
 650         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 651
 652 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 653
 654         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 655         loongson3a as an alias of gs464 for compatibility.
 656         * mips-opc.c (mips_opcodes): Change Comments.
 657
 658 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 659
 660         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 661         option.
 662         (print_mips_disassembler_options): Document -M loongson-ext.
 663         * mips-opc.c (LEXT2): New macro.
 664         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 665
 666 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 667
 668          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 669          descriptors.
 670          (parse_mips_ase_option): Handle -M loongson-ext option.
 671          (print_mips_disassembler_options): Document -M loongson-ext.
 672          * mips-opc.c (IL3A): Delete.
 673          * mips-opc.c (LEXT): New macro.
 674          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 675          instructions.
 676
 677 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 678
 679         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 680         descriptors.
 681         (parse_mips_ase_option): Handle -M loongson-cam option.
 682         (print_mips_disassembler_options): Document -M loongson-cam.
 683         * mips-opc.c (LCAM): New macro.
 684         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 685         instructions.
 686
 687 2018-08-21  Alan Modra  <amodra@gmail.com>
 688
 689         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 690         (skip_optional_operands): Count optional operands, and update
 691         ppc_optional_operand_value call.
 692         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 693         (extract_vlensi): Likewise.
 694         (extract_fxm): Return default value for missing optional operand.
 695         (extract_ls, extract_raq, extract_tbr): Likewise.
 696         (insert_sxl, extract_sxl): New functions.
 697         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 698         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 699         flag and extra entry.
 700         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 701         extract_sxl.
 702
 703 2018-08-20  Alan Modra  <amodra@gmail.com>
 704
 705         * sh-opc.h (MASK): Simplify.
 706
 707 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 708
 709         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 710         BM_RESERVED0 or BM_RESERVED1
 711         (bm_rel_decode, bm_n_bytes): Ditto.
 712
 713 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 714
 715         * s12z.h: Delete.
 716
 717 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 718
 719         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 720         address with the addr32 prefix and without base nor index
 721         registers.
 722
 723 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 724
 725         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 726         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 727         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 728         (cpu_flags): Add CpuCMOV and CpuFXSR.
 729         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 730         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 731         * i386-init.h: Regenerated.
 732         * i386-tbl.h: Likewise.
 733
 734 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 735
 736         * arc-regs.h: Update auxiliary registers.
 737
 738 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 739
 740         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 741         (RegIP, RegIZ): Define.
 742         * i386-reg.tbl: Adjust comments.
 743         (rip): Use Qword instead of BaseIndex. Use RegIP.
 744         (eip): Use Dword instead of BaseIndex. Use RegIP.
 745         (riz): Add Qword. Use RegIZ.
 746         (eiz): Add Dword. Use RegIZ.
 747         * i386-tbl.h: Re-generate.
 748
 749 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 750
 751         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 752         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 753         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 754         * i386-tbl.h: Re-generate.
 755
 756 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 757
 758         * i386-gen.c (operand_types): Remove Mem field.
 759         * i386-opc.h (union i386_operand_type): Remove mem field.
 760         * i386-init.h, i386-tbl.h: Re-generate.
 761
 762 2018-08-01  Alan Modra  <amodra@gmail.com>
 763
 764         * po/POTFILES.in: Regenerate.
 765
 766 2018-07-31  Nick Clifton  <nickc@redhat.com>
 767
 768         * po/sv.po: Updated Swedish translation.
 769
 770 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 771
 772         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 773         * i386-init.h, i386-tbl.h: Re-generate.
 774
 775 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 776
 777         * i386-opc.h (ZEROING_MASKING) Rename to ...
 778         (DYNAMIC_MASKING): ... this. Adjust comment.
 779         * i386-opc.tbl (MaskingMorZ): Define.
 780         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 781         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 782         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 783         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 784         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 785         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 786         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 787         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 788         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 789
 790 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 791
 792         * i386-opc.tbl: Use element rather than vector size for AVX512*
 793         scatter/gather insns.
 794         * i386-tbl.h: Re-generate.
 795
 796 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 797
 798         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 799         (cpu_flags): Drop CpuVREX.
 800         * i386-opc.h (CpuVREX): Delete.
 801         (union i386_cpu_flags): Remove cpuvrex.
 802         * i386-init.h, i386-tbl.h: Re-generate.
 803
 804 2018-07-30  Jim Wilson  <jimw@sifive.com>
 805
 806         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 807         fields.
 808         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 809
 810 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 811
 812         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 813         * Makefile.in: Regenerated.
 814         * configure.ac: Add C-SKY.
 815         * configure: Regenerated.
 816         * csky-dis.c: New file.
 817         * csky-opc.h: New file.
 818         * disassemble.c (ARCH_csky): Define.
 819         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 820         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 821
 822 2018-07-27  Alan Modra  <amodra@gmail.com>
 823
 824         * ppc-opc.c (insert_sprbat): Correct function parameter and
 825         return type.
 826         (extract_sprbat): Likewise, variable too.
 827
 828 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 829             Alan Modra  <amodra@gmail.com>
 830
 831         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 832         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 833         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 834         support disjointed BAT.
 835         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 836         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 837         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 838
 839 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 840             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 841
 842         * i386-gen.c (adjust_broadcast_modifier): New function.
 843         (process_i386_opcode_modifier): Add an argument for operands.
 844         Adjust the Broadcast value based on operands.
 845         (output_i386_opcode): Pass operand_types to
 846         process_i386_opcode_modifier.
 847         (process_i386_opcodes): Pass NULL as operands to
 848         process_i386_opcode_modifier.
 849         * i386-opc.h (BYTE_BROADCAST): New.
 850         (WORD_BROADCAST): Likewise.
 851         (DWORD_BROADCAST): Likewise.
 852         (QWORD_BROADCAST): Likewise.
 853         (i386_opcode_modifier): Expand broadcast to 3 bits.
 854         * i386-tbl.h: Regenerated.
 855
 856 2018-07-24  Alan Modra  <amodra@gmail.com>
 857
 858         PR 23430
 859         * or1k-desc.h: Regenerate.
 860
 861 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 864         vcvtusi2ss, and vcvtusi2sd.
 865         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 866         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 867         * i386-tbl.h: Re-generate.
 868
 869 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 870
 871         * arc-opc.c (extract_w6): Fix extending the sign.
 872
 873 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 874
 875         * arc-tbl.h (vewt): Allow it for ARC EM family.
 876
 877 2018-07-23  Alan Modra  <amodra@gmail.com>
 878
 879         PR 23419
 880         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 881         opcode variants for mtspr/mfspr encodings.
 882
 883 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 884             Maciej W. Rozycki  <macro@mips.com>
 885
 886         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 887         loongson3a descriptors.
 888         (parse_mips_ase_option): Handle -M loongson-mmi option.
 889         (print_mips_disassembler_options): Document -M loongson-mmi.
 890         * mips-opc.c (LMMI): New macro.
 891         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 892         instructions.
 893
 894 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 895
 896         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 897         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 898         IgnoreSize and [XYZ]MMword where applicable.
 899         * i386-tbl.h: Re-generate.
 900
 901 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 902
 903         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 904         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 905         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 906         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 907         * i386-tbl.h: Re-generate.
 908
 909 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 910
 911         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 912         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 913         VPCLMULQDQ templates into their respective AVX512VL counterparts
 914         where possible, using Disp8ShiftVL and CheckRegSize instead of
 915         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 916         * i386-tbl.h: Re-generate.
 917
 918 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 919
 920         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 921         AVX512VL counterparts where possible, using Disp8ShiftVL and
 922         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 923         IgnoreSize) as appropriate.
 924         * i386-tbl.h: Re-generate.
 925
 926 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 927
 928         * i386-opc.tbl: Fold AVX512BW templates into their respective
 929         AVX512VL counterparts where possible, using Disp8ShiftVL and
 930         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 931         IgnoreSize) as appropriate.
 932         * i386-tbl.h: Re-generate.
 933
 934 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-opc.tbl: Fold AVX512CD templates into their respective
 937         AVX512VL counterparts where possible, using Disp8ShiftVL and
 938         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 939         IgnoreSize) as appropriate.
 940         * i386-tbl.h: Re-generate.
 941
 942 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 943
 944         * i386-opc.h (DISP8_SHIFT_VL): New.
 945         * i386-opc.tbl (Disp8ShiftVL):  Define.
 946         (various): Fold AVX512VL templates into their respective
 947         AVX512F counterparts where possible, using Disp8ShiftVL and
 948         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 949         IgnoreSize) as appropriate.
 950         * i386-tbl.h: Re-generate.
 951
 952 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 953
 954         * Makefile.am: Change dependencies and rule for
 955         $(srcdir)/i386-init.h.
 956         * Makefile.in: Re-generate.
 957         * i386-gen.c (process_i386_opcodes): New local variable
 958         "marker". Drop opening of input file. Recognize marker and line
 959         number directives.
 960         * i386-opc.tbl (OPCODE_I386_H): Define.
 961         (i386-opc.h): Include it.
 962         (None): Undefine.
 963
 964 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 965
 966         PR gas/23418
 967         * i386-opc.h (Byte): Update comments.
 968         (Word): Likewise.
 969         (Dword): Likewise.
 970         (Fword): Likewise.
 971         (Qword): Likewise.
 972         (Tbyte): Likewise.
 973         (Xmmword): Likewise.
 974         (Ymmword): Likewise.
 975         (Zmmword): Likewise.
 976         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 977         vcvttps2uqq.
 978         * i386-tbl.h: Regenerated.
 979
 980 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 981
 982         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 983         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 984         * aarch64-asm-2.c: Regenerate.
 985         * aarch64-dis-2.c: Regenerate.
 986         * aarch64-opc-2.c: Regenerate.
 987
 988 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 989
 990         PR binutils/23192
 991         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 992         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 993         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 994         sqdmulh, sqrdmulh): Use Em16.
 995
 996 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 997
 998         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 999         csdb together with them.
1000         (thumb32_opcodes): Likewise.
1001
1002 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1003
1004         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1005         requiring 32-bit registers as operands 2 and 3. Improve
1006         comments.
1007         (mwait, mwaitx): Fold templates. Improve comments.
1008         OPERAND_TYPE_INOUTPORTREG.
1009         * i386-tbl.h: Re-generate.
1010
1011 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1012
1013         * i386-gen.c (operand_type_init): Remove
1014         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1015         OPERAND_TYPE_INOUTPORTREG.
1016         * i386-init.h: Re-generate.
1017
1018 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1019
1020         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1021         (wrssq, wrussq): Add Qword.
1022         * i386-tbl.h: Re-generate.
1023
1024 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1025
1026         * i386-opc.h: Rename OTMax to OTNum.
1027         (OTNumOfUints): Adjust calculation.
1028         (OTUnused): Directly alias to OTNum.
1029
1030 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1031
1032         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1033         `reg_xys'.
1034         (lea_reg_xys): Likewise.
1035         (print_insn_loop_primitive): Rename `reg' local variable to
1036         `reg_dxy'.
1037
1038 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1039
1040         PR binutils/23242
1041         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1042
1043 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1044
1045         PR binutils/23369
1046         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1047         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1048
1049 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1050
1051         PR tdep/8282
1052         * mips-dis.c (mips_option_arg_t): New enumeration.
1053         (mips_options): New variable.
1054         (disassembler_options_mips): New function.
1055         (print_mips_disassembler_options): Reimplement in terms of
1056         `disassembler_options_mips'.
1057         * arm-dis.c (disassembler_options_arm): Adapt to using the
1058         `disasm_options_and_args_t' structure.
1059         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1060         * s390-dis.c (disassembler_options_s390): Likewise.
1061
1062 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1063
1064         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1065         expected result.
1066         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1067         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1068         * testsuite/ld-arm/tls-longplt.d: Likewise.
1069
1070 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1071
1072         PR binutils/23192
1073         * aarch64-asm-2.c: Regenerate.
1074         * aarch64-dis-2.c: Likewise.
1075         * aarch64-opc-2.c: Likewise.
1076         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1077         * aarch64-opc.c (operand_general_constraint_met_p,
1078         aarch64_print_operand): Likewise.
1079         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1080         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1081         fmlal2, fmlsl2.
1082         (AARCH64_OPERANDS): Add Em2.
1083
1084 2018-06-26  Nick Clifton  <nickc@redhat.com>
1085
1086         * po/uk.po: Updated Ukranian translation.
1087         * po/de.po: Updated German translation.
1088         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1089
1090 2018-06-26  Nick Clifton  <nickc@redhat.com>
1091
1092         * nfp-dis.c: Fix spelling mistake.
1093
1094 2018-06-24  Nick Clifton  <nickc@redhat.com>
1095
1096         * configure: Regenerate.
1097         * po/opcodes.pot: Regenerate.
1098
1099 2018-06-24  Nick Clifton  <nickc@redhat.com>
1100
1101         2.31 branch created.
1102
1103 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1104
1105         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1106         * aarch64-asm-2.c: Regenerate.
1107         * aarch64-dis-2.c: Likewise.
1108
1109 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1110
1111         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1112         `-M ginv' option description.
1113
1114 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1115
1116         PR gas/23305
1117         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1118         la and lla.
1119
1120 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1121
1122         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1123         * configure.ac: Remove AC_PREREQ.
1124         * Makefile.in: Re-generate.
1125         * aclocal.m4: Re-generate.
1126         * configure: Re-generate.
1127
1128 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1129
1130         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1131         mips64r6 descriptors.
1132         (parse_mips_ase_option): Handle -Mginv option.
1133         (print_mips_disassembler_options): Document -Mginv.
1134         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1135         (GINV): New macro.
1136         (mips_opcodes): Define ginvi and ginvt.
1137
1138 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1139             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1140
1141         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1142         * mips-opc.c (CRC, CRC64): New macros.
1143         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1144         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1145         crc32cd for CRC64.
1146
1147 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1148
1149         PR 20319
1150         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1151         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1152
1153 2018-06-06  Alan Modra  <amodra@gmail.com>
1154
1155         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1156         setjmp.  Move init for some other vars later too.
1157
1158 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1159
1160         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1161         (dis_private): Add new fields for property section tracking.
1162         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1163         (xtensa_instruction_fits): New functions.
1164         (fetch_data): Bump minimal fetch size to 4.
1165         (print_insn_xtensa): Make struct dis_private static.
1166         Load and prepare property table on section change.
1167         Don't disassemble literals. Don't disassemble instructions that
1168         cross property table boundaries.
1169
1170 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1171
1172         * configure: Regenerated.
1173
1174 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1175
1176         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1177         * i386-tbl.h: Re-generate.
1178
1179 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1180
1181         * i386-opc.tbl (sldt, str): Add NoRex64.
1182         * i386-tbl.h: Re-generate.
1183
1184 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1185
1186         * i386-opc.tbl (invpcid): Add Oword.
1187         * i386-tbl.h: Re-generate.
1188
1189 2018-06-01  Alan Modra  <amodra@gmail.com>
1190
1191         * sysdep.h (_bfd_error_handler): Don't declare.
1192         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1193         * rl78-decode.opc: Likewise.
1194         * msp430-decode.c: Regenerate.
1195         * rl78-decode.c: Regenerate.
1196
1197 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1198
1199         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1200         * i386-init.h : Regenerated.
1201
1202 2018-05-25  Alan Modra  <amodra@gmail.com>
1203
1204         * Makefile.in: Regenerate.
1205         * po/POTFILES.in: Regenerate.
1206
1207 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1208
1209         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1210         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1211         (insert_bab, extract_bab, insert_btab, extract_btab,
1212         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1213         (BAT, BBA VBA RBS XB6S): Delete macros.
1214         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1215         (BB, BD, RBX, XC6): Update for new macros.
1216         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1217         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1218         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1219         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1220
1221 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1222
1223         * Makefile.am: Add support for s12z architecture.
1224         * configure.ac: Likewise.
1225         * disassemble.c: Likewise.
1226         * disassemble.h: Likewise.
1227         * Makefile.in: Regenerate.
1228         * configure: Regenerate.
1229         * s12z-dis.c: New file.
1230         * s12z.h: New file.
1231
1232 2018-05-18  Alan Modra  <amodra@gmail.com>
1233
1234         * nfp-dis.c: Don't #include libbfd.h.
1235         (init_nfp3200_priv): Use bfd_get_section_contents.
1236         (nit_nfp6000_mecsr_sec): Likewise.
1237
1238 2018-05-17  Nick Clifton  <nickc@redhat.com>
1239
1240         * po/zh_CN.po: Updated simplified Chinese translation.
1241
1242 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1243
1244         PR binutils/23109
1245         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1246         * aarch64-dis-2.c: Regenerate.
1247
1248 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1249
1250         PR binutils/21446
1251         * aarch64-asm.c (opintl.h): Include.
1252         (aarch64_ins_sysreg): Enforce read/write constraints.
1253         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1254         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1255         (F_REG_READ, F_REG_WRITE): New.
1256         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1257         AARCH64_OPND_SYSREG.
1258         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1259         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1260         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1261         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1262         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1263         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1264         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1265         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1266         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1267         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1268         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1269         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1270         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1271         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1272         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1273         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1274         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1275
1276 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1277
1278         PR binutils/21446
1279         * aarch64-dis.c (no_notes: New.
1280         (parse_aarch64_dis_option): Support notes.
1281         (aarch64_decode_insn, print_operands): Likewise.
1282         (print_aarch64_disassembler_options): Document notes.
1283         * aarch64-opc.c (aarch64_print_operand): Support notes.
1284
1285 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1286
1287         PR binutils/21446
1288         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1289         and take error struct.
1290         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1291         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1292         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1293         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1294         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1295         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1296         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1297         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1298         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1299         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1300         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1301         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1302         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1303         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1304         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1305         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1306         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1307         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1308         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1309         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1310         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1311         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1312         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1313         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1314         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1315         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1316         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1317         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1318         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1319         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1320         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1321         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1322         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1323         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1324         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1325         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1326         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1327         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1328         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1329         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1330         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1331         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1332         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1333         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1334         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1335         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1336         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1337         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1338         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1339         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1340         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1341         (determine_disassembling_preference, aarch64_decode_insn,
1342         print_insn_aarch64_word, print_insn_data): Take errors struct.
1343         (print_insn_aarch64): Use errors.
1344         * aarch64-asm-2.c: Regenerate.
1345         * aarch64-dis-2.c: Regenerate.
1346         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1347         boolean in aarch64_insert_operan.
1348         (print_operand_extractor): Likewise.
1349         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1350
1351 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1352
1353         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1354
1355 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1356
1357         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1358
1359 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1360
1361         * cr16-opc.c (cr16_instruction): Comment typo fix.
1362         * hppa-dis.c (print_insn_hppa): Likewise.
1363
1364 2018-05-08  Jim Wilson  <jimw@sifive.com>
1365
1366         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1367         (match_c_slli64, match_srxi_as_c_srxi): New.
1368         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1369         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1370         <c.slli, c.srli, c.srai>: Use match_s_slli.
1371         <c.slli64, c.srli64, c.srai64>: New.
1372
1373 2018-05-08  Alan Modra  <amodra@gmail.com>
1374
1375         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1376         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1377         partition opcode space for index lookup.
1378
1379 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1380
1381         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1382         <insn_length>: ...with this.  Update usage.
1383         Remove duplicate call to *info->memory_error_func.
1384
1385 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1386             H.J. Lu  <hongjiu.lu@intel.com>
1387
1388         * i386-dis.c (Gva): New.
1389         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1390         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1391         (prefix_table): New instructions (see prefix above).
1392         (mod_table): New instructions (see prefix above).
1393         (OP_G): Handle va_mode.
1394         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1395         CPU_MOVDIR64B_FLAGS.
1396         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1397         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1398         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1399         * i386-opc.tbl: Add movidir{i,64b}.
1400         * i386-init.h: Regenerated.
1401         * i386-tbl.h: Likewise.
1402
1403 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1404
1405         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1406         AddrPrefixOpReg.
1407         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1408         (AddrPrefixOpReg): This.
1409         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1410         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1411
1412 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1413
1414         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1415         (vle_num_opcodes): Likewise.
1416         (spe2_num_opcodes): Likewise.
1417         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1418         initialization loop.
1419         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1420         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1421         only once.
1422
1423 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1424
1425         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1426
1427 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1428
1429         Makefile.am: Added nfp-dis.c.
1430         configure.ac: Added bfd_nfp_arch.
1431         disassemble.h: Added print_insn_nfp prototype.
1432         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1433         nfp-dis.c: New, for NFP support.
1434         po/POTFILES.in: Added nfp-dis.c to the list.
1435         Makefile.in: Regenerate.
1436         configure: Regenerate.
1437
1438 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1439
1440         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1441         templates into their base ones.
1442         * i386-tlb.h: Re-generate.
1443
1444 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1445
1446         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1447         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1448         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1449         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1450         * i386-init.h: Re-generate.
1451
1452 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1453
1454         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1455         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1456         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1457         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1458         comment.
1459         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1460         and CpuRegMask.
1461         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1462         CpuRegMask: Delete.
1463         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1464         cpuregzmm, and cpuregmask.
1465         * i386-init.h: Re-generate.
1466         * i386-tbl.h: Re-generate.
1467
1468 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1469
1470         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1471         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1472         * i386-init.h: Re-generate.
1473
1474 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1475
1476         * i386-gen.c (VexImmExt): Delete.
1477         * i386-opc.h (VexImmExt, veximmext): Delete.
1478         * i386-opc.tbl: Drop all VexImmExt uses.
1479         * i386-tlb.h: Re-generate.
1480
1481 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1482
1483         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1484         register-only forms.
1485         * i386-tlb.h: Re-generate.
1486
1487 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1488
1489         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1490
1491 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1492
1493         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1494         PREFIX_0F1C.
1495         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1496         (cpu_flags): Add CpuCLDEMOTE.
1497         * i386-init.h: Regenerate.
1498         * i386-opc.h (enum): Add CpuCLDEMOTE,
1499         (i386_cpu_flags): Add cpucldemote.
1500         * i386-opc.tbl: Add cldemote.
1501         * i386-tbl.h: Regenerate.
1502
1503 2018-04-16  Alan Modra  <amodra@gmail.com>
1504
1505         * Makefile.am: Remove sh5 and sh64 support.
1506         * configure.ac: Likewise.
1507         * disassemble.c: Likewise.
1508         * disassemble.h: Likewise.
1509         * sh-dis.c: Likewise.
1510         * sh64-dis.c: Delete.
1511         * sh64-opc.c: Delete.
1512         * sh64-opc.h: Delete.
1513         * Makefile.in: Regenerate.
1514         * configure: Regenerate.
1515         * po/POTFILES.in: Regenerate.
1516
1517 2018-04-16  Alan Modra  <amodra@gmail.com>
1518
1519         * Makefile.am: Remove w65 support.
1520         * configure.ac: Likewise.
1521         * disassemble.c: Likewise.
1522         * disassemble.h: Likewise.
1523         * w65-dis.c: Delete.
1524         * w65-opc.h: Delete.
1525         * Makefile.in: Regenerate.
1526         * configure: Regenerate.
1527         * po/POTFILES.in: Regenerate.
1528
1529 2018-04-16  Alan Modra  <amodra@gmail.com>
1530
1531         * configure.ac: Remove we32k support.
1532         * configure: Regenerate.
1533
1534 2018-04-16  Alan Modra  <amodra@gmail.com>
1535
1536         * Makefile.am: Remove m88k support.
1537         * configure.ac: Likewise.
1538         * disassemble.c: Likewise.
1539         * disassemble.h: Likewise.
1540         * m88k-dis.c: Delete.
1541         * Makefile.in: Regenerate.
1542         * configure: Regenerate.
1543         * po/POTFILES.in: Regenerate.
1544
1545 2018-04-16  Alan Modra  <amodra@gmail.com>
1546
1547         * Makefile.am: Remove i370 support.
1548         * configure.ac: Likewise.
1549         * disassemble.c: Likewise.
1550         * disassemble.h: Likewise.
1551         * i370-dis.c: Delete.
1552         * i370-opc.c: Delete.
1553         * Makefile.in: Regenerate.
1554         * configure: Regenerate.
1555         * po/POTFILES.in: Regenerate.
1556
1557 2018-04-16  Alan Modra  <amodra@gmail.com>
1558
1559         * Makefile.am: Remove h8500 support.
1560         * configure.ac: Likewise.
1561         * disassemble.c: Likewise.
1562         * disassemble.h: Likewise.
1563         * h8500-dis.c: Delete.
1564         * h8500-opc.h: Delete.
1565         * Makefile.in: Regenerate.
1566         * configure: Regenerate.
1567         * po/POTFILES.in: Regenerate.
1568
1569 2018-04-16  Alan Modra  <amodra@gmail.com>
1570
1571         * configure.ac: Remove tahoe support.
1572         * configure: Regenerate.
1573
1574 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1575
1576         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1577         umwait.
1578         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1579         64-bit mode.
1580         * i386-tbl.h: Regenerated.
1581
1582 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1583
1584         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1585         PREFIX_MOD_1_0FAE_REG_6.
1586         (va_mode): New.
1587         (OP_E_register): Use va_mode.
1588         * i386-dis-evex.h (prefix_table):
1589         New instructions (see prefixes above).
1590         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1591         (cpu_flags): Likewise.
1592         * i386-opc.h (enum): Likewise.
1593         (i386_cpu_flags): Likewise.
1594         * i386-opc.tbl: Add umonitor, umwait, tpause.
1595         * i386-init.h: Regenerate.
1596         * i386-tbl.h: Likewise.
1597
1598 2018-04-11  Alan Modra  <amodra@gmail.com>
1599
1600         * opcodes/i860-dis.c: Delete.
1601         * opcodes/i960-dis.c: Delete.
1602         * Makefile.am: Remove i860 and i960 support.
1603         * configure.ac: Likewise.
1604         * disassemble.c: Likewise.
1605         * disassemble.h: Likewise.
1606         * Makefile.in: Regenerate.
1607         * configure: Regenerate.
1608         * po/POTFILES.in: Regenerate.
1609
1610 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1611
1612         PR binutils/23025
1613         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1614         to 0.
1615         (print_insn): Clear vex instead of vex.evex.
1616
1617 2018-04-04  Nick Clifton  <nickc@redhat.com>
1618
1619         * po/es.po: Updated Spanish translation.
1620
1621 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1622
1623         * i386-gen.c (opcode_modifiers): Delete VecESize.
1624         * i386-opc.h (VecESize): Delete.
1625         (struct i386_opcode_modifier): Delete vecesize.
1626         * i386-opc.tbl: Drop VecESize.
1627         * i386-tlb.h: Re-generate.
1628
1629 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1630
1631         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1632         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1633         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1634         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1635         * i386-tlb.h: Re-generate.
1636
1637 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1638
1639         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1640         Fold AVX512 forms
1641         * i386-tlb.h: Re-generate.
1642
1643 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1644
1645         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1646         (vex_len_table): Drop Y for vcvt*2si.
1647         (putop): Replace plain 'Y' handling by abort().
1648
1649 2018-03-28  Nick Clifton  <nickc@redhat.com>
1650
1651         PR 22988
1652         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1653         instructions with only a base address register.
1654         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1655         handle AARHC64_OPND_SVE_ADDR_R.
1656         (aarch64_print_operand): Likewise.
1657         * aarch64-asm-2.c: Regenerate.
1658         * aarch64_dis-2.c: Regenerate.
1659         * aarch64-opc-2.c: Regenerate.
1660
1661 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1662
1663         * i386-opc.tbl: Drop VecESize from register only insn forms and
1664         memory forms not allowing broadcast.
1665         * i386-tlb.h: Re-generate.
1666
1667 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1668
1669         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1670         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1671         sha256*): Drop Disp<N>.
1672
1673 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1674
1675         * i386-dis.c (EbndS, bnd_swap_mode): New.
1676         (prefix_table): Use EbndS.
1677         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1678         * i386-opc.tbl (bndmov): Move misplaced Load.
1679         * i386-tlb.h: Re-generate.
1680
1681 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1682
1683         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1684         templates allowing memory operands and folded ones for register
1685         only flavors.
1686         * i386-tlb.h: Re-generate.
1687
1688 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1689
1690         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1691         256-bit templates. Drop redundant leftover Disp<N>.
1692         * i386-tlb.h: Re-generate.
1693
1694 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1695
1696         * riscv-opc.c (riscv_insn_types): New.
1697
1698 2018-03-13  Nick Clifton  <nickc@redhat.com>
1699
1700         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1701
1702 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1703
1704         * i386-opc.tbl: Add Optimize to clr.
1705         * i386-tbl.h: Regenerated.
1706
1707 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1708
1709         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1710         * i386-opc.h (OldGcc): Removed.
1711         (i386_opcode_modifier): Remove oldgcc.
1712         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1713         instructions for old (<= 2.8.1) versions of gcc.
1714         * i386-tbl.h: Regenerated.
1715
1716 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1717
1718         * i386-opc.h (EVEXDYN): New.
1719         * i386-opc.tbl: Fold various AVX512VL templates.
1720         * i386-tlb.h: Re-generate.
1721
1722 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1723
1724         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1725         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1726         vpexpandd, vpexpandq): Fold AFX512VF templates.
1727         * i386-tlb.h: Re-generate.
1728
1729 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1730
1731         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1732         Fold 128- and 256-bit VEX-encoded templates.
1733         * i386-tlb.h: Re-generate.
1734
1735 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1736
1737         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1738         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1739         vpexpandd, vpexpandq): Fold AVX512F templates.
1740         * i386-tlb.h: Re-generate.
1741
1742 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1743
1744         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1745         64-bit templates. Drop Disp<N>.
1746         * i386-tlb.h: Re-generate.
1747
1748 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1749
1750         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1751         and 256-bit templates.
1752         * i386-tlb.h: Re-generate.
1753
1754 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1755
1756         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1757         * i386-tlb.h: Re-generate.
1758
1759 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1760
1761         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1762         Drop NoAVX.
1763         * i386-tlb.h: Re-generate.
1764
1765 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1766
1767         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1768         * i386-tlb.h: Re-generate.
1769
1770 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1771
1772         * i386-gen.c (opcode_modifiers): Delete FloatD.
1773         * i386-opc.h (FloatD): Delete.
1774         (struct i386_opcode_modifier): Delete floatd.
1775         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1776         FloatD by D.
1777         * i386-tlb.h: Re-generate.
1778
1779 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1780
1781         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1782
1783 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1784
1785         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1786         * i386-tlb.h: Re-generate.
1787
1788 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1789
1790         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1791         forms.
1792         * i386-tlb.h: Re-generate.
1793
1794 2018-03-07  Alan Modra  <amodra@gmail.com>
1795
1796         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1797         bfd_arch_rs6000.
1798         * disassemble.h (print_insn_rs6000): Delete.
1799         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1800         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1801         (print_insn_rs6000): Delete.
1802
1803 2018-03-03  Alan Modra  <amodra@gmail.com>
1804
1805         * sysdep.h (opcodes_error_handler): Define.
1806         (_bfd_error_handler): Declare.
1807         * Makefile.am: Remove stray #.
1808         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1809         EDIT" comment.
1810         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1811         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1812         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1813         opcodes_error_handler to print errors.  Standardize error messages.
1814         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1815         and include opintl.h.
1816         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1817         * i386-gen.c: Standardize error messages.
1818         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1819         * Makefile.in: Regenerate.
1820         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1821         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1822         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1823         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1824         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1825         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1826         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1827         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1828         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1829         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1830         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1831         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1832         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1833
1834 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1835
1836         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1837         vpsub[bwdq] instructions.
1838         * i386-tbl.h: Regenerated.
1839
1840 2018-03-01  Alan Modra  <amodra@gmail.com>
1841
1842         * configure.ac (ALL_LINGUAS): Sort.
1843         * configure: Regenerate.
1844
1845 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1846
1847         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1848         macro by assignements.
1849
1850 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1851
1852         PR gas/22871
1853         * i386-gen.c (opcode_modifiers): Add Optimize.
1854         * i386-opc.h (Optimize): New enum.
1855         (i386_opcode_modifier): Add optimize.
1856         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1857         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1858         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1859         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1860         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1861         vpxord and vpxorq.
1862         * i386-tbl.h: Regenerated.
1863
1864 2018-02-26  Alan Modra  <amodra@gmail.com>
1865
1866         * crx-dis.c (getregliststring): Allocate a large enough buffer
1867         to silence false positive gcc8 warning.
1868
1869 2018-02-22  Shea Levy <shea@shealevy.com>
1870
1871         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1872
1873 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1874
1875         * i386-opc.tbl: Add {rex},
1876         * i386-tbl.h: Regenerated.
1877
1878 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1879
1880         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1881         (mips16_opcodes): Replace `M' with `m' for "restore".
1882
1883 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1884
1885         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1886
1887 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1888
1889         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1890         variable to `function_index'.
1891
1892 2018-02-13  Nick Clifton  <nickc@redhat.com>
1893
1894         PR 22823
1895         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1896         about truncation of printing.
1897
1898 2018-02-12  Henry Wong <henry@stuffedcow.net>
1899
1900         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1901
1902 2018-02-05  Nick Clifton  <nickc@redhat.com>
1903
1904         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1905
1906 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1907
1908         * i386-dis.c (enum): Add pconfig.
1909         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1910         (cpu_flags): Add CpuPCONFIG.
1911         * i386-opc.h (enum): Add CpuPCONFIG.
1912         (i386_cpu_flags): Add cpupconfig.
1913         * i386-opc.tbl: Add PCONFIG instruction.
1914         * i386-init.h: Regenerate.
1915         * i386-tbl.h: Likewise.
1916
1917 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1918
1919         * i386-dis.c (enum): Add PREFIX_0F09.
1920         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1921         (cpu_flags): Add CpuWBNOINVD.
1922         * i386-opc.h (enum): Add CpuWBNOINVD.
1923         (i386_cpu_flags): Add cpuwbnoinvd.
1924         * i386-opc.tbl: Add WBNOINVD instruction.
1925         * i386-init.h: Regenerate.
1926         * i386-tbl.h: Likewise.
1927
1928 2018-01-17  Jim Wilson  <jimw@sifive.com>
1929
1930         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1931
1932 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1933
1934         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1935         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1936         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1937         (cpu_flags): Add CpuIBT, CpuSHSTK.
1938         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1939         (i386_cpu_flags): Add cpuibt, cpushstk.
1940         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1941         * i386-init.h: Regenerate.
1942         * i386-tbl.h: Likewise.
1943
1944 2018-01-16  Nick Clifton  <nickc@redhat.com>
1945
1946         * po/pt_BR.po: Updated Brazilian Portugese translation.
1947         * po/de.po: Updated German translation.
1948
1949 2018-01-15  Jim Wilson  <jimw@sifive.com>
1950
1951         * riscv-opc.c (match_c_nop): New.
1952         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1953
1954 2018-01-15  Nick Clifton  <nickc@redhat.com>
1955
1956         * po/uk.po: Updated Ukranian translation.
1957
1958 2018-01-13  Nick Clifton  <nickc@redhat.com>
1959
1960         * po/opcodes.pot: Regenerated.
1961
1962 2018-01-13  Nick Clifton  <nickc@redhat.com>
1963
1964         * configure: Regenerate.
1965
1966 2018-01-13  Nick Clifton  <nickc@redhat.com>
1967
1968         2.30 branch created.
1969
1970 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1971
1972         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1973         * i386-tbl.h: Regenerate.
1974
1975 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1976
1977         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1978         * i386-tbl.h: Re-generate.
1979
1980 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1981
1982         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1983         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1984         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1985         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1986         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1987         Disp8MemShift of AVX512VL forms.
1988         * i386-tbl.h: Re-generate.
1989
1990 2018-01-09  Jim Wilson  <jimw@sifive.com>
1991
1992         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1993         then the hi_addr value is zero.
1994
1995 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1996
1997         * arm-dis.c (arm_opcodes): Add csdb.
1998         (thumb32_opcodes): Add csdb.
1999
2000 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2001
2002         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2003         * aarch64-asm-2.c: Regenerate.
2004         * aarch64-dis-2.c: Regenerate.
2005         * aarch64-opc-2.c: Regenerate.
2006
2007 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2008
2009         PR gas/22681
2010         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2011         Remove AVX512 vmovd with 64-bit operands.
2012         * i386-tbl.h: Regenerated.
2013
2014 2018-01-05  Jim Wilson  <jimw@sifive.com>
2015
2016         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2017         jalr.
2018
2019 2018-01-03  Alan Modra  <amodra@gmail.com>
2020
2021         Update year range in copyright notice of all files.
2022
2023 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2024
2025         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2026         and OPERAND_TYPE_REGZMM entries.
2027
2028 For older changes see ChangeLog-2017
2029 \f
2030 Copyright (C) 2018 Free Software Foundation, Inc.
2031
2032 Copying and distribution of this file, with or without modification,
2033 are permitted in any medium without royalty provided the copyright
2034 notice and this notice are preserved.
2035
2036 Local Variables:
2037 mode: change-log
2038 left-margin: 8
2039 fill-column: 74
2040 version-control: never
2041 End: