opcodes/ChangeLog

   1 2018-11-06  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
   4         with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
   5
   6 2018-11-06  Alan Modra  <amodra@gmail.com>
   7
   8         * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
   9         (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
  10         (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
  11         (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
  12         Don't return zero on error, insert mask bits instead.
  13         (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
  14         (insert_sh6, extract_sh6): Delete dead code.
  15         (insert_sprbat, insert_sprg): Use unsigned comparisions.
  16         (powerpc_operands <OIMM>): Set shift count rather than using
  17         PPC_OPSHIFT_INV.
  18         <SE_SDH, SE_SDW>: Likewise.  Don't use insert/extract functions.
  19
  20 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  21
  22         * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
  23         vpbroadcast{d,q} with GPR operand.
  24
  25 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
  28         * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
  29         cases up one level in the hierarchy.
  30
  31 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  32
  33         * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
  34         MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
  35         (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
  36         into MOD_VEX_0F93_P_3_LEN_0.
  37         (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
  38         operand cases up one level in the hierarchy.
  39
  40 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  41
  42         * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
  43         VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
  44         EVEX_W_0F3A22_P_2): Delete.
  45         (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
  46         entries up one level in the hierarchy.
  47         (OP_E_memory): Handle dq_mode when determining Disp8 shift
  48         value.
  49         * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
  50         entries up one level in the hierarchy.
  51         * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
  52         VexWIG for AVX flavors.
  53         * i386-tbl.h: Re-generate.
  54
  55 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  56
  57         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
  58         vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
  59         vcvtusi2ss, kmovd): Drop VexW=1.
  60         * i386-tbl.h: Re-generate.
  61
  62 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  63
  64         * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
  65         EVex512, EVexLIG, EVexDYN): New.
  66         (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
  67         insns): Use Vex128 instead of Vex=3 (aka VexLIG).
  68         (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
  69         of EVex=4 (aka EVexLIG).
  70         * i386-tbl.h: Re-generate.
  71
  72 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
  75         (vpmaxub): Re-order attributes on AVX512BW flavor.
  76         * i386-tbl.h: Re-generate.
  77
  78 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  79
  80         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
  81         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
  82         Vex=1 on AVX / AVX2 flavors.
  83         (vpmaxub): Re-order attributes on AVX512BW flavor.
  84         * i386-tbl.h: Re-generate.
  85
  86 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  87
  88         * i386-opc.tbl (VexW0, VexW1): New.
  89         (vphadd*, vphsub*): Use VexW0 on XOP variants.
  90         * i386-tbl.h: Re-generate.
  91
  92 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
  93
  94         * s12z-dis.c (decode_possible_symbol): Add fallback case.
  95         (rel_15_7): Likewise.
  96
  97 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
  98
  99         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
 100         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
 101         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
 102
 103 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
 104
 105         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
 106         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
 107
 108 2018-10-10  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
 111         Size64. Add Size.
 112         * i386-opc.h (Size16, Size32, Size64): Delete.
 113         (Size): New.
 114         (SIZE16, SIZE32, SIZE64): Define.
 115         (struct i386_opcode_modifier): Drop size16, size32, and size64.
 116         Add size.
 117         * i386-opc.tbl (Size16, Size32, Size64): Define.
 118         * i386-tbl.h: Re-generate.
 119
 120 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 121
 122         * aarch64-opc.c (operand_general_constraint_met_p): Add
 123         SSBS in the check for one-bit immediate.
 124         (aarch64_sys_regs): New entry for SSBS.
 125         (aarch64_sys_reg_supported_p): New check for above.
 126         (aarch64_pstatefields): New entry for SSBS.
 127         (aarch64_pstatefield_supported_p): New check for above.
 128
 129 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 130
 131         * aarch64-opc.c (aarch64_sys_regs): New entries for
 132         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
 133         (aarch64_sys_reg_supported_p): New checks for above.
 134
 135 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 136
 137         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
 138         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
 139         with the hint immediate.
 140         * aarch64-opc.c (aarch64_hint_options): New entries for
 141         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
 142         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
 143         while checking for HINT_OPD_F_NOPRINT flag.
 144         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
 145         extract value.
 146         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
 147         (aarch64_opcode_table): Add entry for BTI.
 148         (AARCH64_OPERANDS): Add new description for BTI targets.
 149         * aarch64-asm-2.c: Regenerate.
 150         * aarch64-dis-2.c: Regenerate.
 151         * aarch64-opc-2.c: Regenerate.
 152
 153 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 154
 155         * aarch64-opc.c (aarch64_sys_regs): New entries for
 156         rndr and rndrrs.
 157         (aarch64_sys_reg_supported_p): New check for above.
 158
 159 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 160
 161         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
 162         (aarch64_sys_ins_reg_supported_p): New check for above.
 163
 164 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 165
 166         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
 167         AARCH64_OPND_SYSREG_SR.
 168         * aarch64-opc.c (aarch64_print_operand): Likewise.
 169         (aarch64_sys_regs_sr): Define table.
 170         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
 171         AARCH64_FEATURE_PREDRES.
 172         * aarch64-tbl.h (aarch64_feature_predres): New.
 173         (PREDRES, PREDRES_INSN): New.
 174         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
 175         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
 176         * aarch64-asm-2.c: Regenerate.
 177         * aarch64-dis-2.c: Regenerate.
 178         * aarch64-opc-2.c: Regenerate.
 179
 180 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 181
 182         * aarch64-tbl.h (aarch64_feature_sb): New.
 183         (SB, SB_INSN): New.
 184         (aarch64_opcode_table): Add entry for sb.
 185         * aarch64-asm-2.c: Regenerate.
 186         * aarch64-dis-2.c: Regenerate.
 187         * aarch64-opc-2.c: Regenerate.
 188
 189 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 190
 191         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 192         (aarch64_feature_frintts): New.
 193         (FLAGMANIP, FRINTTS): New.
 194         (aarch64_opcode_table): Add entries for xaflag, axflag
 195         and frint[32,64][x,z] instructions.
 196         * aarch64-asm-2.c: Regenerate.
 197         * aarch64-dis-2.c: Regenerate.
 198         * aarch64-opc-2.c: Regenerate.
 199
 200 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 201
 202         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 203         (ARMV8_5, V8_5_INSN): New.
 204
 205 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 206
 207         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 208
 209 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 210
 211         * i386-dis.c (rm_table): Add enclv.
 212         * i386-opc.tbl: Add enclv.
 213         * i386-tbl.h: Regenerated.
 214
 215 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 216
 217         * arm-dis.c (arm_opcodes): Add sb.
 218         (thumb32_opcodes): Likewise.
 219
 220 2018-10-05  Richard Henderson  <rth@twiddle.net>
 221             Stafford Horne  <shorne@gmail.com>
 222
 223         * or1k-desc.c: Regenerate.
 224         * or1k-desc.h: Regenerate.
 225         * or1k-opc.c: Regenerate.
 226         * or1k-opc.h: Regenerate.
 227         * or1k-opinst.c: Regenerate.
 228
 229 2018-10-05  Richard Henderson  <rth@twiddle.net>
 230
 231         * or1k-asm.c: Regenerated.
 232         * or1k-desc.c: Regenerated.
 233         * or1k-desc.h: Regenerated.
 234         * or1k-dis.c: Regenerated.
 235         * or1k-ibld.c: Regenerated.
 236         * or1k-opc.c: Regenerated.
 237         * or1k-opc.h: Regenerated.
 238         * or1k-opinst.c: Regenerated.
 239
 240 2018-10-05  Richard Henderson  <rth@twiddle.net>
 241
 242         * or1k-asm.c: Regenerate.
 243
 244 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 245
 246         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 247         * aarch64-dis.c (print_operands): Refactor to take notes.
 248         (print_verifier_notes): New.
 249         (print_aarch64_insn): Apply constraint verifier.
 250         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 251         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 252
 253 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 254
 255         * aarch64-opc.c (init_insn_block): New.
 256         (verify_constraints, aarch64_is_destructive_by_operands): New.
 257         * aarch64-opc.h (verify_constraints): New.
 258
 259 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 260
 261         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 262         * aarch64-opc.c (verify_ldpsw): Update arguments.
 263
 264 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 265
 266         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 267         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 268
 269 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 270
 271         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 272         * aarch64-dis.c (insn_sequence): New.
 273
 274 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 275
 276         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 277         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 278         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 279         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 280         constraints.
 281         (_SVE_INSNC): New.
 282         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 283         constraints.
 284         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 285         F_SCAN flags.
 286         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 287         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 288         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 289         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 290         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 291         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 292         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 293
 294 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 295
 296         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 297
 298 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 299
 300         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 301         are used when extracting signed fields and converting them to
 302         potentially 64-bit types.
 303
 304 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 305
 306         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 307         * Makefile.in: Re-generate.
 308         * aclocal.m4: Re-generate.
 309         * configure: Re-generate.
 310         * configure.ac: Remove check for -Wno-missing-field-initializers.
 311         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 312         (csky_v2_opcodes): Likewise.
 313
 314 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 315
 316         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 317
 318 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 319
 320         * nds32-asm.c (operand_fields): Remove the unused fields.
 321         (nds32_opcodes): Remove the unused instructions.
 322         * nds32-dis.c (nds32_ex9_info): Removed.
 323         (nds32_parse_opcode): Updated.
 324         (print_insn_nds32): Likewise.
 325         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 326         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 327         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 328         build_opcode_hash_table): New functions.
 329         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 330         nds32_opcode_table): New.
 331         (hw_ktabs): Declare it to a pointer rather than an array.
 332         (build_hash_table): Removed.
 333         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 334         SYN_ROPT and upadte HW_GPR and HW_INT.
 335         * nds32-dis.c (keywords): Remove const.
 336         (match_field): New function.
 337         (nds32_parse_opcode): Updated.
 338         * disassemble.c (disassemble_init_for_target):
 339         Add disassemble_init_nds32.
 340         * nds32-dis.c (eum map_type): New.
 341         (nds32_private_data): Likewise.
 342         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 343         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 344         (print_insn_nds32): Updated.
 345         * nds32-asm.c (parse_aext_reg): Add new parameter.
 346         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 347         are allowed to use.
 348         All callers changed.
 349         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 350         (operand_fields): Add new fields.
 351         (nds32_opcodes): Add new instructions.
 352         (keyword_aridxi_mx): New keyword.
 353         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 354         and NASM_ATTR_ZOL.
 355         (ALU2_1, ALU2_2, ALU2_3): New macros.
 356         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 357
 358 2018-09-17  Kito Cheng  <kito@andestech.com>
 359
 360         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 361
 362 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 363
 364         PR gas/23670
 365         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 366         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 367         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 368         (EVEX_LEN_0F7E_P_1): Likewise.
 369         (EVEX_LEN_0F7E_P_2): Likewise.
 370         (EVEX_LEN_0FD6_P_2): Likewise.
 371         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 372         (EVEX_LEN_TABLE): Likewise.
 373         (EVEX_LEN_0F6E_P_2): New enum.
 374         (EVEX_LEN_0F7E_P_1): Likewise.
 375         (EVEX_LEN_0F7E_P_2): Likewise.
 376         (EVEX_LEN_0FD6_P_2): Likewise.
 377         (evex_len_table): New.
 378         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 379         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 380         * i386-tbl.h: Regenerated.
 381
 382 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         PR gas/23665
 385         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 386         VEX_LEN_0F7E_P_2 entries.
 387         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 388         * i386-tbl.h: Regenerated.
 389
 390 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 391
 392         * i386-dis.c (VZERO_Fixup): Removed.
 393         (VZERO): Likewise.
 394         (VEX_LEN_0F10_P_1): Likewise.
 395         (VEX_LEN_0F10_P_3): Likewise.
 396         (VEX_LEN_0F11_P_1): Likewise.
 397         (VEX_LEN_0F11_P_3): Likewise.
 398         (VEX_LEN_0F2E_P_0): Likewise.
 399         (VEX_LEN_0F2E_P_2): Likewise.
 400         (VEX_LEN_0F2F_P_0): Likewise.
 401         (VEX_LEN_0F2F_P_2): Likewise.
 402         (VEX_LEN_0F51_P_1): Likewise.
 403         (VEX_LEN_0F51_P_3): Likewise.
 404         (VEX_LEN_0F52_P_1): Likewise.
 405         (VEX_LEN_0F53_P_1): Likewise.
 406         (VEX_LEN_0F58_P_1): Likewise.
 407         (VEX_LEN_0F58_P_3): Likewise.
 408         (VEX_LEN_0F59_P_1): Likewise.
 409         (VEX_LEN_0F59_P_3): Likewise.
 410         (VEX_LEN_0F5A_P_1): Likewise.
 411         (VEX_LEN_0F5A_P_3): Likewise.
 412         (VEX_LEN_0F5C_P_1): Likewise.
 413         (VEX_LEN_0F5C_P_3): Likewise.
 414         (VEX_LEN_0F5D_P_1): Likewise.
 415         (VEX_LEN_0F5D_P_3): Likewise.
 416         (VEX_LEN_0F5E_P_1): Likewise.
 417         (VEX_LEN_0F5E_P_3): Likewise.
 418         (VEX_LEN_0F5F_P_1): Likewise.
 419         (VEX_LEN_0F5F_P_3): Likewise.
 420         (VEX_LEN_0FC2_P_1): Likewise.
 421         (VEX_LEN_0FC2_P_3): Likewise.
 422         (VEX_LEN_0F3A0A_P_2): Likewise.
 423         (VEX_LEN_0F3A0B_P_2): Likewise.
 424         (VEX_W_0F10_P_0): Likewise.
 425         (VEX_W_0F10_P_1): Likewise.
 426         (VEX_W_0F10_P_2): Likewise.
 427         (VEX_W_0F10_P_3): Likewise.
 428         (VEX_W_0F11_P_0): Likewise.
 429         (VEX_W_0F11_P_1): Likewise.
 430         (VEX_W_0F11_P_2): Likewise.
 431         (VEX_W_0F11_P_3): Likewise.
 432         (VEX_W_0F12_P_0_M_0): Likewise.
 433         (VEX_W_0F12_P_0_M_1): Likewise.
 434         (VEX_W_0F12_P_1): Likewise.
 435         (VEX_W_0F12_P_2): Likewise.
 436         (VEX_W_0F12_P_3): Likewise.
 437         (VEX_W_0F13_M_0): Likewise.
 438         (VEX_W_0F14): Likewise.
 439         (VEX_W_0F15): Likewise.
 440         (VEX_W_0F16_P_0_M_0): Likewise.
 441         (VEX_W_0F16_P_0_M_1): Likewise.
 442         (VEX_W_0F16_P_1): Likewise.
 443         (VEX_W_0F16_P_2): Likewise.
 444         (VEX_W_0F17_M_0): Likewise.
 445         (VEX_W_0F28): Likewise.
 446         (VEX_W_0F29): Likewise.
 447         (VEX_W_0F2B_M_0): Likewise.
 448         (VEX_W_0F2E_P_0): Likewise.
 449         (VEX_W_0F2E_P_2): Likewise.
 450         (VEX_W_0F2F_P_0): Likewise.
 451         (VEX_W_0F2F_P_2): Likewise.
 452         (VEX_W_0F50_M_0): Likewise.
 453         (VEX_W_0F51_P_0): Likewise.
 454         (VEX_W_0F51_P_1): Likewise.
 455         (VEX_W_0F51_P_2): Likewise.
 456         (VEX_W_0F51_P_3): Likewise.
 457         (VEX_W_0F52_P_0): Likewise.
 458         (VEX_W_0F52_P_1): Likewise.
 459         (VEX_W_0F53_P_0): Likewise.
 460         (VEX_W_0F53_P_1): Likewise.
 461         (VEX_W_0F58_P_0): Likewise.
 462         (VEX_W_0F58_P_1): Likewise.
 463         (VEX_W_0F58_P_2): Likewise.
 464         (VEX_W_0F58_P_3): Likewise.
 465         (VEX_W_0F59_P_0): Likewise.
 466         (VEX_W_0F59_P_1): Likewise.
 467         (VEX_W_0F59_P_2): Likewise.
 468         (VEX_W_0F59_P_3): Likewise.
 469         (VEX_W_0F5A_P_0): Likewise.
 470         (VEX_W_0F5A_P_1): Likewise.
 471         (VEX_W_0F5A_P_3): Likewise.
 472         (VEX_W_0F5B_P_0): Likewise.
 473         (VEX_W_0F5B_P_1): Likewise.
 474         (VEX_W_0F5B_P_2): Likewise.
 475         (VEX_W_0F5C_P_0): Likewise.
 476         (VEX_W_0F5C_P_1): Likewise.
 477         (VEX_W_0F5C_P_2): Likewise.
 478         (VEX_W_0F5C_P_3): Likewise.
 479         (VEX_W_0F5D_P_0): Likewise.
 480         (VEX_W_0F5D_P_1): Likewise.
 481         (VEX_W_0F5D_P_2): Likewise.
 482         (VEX_W_0F5D_P_3): Likewise.
 483         (VEX_W_0F5E_P_0): Likewise.
 484         (VEX_W_0F5E_P_1): Likewise.
 485         (VEX_W_0F5E_P_2): Likewise.
 486         (VEX_W_0F5E_P_3): Likewise.
 487         (VEX_W_0F5F_P_0): Likewise.
 488         (VEX_W_0F5F_P_1): Likewise.
 489         (VEX_W_0F5F_P_2): Likewise.
 490         (VEX_W_0F5F_P_3): Likewise.
 491         (VEX_W_0F60_P_2): Likewise.
 492         (VEX_W_0F61_P_2): Likewise.
 493         (VEX_W_0F62_P_2): Likewise.
 494         (VEX_W_0F63_P_2): Likewise.
 495         (VEX_W_0F64_P_2): Likewise.
 496         (VEX_W_0F65_P_2): Likewise.
 497         (VEX_W_0F66_P_2): Likewise.
 498         (VEX_W_0F67_P_2): Likewise.
 499         (VEX_W_0F68_P_2): Likewise.
 500         (VEX_W_0F69_P_2): Likewise.
 501         (VEX_W_0F6A_P_2): Likewise.
 502         (VEX_W_0F6B_P_2): Likewise.
 503         (VEX_W_0F6C_P_2): Likewise.
 504         (VEX_W_0F6D_P_2): Likewise.
 505         (VEX_W_0F6F_P_1): Likewise.
 506         (VEX_W_0F6F_P_2): Likewise.
 507         (VEX_W_0F70_P_1): Likewise.
 508         (VEX_W_0F70_P_2): Likewise.
 509         (VEX_W_0F70_P_3): Likewise.
 510         (VEX_W_0F71_R_2_P_2): Likewise.
 511         (VEX_W_0F71_R_4_P_2): Likewise.
 512         (VEX_W_0F71_R_6_P_2): Likewise.
 513         (VEX_W_0F72_R_2_P_2): Likewise.
 514         (VEX_W_0F72_R_4_P_2): Likewise.
 515         (VEX_W_0F72_R_6_P_2): Likewise.
 516         (VEX_W_0F73_R_2_P_2): Likewise.
 517         (VEX_W_0F73_R_3_P_2): Likewise.
 518         (VEX_W_0F73_R_6_P_2): Likewise.
 519         (VEX_W_0F73_R_7_P_2): Likewise.
 520         (VEX_W_0F74_P_2): Likewise.
 521         (VEX_W_0F75_P_2): Likewise.
 522         (VEX_W_0F76_P_2): Likewise.
 523         (VEX_W_0F77_P_0): Likewise.
 524         (VEX_W_0F7C_P_2): Likewise.
 525         (VEX_W_0F7C_P_3): Likewise.
 526         (VEX_W_0F7D_P_2): Likewise.
 527         (VEX_W_0F7D_P_3): Likewise.
 528         (VEX_W_0F7E_P_1): Likewise.
 529         (VEX_W_0F7F_P_1): Likewise.
 530         (VEX_W_0F7F_P_2): Likewise.
 531         (VEX_W_0FAE_R_2_M_0): Likewise.
 532         (VEX_W_0FAE_R_3_M_0): Likewise.
 533         (VEX_W_0FC2_P_0): Likewise.
 534         (VEX_W_0FC2_P_1): Likewise.
 535         (VEX_W_0FC2_P_2): Likewise.
 536         (VEX_W_0FC2_P_3): Likewise.
 537         (VEX_W_0FD0_P_2): Likewise.
 538         (VEX_W_0FD0_P_3): Likewise.
 539         (VEX_W_0FD1_P_2): Likewise.
 540         (VEX_W_0FD2_P_2): Likewise.
 541         (VEX_W_0FD3_P_2): Likewise.
 542         (VEX_W_0FD4_P_2): Likewise.
 543         (VEX_W_0FD5_P_2): Likewise.
 544         (VEX_W_0FD6_P_2): Likewise.
 545         (VEX_W_0FD7_P_2_M_1): Likewise.
 546         (VEX_W_0FD8_P_2): Likewise.
 547         (VEX_W_0FD9_P_2): Likewise.
 548         (VEX_W_0FDA_P_2): Likewise.
 549         (VEX_W_0FDB_P_2): Likewise.
 550         (VEX_W_0FDC_P_2): Likewise.
 551         (VEX_W_0FDD_P_2): Likewise.
 552         (VEX_W_0FDE_P_2): Likewise.
 553         (VEX_W_0FDF_P_2): Likewise.
 554         (VEX_W_0FE0_P_2): Likewise.
 555         (VEX_W_0FE1_P_2): Likewise.
 556         (VEX_W_0FE2_P_2): Likewise.
 557         (VEX_W_0FE3_P_2): Likewise.
 558         (VEX_W_0FE4_P_2): Likewise.
 559         (VEX_W_0FE5_P_2): Likewise.
 560         (VEX_W_0FE6_P_1): Likewise.
 561         (VEX_W_0FE6_P_2): Likewise.
 562         (VEX_W_0FE6_P_3): Likewise.
 563         (VEX_W_0FE7_P_2_M_0): Likewise.
 564         (VEX_W_0FE8_P_2): Likewise.
 565         (VEX_W_0FE9_P_2): Likewise.
 566         (VEX_W_0FEA_P_2): Likewise.
 567         (VEX_W_0FEB_P_2): Likewise.
 568         (VEX_W_0FEC_P_2): Likewise.
 569         (VEX_W_0FED_P_2): Likewise.
 570         (VEX_W_0FEE_P_2): Likewise.
 571         (VEX_W_0FEF_P_2): Likewise.
 572         (VEX_W_0FF0_P_3_M_0): Likewise.
 573         (VEX_W_0FF1_P_2): Likewise.
 574         (VEX_W_0FF2_P_2): Likewise.
 575         (VEX_W_0FF3_P_2): Likewise.
 576         (VEX_W_0FF4_P_2): Likewise.
 577         (VEX_W_0FF5_P_2): Likewise.
 578         (VEX_W_0FF6_P_2): Likewise.
 579         (VEX_W_0FF7_P_2): Likewise.
 580         (VEX_W_0FF8_P_2): Likewise.
 581         (VEX_W_0FF9_P_2): Likewise.
 582         (VEX_W_0FFA_P_2): Likewise.
 583         (VEX_W_0FFB_P_2): Likewise.
 584         (VEX_W_0FFC_P_2): Likewise.
 585         (VEX_W_0FFD_P_2): Likewise.
 586         (VEX_W_0FFE_P_2): Likewise.
 587         (VEX_W_0F3800_P_2): Likewise.
 588         (VEX_W_0F3801_P_2): Likewise.
 589         (VEX_W_0F3802_P_2): Likewise.
 590         (VEX_W_0F3803_P_2): Likewise.
 591         (VEX_W_0F3804_P_2): Likewise.
 592         (VEX_W_0F3805_P_2): Likewise.
 593         (VEX_W_0F3806_P_2): Likewise.
 594         (VEX_W_0F3807_P_2): Likewise.
 595         (VEX_W_0F3808_P_2): Likewise.
 596         (VEX_W_0F3809_P_2): Likewise.
 597         (VEX_W_0F380A_P_2): Likewise.
 598         (VEX_W_0F380B_P_2): Likewise.
 599         (VEX_W_0F3817_P_2): Likewise.
 600         (VEX_W_0F381C_P_2): Likewise.
 601         (VEX_W_0F381D_P_2): Likewise.
 602         (VEX_W_0F381E_P_2): Likewise.
 603         (VEX_W_0F3820_P_2): Likewise.
 604         (VEX_W_0F3821_P_2): Likewise.
 605         (VEX_W_0F3822_P_2): Likewise.
 606         (VEX_W_0F3823_P_2): Likewise.
 607         (VEX_W_0F3824_P_2): Likewise.
 608         (VEX_W_0F3825_P_2): Likewise.
 609         (VEX_W_0F3828_P_2): Likewise.
 610         (VEX_W_0F3829_P_2): Likewise.
 611         (VEX_W_0F382A_P_2_M_0): Likewise.
 612         (VEX_W_0F382B_P_2): Likewise.
 613         (VEX_W_0F3830_P_2): Likewise.
 614         (VEX_W_0F3831_P_2): Likewise.
 615         (VEX_W_0F3832_P_2): Likewise.
 616         (VEX_W_0F3833_P_2): Likewise.
 617         (VEX_W_0F3834_P_2): Likewise.
 618         (VEX_W_0F3835_P_2): Likewise.
 619         (VEX_W_0F3837_P_2): Likewise.
 620         (VEX_W_0F3838_P_2): Likewise.
 621         (VEX_W_0F3839_P_2): Likewise.
 622         (VEX_W_0F383A_P_2): Likewise.
 623         (VEX_W_0F383B_P_2): Likewise.
 624         (VEX_W_0F383C_P_2): Likewise.
 625         (VEX_W_0F383D_P_2): Likewise.
 626         (VEX_W_0F383E_P_2): Likewise.
 627         (VEX_W_0F383F_P_2): Likewise.
 628         (VEX_W_0F3840_P_2): Likewise.
 629         (VEX_W_0F3841_P_2): Likewise.
 630         (VEX_W_0F38DB_P_2): Likewise.
 631         (VEX_W_0F3A08_P_2): Likewise.
 632         (VEX_W_0F3A09_P_2): Likewise.
 633         (VEX_W_0F3A0A_P_2): Likewise.
 634         (VEX_W_0F3A0B_P_2): Likewise.
 635         (VEX_W_0F3A0C_P_2): Likewise.
 636         (VEX_W_0F3A0D_P_2): Likewise.
 637         (VEX_W_0F3A0E_P_2): Likewise.
 638         (VEX_W_0F3A0F_P_2): Likewise.
 639         (VEX_W_0F3A21_P_2): Likewise.
 640         (VEX_W_0F3A40_P_2): Likewise.
 641         (VEX_W_0F3A41_P_2): Likewise.
 642         (VEX_W_0F3A42_P_2): Likewise.
 643         (VEX_W_0F3A62_P_2): Likewise.
 644         (VEX_W_0F3A63_P_2): Likewise.
 645         (VEX_W_0F3ADF_P_2): Likewise.
 646         (VEX_LEN_0F77_P_0): New.
 647         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 648         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 649         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 650         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 651         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 652         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 653         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 654         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 655         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 656         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 657         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 658         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 659         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 660         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 661         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 662         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 663         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 664         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 665         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 666         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 667         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 668         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 669         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 670         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 671         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 672         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 673         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 674         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 675         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 676         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 677         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 678         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 679         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 680         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 681         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 682         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 683         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 684         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 685         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 686         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 687         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 688         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 689         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 690         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 691         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 692         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 693         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 694         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 695         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 696         (vex_table): Update VEX 0F28 and 0F29 entries.
 697         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 698         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 699         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 700         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 701         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 702         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 703         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 704         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 705         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 706         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 707         VEX_LEN_0F3A0B_P_2 entries.
 708         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 709         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 710         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 711         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 712         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 713         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 714         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 715         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 716         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 717         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 718         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 719         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 720         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 721         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 722         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 723         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 724         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 725         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 726         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 727         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 728         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 729         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 730         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 731         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 732         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 733         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 734         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 735         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 736         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 737         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 738         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 739         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 740         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 741         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 742         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 743         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 744         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 745         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 746         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 747         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 748         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 749         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 750         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 751         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 752         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 753         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 754         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 755         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 756         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 757         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 758         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 759         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 760         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 761         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 762         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 763         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 764         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 765         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 766         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 767         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 768         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 769         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 770         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 771         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 772         VEX_W_0F3ADF_P_2 entries.
 773         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 774         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 775         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 776
 777 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 778
 779         * i386-opc.tbl (VexWIG): New.
 780         Replace VexW=3 with VexWIG.
 781
 782 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 783
 784         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 785         * i386-tbl.h: Regenerated.
 786
 787 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 788
 789         PR gas/23665
 790         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 791         VEX_LEN_0FD6_P_2 entries.
 792         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 793         * i386-tbl.h: Regenerated.
 794
 795 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 796
 797         PR gas/23642
 798         * i386-opc.h (VEXWIG): New.
 799         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 800         * i386-tbl.h: Regenerated.
 801
 802 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 803
 804         PR binutils/23655
 805         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 806         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 807         * i386-dis.c (EXxEVexR64): New.
 808         (evex_rounding_64_mode): Likewise.
 809         (OP_Rounding): Handle evex_rounding_64_mode.
 810
 811 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 812
 813         PR binutils/23655
 814         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 815         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 816         * i386-dis.c (Edqa): New.
 817         (dqa_mode): Likewise.
 818         (intel_operand_size): Handle dqa_mode as m_mode.
 819         (OP_E_register): Handle dqa_mode as dq_mode.
 820         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 821
 822 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 823
 824         * i386-dis.c (OP_E_memory): Reformat.
 825
 826 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 827
 828         * i386-opc.tbl (crc32): Fold byte and word forms.
 829         * i386-tbl.h: Re-generate.
 830
 831 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 832
 833         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 834         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 835         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 836         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 837         * i386-tbl.h: Regenerated.
 838
 839 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 840
 841         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 842         meaningless.
 843         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 844         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 845         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 846         * i386-tbl.h: Re-generate.
 847
 848 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 849
 850         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 851         AVX512_4VNNIW insns.
 852         * i386-tbl.h: Re-generate.
 853
 854 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 855
 856         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 857         meaningless.
 858         * i386-tbl.h: Re-generate.
 859
 860 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 861
 862         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 863         meaningless.
 864         * i386-tbl.h: Re-generate.
 865
 866 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 867
 868         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 869         meaningless.
 870         * i386-tbl.h: Re-generate.
 871
 872 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 875         meaningless.
 876         * i386-tbl.h: Re-generate.
 877
 878 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 879
 880         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 881         meaningless.
 882         * i386-tbl.h: Re-generate.
 883
 884 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 885
 886         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 887         * i386-tbl.h: Re-generate.
 888
 889 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 890
 891         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 892         * i386-tbl.h: Re-generate.
 893
 894 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 895
 896         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 897         meaningless.
 898         * i386-tbl.h: Re-generate.
 899
 900 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 901
 902         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 903         meaningless.
 904         * i386-tbl.h: Re-generate.
 905
 906 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 907
 908         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 909         * i386-tbl.h: Re-generate.
 910
 911 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 912
 913         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 914         * i386-tbl.h: Re-generate.
 915
 916 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 917
 918         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 919         * i386-tbl.h: Re-generate.
 920
 921 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 922
 923         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 924         meaningless.
 925         * i386-tbl.h: Re-generate.
 926
 927 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 928
 929         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 930         meaningless.
 931         * i386-tbl.h: Re-generate.
 932
 933 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 934
 935         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 936         meaningless.
 937         * i386-tbl.h: Re-generate.
 938
 939 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 940
 941         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 942         * i386-tbl.h: Re-generate.
 943
 944 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 945
 946         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 947         * i386-tbl.h: Re-generate.
 948
 949 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 950
 951         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 952         * i386-tbl.h: Re-generate.
 953
 954 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 957         (vpbroadcastw, rdpid): Drop NoRex64.
 958         * i386-tbl.h: Re-generate.
 959
 960 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 961
 962         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 963         store templates, adding D.
 964         * i386-tbl.h: Re-generate.
 965
 966 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 967
 968         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 969         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 970         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 971         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 972         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 973         Fold load and store templates where possible, adding D. Drop
 974         IgnoreSize where it was pointlessly present. Drop redundant
 975         *word.
 976         * i386-tbl.h: Re-generate.
 977
 978 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 979
 980         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 981         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 982         (intel_operand_size): Handle v_bndmk_mode.
 983         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 984
 985 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 986
 987         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 988
 989 2018-08-31  Kito Cheng  <kito@andestech.com>
 990
 991         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 992         compressed floating point instructions.
 993
 994 2018-08-30  Kito Cheng  <kito@andestech.com>
 995
 996         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 997         riscv_opcode.xlen_requirement.
 998         * riscv-opc.c (riscv_opcodes): Update for struct change.
 999
1000 2018-08-29  Martin Aberg  <maberg@gaisler.com>
1001
1002         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1003         psr (PWRPSR) instruction.
1004
1005 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1006
1007         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1008
1009 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1010
1011         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1012
1013 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1014
1015         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1016         loongson3a as an alias of gs464 for compatibility.
1017         * mips-opc.c (mips_opcodes): Change Comments.
1018
1019 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1020
1021         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1022         option.
1023         (print_mips_disassembler_options): Document -M loongson-ext.
1024         * mips-opc.c (LEXT2): New macro.
1025         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1026
1027 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1028
1029          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1030          descriptors.
1031          (parse_mips_ase_option): Handle -M loongson-ext option.
1032          (print_mips_disassembler_options): Document -M loongson-ext.
1033          * mips-opc.c (IL3A): Delete.
1034          * mips-opc.c (LEXT): New macro.
1035          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1036          instructions.
1037
1038 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1039
1040         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1041         descriptors.
1042         (parse_mips_ase_option): Handle -M loongson-cam option.
1043         (print_mips_disassembler_options): Document -M loongson-cam.
1044         * mips-opc.c (LCAM): New macro.
1045         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1046         instructions.
1047
1048 2018-08-21  Alan Modra  <amodra@gmail.com>
1049
1050         * ppc-dis.c (operand_value_powerpc): Init "invalid".
1051         (skip_optional_operands): Count optional operands, and update
1052         ppc_optional_operand_value call.
1053         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1054         (extract_vlensi): Likewise.
1055         (extract_fxm): Return default value for missing optional operand.
1056         (extract_ls, extract_raq, extract_tbr): Likewise.
1057         (insert_sxl, extract_sxl): New functions.
1058         (insert_esync, extract_esync): Remove Power9 handling and simplify.
1059         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1060         flag and extra entry.
1061         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1062         extract_sxl.
1063
1064 2018-08-20  Alan Modra  <amodra@gmail.com>
1065
1066         * sh-opc.h (MASK): Simplify.
1067
1068 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1069
1070         * s12z-dis.c (bm_decode): Deal with cases where the mode is
1071         BM_RESERVED0 or BM_RESERVED1
1072         (bm_rel_decode, bm_n_bytes): Ditto.
1073
1074 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1075
1076         * s12z.h: Delete.
1077
1078 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1079
1080         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1081         address with the addr32 prefix and without base nor index
1082         registers.
1083
1084 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1085
1086         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1087         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1088         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1089         (cpu_flags): Add CpuCMOV and CpuFXSR.
1090         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1091         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1092         * i386-init.h: Regenerated.
1093         * i386-tbl.h: Likewise.
1094
1095 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1096
1097         * arc-regs.h: Update auxiliary registers.
1098
1099 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1100
1101         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1102         (RegIP, RegIZ): Define.
1103         * i386-reg.tbl: Adjust comments.
1104         (rip): Use Qword instead of BaseIndex. Use RegIP.
1105         (eip): Use Dword instead of BaseIndex. Use RegIP.
1106         (riz): Add Qword. Use RegIZ.
1107         (eiz): Add Dword. Use RegIZ.
1108         * i386-tbl.h: Re-generate.
1109
1110 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1111
1112         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1113         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1114         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1115         * i386-tbl.h: Re-generate.
1116
1117 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1118
1119         * i386-gen.c (operand_types): Remove Mem field.
1120         * i386-opc.h (union i386_operand_type): Remove mem field.
1121         * i386-init.h, i386-tbl.h: Re-generate.
1122
1123 2018-08-01  Alan Modra  <amodra@gmail.com>
1124
1125         * po/POTFILES.in: Regenerate.
1126
1127 2018-07-31  Nick Clifton  <nickc@redhat.com>
1128
1129         * po/sv.po: Updated Swedish translation.
1130
1131 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1132
1133         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1134         * i386-init.h, i386-tbl.h: Re-generate.
1135
1136 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1137
1138         * i386-opc.h (ZEROING_MASKING) Rename to ...
1139         (DYNAMIC_MASKING): ... this. Adjust comment.
1140         * i386-opc.tbl (MaskingMorZ): Define.
1141         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1142         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1143         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1144         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1145         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1146         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1147         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1148         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1149         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1150
1151 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1152
1153         * i386-opc.tbl: Use element rather than vector size for AVX512*
1154         scatter/gather insns.
1155         * i386-tbl.h: Re-generate.
1156
1157 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1158
1159         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1160         (cpu_flags): Drop CpuVREX.
1161         * i386-opc.h (CpuVREX): Delete.
1162         (union i386_cpu_flags): Remove cpuvrex.
1163         * i386-init.h, i386-tbl.h: Re-generate.
1164
1165 2018-07-30  Jim Wilson  <jimw@sifive.com>
1166
1167         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1168         fields.
1169         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1170
1171 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1172
1173         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1174         * Makefile.in: Regenerated.
1175         * configure.ac: Add C-SKY.
1176         * configure: Regenerated.
1177         * csky-dis.c: New file.
1178         * csky-opc.h: New file.
1179         * disassemble.c (ARCH_csky): Define.
1180         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1181         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1182
1183 2018-07-27  Alan Modra  <amodra@gmail.com>
1184
1185         * ppc-opc.c (insert_sprbat): Correct function parameter and
1186         return type.
1187         (extract_sprbat): Likewise, variable too.
1188
1189 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1190             Alan Modra  <amodra@gmail.com>
1191
1192         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1193         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1194         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1195         support disjointed BAT.
1196         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1197         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1198         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1199
1200 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1201             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1202
1203         * i386-gen.c (adjust_broadcast_modifier): New function.
1204         (process_i386_opcode_modifier): Add an argument for operands.
1205         Adjust the Broadcast value based on operands.
1206         (output_i386_opcode): Pass operand_types to
1207         process_i386_opcode_modifier.
1208         (process_i386_opcodes): Pass NULL as operands to
1209         process_i386_opcode_modifier.
1210         * i386-opc.h (BYTE_BROADCAST): New.
1211         (WORD_BROADCAST): Likewise.
1212         (DWORD_BROADCAST): Likewise.
1213         (QWORD_BROADCAST): Likewise.
1214         (i386_opcode_modifier): Expand broadcast to 3 bits.
1215         * i386-tbl.h: Regenerated.
1216
1217 2018-07-24  Alan Modra  <amodra@gmail.com>
1218
1219         PR 23430
1220         * or1k-desc.h: Regenerate.
1221
1222 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1223
1224         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1225         vcvtusi2ss, and vcvtusi2sd.
1226         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1227         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1228         * i386-tbl.h: Re-generate.
1229
1230 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1231
1232         * arc-opc.c (extract_w6): Fix extending the sign.
1233
1234 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1235
1236         * arc-tbl.h (vewt): Allow it for ARC EM family.
1237
1238 2018-07-23  Alan Modra  <amodra@gmail.com>
1239
1240         PR 23419
1241         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1242         opcode variants for mtspr/mfspr encodings.
1243
1244 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1245             Maciej W. Rozycki  <macro@mips.com>
1246
1247         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1248         loongson3a descriptors.
1249         (parse_mips_ase_option): Handle -M loongson-mmi option.
1250         (print_mips_disassembler_options): Document -M loongson-mmi.
1251         * mips-opc.c (LMMI): New macro.
1252         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1253         instructions.
1254
1255 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1256
1257         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1258         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1259         IgnoreSize and [XYZ]MMword where applicable.
1260         * i386-tbl.h: Re-generate.
1261
1262 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1263
1264         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1265         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1266         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1267         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1268         * i386-tbl.h: Re-generate.
1269
1270 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1271
1272         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1273         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1274         VPCLMULQDQ templates into their respective AVX512VL counterparts
1275         where possible, using Disp8ShiftVL and CheckRegSize instead of
1276         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1277         * i386-tbl.h: Re-generate.
1278
1279 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1280
1281         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1282         AVX512VL counterparts where possible, using Disp8ShiftVL and
1283         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1284         IgnoreSize) as appropriate.
1285         * i386-tbl.h: Re-generate.
1286
1287 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1288
1289         * i386-opc.tbl: Fold AVX512BW templates into their respective
1290         AVX512VL counterparts where possible, using Disp8ShiftVL and
1291         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1292         IgnoreSize) as appropriate.
1293         * i386-tbl.h: Re-generate.
1294
1295 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1296
1297         * i386-opc.tbl: Fold AVX512CD templates into their respective
1298         AVX512VL counterparts where possible, using Disp8ShiftVL and
1299         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1300         IgnoreSize) as appropriate.
1301         * i386-tbl.h: Re-generate.
1302
1303 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1304
1305         * i386-opc.h (DISP8_SHIFT_VL): New.
1306         * i386-opc.tbl (Disp8ShiftVL):  Define.
1307         (various): Fold AVX512VL templates into their respective
1308         AVX512F counterparts where possible, using Disp8ShiftVL and
1309         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1310         IgnoreSize) as appropriate.
1311         * i386-tbl.h: Re-generate.
1312
1313 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1314
1315         * Makefile.am: Change dependencies and rule for
1316         $(srcdir)/i386-init.h.
1317         * Makefile.in: Re-generate.
1318         * i386-gen.c (process_i386_opcodes): New local variable
1319         "marker". Drop opening of input file. Recognize marker and line
1320         number directives.
1321         * i386-opc.tbl (OPCODE_I386_H): Define.
1322         (i386-opc.h): Include it.
1323         (None): Undefine.
1324
1325 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1326
1327         PR gas/23418
1328         * i386-opc.h (Byte): Update comments.
1329         (Word): Likewise.
1330         (Dword): Likewise.
1331         (Fword): Likewise.
1332         (Qword): Likewise.
1333         (Tbyte): Likewise.
1334         (Xmmword): Likewise.
1335         (Ymmword): Likewise.
1336         (Zmmword): Likewise.
1337         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1338         vcvttps2uqq.
1339         * i386-tbl.h: Regenerated.
1340
1341 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1342
1343         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1344         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1345         * aarch64-asm-2.c: Regenerate.
1346         * aarch64-dis-2.c: Regenerate.
1347         * aarch64-opc-2.c: Regenerate.
1348
1349 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1350
1351         PR binutils/23192
1352         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1353         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1354         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1355         sqdmulh, sqrdmulh): Use Em16.
1356
1357 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1358
1359         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1360         csdb together with them.
1361         (thumb32_opcodes): Likewise.
1362
1363 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1364
1365         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1366         requiring 32-bit registers as operands 2 and 3. Improve
1367         comments.
1368         (mwait, mwaitx): Fold templates. Improve comments.
1369         OPERAND_TYPE_INOUTPORTREG.
1370         * i386-tbl.h: Re-generate.
1371
1372 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1373
1374         * i386-gen.c (operand_type_init): Remove
1375         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1376         OPERAND_TYPE_INOUTPORTREG.
1377         * i386-init.h: Re-generate.
1378
1379 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1380
1381         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1382         (wrssq, wrussq): Add Qword.
1383         * i386-tbl.h: Re-generate.
1384
1385 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1386
1387         * i386-opc.h: Rename OTMax to OTNum.
1388         (OTNumOfUints): Adjust calculation.
1389         (OTUnused): Directly alias to OTNum.
1390
1391 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1392
1393         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1394         `reg_xys'.
1395         (lea_reg_xys): Likewise.
1396         (print_insn_loop_primitive): Rename `reg' local variable to
1397         `reg_dxy'.
1398
1399 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1400
1401         PR binutils/23242
1402         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1403
1404 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1405
1406         PR binutils/23369
1407         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1408         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1409
1410 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1411
1412         PR tdep/8282
1413         * mips-dis.c (mips_option_arg_t): New enumeration.
1414         (mips_options): New variable.
1415         (disassembler_options_mips): New function.
1416         (print_mips_disassembler_options): Reimplement in terms of
1417         `disassembler_options_mips'.
1418         * arm-dis.c (disassembler_options_arm): Adapt to using the
1419         `disasm_options_and_args_t' structure.
1420         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1421         * s390-dis.c (disassembler_options_s390): Likewise.
1422
1423 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1424
1425         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1426         expected result.
1427         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1428         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1429         * testsuite/ld-arm/tls-longplt.d: Likewise.
1430
1431 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1432
1433         PR binutils/23192
1434         * aarch64-asm-2.c: Regenerate.
1435         * aarch64-dis-2.c: Likewise.
1436         * aarch64-opc-2.c: Likewise.
1437         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1438         * aarch64-opc.c (operand_general_constraint_met_p,
1439         aarch64_print_operand): Likewise.
1440         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1441         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1442         fmlal2, fmlsl2.
1443         (AARCH64_OPERANDS): Add Em2.
1444
1445 2018-06-26  Nick Clifton  <nickc@redhat.com>
1446
1447         * po/uk.po: Updated Ukranian translation.
1448         * po/de.po: Updated German translation.
1449         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1450
1451 2018-06-26  Nick Clifton  <nickc@redhat.com>
1452
1453         * nfp-dis.c: Fix spelling mistake.
1454
1455 2018-06-24  Nick Clifton  <nickc@redhat.com>
1456
1457         * configure: Regenerate.
1458         * po/opcodes.pot: Regenerate.
1459
1460 2018-06-24  Nick Clifton  <nickc@redhat.com>
1461
1462         2.31 branch created.
1463
1464 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1465
1466         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1467         * aarch64-asm-2.c: Regenerate.
1468         * aarch64-dis-2.c: Likewise.
1469
1470 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1471
1472         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1473         `-M ginv' option description.
1474
1475 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1476
1477         PR gas/23305
1478         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1479         la and lla.
1480
1481 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1482
1483         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1484         * configure.ac: Remove AC_PREREQ.
1485         * Makefile.in: Re-generate.
1486         * aclocal.m4: Re-generate.
1487         * configure: Re-generate.
1488
1489 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1490
1491         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1492         mips64r6 descriptors.
1493         (parse_mips_ase_option): Handle -Mginv option.
1494         (print_mips_disassembler_options): Document -Mginv.
1495         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1496         (GINV): New macro.
1497         (mips_opcodes): Define ginvi and ginvt.
1498
1499 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1500             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1501
1502         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1503         * mips-opc.c (CRC, CRC64): New macros.
1504         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1505         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1506         crc32cd for CRC64.
1507
1508 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1509
1510         PR 20319
1511         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1512         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1513
1514 2018-06-06  Alan Modra  <amodra@gmail.com>
1515
1516         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1517         setjmp.  Move init for some other vars later too.
1518
1519 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1520
1521         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1522         (dis_private): Add new fields for property section tracking.
1523         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1524         (xtensa_instruction_fits): New functions.
1525         (fetch_data): Bump minimal fetch size to 4.
1526         (print_insn_xtensa): Make struct dis_private static.
1527         Load and prepare property table on section change.
1528         Don't disassemble literals. Don't disassemble instructions that
1529         cross property table boundaries.
1530
1531 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1532
1533         * configure: Regenerated.
1534
1535 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1536
1537         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1538         * i386-tbl.h: Re-generate.
1539
1540 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1541
1542         * i386-opc.tbl (sldt, str): Add NoRex64.
1543         * i386-tbl.h: Re-generate.
1544
1545 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1546
1547         * i386-opc.tbl (invpcid): Add Oword.
1548         * i386-tbl.h: Re-generate.
1549
1550 2018-06-01  Alan Modra  <amodra@gmail.com>
1551
1552         * sysdep.h (_bfd_error_handler): Don't declare.
1553         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1554         * rl78-decode.opc: Likewise.
1555         * msp430-decode.c: Regenerate.
1556         * rl78-decode.c: Regenerate.
1557
1558 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1559
1560         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1561         * i386-init.h : Regenerated.
1562
1563 2018-05-25  Alan Modra  <amodra@gmail.com>
1564
1565         * Makefile.in: Regenerate.
1566         * po/POTFILES.in: Regenerate.
1567
1568 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1569
1570         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1571         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1572         (insert_bab, extract_bab, insert_btab, extract_btab,
1573         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1574         (BAT, BBA VBA RBS XB6S): Delete macros.
1575         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1576         (BB, BD, RBX, XC6): Update for new macros.
1577         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1578         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1579         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1580         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1581
1582 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1583
1584         * Makefile.am: Add support for s12z architecture.
1585         * configure.ac: Likewise.
1586         * disassemble.c: Likewise.
1587         * disassemble.h: Likewise.
1588         * Makefile.in: Regenerate.
1589         * configure: Regenerate.
1590         * s12z-dis.c: New file.
1591         * s12z.h: New file.
1592
1593 2018-05-18  Alan Modra  <amodra@gmail.com>
1594
1595         * nfp-dis.c: Don't #include libbfd.h.
1596         (init_nfp3200_priv): Use bfd_get_section_contents.
1597         (nit_nfp6000_mecsr_sec): Likewise.
1598
1599 2018-05-17  Nick Clifton  <nickc@redhat.com>
1600
1601         * po/zh_CN.po: Updated simplified Chinese translation.
1602
1603 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1604
1605         PR binutils/23109
1606         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1607         * aarch64-dis-2.c: Regenerate.
1608
1609 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1610
1611         PR binutils/21446
1612         * aarch64-asm.c (opintl.h): Include.
1613         (aarch64_ins_sysreg): Enforce read/write constraints.
1614         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1615         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1616         (F_REG_READ, F_REG_WRITE): New.
1617         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1618         AARCH64_OPND_SYSREG.
1619         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1620         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1621         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1622         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1623         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1624         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1625         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1626         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1627         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1628         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1629         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1630         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1631         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1632         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1633         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1634         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1635         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1636
1637 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1638
1639         PR binutils/21446
1640         * aarch64-dis.c (no_notes: New.
1641         (parse_aarch64_dis_option): Support notes.
1642         (aarch64_decode_insn, print_operands): Likewise.
1643         (print_aarch64_disassembler_options): Document notes.
1644         * aarch64-opc.c (aarch64_print_operand): Support notes.
1645
1646 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1647
1648         PR binutils/21446
1649         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1650         and take error struct.
1651         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1652         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1653         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1654         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1655         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1656         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1657         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1658         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1659         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1660         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1661         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1662         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1663         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1664         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1665         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1666         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1667         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1668         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1669         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1670         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1671         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1672         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1673         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1674         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1675         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1676         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1677         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1678         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1679         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1680         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1681         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1682         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1683         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1684         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1685         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1686         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1687         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1688         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1689         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1690         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1691         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1692         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1693         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1694         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1695         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1696         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1697         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1698         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1699         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1700         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1701         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1702         (determine_disassembling_preference, aarch64_decode_insn,
1703         print_insn_aarch64_word, print_insn_data): Take errors struct.
1704         (print_insn_aarch64): Use errors.
1705         * aarch64-asm-2.c: Regenerate.
1706         * aarch64-dis-2.c: Regenerate.
1707         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1708         boolean in aarch64_insert_operan.
1709         (print_operand_extractor): Likewise.
1710         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1711
1712 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1713
1714         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1715
1716 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1717
1718         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1719
1720 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1721
1722         * cr16-opc.c (cr16_instruction): Comment typo fix.
1723         * hppa-dis.c (print_insn_hppa): Likewise.
1724
1725 2018-05-08  Jim Wilson  <jimw@sifive.com>
1726
1727         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1728         (match_c_slli64, match_srxi_as_c_srxi): New.
1729         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1730         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1731         <c.slli, c.srli, c.srai>: Use match_s_slli.
1732         <c.slli64, c.srli64, c.srai64>: New.
1733
1734 2018-05-08  Alan Modra  <amodra@gmail.com>
1735
1736         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1737         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1738         partition opcode space for index lookup.
1739
1740 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1741
1742         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1743         <insn_length>: ...with this.  Update usage.
1744         Remove duplicate call to *info->memory_error_func.
1745
1746 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1747             H.J. Lu  <hongjiu.lu@intel.com>
1748
1749         * i386-dis.c (Gva): New.
1750         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1751         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1752         (prefix_table): New instructions (see prefix above).
1753         (mod_table): New instructions (see prefix above).
1754         (OP_G): Handle va_mode.
1755         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1756         CPU_MOVDIR64B_FLAGS.
1757         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1758         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1759         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1760         * i386-opc.tbl: Add movidir{i,64b}.
1761         * i386-init.h: Regenerated.
1762         * i386-tbl.h: Likewise.
1763
1764 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1765
1766         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1767         AddrPrefixOpReg.
1768         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1769         (AddrPrefixOpReg): This.
1770         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1771         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1772
1773 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1774
1775         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1776         (vle_num_opcodes): Likewise.
1777         (spe2_num_opcodes): Likewise.
1778         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1779         initialization loop.
1780         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1781         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1782         only once.
1783
1784 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1785
1786         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1787
1788 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1789
1790         Makefile.am: Added nfp-dis.c.
1791         configure.ac: Added bfd_nfp_arch.
1792         disassemble.h: Added print_insn_nfp prototype.
1793         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1794         nfp-dis.c: New, for NFP support.
1795         po/POTFILES.in: Added nfp-dis.c to the list.
1796         Makefile.in: Regenerate.
1797         configure: Regenerate.
1798
1799 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1800
1801         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1802         templates into their base ones.
1803         * i386-tlb.h: Re-generate.
1804
1805 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1806
1807         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1808         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1809         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1810         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1811         * i386-init.h: Re-generate.
1812
1813 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1814
1815         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1816         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1817         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1818         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1819         comment.
1820         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1821         and CpuRegMask.
1822         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1823         CpuRegMask: Delete.
1824         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1825         cpuregzmm, and cpuregmask.
1826         * i386-init.h: Re-generate.
1827         * i386-tbl.h: Re-generate.
1828
1829 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1830
1831         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1832         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1833         * i386-init.h: Re-generate.
1834
1835 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1836
1837         * i386-gen.c (VexImmExt): Delete.
1838         * i386-opc.h (VexImmExt, veximmext): Delete.
1839         * i386-opc.tbl: Drop all VexImmExt uses.
1840         * i386-tlb.h: Re-generate.
1841
1842 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1843
1844         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1845         register-only forms.
1846         * i386-tlb.h: Re-generate.
1847
1848 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1849
1850         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1851
1852 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1853
1854         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1855         PREFIX_0F1C.
1856         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1857         (cpu_flags): Add CpuCLDEMOTE.
1858         * i386-init.h: Regenerate.
1859         * i386-opc.h (enum): Add CpuCLDEMOTE,
1860         (i386_cpu_flags): Add cpucldemote.
1861         * i386-opc.tbl: Add cldemote.
1862         * i386-tbl.h: Regenerate.
1863
1864 2018-04-16  Alan Modra  <amodra@gmail.com>
1865
1866         * Makefile.am: Remove sh5 and sh64 support.
1867         * configure.ac: Likewise.
1868         * disassemble.c: Likewise.
1869         * disassemble.h: Likewise.
1870         * sh-dis.c: Likewise.
1871         * sh64-dis.c: Delete.
1872         * sh64-opc.c: Delete.
1873         * sh64-opc.h: Delete.
1874         * Makefile.in: Regenerate.
1875         * configure: Regenerate.
1876         * po/POTFILES.in: Regenerate.
1877
1878 2018-04-16  Alan Modra  <amodra@gmail.com>
1879
1880         * Makefile.am: Remove w65 support.
1881         * configure.ac: Likewise.
1882         * disassemble.c: Likewise.
1883         * disassemble.h: Likewise.
1884         * w65-dis.c: Delete.
1885         * w65-opc.h: Delete.
1886         * Makefile.in: Regenerate.
1887         * configure: Regenerate.
1888         * po/POTFILES.in: Regenerate.
1889
1890 2018-04-16  Alan Modra  <amodra@gmail.com>
1891
1892         * configure.ac: Remove we32k support.
1893         * configure: Regenerate.
1894
1895 2018-04-16  Alan Modra  <amodra@gmail.com>
1896
1897         * Makefile.am: Remove m88k support.
1898         * configure.ac: Likewise.
1899         * disassemble.c: Likewise.
1900         * disassemble.h: Likewise.
1901         * m88k-dis.c: Delete.
1902         * Makefile.in: Regenerate.
1903         * configure: Regenerate.
1904         * po/POTFILES.in: Regenerate.
1905
1906 2018-04-16  Alan Modra  <amodra@gmail.com>
1907
1908         * Makefile.am: Remove i370 support.
1909         * configure.ac: Likewise.
1910         * disassemble.c: Likewise.
1911         * disassemble.h: Likewise.
1912         * i370-dis.c: Delete.
1913         * i370-opc.c: Delete.
1914         * Makefile.in: Regenerate.
1915         * configure: Regenerate.
1916         * po/POTFILES.in: Regenerate.
1917
1918 2018-04-16  Alan Modra  <amodra@gmail.com>
1919
1920         * Makefile.am: Remove h8500 support.
1921         * configure.ac: Likewise.
1922         * disassemble.c: Likewise.
1923         * disassemble.h: Likewise.
1924         * h8500-dis.c: Delete.
1925         * h8500-opc.h: Delete.
1926         * Makefile.in: Regenerate.
1927         * configure: Regenerate.
1928         * po/POTFILES.in: Regenerate.
1929
1930 2018-04-16  Alan Modra  <amodra@gmail.com>
1931
1932         * configure.ac: Remove tahoe support.
1933         * configure: Regenerate.
1934
1935 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1936
1937         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1938         umwait.
1939         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1940         64-bit mode.
1941         * i386-tbl.h: Regenerated.
1942
1943 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1944
1945         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1946         PREFIX_MOD_1_0FAE_REG_6.
1947         (va_mode): New.
1948         (OP_E_register): Use va_mode.
1949         * i386-dis-evex.h (prefix_table):
1950         New instructions (see prefixes above).
1951         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1952         (cpu_flags): Likewise.
1953         * i386-opc.h (enum): Likewise.
1954         (i386_cpu_flags): Likewise.
1955         * i386-opc.tbl: Add umonitor, umwait, tpause.
1956         * i386-init.h: Regenerate.
1957         * i386-tbl.h: Likewise.
1958
1959 2018-04-11  Alan Modra  <amodra@gmail.com>
1960
1961         * opcodes/i860-dis.c: Delete.
1962         * opcodes/i960-dis.c: Delete.
1963         * Makefile.am: Remove i860 and i960 support.
1964         * configure.ac: Likewise.
1965         * disassemble.c: Likewise.
1966         * disassemble.h: Likewise.
1967         * Makefile.in: Regenerate.
1968         * configure: Regenerate.
1969         * po/POTFILES.in: Regenerate.
1970
1971 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1972
1973         PR binutils/23025
1974         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1975         to 0.
1976         (print_insn): Clear vex instead of vex.evex.
1977
1978 2018-04-04  Nick Clifton  <nickc@redhat.com>
1979
1980         * po/es.po: Updated Spanish translation.
1981
1982 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1983
1984         * i386-gen.c (opcode_modifiers): Delete VecESize.
1985         * i386-opc.h (VecESize): Delete.
1986         (struct i386_opcode_modifier): Delete vecesize.
1987         * i386-opc.tbl: Drop VecESize.
1988         * i386-tlb.h: Re-generate.
1989
1990 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1991
1992         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1993         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1994         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1995         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1996         * i386-tlb.h: Re-generate.
1997
1998 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1999
2000         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2001         Fold AVX512 forms
2002         * i386-tlb.h: Re-generate.
2003
2004 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2005
2006         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2007         (vex_len_table): Drop Y for vcvt*2si.
2008         (putop): Replace plain 'Y' handling by abort().
2009
2010 2018-03-28  Nick Clifton  <nickc@redhat.com>
2011
2012         PR 22988
2013         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2014         instructions with only a base address register.
2015         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2016         handle AARHC64_OPND_SVE_ADDR_R.
2017         (aarch64_print_operand): Likewise.
2018         * aarch64-asm-2.c: Regenerate.
2019         * aarch64_dis-2.c: Regenerate.
2020         * aarch64-opc-2.c: Regenerate.
2021
2022 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2023
2024         * i386-opc.tbl: Drop VecESize from register only insn forms and
2025         memory forms not allowing broadcast.
2026         * i386-tlb.h: Re-generate.
2027
2028 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2029
2030         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2031         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2032         sha256*): Drop Disp<N>.
2033
2034 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2035
2036         * i386-dis.c (EbndS, bnd_swap_mode): New.
2037         (prefix_table): Use EbndS.
2038         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2039         * i386-opc.tbl (bndmov): Move misplaced Load.
2040         * i386-tlb.h: Re-generate.
2041
2042 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2043
2044         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2045         templates allowing memory operands and folded ones for register
2046         only flavors.
2047         * i386-tlb.h: Re-generate.
2048
2049 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2050
2051         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2052         256-bit templates. Drop redundant leftover Disp<N>.
2053         * i386-tlb.h: Re-generate.
2054
2055 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
2056
2057         * riscv-opc.c (riscv_insn_types): New.
2058
2059 2018-03-13  Nick Clifton  <nickc@redhat.com>
2060
2061         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2062
2063 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2064
2065         * i386-opc.tbl: Add Optimize to clr.
2066         * i386-tbl.h: Regenerated.
2067
2068 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2069
2070         * i386-gen.c (opcode_modifiers): Remove OldGcc.
2071         * i386-opc.h (OldGcc): Removed.
2072         (i386_opcode_modifier): Remove oldgcc.
2073         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2074         instructions for old (<= 2.8.1) versions of gcc.
2075         * i386-tbl.h: Regenerated.
2076
2077 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2078
2079         * i386-opc.h (EVEXDYN): New.
2080         * i386-opc.tbl: Fold various AVX512VL templates.
2081         * i386-tlb.h: Re-generate.
2082
2083 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2084
2085         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2086         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2087         vpexpandd, vpexpandq): Fold AFX512VF templates.
2088         * i386-tlb.h: Re-generate.
2089
2090 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2091
2092         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2093         Fold 128- and 256-bit VEX-encoded templates.
2094         * i386-tlb.h: Re-generate.
2095
2096 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2097
2098         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2099         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2100         vpexpandd, vpexpandq): Fold AVX512F templates.
2101         * i386-tlb.h: Re-generate.
2102
2103 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2104
2105         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2106         64-bit templates. Drop Disp<N>.
2107         * i386-tlb.h: Re-generate.
2108
2109 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2110
2111         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2112         and 256-bit templates.
2113         * i386-tlb.h: Re-generate.
2114
2115 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2116
2117         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2118         * i386-tlb.h: Re-generate.
2119
2120 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2121
2122         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2123         Drop NoAVX.
2124         * i386-tlb.h: Re-generate.
2125
2126 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2127
2128         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2129         * i386-tlb.h: Re-generate.
2130
2131 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2132
2133         * i386-gen.c (opcode_modifiers): Delete FloatD.
2134         * i386-opc.h (FloatD): Delete.
2135         (struct i386_opcode_modifier): Delete floatd.
2136         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2137         FloatD by D.
2138         * i386-tlb.h: Re-generate.
2139
2140 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2141
2142         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2143
2144 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2145
2146         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2147         * i386-tlb.h: Re-generate.
2148
2149 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2150
2151         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2152         forms.
2153         * i386-tlb.h: Re-generate.
2154
2155 2018-03-07  Alan Modra  <amodra@gmail.com>
2156
2157         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2158         bfd_arch_rs6000.
2159         * disassemble.h (print_insn_rs6000): Delete.
2160         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2161         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2162         (print_insn_rs6000): Delete.
2163
2164 2018-03-03  Alan Modra  <amodra@gmail.com>
2165
2166         * sysdep.h (opcodes_error_handler): Define.
2167         (_bfd_error_handler): Declare.
2168         * Makefile.am: Remove stray #.
2169         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2170         EDIT" comment.
2171         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2172         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2173         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2174         opcodes_error_handler to print errors.  Standardize error messages.
2175         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2176         and include opintl.h.
2177         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2178         * i386-gen.c: Standardize error messages.
2179         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2180         * Makefile.in: Regenerate.
2181         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2182         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2183         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2184         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2185         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2186         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2187         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2188         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2189         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2190         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2191         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2192         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2193         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2194
2195 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2196
2197         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2198         vpsub[bwdq] instructions.
2199         * i386-tbl.h: Regenerated.
2200
2201 2018-03-01  Alan Modra  <amodra@gmail.com>
2202
2203         * configure.ac (ALL_LINGUAS): Sort.
2204         * configure: Regenerate.
2205
2206 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2207
2208         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2209         macro by assignements.
2210
2211 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2212
2213         PR gas/22871
2214         * i386-gen.c (opcode_modifiers): Add Optimize.
2215         * i386-opc.h (Optimize): New enum.
2216         (i386_opcode_modifier): Add optimize.
2217         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2218         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2219         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2220         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2221         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2222         vpxord and vpxorq.
2223         * i386-tbl.h: Regenerated.
2224
2225 2018-02-26  Alan Modra  <amodra@gmail.com>
2226
2227         * crx-dis.c (getregliststring): Allocate a large enough buffer
2228         to silence false positive gcc8 warning.
2229
2230 2018-02-22  Shea Levy <shea@shealevy.com>
2231
2232         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2233
2234 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2235
2236         * i386-opc.tbl: Add {rex},
2237         * i386-tbl.h: Regenerated.
2238
2239 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2240
2241         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2242         (mips16_opcodes): Replace `M' with `m' for "restore".
2243
2244 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2245
2246         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2247
2248 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2249
2250         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2251         variable to `function_index'.
2252
2253 2018-02-13  Nick Clifton  <nickc@redhat.com>
2254
2255         PR 22823
2256         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2257         about truncation of printing.
2258
2259 2018-02-12  Henry Wong <henry@stuffedcow.net>
2260
2261         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2262
2263 2018-02-05  Nick Clifton  <nickc@redhat.com>
2264
2265         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2266
2267 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2268
2269         * i386-dis.c (enum): Add pconfig.
2270         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2271         (cpu_flags): Add CpuPCONFIG.
2272         * i386-opc.h (enum): Add CpuPCONFIG.
2273         (i386_cpu_flags): Add cpupconfig.
2274         * i386-opc.tbl: Add PCONFIG instruction.
2275         * i386-init.h: Regenerate.
2276         * i386-tbl.h: Likewise.
2277
2278 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2279
2280         * i386-dis.c (enum): Add PREFIX_0F09.
2281         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2282         (cpu_flags): Add CpuWBNOINVD.
2283         * i386-opc.h (enum): Add CpuWBNOINVD.
2284         (i386_cpu_flags): Add cpuwbnoinvd.
2285         * i386-opc.tbl: Add WBNOINVD instruction.
2286         * i386-init.h: Regenerate.
2287         * i386-tbl.h: Likewise.
2288
2289 2018-01-17  Jim Wilson  <jimw@sifive.com>
2290
2291         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2292
2293 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2294
2295         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2296         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2297         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2298         (cpu_flags): Add CpuIBT, CpuSHSTK.
2299         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2300         (i386_cpu_flags): Add cpuibt, cpushstk.
2301         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2302         * i386-init.h: Regenerate.
2303         * i386-tbl.h: Likewise.
2304
2305 2018-01-16  Nick Clifton  <nickc@redhat.com>
2306
2307         * po/pt_BR.po: Updated Brazilian Portugese translation.
2308         * po/de.po: Updated German translation.
2309
2310 2018-01-15  Jim Wilson  <jimw@sifive.com>
2311
2312         * riscv-opc.c (match_c_nop): New.
2313         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2314
2315 2018-01-15  Nick Clifton  <nickc@redhat.com>
2316
2317         * po/uk.po: Updated Ukranian translation.
2318
2319 2018-01-13  Nick Clifton  <nickc@redhat.com>
2320
2321         * po/opcodes.pot: Regenerated.
2322
2323 2018-01-13  Nick Clifton  <nickc@redhat.com>
2324
2325         * configure: Regenerate.
2326
2327 2018-01-13  Nick Clifton  <nickc@redhat.com>
2328
2329         2.30 branch created.
2330
2331 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2332
2333         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2334         * i386-tbl.h: Regenerate.
2335
2336 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2337
2338         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2339         * i386-tbl.h: Re-generate.
2340
2341 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2342
2343         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2344         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2345         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2346         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2347         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2348         Disp8MemShift of AVX512VL forms.
2349         * i386-tbl.h: Re-generate.
2350
2351 2018-01-09  Jim Wilson  <jimw@sifive.com>
2352
2353         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2354         then the hi_addr value is zero.
2355
2356 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2357
2358         * arm-dis.c (arm_opcodes): Add csdb.
2359         (thumb32_opcodes): Add csdb.
2360
2361 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2362
2363         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2364         * aarch64-asm-2.c: Regenerate.
2365         * aarch64-dis-2.c: Regenerate.
2366         * aarch64-opc-2.c: Regenerate.
2367
2368 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2369
2370         PR gas/22681
2371         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2372         Remove AVX512 vmovd with 64-bit operands.
2373         * i386-tbl.h: Regenerated.
2374
2375 2018-01-05  Jim Wilson  <jimw@sifive.com>
2376
2377         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2378         jalr.
2379
2380 2018-01-03  Alan Modra  <amodra@gmail.com>
2381
2382         Update year range in copyright notice of all files.
2383
2384 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2385
2386         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2387         and OPERAND_TYPE_REGZMM entries.
2388
2389 For older changes see ChangeLog-2017
2390 \f
2391 Copyright (C) 2018 Free Software Foundation, Inc.
2392
2393 Copying and distribution of this file, with or without modification,
2394 are permitted in any medium without royalty provided the copyright
2395 notice and this notice are preserved.
2396
2397 Local Variables:
2398 mode: change-log
2399 left-margin: 8
2400 fill-column: 74
2401 version-control: never
2402 End: