opcodes/ChangeLog

   1 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
   4         * i386-tbl.h: Re-generate.
   5
   6 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
   9         meaningless.
  10         * i386-tbl.h: Re-generate.
  11
  12 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  13
  14         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
  15         meaningless.
  16         * i386-tbl.h: Re-generate.
  17
  18 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  19
  20         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
  21         * i386-tbl.h: Re-generate.
  22
  23 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
  26         * i386-tbl.h: Re-generate.
  27
  28 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
  31         * i386-tbl.h: Re-generate.
  32
  33 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
  36         meaningless.
  37         * i386-tbl.h: Re-generate.
  38
  39 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
  42         meaningless.
  43         * i386-tbl.h: Re-generate.
  44
  45 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
  48         meaningless.
  49         * i386-tbl.h: Re-generate.
  50
  51 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
  54         * i386-tbl.h: Re-generate.
  55
  56 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  57
  58         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
  59         * i386-tbl.h: Re-generate.
  60
  61 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  62
  63         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
  64         * i386-tbl.h: Re-generate.
  65
  66 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
  69         (vpbroadcastw, rdpid): Drop NoRex64.
  70         * i386-tbl.h: Re-generate.
  71
  72 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
  75         store templates, adding D.
  76         * i386-tbl.h: Re-generate.
  77
  78 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  79
  80         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
  81         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
  82         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
  83         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
  84         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
  85         Fold load and store templates where possible, adding D. Drop
  86         IgnoreSize where it was pointlessly present. Drop redundant
  87         *word.
  88         * i386-tbl.h: Re-generate.
  89
  90 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
  93         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
  94         (intel_operand_size): Handle v_bndmk_mode.
  95         (OP_E_memory): Likewise. Produce (bad) when also riprel.
  96
  97 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
  98
  99         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 100
 101 2018-08-31  Kito Cheng  <kito@andestech.com>
 102
 103         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 104         compressed floating point instructions.
 105
 106 2018-08-30  Kito Cheng  <kito@andestech.com>
 107
 108         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 109         riscv_opcode.xlen_requirement.
 110         * riscv-opc.c (riscv_opcodes): Update for struct change.
 111
 112 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 113
 114         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 115         psr (PWRPSR) instruction.
 116
 117 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 118
 119         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 120
 121 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 122
 123         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 124
 125 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 126
 127         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 128         loongson3a as an alias of gs464 for compatibility.
 129         * mips-opc.c (mips_opcodes): Change Comments.
 130
 131 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 132
 133         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 134         option.
 135         (print_mips_disassembler_options): Document -M loongson-ext.
 136         * mips-opc.c (LEXT2): New macro.
 137         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 138
 139 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 140
 141          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 142          descriptors.
 143          (parse_mips_ase_option): Handle -M loongson-ext option.
 144          (print_mips_disassembler_options): Document -M loongson-ext.
 145          * mips-opc.c (IL3A): Delete.
 146          * mips-opc.c (LEXT): New macro.
 147          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 148          instructions.
 149
 150 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 151
 152         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 153         descriptors.
 154         (parse_mips_ase_option): Handle -M loongson-cam option.
 155         (print_mips_disassembler_options): Document -M loongson-cam.
 156         * mips-opc.c (LCAM): New macro.
 157         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 158         instructions.
 159
 160 2018-08-21  Alan Modra  <amodra@gmail.com>
 161
 162         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 163         (skip_optional_operands): Count optional operands, and update
 164         ppc_optional_operand_value call.
 165         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 166         (extract_vlensi): Likewise.
 167         (extract_fxm): Return default value for missing optional operand.
 168         (extract_ls, extract_raq, extract_tbr): Likewise.
 169         (insert_sxl, extract_sxl): New functions.
 170         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 171         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 172         flag and extra entry.
 173         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 174         extract_sxl.
 175
 176 2018-08-20  Alan Modra  <amodra@gmail.com>
 177
 178         * sh-opc.h (MASK): Simplify.
 179
 180 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 181
 182         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 183         BM_RESERVED0 or BM_RESERVED1
 184         (bm_rel_decode, bm_n_bytes): Ditto.
 185
 186 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 187
 188         * s12z.h: Delete.
 189
 190 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 191
 192         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 193         address with the addr32 prefix and without base nor index
 194         registers.
 195
 196 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 197
 198         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 199         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 200         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 201         (cpu_flags): Add CpuCMOV and CpuFXSR.
 202         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 203         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 204         * i386-init.h: Regenerated.
 205         * i386-tbl.h: Likewise.
 206
 207 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 208
 209         * arc-regs.h: Update auxiliary registers.
 210
 211 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 212
 213         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 214         (RegIP, RegIZ): Define.
 215         * i386-reg.tbl: Adjust comments.
 216         (rip): Use Qword instead of BaseIndex. Use RegIP.
 217         (eip): Use Dword instead of BaseIndex. Use RegIP.
 218         (riz): Add Qword. Use RegIZ.
 219         (eiz): Add Dword. Use RegIZ.
 220         * i386-tbl.h: Re-generate.
 221
 222 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 223
 224         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 225         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 226         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 227         * i386-tbl.h: Re-generate.
 228
 229 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-gen.c (operand_types): Remove Mem field.
 232         * i386-opc.h (union i386_operand_type): Remove mem field.
 233         * i386-init.h, i386-tbl.h: Re-generate.
 234
 235 2018-08-01  Alan Modra  <amodra@gmail.com>
 236
 237         * po/POTFILES.in: Regenerate.
 238
 239 2018-07-31  Nick Clifton  <nickc@redhat.com>
 240
 241         * po/sv.po: Updated Swedish translation.
 242
 243 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 244
 245         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 246         * i386-init.h, i386-tbl.h: Re-generate.
 247
 248 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 249
 250         * i386-opc.h (ZEROING_MASKING) Rename to ...
 251         (DYNAMIC_MASKING): ... this. Adjust comment.
 252         * i386-opc.tbl (MaskingMorZ): Define.
 253         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 254         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 255         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 256         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 257         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 258         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 259         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 260         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 261         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 262
 263 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-opc.tbl: Use element rather than vector size for AVX512*
 266         scatter/gather insns.
 267         * i386-tbl.h: Re-generate.
 268
 269 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 272         (cpu_flags): Drop CpuVREX.
 273         * i386-opc.h (CpuVREX): Delete.
 274         (union i386_cpu_flags): Remove cpuvrex.
 275         * i386-init.h, i386-tbl.h: Re-generate.
 276
 277 2018-07-30  Jim Wilson  <jimw@sifive.com>
 278
 279         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 280         fields.
 281         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 282
 283 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 284
 285         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 286         * Makefile.in: Regenerated.
 287         * configure.ac: Add C-SKY.
 288         * configure: Regenerated.
 289         * csky-dis.c: New file.
 290         * csky-opc.h: New file.
 291         * disassemble.c (ARCH_csky): Define.
 292         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 293         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 294
 295 2018-07-27  Alan Modra  <amodra@gmail.com>
 296
 297         * ppc-opc.c (insert_sprbat): Correct function parameter and
 298         return type.
 299         (extract_sprbat): Likewise, variable too.
 300
 301 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 302             Alan Modra  <amodra@gmail.com>
 303
 304         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 305         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 306         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 307         support disjointed BAT.
 308         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 309         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 310         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 311
 312 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 313             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 314
 315         * i386-gen.c (adjust_broadcast_modifier): New function.
 316         (process_i386_opcode_modifier): Add an argument for operands.
 317         Adjust the Broadcast value based on operands.
 318         (output_i386_opcode): Pass operand_types to
 319         process_i386_opcode_modifier.
 320         (process_i386_opcodes): Pass NULL as operands to
 321         process_i386_opcode_modifier.
 322         * i386-opc.h (BYTE_BROADCAST): New.
 323         (WORD_BROADCAST): Likewise.
 324         (DWORD_BROADCAST): Likewise.
 325         (QWORD_BROADCAST): Likewise.
 326         (i386_opcode_modifier): Expand broadcast to 3 bits.
 327         * i386-tbl.h: Regenerated.
 328
 329 2018-07-24  Alan Modra  <amodra@gmail.com>
 330
 331         PR 23430
 332         * or1k-desc.h: Regenerate.
 333
 334 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 335
 336         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 337         vcvtusi2ss, and vcvtusi2sd.
 338         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 339         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 340         * i386-tbl.h: Re-generate.
 341
 342 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 343
 344         * arc-opc.c (extract_w6): Fix extending the sign.
 345
 346 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 347
 348         * arc-tbl.h (vewt): Allow it for ARC EM family.
 349
 350 2018-07-23  Alan Modra  <amodra@gmail.com>
 351
 352         PR 23419
 353         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 354         opcode variants for mtspr/mfspr encodings.
 355
 356 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 357             Maciej W. Rozycki  <macro@mips.com>
 358
 359         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 360         loongson3a descriptors.
 361         (parse_mips_ase_option): Handle -M loongson-mmi option.
 362         (print_mips_disassembler_options): Document -M loongson-mmi.
 363         * mips-opc.c (LMMI): New macro.
 364         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 365         instructions.
 366
 367 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 368
 369         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 370         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 371         IgnoreSize and [XYZ]MMword where applicable.
 372         * i386-tbl.h: Re-generate.
 373
 374 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 375
 376         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 377         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 378         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 379         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 380         * i386-tbl.h: Re-generate.
 381
 382 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 383
 384         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 385         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 386         VPCLMULQDQ templates into their respective AVX512VL counterparts
 387         where possible, using Disp8ShiftVL and CheckRegSize instead of
 388         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 389         * i386-tbl.h: Re-generate.
 390
 391 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 392
 393         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 394         AVX512VL counterparts where possible, using Disp8ShiftVL and
 395         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 396         IgnoreSize) as appropriate.
 397         * i386-tbl.h: Re-generate.
 398
 399 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 400
 401         * i386-opc.tbl: Fold AVX512BW templates into their respective
 402         AVX512VL counterparts where possible, using Disp8ShiftVL and
 403         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 404         IgnoreSize) as appropriate.
 405         * i386-tbl.h: Re-generate.
 406
 407 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-opc.tbl: Fold AVX512CD templates into their respective
 410         AVX512VL counterparts where possible, using Disp8ShiftVL and
 411         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 412         IgnoreSize) as appropriate.
 413         * i386-tbl.h: Re-generate.
 414
 415 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-opc.h (DISP8_SHIFT_VL): New.
 418         * i386-opc.tbl (Disp8ShiftVL):  Define.
 419         (various): Fold AVX512VL templates into their respective
 420         AVX512F counterparts where possible, using Disp8ShiftVL and
 421         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 422         IgnoreSize) as appropriate.
 423         * i386-tbl.h: Re-generate.
 424
 425 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 426
 427         * Makefile.am: Change dependencies and rule for
 428         $(srcdir)/i386-init.h.
 429         * Makefile.in: Re-generate.
 430         * i386-gen.c (process_i386_opcodes): New local variable
 431         "marker". Drop opening of input file. Recognize marker and line
 432         number directives.
 433         * i386-opc.tbl (OPCODE_I386_H): Define.
 434         (i386-opc.h): Include it.
 435         (None): Undefine.
 436
 437 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         PR gas/23418
 440         * i386-opc.h (Byte): Update comments.
 441         (Word): Likewise.
 442         (Dword): Likewise.
 443         (Fword): Likewise.
 444         (Qword): Likewise.
 445         (Tbyte): Likewise.
 446         (Xmmword): Likewise.
 447         (Ymmword): Likewise.
 448         (Zmmword): Likewise.
 449         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 450         vcvttps2uqq.
 451         * i386-tbl.h: Regenerated.
 452
 453 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 454
 455         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 456         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 457         * aarch64-asm-2.c: Regenerate.
 458         * aarch64-dis-2.c: Regenerate.
 459         * aarch64-opc-2.c: Regenerate.
 460
 461 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 462
 463         PR binutils/23192
 464         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 465         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 466         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 467         sqdmulh, sqrdmulh): Use Em16.
 468
 469 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 470
 471         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 472         csdb together with them.
 473         (thumb32_opcodes): Likewise.
 474
 475 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 476
 477         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 478         requiring 32-bit registers as operands 2 and 3. Improve
 479         comments.
 480         (mwait, mwaitx): Fold templates. Improve comments.
 481         OPERAND_TYPE_INOUTPORTREG.
 482         * i386-tbl.h: Re-generate.
 483
 484 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 485
 486         * i386-gen.c (operand_type_init): Remove
 487         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 488         OPERAND_TYPE_INOUTPORTREG.
 489         * i386-init.h: Re-generate.
 490
 491 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 494         (wrssq, wrussq): Add Qword.
 495         * i386-tbl.h: Re-generate.
 496
 497 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 498
 499         * i386-opc.h: Rename OTMax to OTNum.
 500         (OTNumOfUints): Adjust calculation.
 501         (OTUnused): Directly alias to OTNum.
 502
 503 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 504
 505         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 506         `reg_xys'.
 507         (lea_reg_xys): Likewise.
 508         (print_insn_loop_primitive): Rename `reg' local variable to
 509         `reg_dxy'.
 510
 511 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 512
 513         PR binutils/23242
 514         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 515
 516 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 517
 518         PR binutils/23369
 519         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 520         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 521
 522 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 523
 524         PR tdep/8282
 525         * mips-dis.c (mips_option_arg_t): New enumeration.
 526         (mips_options): New variable.
 527         (disassembler_options_mips): New function.
 528         (print_mips_disassembler_options): Reimplement in terms of
 529         `disassembler_options_mips'.
 530         * arm-dis.c (disassembler_options_arm): Adapt to using the
 531         `disasm_options_and_args_t' structure.
 532         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 533         * s390-dis.c (disassembler_options_s390): Likewise.
 534
 535 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 536
 537         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 538         expected result.
 539         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 540         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 541         * testsuite/ld-arm/tls-longplt.d: Likewise.
 542
 543 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 544
 545         PR binutils/23192
 546         * aarch64-asm-2.c: Regenerate.
 547         * aarch64-dis-2.c: Likewise.
 548         * aarch64-opc-2.c: Likewise.
 549         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 550         * aarch64-opc.c (operand_general_constraint_met_p,
 551         aarch64_print_operand): Likewise.
 552         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 553         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 554         fmlal2, fmlsl2.
 555         (AARCH64_OPERANDS): Add Em2.
 556
 557 2018-06-26  Nick Clifton  <nickc@redhat.com>
 558
 559         * po/uk.po: Updated Ukranian translation.
 560         * po/de.po: Updated German translation.
 561         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 562
 563 2018-06-26  Nick Clifton  <nickc@redhat.com>
 564
 565         * nfp-dis.c: Fix spelling mistake.
 566
 567 2018-06-24  Nick Clifton  <nickc@redhat.com>
 568
 569         * configure: Regenerate.
 570         * po/opcodes.pot: Regenerate.
 571
 572 2018-06-24  Nick Clifton  <nickc@redhat.com>
 573
 574         2.31 branch created.
 575
 576 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 577
 578         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 579         * aarch64-asm-2.c: Regenerate.
 580         * aarch64-dis-2.c: Likewise.
 581
 582 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 583
 584         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 585         `-M ginv' option description.
 586
 587 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 588
 589         PR gas/23305
 590         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 591         la and lla.
 592
 593 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 594
 595         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 596         * configure.ac: Remove AC_PREREQ.
 597         * Makefile.in: Re-generate.
 598         * aclocal.m4: Re-generate.
 599         * configure: Re-generate.
 600
 601 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 602
 603         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 604         mips64r6 descriptors.
 605         (parse_mips_ase_option): Handle -Mginv option.
 606         (print_mips_disassembler_options): Document -Mginv.
 607         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 608         (GINV): New macro.
 609         (mips_opcodes): Define ginvi and ginvt.
 610
 611 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 612             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 613
 614         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 615         * mips-opc.c (CRC, CRC64): New macros.
 616         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 617         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 618         crc32cd for CRC64.
 619
 620 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 621
 622         PR 20319
 623         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 624         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 625
 626 2018-06-06  Alan Modra  <amodra@gmail.com>
 627
 628         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 629         setjmp.  Move init for some other vars later too.
 630
 631 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 632
 633         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 634         (dis_private): Add new fields for property section tracking.
 635         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 636         (xtensa_instruction_fits): New functions.
 637         (fetch_data): Bump minimal fetch size to 4.
 638         (print_insn_xtensa): Make struct dis_private static.
 639         Load and prepare property table on section change.
 640         Don't disassemble literals. Don't disassemble instructions that
 641         cross property table boundaries.
 642
 643 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 644
 645         * configure: Regenerated.
 646
 647 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 648
 649         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 650         * i386-tbl.h: Re-generate.
 651
 652 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-opc.tbl (sldt, str): Add NoRex64.
 655         * i386-tbl.h: Re-generate.
 656
 657 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-opc.tbl (invpcid): Add Oword.
 660         * i386-tbl.h: Re-generate.
 661
 662 2018-06-01  Alan Modra  <amodra@gmail.com>
 663
 664         * sysdep.h (_bfd_error_handler): Don't declare.
 665         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 666         * rl78-decode.opc: Likewise.
 667         * msp430-decode.c: Regenerate.
 668         * rl78-decode.c: Regenerate.
 669
 670 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 671
 672         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 673         * i386-init.h : Regenerated.
 674
 675 2018-05-25  Alan Modra  <amodra@gmail.com>
 676
 677         * Makefile.in: Regenerate.
 678         * po/POTFILES.in: Regenerate.
 679
 680 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 681
 682         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 683         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 684         (insert_bab, extract_bab, insert_btab, extract_btab,
 685         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 686         (BAT, BBA VBA RBS XB6S): Delete macros.
 687         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 688         (BB, BD, RBX, XC6): Update for new macros.
 689         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 690         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 691         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 692         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 693
 694 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 695
 696         * Makefile.am: Add support for s12z architecture.
 697         * configure.ac: Likewise.
 698         * disassemble.c: Likewise.
 699         * disassemble.h: Likewise.
 700         * Makefile.in: Regenerate.
 701         * configure: Regenerate.
 702         * s12z-dis.c: New file.
 703         * s12z.h: New file.
 704
 705 2018-05-18  Alan Modra  <amodra@gmail.com>
 706
 707         * nfp-dis.c: Don't #include libbfd.h.
 708         (init_nfp3200_priv): Use bfd_get_section_contents.
 709         (nit_nfp6000_mecsr_sec): Likewise.
 710
 711 2018-05-17  Nick Clifton  <nickc@redhat.com>
 712
 713         * po/zh_CN.po: Updated simplified Chinese translation.
 714
 715 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 716
 717         PR binutils/23109
 718         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 719         * aarch64-dis-2.c: Regenerate.
 720
 721 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 722
 723         PR binutils/21446
 724         * aarch64-asm.c (opintl.h): Include.
 725         (aarch64_ins_sysreg): Enforce read/write constraints.
 726         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 727         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 728         (F_REG_READ, F_REG_WRITE): New.
 729         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 730         AARCH64_OPND_SYSREG.
 731         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 732         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 733         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 734         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 735         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 736         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 737         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 738         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 739         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 740         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 741         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 742         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 743         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 744         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 745         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 746         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 747         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 748
 749 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 750
 751         PR binutils/21446
 752         * aarch64-dis.c (no_notes: New.
 753         (parse_aarch64_dis_option): Support notes.
 754         (aarch64_decode_insn, print_operands): Likewise.
 755         (print_aarch64_disassembler_options): Document notes.
 756         * aarch64-opc.c (aarch64_print_operand): Support notes.
 757
 758 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 759
 760         PR binutils/21446
 761         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 762         and take error struct.
 763         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 764         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 765         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 766         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 767         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 768         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 769         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 770         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 771         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 772         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 773         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 774         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 775         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 776         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 777         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 778         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 779         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 780         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 781         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 782         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 783         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 784         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 785         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 786         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 787         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 788         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 789         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 790         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 791         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 792         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 793         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 794         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 795         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 796         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 797         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 798         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 799         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 800         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 801         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 802         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 803         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 804         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 805         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 806         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 807         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 808         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 809         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 810         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 811         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 812         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 813         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 814         (determine_disassembling_preference, aarch64_decode_insn,
 815         print_insn_aarch64_word, print_insn_data): Take errors struct.
 816         (print_insn_aarch64): Use errors.
 817         * aarch64-asm-2.c: Regenerate.
 818         * aarch64-dis-2.c: Regenerate.
 819         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 820         boolean in aarch64_insert_operan.
 821         (print_operand_extractor): Likewise.
 822         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 823
 824 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 825
 826         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 827
 828 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 829
 830         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 831
 832 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 833
 834         * cr16-opc.c (cr16_instruction): Comment typo fix.
 835         * hppa-dis.c (print_insn_hppa): Likewise.
 836
 837 2018-05-08  Jim Wilson  <jimw@sifive.com>
 838
 839         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 840         (match_c_slli64, match_srxi_as_c_srxi): New.
 841         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 842         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 843         <c.slli, c.srli, c.srai>: Use match_s_slli.
 844         <c.slli64, c.srli64, c.srai64>: New.
 845
 846 2018-05-08  Alan Modra  <amodra@gmail.com>
 847
 848         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 849         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 850         partition opcode space for index lookup.
 851
 852 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 853
 854         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 855         <insn_length>: ...with this.  Update usage.
 856         Remove duplicate call to *info->memory_error_func.
 857
 858 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 859             H.J. Lu  <hongjiu.lu@intel.com>
 860
 861         * i386-dis.c (Gva): New.
 862         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 863         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 864         (prefix_table): New instructions (see prefix above).
 865         (mod_table): New instructions (see prefix above).
 866         (OP_G): Handle va_mode.
 867         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 868         CPU_MOVDIR64B_FLAGS.
 869         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 870         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 871         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 872         * i386-opc.tbl: Add movidir{i,64b}.
 873         * i386-init.h: Regenerated.
 874         * i386-tbl.h: Likewise.
 875
 876 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 877
 878         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 879         AddrPrefixOpReg.
 880         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 881         (AddrPrefixOpReg): This.
 882         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 883         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 884
 885 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 886
 887         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 888         (vle_num_opcodes): Likewise.
 889         (spe2_num_opcodes): Likewise.
 890         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 891         initialization loop.
 892         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 893         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 894         only once.
 895
 896 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 897
 898         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 899
 900 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 901
 902         Makefile.am: Added nfp-dis.c.
 903         configure.ac: Added bfd_nfp_arch.
 904         disassemble.h: Added print_insn_nfp prototype.
 905         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 906         nfp-dis.c: New, for NFP support.
 907         po/POTFILES.in: Added nfp-dis.c to the list.
 908         Makefile.in: Regenerate.
 909         configure: Regenerate.
 910
 911 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 912
 913         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 914         templates into their base ones.
 915         * i386-tlb.h: Re-generate.
 916
 917 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 918
 919         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 920         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 921         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 922         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 923         * i386-init.h: Re-generate.
 924
 925 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 926
 927         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 928         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 929         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 930         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 931         comment.
 932         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 933         and CpuRegMask.
 934         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 935         CpuRegMask: Delete.
 936         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 937         cpuregzmm, and cpuregmask.
 938         * i386-init.h: Re-generate.
 939         * i386-tbl.h: Re-generate.
 940
 941 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 942
 943         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 944         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 945         * i386-init.h: Re-generate.
 946
 947 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 948
 949         * i386-gen.c (VexImmExt): Delete.
 950         * i386-opc.h (VexImmExt, veximmext): Delete.
 951         * i386-opc.tbl: Drop all VexImmExt uses.
 952         * i386-tlb.h: Re-generate.
 953
 954 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 957         register-only forms.
 958         * i386-tlb.h: Re-generate.
 959
 960 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 961
 962         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 963
 964 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 965
 966         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 967         PREFIX_0F1C.
 968         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 969         (cpu_flags): Add CpuCLDEMOTE.
 970         * i386-init.h: Regenerate.
 971         * i386-opc.h (enum): Add CpuCLDEMOTE,
 972         (i386_cpu_flags): Add cpucldemote.
 973         * i386-opc.tbl: Add cldemote.
 974         * i386-tbl.h: Regenerate.
 975
 976 2018-04-16  Alan Modra  <amodra@gmail.com>
 977
 978         * Makefile.am: Remove sh5 and sh64 support.
 979         * configure.ac: Likewise.
 980         * disassemble.c: Likewise.
 981         * disassemble.h: Likewise.
 982         * sh-dis.c: Likewise.
 983         * sh64-dis.c: Delete.
 984         * sh64-opc.c: Delete.
 985         * sh64-opc.h: Delete.
 986         * Makefile.in: Regenerate.
 987         * configure: Regenerate.
 988         * po/POTFILES.in: Regenerate.
 989
 990 2018-04-16  Alan Modra  <amodra@gmail.com>
 991
 992         * Makefile.am: Remove w65 support.
 993         * configure.ac: Likewise.
 994         * disassemble.c: Likewise.
 995         * disassemble.h: Likewise.
 996         * w65-dis.c: Delete.
 997         * w65-opc.h: Delete.
 998         * Makefile.in: Regenerate.
 999         * configure: Regenerate.
1000         * po/POTFILES.in: Regenerate.
1001
1002 2018-04-16  Alan Modra  <amodra@gmail.com>
1003
1004         * configure.ac: Remove we32k support.
1005         * configure: Regenerate.
1006
1007 2018-04-16  Alan Modra  <amodra@gmail.com>
1008
1009         * Makefile.am: Remove m88k support.
1010         * configure.ac: Likewise.
1011         * disassemble.c: Likewise.
1012         * disassemble.h: Likewise.
1013         * m88k-dis.c: Delete.
1014         * Makefile.in: Regenerate.
1015         * configure: Regenerate.
1016         * po/POTFILES.in: Regenerate.
1017
1018 2018-04-16  Alan Modra  <amodra@gmail.com>
1019
1020         * Makefile.am: Remove i370 support.
1021         * configure.ac: Likewise.
1022         * disassemble.c: Likewise.
1023         * disassemble.h: Likewise.
1024         * i370-dis.c: Delete.
1025         * i370-opc.c: Delete.
1026         * Makefile.in: Regenerate.
1027         * configure: Regenerate.
1028         * po/POTFILES.in: Regenerate.
1029
1030 2018-04-16  Alan Modra  <amodra@gmail.com>
1031
1032         * Makefile.am: Remove h8500 support.
1033         * configure.ac: Likewise.
1034         * disassemble.c: Likewise.
1035         * disassemble.h: Likewise.
1036         * h8500-dis.c: Delete.
1037         * h8500-opc.h: Delete.
1038         * Makefile.in: Regenerate.
1039         * configure: Regenerate.
1040         * po/POTFILES.in: Regenerate.
1041
1042 2018-04-16  Alan Modra  <amodra@gmail.com>
1043
1044         * configure.ac: Remove tahoe support.
1045         * configure: Regenerate.
1046
1047 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1048
1049         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1050         umwait.
1051         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1052         64-bit mode.
1053         * i386-tbl.h: Regenerated.
1054
1055 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1056
1057         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1058         PREFIX_MOD_1_0FAE_REG_6.
1059         (va_mode): New.
1060         (OP_E_register): Use va_mode.
1061         * i386-dis-evex.h (prefix_table):
1062         New instructions (see prefixes above).
1063         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1064         (cpu_flags): Likewise.
1065         * i386-opc.h (enum): Likewise.
1066         (i386_cpu_flags): Likewise.
1067         * i386-opc.tbl: Add umonitor, umwait, tpause.
1068         * i386-init.h: Regenerate.
1069         * i386-tbl.h: Likewise.
1070
1071 2018-04-11  Alan Modra  <amodra@gmail.com>
1072
1073         * opcodes/i860-dis.c: Delete.
1074         * opcodes/i960-dis.c: Delete.
1075         * Makefile.am: Remove i860 and i960 support.
1076         * configure.ac: Likewise.
1077         * disassemble.c: Likewise.
1078         * disassemble.h: Likewise.
1079         * Makefile.in: Regenerate.
1080         * configure: Regenerate.
1081         * po/POTFILES.in: Regenerate.
1082
1083 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1084
1085         PR binutils/23025
1086         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1087         to 0.
1088         (print_insn): Clear vex instead of vex.evex.
1089
1090 2018-04-04  Nick Clifton  <nickc@redhat.com>
1091
1092         * po/es.po: Updated Spanish translation.
1093
1094 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1095
1096         * i386-gen.c (opcode_modifiers): Delete VecESize.
1097         * i386-opc.h (VecESize): Delete.
1098         (struct i386_opcode_modifier): Delete vecesize.
1099         * i386-opc.tbl: Drop VecESize.
1100         * i386-tlb.h: Re-generate.
1101
1102 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1103
1104         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1105         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1106         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1107         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1108         * i386-tlb.h: Re-generate.
1109
1110 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1111
1112         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1113         Fold AVX512 forms
1114         * i386-tlb.h: Re-generate.
1115
1116 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1117
1118         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1119         (vex_len_table): Drop Y for vcvt*2si.
1120         (putop): Replace plain 'Y' handling by abort().
1121
1122 2018-03-28  Nick Clifton  <nickc@redhat.com>
1123
1124         PR 22988
1125         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1126         instructions with only a base address register.
1127         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1128         handle AARHC64_OPND_SVE_ADDR_R.
1129         (aarch64_print_operand): Likewise.
1130         * aarch64-asm-2.c: Regenerate.
1131         * aarch64_dis-2.c: Regenerate.
1132         * aarch64-opc-2.c: Regenerate.
1133
1134 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1135
1136         * i386-opc.tbl: Drop VecESize from register only insn forms and
1137         memory forms not allowing broadcast.
1138         * i386-tlb.h: Re-generate.
1139
1140 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1141
1142         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1143         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1144         sha256*): Drop Disp<N>.
1145
1146 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1147
1148         * i386-dis.c (EbndS, bnd_swap_mode): New.
1149         (prefix_table): Use EbndS.
1150         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1151         * i386-opc.tbl (bndmov): Move misplaced Load.
1152         * i386-tlb.h: Re-generate.
1153
1154 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1155
1156         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1157         templates allowing memory operands and folded ones for register
1158         only flavors.
1159         * i386-tlb.h: Re-generate.
1160
1161 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1162
1163         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1164         256-bit templates. Drop redundant leftover Disp<N>.
1165         * i386-tlb.h: Re-generate.
1166
1167 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1168
1169         * riscv-opc.c (riscv_insn_types): New.
1170
1171 2018-03-13  Nick Clifton  <nickc@redhat.com>
1172
1173         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1174
1175 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1176
1177         * i386-opc.tbl: Add Optimize to clr.
1178         * i386-tbl.h: Regenerated.
1179
1180 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1181
1182         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1183         * i386-opc.h (OldGcc): Removed.
1184         (i386_opcode_modifier): Remove oldgcc.
1185         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1186         instructions for old (<= 2.8.1) versions of gcc.
1187         * i386-tbl.h: Regenerated.
1188
1189 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1190
1191         * i386-opc.h (EVEXDYN): New.
1192         * i386-opc.tbl: Fold various AVX512VL templates.
1193         * i386-tlb.h: Re-generate.
1194
1195 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1196
1197         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1198         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1199         vpexpandd, vpexpandq): Fold AFX512VF templates.
1200         * i386-tlb.h: Re-generate.
1201
1202 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1203
1204         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1205         Fold 128- and 256-bit VEX-encoded templates.
1206         * i386-tlb.h: Re-generate.
1207
1208 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1209
1210         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1211         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1212         vpexpandd, vpexpandq): Fold AVX512F templates.
1213         * i386-tlb.h: Re-generate.
1214
1215 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1216
1217         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1218         64-bit templates. Drop Disp<N>.
1219         * i386-tlb.h: Re-generate.
1220
1221 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1222
1223         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1224         and 256-bit templates.
1225         * i386-tlb.h: Re-generate.
1226
1227 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1228
1229         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1230         * i386-tlb.h: Re-generate.
1231
1232 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1233
1234         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1235         Drop NoAVX.
1236         * i386-tlb.h: Re-generate.
1237
1238 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1239
1240         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1241         * i386-tlb.h: Re-generate.
1242
1243 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1244
1245         * i386-gen.c (opcode_modifiers): Delete FloatD.
1246         * i386-opc.h (FloatD): Delete.
1247         (struct i386_opcode_modifier): Delete floatd.
1248         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1249         FloatD by D.
1250         * i386-tlb.h: Re-generate.
1251
1252 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1253
1254         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1255
1256 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1257
1258         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1259         * i386-tlb.h: Re-generate.
1260
1261 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1262
1263         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1264         forms.
1265         * i386-tlb.h: Re-generate.
1266
1267 2018-03-07  Alan Modra  <amodra@gmail.com>
1268
1269         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1270         bfd_arch_rs6000.
1271         * disassemble.h (print_insn_rs6000): Delete.
1272         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1273         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1274         (print_insn_rs6000): Delete.
1275
1276 2018-03-03  Alan Modra  <amodra@gmail.com>
1277
1278         * sysdep.h (opcodes_error_handler): Define.
1279         (_bfd_error_handler): Declare.
1280         * Makefile.am: Remove stray #.
1281         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1282         EDIT" comment.
1283         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1284         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1285         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1286         opcodes_error_handler to print errors.  Standardize error messages.
1287         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1288         and include opintl.h.
1289         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1290         * i386-gen.c: Standardize error messages.
1291         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1292         * Makefile.in: Regenerate.
1293         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1294         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1295         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1296         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1297         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1298         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1299         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1300         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1301         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1302         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1303         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1304         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1305         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1306
1307 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1308
1309         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1310         vpsub[bwdq] instructions.
1311         * i386-tbl.h: Regenerated.
1312
1313 2018-03-01  Alan Modra  <amodra@gmail.com>
1314
1315         * configure.ac (ALL_LINGUAS): Sort.
1316         * configure: Regenerate.
1317
1318 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1319
1320         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1321         macro by assignements.
1322
1323 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1324
1325         PR gas/22871
1326         * i386-gen.c (opcode_modifiers): Add Optimize.
1327         * i386-opc.h (Optimize): New enum.
1328         (i386_opcode_modifier): Add optimize.
1329         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1330         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1331         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1332         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1333         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1334         vpxord and vpxorq.
1335         * i386-tbl.h: Regenerated.
1336
1337 2018-02-26  Alan Modra  <amodra@gmail.com>
1338
1339         * crx-dis.c (getregliststring): Allocate a large enough buffer
1340         to silence false positive gcc8 warning.
1341
1342 2018-02-22  Shea Levy <shea@shealevy.com>
1343
1344         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1345
1346 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1347
1348         * i386-opc.tbl: Add {rex},
1349         * i386-tbl.h: Regenerated.
1350
1351 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1352
1353         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1354         (mips16_opcodes): Replace `M' with `m' for "restore".
1355
1356 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1357
1358         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1359
1360 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1361
1362         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1363         variable to `function_index'.
1364
1365 2018-02-13  Nick Clifton  <nickc@redhat.com>
1366
1367         PR 22823
1368         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1369         about truncation of printing.
1370
1371 2018-02-12  Henry Wong <henry@stuffedcow.net>
1372
1373         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1374
1375 2018-02-05  Nick Clifton  <nickc@redhat.com>
1376
1377         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1378
1379 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1380
1381         * i386-dis.c (enum): Add pconfig.
1382         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1383         (cpu_flags): Add CpuPCONFIG.
1384         * i386-opc.h (enum): Add CpuPCONFIG.
1385         (i386_cpu_flags): Add cpupconfig.
1386         * i386-opc.tbl: Add PCONFIG instruction.
1387         * i386-init.h: Regenerate.
1388         * i386-tbl.h: Likewise.
1389
1390 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1391
1392         * i386-dis.c (enum): Add PREFIX_0F09.
1393         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1394         (cpu_flags): Add CpuWBNOINVD.
1395         * i386-opc.h (enum): Add CpuWBNOINVD.
1396         (i386_cpu_flags): Add cpuwbnoinvd.
1397         * i386-opc.tbl: Add WBNOINVD instruction.
1398         * i386-init.h: Regenerate.
1399         * i386-tbl.h: Likewise.
1400
1401 2018-01-17  Jim Wilson  <jimw@sifive.com>
1402
1403         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1404
1405 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1406
1407         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1408         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1409         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1410         (cpu_flags): Add CpuIBT, CpuSHSTK.
1411         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1412         (i386_cpu_flags): Add cpuibt, cpushstk.
1413         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1414         * i386-init.h: Regenerate.
1415         * i386-tbl.h: Likewise.
1416
1417 2018-01-16  Nick Clifton  <nickc@redhat.com>
1418
1419         * po/pt_BR.po: Updated Brazilian Portugese translation.
1420         * po/de.po: Updated German translation.
1421
1422 2018-01-15  Jim Wilson  <jimw@sifive.com>
1423
1424         * riscv-opc.c (match_c_nop): New.
1425         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1426
1427 2018-01-15  Nick Clifton  <nickc@redhat.com>
1428
1429         * po/uk.po: Updated Ukranian translation.
1430
1431 2018-01-13  Nick Clifton  <nickc@redhat.com>
1432
1433         * po/opcodes.pot: Regenerated.
1434
1435 2018-01-13  Nick Clifton  <nickc@redhat.com>
1436
1437         * configure: Regenerate.
1438
1439 2018-01-13  Nick Clifton  <nickc@redhat.com>
1440
1441         2.30 branch created.
1442
1443 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1444
1445         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1446         * i386-tbl.h: Regenerate.
1447
1448 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1449
1450         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1451         * i386-tbl.h: Re-generate.
1452
1453 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1454
1455         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1456         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1457         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1458         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1459         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1460         Disp8MemShift of AVX512VL forms.
1461         * i386-tbl.h: Re-generate.
1462
1463 2018-01-09  Jim Wilson  <jimw@sifive.com>
1464
1465         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1466         then the hi_addr value is zero.
1467
1468 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1469
1470         * arm-dis.c (arm_opcodes): Add csdb.
1471         (thumb32_opcodes): Add csdb.
1472
1473 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1474
1475         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1476         * aarch64-asm-2.c: Regenerate.
1477         * aarch64-dis-2.c: Regenerate.
1478         * aarch64-opc-2.c: Regenerate.
1479
1480 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1481
1482         PR gas/22681
1483         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1484         Remove AVX512 vmovd with 64-bit operands.
1485         * i386-tbl.h: Regenerated.
1486
1487 2018-01-05  Jim Wilson  <jimw@sifive.com>
1488
1489         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1490         jalr.
1491
1492 2018-01-03  Alan Modra  <amodra@gmail.com>
1493
1494         Update year range in copyright notice of all files.
1495
1496 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1497
1498         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1499         and OPERAND_TYPE_REGZMM entries.
1500
1501 For older changes see ChangeLog-2017
1502 \f
1503 Copyright (C) 2018 Free Software Foundation, Inc.
1504
1505 Copying and distribution of this file, with or without modification,
1506 are permitted in any medium without royalty provided the copyright
1507 notice and this notice are preserved.
1508
1509 Local Variables:
1510 mode: change-log
1511 left-margin: 8
1512 fill-column: 74
1513 version-control: never
1514 End: