opcodes/ChangeLog

   1 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-opc.tbl: Merge AVX512F vmovq.
   4         * i386-tbl.h: Regerated.
   5
   6 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         PR binutils/20701
   9         * i386-dis.c (THREE_BYTE_0F7A): Removed.
  10         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
  11         (three_byte_table): Remove THREE_BYTE_0F7A.
  12
  13 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
  14
  15         PR binutils/20775
  16         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
  17         (FGRPd9_4): Replace 1 with 2.
  18         (FGRPd9_5): Replace 2 with 3.
  19         (FGRPd9_6): Replace 3 with 4.
  20         (FGRPd9_7): Replace 4 with 5.
  21         (FGRPda_5): Replace 5 with 6.
  22         (FGRPdb_4): Replace 6 with 7.
  23         (FGRPde_3): Replace 7 with 8.
  24         (FGRPdf_4): Replace 8 with 9.
  25         (fgrps): Add an entry for Bad_Opcode.
  26
  27 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
  28
  29         * arc-opc.c (arc_flag_operands): Add F_DI14.
  30         (arc_flag_classes): Add C_DI14.
  31         * arc-nps400-tbl.h: Add new exc instructions.
  32
  33 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
  34
  35         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
  36         major opcode 0xa.
  37         * arc-nps-400-tbl.h: Add dcmac instruction.
  38         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
  39         (insert_nps_rbdouble_64): Added.
  40         (extract_nps_rbdouble_64): Added.
  41         (insert_nps_proto_size): Added.
  42         (extract_nps_proto_size): Added.
  43
  44 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
  45
  46         * arc-dis.c (struct arc_operand_iterator): Remove all fields
  47         relating to long instruction processing, add new limm field.
  48         (OPCODE): Rename to...
  49         (OPCODE_32BIT_INSN): ...this.
  50         (OPCODE_AC): Delete.
  51         (skip_this_opcode): Handle different instruction lengths, update
  52         macro name.
  53         (special_flag_p): Update parameter type.
  54         (find_format_from_table): Update for more instruction lengths.
  55         (find_format_long_instructions): Delete.
  56         (find_format): Update for more instruction lengths.
  57         (arc_insn_length): Likewise.
  58         (extract_operand_value): Update for more instruction lengths.
  59         (operand_iterator_next): Remove code relating to long
  60         instructions.
  61         (arc_opcode_to_insn_type): New function.
  62         (print_insn_arc):Update for more instructions lengths.
  63         * arc-ext.c (extInstruction_t): Change argument type.
  64         * arc-ext.h (extInstruction_t): Change argument type.
  65         * arc-fxi.h: Change type unsigned to unsigned long long
  66         extensively throughout.
  67         * arc-nps400-tbl.h: Add long instructions taken from
  68         arc_long_opcodes table in arc-opc.c.
  69         * arc-opc.c: Update parameter types on insert/extract handlers.
  70         (arc_long_opcodes): Delete.
  71         (arc_num_long_opcodes): Delete.
  72         (arc_opcode_len): Update for more instruction lengths.
  73
  74 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
  75
  76         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
  77
  78 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
  79
  80         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
  81         with arc_opcode_len.
  82         (find_format_long_instructions): Likewise.
  83         * arc-opc.c (arc_opcode_len): New function.
  84
  85 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
  86
  87         * arc-nps400-tbl.h: Fix some instruction masks.
  88
  89 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
  90
  91         * i386-dis.c (REG_82): Removed.
  92         (X86_64_82_REG_0): Likewise.
  93         (X86_64_82_REG_1): Likewise.
  94         (X86_64_82_REG_2): Likewise.
  95         (X86_64_82_REG_3): Likewise.
  96         (X86_64_82_REG_4): Likewise.
  97         (X86_64_82_REG_5): Likewise.
  98         (X86_64_82_REG_6): Likewise.
  99         (X86_64_82_REG_7): Likewise.
 100         (X86_64_82): New.
 101         (dis386): Use X86_64_82 instead of REG_82.
 102         (reg_table): Remove REG_82.
 103         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 104         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 105         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 106         X86_64_82_REG_7.
 107
 108 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 109
 110         PR binutils/20754
 111         * i386-dis.c (REG_82): New.
 112         (X86_64_82_REG_0): Likewise.
 113         (X86_64_82_REG_1): Likewise.
 114         (X86_64_82_REG_2): Likewise.
 115         (X86_64_82_REG_3): Likewise.
 116         (X86_64_82_REG_4): Likewise.
 117         (X86_64_82_REG_5): Likewise.
 118         (X86_64_82_REG_6): Likewise.
 119         (X86_64_82_REG_7): Likewise.
 120         (dis386): Use REG_82.
 121         (reg_table): Add REG_82.
 122         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 123         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 124         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 125
 126 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 127
 128         * i386-dis.c (REG_82): Renamed to ...
 129         (REG_83): This.
 130         (dis386): Updated.
 131         (reg_table): Likewise.
 132
 133 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 134
 135         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 136         * i386-dis-evex.h (evex_table): Updated.
 137         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 138         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 139         (cpu_flags): Add CpuAVX512_4VNNIW.
 140         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 141         (i386_cpu_flags): Add cpuavx512_4vnniw.
 142         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 143         * i386-init.h: Regenerate.
 144         * i386-tbl.h: Ditto.
 145
 146 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 147
 148         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 149         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 150         * i386-dis-evex.h (evex_table): Updated.
 151         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 152         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 153         (cpu_flags): Add CpuAVX512_4FMAPS.
 154         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 155         * i386-opc.h (AVX512_4FMAP): New.
 156         (i386_cpu_flags): Add cpuavx512_4fmaps.
 157         (ImplicitQuadGroup): New.
 158         (i386_opcode_modifier): Add implicitquadgroup.
 159         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 160         * i386-init.h: Regenerate.
 161         * i386-tbl.h: Ditto.
 162
 163 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 164             Andrew Waterman <andrew@sifive.com>
 165
 166         Add support for RISC-V architecture.
 167         * configure.ac: Add entry for bfd_riscv_arch.
 168         * configure: Regenerate.
 169         * disassemble.c (disassembler): Add support for riscv.
 170         (disassembler_usage): Likewise.
 171         * riscv-dis.c: New file.
 172         * riscv-opc.c: New file.
 173
 174 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 175
 176         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 177         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 178         (rm_table): Update the RM_0FAE_REG_7 entry.
 179         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 180         (cpu_flags): Remove CpuPCOMMIT.
 181         * i386-opc.h (CpuPCOMMIT): Removed.
 182         (i386_cpu_flags): Remove cpupcommit.
 183         * i386-opc.tbl: Remove pcommit.
 184         * i386-init.h: Regenerated.
 185         * i386-tbl.h: Likewise.
 186
 187 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 188
 189         PR binutis/20705
 190         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 191         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 192         32-bit mode.  Don't check vex.register_specifier in 32-bit
 193         mode.
 194         (OP_VEX): Check for invalid mask registers.
 195
 196 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 197
 198         PR binutis/20699
 199         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 200         sizeflag.
 201
 202 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 203
 204         PR binutis/20704
 205         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 206
 207 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 208
 209         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 210         local variable to `index_regno'.
 211
 212 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 213
 214         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 215
 216 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 217
 218         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 219         usage on ISA basis.
 220
 221 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 222
 223         PR target/20666
 224         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 225
 226 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 227
 228         PR target/20667
 229         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 230         available.
 231
 232 2016-10-07  Alan Modra  <amodra@gmail.com>
 233
 234         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 235
 236 2016-10-06  Alan Modra  <amodra@gmail.com>
 237
 238         * aarch64-opc.c: Spell fall through comments consistently.
 239         * i386-dis.c: Likewise.
 240         * aarch64-dis.c: Add missing fall through comments.
 241         * aarch64-opc.c: Likewise.
 242         * arc-dis.c: Likewise.
 243         * arm-dis.c: Likewise.
 244         * i386-dis.c: Likewise.
 245         * m68k-dis.c: Likewise.
 246         * mep-asm.c: Likewise.
 247         * ns32k-dis.c: Likewise.
 248         * sh-dis.c: Likewise.
 249         * tic4x-dis.c: Likewise.
 250         * tic6x-dis.c: Likewise.
 251         * vax-dis.c: Likewise.
 252
 253 2016-10-06  Alan Modra  <amodra@gmail.com>
 254
 255         * arc-ext.c (create_map): Add missing break.
 256         * msp430-decode.opc (encode_as): Likewise.
 257         * msp430-decode.c: Regenerate.
 258
 259 2016-10-06  Alan Modra  <amodra@gmail.com>
 260
 261         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 262         * crx-dis.c (print_insn_crx): Likewise.
 263
 264 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 265
 266         PR binutils/20657
 267         * i386-dis.c (putop): Don't assign alt twice.
 268
 269 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 270
 271         PR target/20553
 272         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 273
 274 2016-09-29  Alan Modra  <amodra@gmail.com>
 275
 276         * ppc-opc.c (L): Make compulsory.
 277         (LOPT): New, optional form of L.
 278         (HTM_R): Define as LOPT.
 279         (L0, L1): Delete.
 280         (L32OPT): New, optional for 32-bit L.
 281         (L2OPT): New, 2-bit L for dcbf.
 282         (SVC_LEC): Update.
 283         (L2): Define.
 284         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 285         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 286         <dcbf>: Use L2OPT.
 287         <tlbiel, tlbie>: Use LOPT.
 288         <wclr, wclrall>: Use L2.
 289
 290 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 291
 292         * Makefile.in: Regenerate.
 293         * configure: Likewise.
 294
 295 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 296
 297         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 298         (EXTINSN2OP): Use EXTINSN2OPF.
 299         (bspeekm, bspop, modapp): New extension instructions.
 300         * arc-opc.c (F_DNZ_ND): Define.
 301         (F_DNZ_D): Likewise.
 302         (F_SIZEB1): Changed.
 303         (C_DNZ_D): Define.
 304         (C_HARD): Changed.
 305         * arc-tbl.h (dbnz): New instruction.
 306         (prealloc): Allow it for ARC EM.
 307         (xbfu): Likewise.
 308
 309 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 310
 311         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 312         after commas in addresses.
 313         (aarch64_print_operand): Likewise.
 314
 315 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 316
 317         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 318         rather than "should be" or "expected to be" in error messages.
 319
 320 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 321
 322         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 323         (print_mnemonic_name): ...here.
 324         (print_comment): New function.
 325         (print_aarch64_insn): Call it.
 326         * aarch64-opc.c (aarch64_conds): Add SVE names.
 327         (aarch64_print_operand): Print alternative condition names in
 328         a comment.
 329
 330 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 331
 332         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 333         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 334         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 335         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 336         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 337         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 338         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 339         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 340         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 341         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 342         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 343         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 344         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 345         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 346         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 347         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 348         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 349         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 350         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 351         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 352         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 353         (aarch64_feature_sve): New variable.
 354         (SVE): New macro.
 355         (_SVE_INSN): Likewise.
 356         (aarch64_opcode_table): Add SVE instructions.
 357         * aarch64-opc.h (extract_fields): Declare.
 358         * aarch64-opc-2.c: Regenerate.
 359         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 360         * aarch64-asm-2.c: Regenerate.
 361         * aarch64-dis.c (extract_fields): Make global.
 362         (do_misc_decoding): Handle the new SVE aarch64_ops.
 363         * aarch64-dis-2.c: Regenerate.
 364
 365 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 366
 367         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 368         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 369         aarch64_field_kinds.
 370         * aarch64-opc.c (fields): Add corresponding entries.
 371         * aarch64-asm.c (aarch64_get_variant): New function.
 372         (aarch64_encode_variant_using_iclass): Likewise.
 373         (aarch64_opcode_encode): Call it.
 374         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 375         (aarch64_opcode_decode): Call it.
 376
 377 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 378
 379         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 380         and FP register operands.
 381         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 382         (FLD_SVE_Vn): New aarch64_field_kinds.
 383         * aarch64-opc.c (fields): Add corresponding entries.
 384         (aarch64_print_operand): Handle the new SVE core and FP register
 385         operands.
 386         * aarch64-opc-2.c: Regenerate.
 387         * aarch64-asm-2.c: Likewise.
 388         * aarch64-dis-2.c: Likewise.
 389
 390 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 391
 392         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 393         immediate operands.
 394         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 395         * aarch64-opc.c (fields): Add corresponding entry.
 396         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 397         operands.
 398         (aarch64_print_operand): Likewise.
 399         * aarch64-opc-2.c: Regenerate.
 400         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 401         (ins_sve_float_zero_one): New inserters.
 402         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 403         (aarch64_ins_sve_float_half_two): Likewise.
 404         (aarch64_ins_sve_float_zero_one): Likewise.
 405         * aarch64-asm-2.c: Regenerate.
 406         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 407         (ext_sve_float_zero_one): New extractors.
 408         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 409         (aarch64_ext_sve_float_half_two): Likewise.
 410         (aarch64_ext_sve_float_zero_one): Likewise.
 411         * aarch64-dis-2.c: Regenerate.
 412
 413 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 414
 415         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 416         integer immediate operands.
 417         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 418         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 419         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 420         * aarch64-opc.c (fields): Add corresponding entries.
 421         (operand_general_constraint_met_p): Handle the new SVE integer
 422         immediate operands.
 423         (aarch64_print_operand): Likewise.
 424         (aarch64_sve_dupm_mov_immediate_p): New function.
 425         * aarch64-opc-2.c: Regenerate.
 426         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 427         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 428         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 429         (aarch64_ins_limm): ...here.
 430         (aarch64_ins_inv_limm): New function.
 431         (aarch64_ins_sve_aimm): Likewise.
 432         (aarch64_ins_sve_asimm): Likewise.
 433         (aarch64_ins_sve_limm_mov): Likewise.
 434         (aarch64_ins_sve_shlimm): Likewise.
 435         (aarch64_ins_sve_shrimm): Likewise.
 436         * aarch64-asm-2.c: Regenerate.
 437         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 438         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 439         * aarch64-dis.c (decode_limm): New function, split out from...
 440         (aarch64_ext_limm): ...here.
 441         (aarch64_ext_inv_limm): New function.
 442         (decode_sve_aimm): Likewise.
 443         (aarch64_ext_sve_aimm): Likewise.
 444         (aarch64_ext_sve_asimm): Likewise.
 445         (aarch64_ext_sve_limm_mov): Likewise.
 446         (aarch64_top_bit): Likewise.
 447         (aarch64_ext_sve_shlimm): Likewise.
 448         (aarch64_ext_sve_shrimm): Likewise.
 449         * aarch64-dis-2.c: Regenerate.
 450
 451 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 452
 453         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 454         operands.
 455         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 456         the AARCH64_MOD_MUL_VL entry.
 457         (value_aligned_p): Cope with non-power-of-two alignments.
 458         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 459         (print_immediate_offset_address): Likewise.
 460         (aarch64_print_operand): Likewise.
 461         * aarch64-opc-2.c: Regenerate.
 462         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 463         (ins_sve_addr_ri_s9xvl): New inserters.
 464         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 465         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 466         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 467         * aarch64-asm-2.c: Regenerate.
 468         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 469         (ext_sve_addr_ri_s9xvl): New extractors.
 470         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 471         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 472         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 473         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 474         * aarch64-dis-2.c: Regenerate.
 475
 476 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 477
 478         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 479         address operands.
 480         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 481         (FLD_SVE_xs_22): New aarch64_field_kinds.
 482         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 483         (get_operand_specific_data): New function.
 484         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 485         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 486         (operand_general_constraint_met_p): Handle the new SVE address
 487         operands.
 488         (sve_reg): New array.
 489         (get_addr_sve_reg_name): New function.
 490         (aarch64_print_operand): Handle the new SVE address operands.
 491         * aarch64-opc-2.c: Regenerate.
 492         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 493         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 494         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 495         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 496         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 497         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 498         (aarch64_ins_sve_addr_zi_u5): Likewise.
 499         (aarch64_ins_sve_addr_zz): Likewise.
 500         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 501         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 502         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 503         * aarch64-asm-2.c: Regenerate.
 504         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 505         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 506         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 507         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 508         (aarch64_ext_sve_addr_ri_u6): Likewise.
 509         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 510         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 511         (aarch64_ext_sve_addr_zi_u5): Likewise.
 512         (aarch64_ext_sve_addr_zz): Likewise.
 513         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 514         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 515         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 516         * aarch64-dis-2.c: Regenerate.
 517
 518 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 519
 520         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 521         AARCH64_OPND_SVE_PATTERN_SCALED.
 522         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 523         * aarch64-opc.c (fields): Add a corresponding entry.
 524         (set_multiplier_out_of_range_error): New function.
 525         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 526         (operand_general_constraint_met_p): Handle
 527         AARCH64_OPND_SVE_PATTERN_SCALED.
 528         (print_register_offset_address): Use PRIi64 to print the
 529         shift amount.
 530         (aarch64_print_operand): Likewise.  Handle
 531         AARCH64_OPND_SVE_PATTERN_SCALED.
 532         * aarch64-opc-2.c: Regenerate.
 533         * aarch64-asm.h (ins_sve_scale): New inserter.
 534         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 535         * aarch64-asm-2.c: Regenerate.
 536         * aarch64-dis.h (ext_sve_scale): New inserter.
 537         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 538         * aarch64-dis-2.c: Regenerate.
 539
 540 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 541
 542         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 543         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 544         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 545         (FLD_SVE_prfop): Likewise.
 546         * aarch64-opc.c: Include libiberty.h.
 547         (aarch64_sve_pattern_array): New variable.
 548         (aarch64_sve_prfop_array): Likewise.
 549         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 550         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 551         AARCH64_OPND_SVE_PRFOP.
 552         * aarch64-asm-2.c: Regenerate.
 553         * aarch64-dis-2.c: Likewise.
 554         * aarch64-opc-2.c: Likewise.
 555
 556 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 557
 558         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 559         AARCH64_OPND_QLF_P_[ZM].
 560         (aarch64_print_operand): Print /z and /m where appropriate.
 561
 562 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 563
 564         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 565         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 566         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 567         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 568         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 569         * aarch64-opc.c (fields): Add corresponding entries here.
 570         (operand_general_constraint_met_p): Check that SVE register lists
 571         have the correct length.  Check the ranges of SVE index registers.
 572         Check for cases where p8-p15 are used in 3-bit predicate fields.
 573         (aarch64_print_operand): Handle the new SVE operands.
 574         * aarch64-opc-2.c: Regenerate.
 575         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 576         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 577         (aarch64_ins_sve_reglist): Likewise.
 578         * aarch64-asm-2.c: Regenerate.
 579         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 580         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 581         (aarch64_ext_sve_reglist): Likewise.
 582         * aarch64-dis-2.c: Regenerate.
 583
 584 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 585
 586         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 587         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 588         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 589         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 590         tied operands.
 591
 592 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 593
 594         * aarch64-opc.c (get_offset_int_reg_name): New function.
 595         (print_immediate_offset_address): Likewise.
 596         (print_register_offset_address): Take the base and offset
 597         registers as parameters.
 598         (aarch64_print_operand): Update caller accordingly.  Use
 599         print_immediate_offset_address.
 600
 601 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 602
 603         * aarch64-opc.c (BANK): New macro.
 604         (R32, R64): Take a register number as argument
 605         (int_reg): Use BANK.
 606
 607 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 608
 609         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 610         (aarch64_print_operand): Update accordingly.
 611
 612 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 613
 614         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 615         for FPIMM.
 616         * aarch64-asm.h (ins_fpimm): New inserter.
 617         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 618         * aarch64-asm-2.c: Regenerate.
 619         * aarch64-dis.h (ext_fpimm): New extractor.
 620         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 621         (aarch64_ext_fpimm): New function.
 622         * aarch64-dis-2.c: Regenerate.
 623
 624 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 625
 626         * aarch64-asm.c: Include libiberty.h.
 627         (insert_fields): New function.
 628         (aarch64_ins_imm): Use it.
 629         * aarch64-dis.c (extract_fields): New function.
 630         (aarch64_ext_imm): Use it.
 631
 632 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 633
 634         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 635         with an esize parameter.
 636         (operand_general_constraint_met_p): Update accordingly.
 637         Fix misindented code.
 638         * aarch64-asm.c (aarch64_ins_limm): Update call to
 639         aarch64_logical_immediate_p.
 640
 641 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 642
 643         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 644
 645 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 646
 647         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 648
 649 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 650
 651         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 652
 653 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 654
 655         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 656         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 657         xor3>: Delete mnemonics.
 658         <cp_abort>: Rename mnemonic from ...
 659         <cpabort>: ...to this.
 660         <setb>: Change to a X form instruction.
 661         <sync>: Change to 1 operand form.
 662         <copy>: Delete mnemonic.
 663         <copy_first>: Rename mnemonic from ...
 664         <copy>: ...to this.
 665         <paste, paste.>: Delete mnemonics.
 666         <paste_last>: Rename mnemonic from ...
 667         <paste.>: ...to this.
 668
 669 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 670
 671         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 672
 673 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 674
 675         * s390-mkopc.c (main): Support alternate arch strings.
 676
 677 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 678
 679         * s390-opc.txt: Fix kmctr instruction type.
 680
 681 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 682
 683         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 684         * i386-init.h: Regenerated.
 685
 686 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 687
 688         * opcodes/arc-dis.c (print_insn_arc): Changed.
 689
 690 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 691
 692         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 693         camellia_fl.
 694
 695 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 696
 697         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 698         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 699         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 700
 701 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 702
 703         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 704         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 705         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 706         PREFIX_MOD_3_0FAE_REG_4.
 707         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 708         PREFIX_MOD_3_0FAE_REG_4.
 709         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 710         (cpu_flags): Add CpuPTWRITE.
 711         * i386-opc.h (CpuPTWRITE): New.
 712         (i386_cpu_flags): Add cpuptwrite.
 713         * i386-opc.tbl: Add ptwrite instruction.
 714         * i386-init.h: Regenerated.
 715         * i386-tbl.h: Likewise.
 716
 717 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 718
 719         * arc-dis.h: Wrap around in extern "C".
 720
 721 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 722
 723         * aarch64-tbl.h (V8_2_INSN): New macro.
 724         (aarch64_opcode_table): Use it.
 725
 726 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 727
 728         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 729         CORE_INSN, __FP_INSN and SIMD_INSN.
 730
 731 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 732
 733         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 734         (aarch64_opcode_table): Update uses accordingly.
 735
 736 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 737         Kwok Cheung Yeung  <kcy@codesourcery.com>
 738
 739         opcodes/
 740         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 741         'e_cmplwi' to 'e_cmpli' instead.
 742         (OPVUPRT, OPVUPRT_MASK): Define.
 743         (powerpc_opcodes): Add E200Z4 insns.
 744         (vle_opcodes): Add context save/restore insns.
 745
 746 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 747
 748         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 749         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 750         "j".
 751
 752 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 753
 754         * arc-nps400-tbl.h: Change block comments to GNU format.
 755         * arc-dis.c: Add new globals addrtypenames,
 756         addrtypenames_max, and addtypeunknown.
 757         (get_addrtype): New function.
 758         (print_insn_arc): Print colons and address types when
 759         required.
 760         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 761         define insert and extract functions for all address types.
 762         (arc_operands): Add operands for colon and all address
 763         types.
 764         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 765         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 766         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 767         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 768         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 769         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 770
 771 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 772
 773         * configure: Regenerated.
 774
 775 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 776
 777         * arc-dis.c (skipclass): New structure.
 778         (decodelist): New variable.
 779         (is_compatible_p): New function.
 780         (new_element): Likewise.
 781         (skip_class_p): Likewise.
 782         (find_format_from_table): Use skip_class_p function.
 783         (find_format): Decode first the extension instructions.
 784         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 785         e_flags.
 786         (parse_option): New function.
 787         (parse_disassembler_options): Likewise.
 788         (print_arc_disassembler_options): Likewise.
 789         (print_insn_arc): Use parse_disassembler_options function.  Proper
 790         select ARCv2 cpu variant.
 791         * disassemble.c (disassembler_usage): Add ARC disassembler
 792         options.
 793
 794 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 795
 796         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 797         annotation from the "nal" entry and reorder it beyond "bltzal".
 798
 799 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 800
 801         * sparc-opc.c (ldtxa): New macro.
 802         (sparc_opcodes): Use the macro defined above to add entries for
 803         the LDTXA instructions.
 804         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 805         instruction.
 806
 807 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 808
 809         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 810         and "jmpc".
 811
 812 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 815         (movzb): Adjust to cover all permitted suffixes.
 816         (movzw): New.
 817         * i386-tbl.h: Re-generate.
 818
 819 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 820
 821         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 822         (lgdt): Remove Tbyte from non-64-bit variant.
 823         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 824         xsaves64, xsavec64): Remove Disp16.
 825         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 826         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 827         64-bit variants.
 828         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 829         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 830         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 831         64-bit variants.
 832         * i386-tbl.h: Re-generate.
 833
 834 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 835
 836         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 837         * i386-tbl.h: Re-generate.
 838
 839 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 840
 841         * arm-dis.c (print_insn): Fix typo in comment.
 842
 843 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 844
 845         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 846         range of ldst_elemlist operands.
 847         (print_register_list): Use PRIi64 to print the index.
 848         (aarch64_print_operand): Likewise.
 849
 850 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 851
 852         * mcore-opc.h: Remove sentinal.
 853         * mcore-dis.c (print_insn_mcore): Adjust.
 854
 855 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 856
 857         * arc-opc.c: Correct description of availability of NPS400
 858         features.
 859
 860 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 861
 862         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 863         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 864         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 865         xor3>: New mnemonics.
 866         <setb>: Change to a VX form instruction.
 867         (insert_sh6): Add support for rldixor.
 868         (extract_sh6): Likewise.
 869
 870 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 871
 872         * arc-ext.h: Wrap in extern C.
 873
 874 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 875
 876         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 877         Use same method for determining instruction length on ARC700 and
 878         NPS-400.
 879         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 880         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 881         with the NPS400 subclass.
 882         * arc-opc.c: Likewise.
 883
 884 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 885
 886         * sparc-opc.c (rdasr): New macro.
 887         (wrasr): Likewise.
 888         (rdpr): Likewise.
 889         (wrpr): Likewise.
 890         (rdhpr): Likewise.
 891         (wrhpr): Likewise.
 892         (sparc_opcodes): Use the macros above to fix and expand the
 893         definition of read/write instructions from/to
 894         asr/privileged/hyperprivileged instructions.
 895         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 896         %hva_mask_nz.  Prefer softint_set and softint_clear over
 897         set_softint and clear_softint.
 898         (print_insn_sparc): Support %ver in Rd.
 899
 900 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 901
 902         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 903         architecture according to the hardware capabilities they require.
 904
 905 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 906
 907         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 908         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 909         bfd_mach_sparc_v9{c,d,e,v,m}.
 910         * sparc-opc.c (MASK_V9C): Define.
 911         (MASK_V9D): Likewise.
 912         (MASK_V9E): Likewise.
 913         (MASK_V9V): Likewise.
 914         (MASK_V9M): Likewise.
 915         (v6): Add MASK_V9{C,D,E,V,M}.
 916         (v6notlet): Likewise.
 917         (v7): Likewise.
 918         (v8): Likewise.
 919         (v9): Likewise.
 920         (v9andleon): Likewise.
 921         (v9a): Likewise.
 922         (v9b): Likewise.
 923         (v9c): Define.
 924         (v9d): Likewise.
 925         (v9e): Likewise.
 926         (v9v): Likewise.
 927         (v9m): Likewise.
 928         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 929
 930 2016-06-15  Nick Clifton  <nickc@redhat.com>
 931
 932         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 933         constants to match expected behaviour.
 934         (nds32_parse_opcode): Likewise.  Also for whitespace.
 935
 936 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 937
 938         * arc-opc.c (extract_rhv1): Extract value from insn.
 939
 940 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 941
 942         * arc-nps400-tbl.h: Add ldbit instruction.
 943         * arc-opc.c: Add flag classes required for ldbit.
 944
 945 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 946
 947         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 948         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 949         support the above instructions.
 950
 951 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 952
 953         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 954         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 955         csma, cbba, zncv, and hofs.
 956         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 957         support the above instructions.
 958
 959 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 960
 961         * arc-nps400-tbl.h: Add andab and orab instructions.
 962
 963 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 964
 965         * arc-nps400-tbl.h: Add addl-like instructions.
 966
 967 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 968
 969         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 970
 971 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 972
 973         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 974         instructions.
 975
 976 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 977
 978         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 979         variable.
 980         (init_disasm): Handle new command line option "insnlength".
 981         (print_s390_disassembler_options): Mention new option in help
 982         output.
 983         (print_insn_s390): Use the encoded insn length when dumping
 984         unknown instructions.
 985
 986 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 987
 988         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 989          to the address and set as symbol address for LDS/ STS immediate operands.
 990
 991 2016-06-07  Alan Modra  <amodra@gmail.com>
 992
 993         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 994         cpu for "vle" to e500.
 995         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 996         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 997         (PPCNONE): Delete, substitute throughout.
 998         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 999         except for major opcode 4 and 31.
1000         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1001
1002 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1003
1004         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1005         ARM_EXT_RAS in relevant entries.
1006
1007 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1008
1009         PR binutils/20196
1010         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1011         opcodes for E6500.
1012
1013 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1014
1015         PR binutis/18386
1016         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1017         (indir_v_mode): New.
1018         Add comments for '&'.
1019         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1020         (putop): Handle '&'.
1021         (intel_operand_size): Handle indir_v_mode.
1022         (OP_E_register): Likewise.
1023         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1024         64-bit indirect call/jmp for AMD64.
1025         * i386-tbl.h: Regenerated
1026
1027 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1028
1029         * arc-dis.c (struct arc_operand_iterator): New structure.
1030         (find_format_from_table): All the old content from find_format,
1031         with some minor adjustments, and parameter renaming.
1032         (find_format_long_instructions): New function.
1033         (find_format): Rewritten.
1034         (arc_insn_length): Add LSB parameter.
1035         (extract_operand_value): New function.
1036         (operand_iterator_next): New function.
1037         (print_insn_arc): Use new functions to find opcode, and iterator
1038         over operands.
1039         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1040         (extract_nps_3bit_dst_short): New function.
1041         (insert_nps_3bit_src2_short): New function.
1042         (extract_nps_3bit_src2_short): New function.
1043         (insert_nps_bitop1_size): New function.
1044         (extract_nps_bitop1_size): New function.
1045         (insert_nps_bitop2_size): New function.
1046         (extract_nps_bitop2_size): New function.
1047         (insert_nps_bitop_mod4_msb): New function.
1048         (extract_nps_bitop_mod4_msb): New function.
1049         (insert_nps_bitop_mod4_lsb): New function.
1050         (extract_nps_bitop_mod4_lsb): New function.
1051         (insert_nps_bitop_dst_pos3_pos4): New function.
1052         (extract_nps_bitop_dst_pos3_pos4): New function.
1053         (insert_nps_bitop_ins_ext): New function.
1054         (extract_nps_bitop_ins_ext): New function.
1055         (arc_operands): Add new operands.
1056         (arc_long_opcodes): New global array.
1057         (arc_num_long_opcodes): New global.
1058         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1059
1060 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1061
1062         * nds32-asm.h: Add extern "C".
1063         * sh-opc.h: Likewise.
1064
1065 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1066
1067         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1068         0,b,limm to the rflt instruction.
1069
1070 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1071
1072         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1073         constant.
1074
1075 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1076
1077         PR gas/20145
1078         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1079         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1080         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1081         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1082         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1083         * i386-init.h: Regenerated.
1084
1085 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1086
1087         PR gas/20145
1088         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1089         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1090         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1091         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1092         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1093         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1094         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1095         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1096         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1097         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1098         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1099         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1100         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1101         CpuRegMask for AVX512.
1102         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1103         and CpuRegMask.
1104         (set_bitfield_from_cpu_flag_init): New function.
1105         (set_bitfield): Remove const on f.  Call
1106         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1107         * i386-opc.h (CpuRegMMX): New.
1108         (CpuRegXMM): Likewise.
1109         (CpuRegYMM): Likewise.
1110         (CpuRegZMM): Likewise.
1111         (CpuRegMask): Likewise.
1112         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1113         and cpuregmask.
1114         * i386-init.h: Regenerated.
1115         * i386-tbl.h: Likewise.
1116
1117 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1118
1119         PR gas/20154
1120         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1121         (opcode_modifiers): Add AMD64 and Intel64.
1122         (main): Properly verify CpuMax.
1123         * i386-opc.h (CpuAMD64): Removed.
1124         (CpuIntel64): Likewise.
1125         (CpuMax): Set to CpuNo64.
1126         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1127         (AMD64): New.
1128         (Intel64): Likewise.
1129         (i386_opcode_modifier): Add amd64 and intel64.
1130         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1131         on call and jmp.
1132         * i386-init.h: Regenerated.
1133         * i386-tbl.h: Likewise.
1134
1135 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1136
1137         PR gas/20154
1138         * i386-gen.c (main): Fail if CpuMax is incorrect.
1139         * i386-opc.h (CpuMax): Set to CpuIntel64.
1140         * i386-tbl.h: Regenerated.
1141
1142 2016-05-27  Nick Clifton  <nickc@redhat.com>
1143
1144         PR target/20150
1145         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1146         (msp430dis_opcode_unsigned): New function.
1147         (msp430dis_opcode_signed): New function.
1148         (msp430_singleoperand): Use the new opcode reading functions.
1149         Only disassenmble bytes if they were successfully read.
1150         (msp430_doubleoperand): Likewise.
1151         (msp430_branchinstr): Likewise.
1152         (msp430x_callx_instr): Likewise.
1153         (print_insn_msp430): Check that it is safe to read bytes before
1154         attempting disassembly.  Use the new opcode reading functions.
1155
1156 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1157
1158         * ppc-opc.c (CY): New define.  Document it.
1159         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1160
1161 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1162
1163         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1164         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1165         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1166         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1167         CPU_ANY_AVX_FLAGS.
1168         * i386-init.h: Regenerated.
1169
1170 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1171
1172         PR gas/20141
1173         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1174         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1175         * i386-init.h: Regenerated.
1176
1177 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1178
1179         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1180         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1181         * i386-init.h: Regenerated.
1182
1183 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1184
1185         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1186         information.
1187         (print_insn_arc): Set insn_type information.
1188         * arc-opc.c (C_CC): Add F_CLASS_COND.
1189         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1190         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1191         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1192         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1193         (brne, brne_s, jeq_s, jne_s): Likewise.
1194
1195 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1196
1197         * arc-tbl.h (neg): New instruction variant.
1198
1199 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1200
1201         * arc-dis.c (find_format, find_format, get_auxreg)
1202         (print_insn_arc): Changed.
1203         * arc-ext.h (INSERT_XOP): Likewise.
1204
1205 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1206
1207         * tic54x-dis.c (sprint_mmr): Adjust.
1208         * tic54x-opc.c: Likewise.
1209
1210 2016-05-19  Alan Modra  <amodra@gmail.com>
1211
1212         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1213
1214 2016-05-19  Alan Modra  <amodra@gmail.com>
1215
1216         * ppc-opc.c: Formatting.
1217         (NSISIGNOPT): Define.
1218         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1219
1220 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1221
1222         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1223         replacing references to `micromips_ase' throughout.
1224         (_print_insn_mips): Don't use file-level microMIPS annotation to
1225         determine the disassembly mode with the symbol table.
1226
1227 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1228
1229         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1230
1231 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1232
1233         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1234         mips64r6.
1235         * mips-opc.c (D34): New macro.
1236         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1237
1238 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1239
1240         * i386-dis.c (prefix_table): Add RDPID instruction.
1241         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1242         (cpu_flags): Add RDPID bitfield.
1243         * i386-opc.h (enum): Add RDPID element.
1244         (i386_cpu_flags): Add RDPID field.
1245         * i386-opc.tbl: Add RDPID instruction.
1246         * i386-init.h: Regenerate.
1247         * i386-tbl.h: Regenerate.
1248
1249 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1250
1251         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1252         branch type of a symbol.
1253         (print_insn): Likewise.
1254
1255 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1256
1257         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1258         Mainline Security Extensions instructions.
1259         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1260         Extensions instructions.
1261         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1262         instructions.
1263         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1264         special registers.
1265
1266 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1267
1268         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1269
1270 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1271
1272         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1273         (arcExtMap_genOpcode): Likewise.
1274         * arc-opc.c (arg_32bit_rc): Define new variable.
1275         (arg_32bit_u6): Likewise.
1276         (arg_32bit_limm): Likewise.
1277
1278 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1279
1280         * aarch64-gen.c (VERIFIER): Define.
1281         * aarch64-opc.c (VERIFIER): Define.
1282         (verify_ldpsw): Use static linkage.
1283         * aarch64-opc.h (verify_ldpsw): Remove.
1284         * aarch64-tbl.h: Use VERIFIER for verifiers.
1285
1286 2016-04-28  Nick Clifton  <nickc@redhat.com>
1287
1288         PR target/19722
1289         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1290         * aarch64-opc.c (verify_ldpsw): New function.
1291         * aarch64-opc.h (verify_ldpsw): New prototype.
1292         * aarch64-tbl.h: Add initialiser for verifier field.
1293         (LDPSW): Set verifier to verify_ldpsw.
1294
1295 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1296
1297         PR binutils/19983
1298         PR binutils/19984
1299         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1300         smaller than address size.
1301
1302 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1303
1304         * alpha-dis.c: Regenerate.
1305         * crx-dis.c: Likewise.
1306         * disassemble.c: Likewise.
1307         * epiphany-opc.c: Likewise.
1308         * fr30-opc.c: Likewise.
1309         * frv-opc.c: Likewise.
1310         * ip2k-opc.c: Likewise.
1311         * iq2000-opc.c: Likewise.
1312         * lm32-opc.c: Likewise.
1313         * lm32-opinst.c: Likewise.
1314         * m32c-opc.c: Likewise.
1315         * m32r-opc.c: Likewise.
1316         * m32r-opinst.c: Likewise.
1317         * mep-opc.c: Likewise.
1318         * mt-opc.c: Likewise.
1319         * or1k-opc.c: Likewise.
1320         * or1k-opinst.c: Likewise.
1321         * tic80-opc.c: Likewise.
1322         * xc16x-opc.c: Likewise.
1323         * xstormy16-opc.c: Likewise.
1324
1325 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1326
1327         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1328         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1329         calcsd, and calcxd instructions.
1330         * arc-opc.c (insert_nps_bitop_size): Delete.
1331         (extract_nps_bitop_size): Delete.
1332         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1333         (extract_nps_qcmp_m3): Define.
1334         (extract_nps_qcmp_m2): Define.
1335         (extract_nps_qcmp_m1): Define.
1336         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1337         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1338         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1339         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1340         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1341         NPS_QCMP_M3.
1342
1343 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1344
1345         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1346
1347 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1348
1349         * Makefile.in: Regenerated with automake 1.11.6.
1350         * aclocal.m4: Likewise.
1351
1352 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1353
1354         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1355         instructions.
1356         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1357         (extract_nps_cmem_uimm16): New function.
1358         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1359
1360 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1361
1362         * arc-dis.c (arc_insn_length): New function.
1363         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1364         (find_format): Change insnLen parameter to unsigned.
1365
1366 2016-04-13  Nick Clifton  <nickc@redhat.com>
1367
1368         PR target/19937
1369         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1370         the LD.B and LD.BU instructions.
1371
1372 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1373
1374         * arc-dis.c (find_format): Check for extension flags.
1375         (print_flags): New function.
1376         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1377         .extAuxRegister.
1378         * arc-ext.c (arcExtMap_coreRegName): Use
1379         LAST_EXTENSION_CORE_REGISTER.
1380         (arcExtMap_coreReadWrite): Likewise.
1381         (dump_ARC_extmap): Update printing.
1382         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1383         (arc_aux_regs): Add cpu field.
1384         * arc-regs.h: Add cpu field, lower case name aux registers.
1385
1386 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1387
1388         * arc-tbl.h: Add rtsc, sleep with no arguments.
1389
1390 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1391
1392         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1393         Initialize.
1394         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1395         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1396         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1397         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1398         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1399         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1400         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1401         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1402         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1403         (arc_opcode arc_opcodes): Null terminate the array.
1404         (arc_num_opcodes): Remove.
1405         * arc-ext.h (INSERT_XOP): Define.
1406         (extInstruction_t): Likewise.
1407         (arcExtMap_instName): Delete.
1408         (arcExtMap_insn): New function.
1409         (arcExtMap_genOpcode): Likewise.
1410         * arc-ext.c (ExtInstruction): Remove.
1411         (create_map): Zero initialize instruction fields.
1412         (arcExtMap_instName): Remove.
1413         (arcExtMap_insn): New function.
1414         (dump_ARC_extmap): More info while debuging.
1415         (arcExtMap_genOpcode): New function.
1416         * arc-dis.c (find_format): New function.
1417         (print_insn_arc): Use find_format.
1418         (arc_get_disassembler): Enable dump_ARC_extmap only when
1419         debugging.
1420
1421 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1422
1423         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1424         instruction bits out.
1425
1426 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1427
1428         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1429         * arc-opc.c (arc_flag_operands): Add new flags.
1430         (arc_flag_classes): Add new classes.
1431
1432 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1433
1434         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1435
1436 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1437
1438         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1439         encode1, rflt, crc16, and crc32 instructions.
1440         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1441         (arc_flag_classes): Add C_NPS_R.
1442         (insert_nps_bitop_size_2b): New function.
1443         (extract_nps_bitop_size_2b): Likewise.
1444         (insert_nps_bitop_uimm8): Likewise.
1445         (extract_nps_bitop_uimm8): Likewise.
1446         (arc_operands): Add new operand entries.
1447
1448 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1449
1450         * arc-regs.h: Add a new subclass field.  Add double assist
1451         accumulator register values.
1452         * arc-tbl.h: Use DPA subclass to mark the double assist
1453         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1454         * arc-opc.c (RSP): Define instead of SP.
1455         (arc_aux_regs): Add the subclass field.
1456
1457 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1458
1459         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1460
1461 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1462
1463         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1464         NPS_R_SRC1.
1465
1466 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1467
1468         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1469         issues.  No functional changes.
1470
1471 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1472
1473         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1474         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1475         (RTT): Remove duplicate.
1476         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1477         (PCT_CONFIG*): Remove.
1478         (D1L, D1H, D2H, D2L): Define.
1479
1480 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1481
1482         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1483
1484 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1485
1486         * arc-tbl.h (invld07): Remove.
1487         * arc-ext-tbl.h: New file.
1488         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1489         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1490
1491 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1492
1493         Fix -Wstack-usage warnings.
1494         * aarch64-dis.c (print_operands): Substitute size.
1495         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1496
1497 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1498
1499         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1500         to get a proper diagnostic when an invalid ASR register is used.
1501
1502 2016-03-22  Nick Clifton  <nickc@redhat.com>
1503
1504         * configure: Regenerate.
1505
1506 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1507
1508         * arc-nps400-tbl.h: New file.
1509         * arc-opc.c: Add top level comment.
1510         (insert_nps_3bit_dst): New function.
1511         (extract_nps_3bit_dst): New function.
1512         (insert_nps_3bit_src2): New function.
1513         (extract_nps_3bit_src2): New function.
1514         (insert_nps_bitop_size): New function.
1515         (extract_nps_bitop_size): New function.
1516         (arc_flag_operands): Add nps400 entries.
1517         (arc_flag_classes): Add nps400 entries.
1518         (arc_operands): Add nps400 entries.
1519         (arc_opcodes): Add nps400 include.
1520
1521 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1522
1523         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1524         the new class enum values.
1525
1526 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1527
1528         * arc-dis.c (print_insn_arc): Handle nps400.
1529
1530 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1531
1532         * arc-opc.c (BASE): Delete.
1533
1534 2016-03-18  Nick Clifton  <nickc@redhat.com>
1535
1536         PR target/19721
1537         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1538         of MOV insn that aliases an ORR insn.
1539
1540 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1541
1542         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1543
1544 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1545
1546         * mcore-opc.h: Add const qualifiers.
1547         * microblaze-opc.h (struct op_code_struct): Likewise.
1548         * sh-opc.h: Likewise.
1549         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1550         (tic4x_print_op): Likewise.
1551
1552 2016-03-02  Alan Modra  <amodra@gmail.com>
1553
1554         * or1k-desc.h: Regenerate.
1555         * fr30-ibld.c: Regenerate.
1556         * rl78-decode.c: Regenerate.
1557
1558 2016-03-01  Nick Clifton  <nickc@redhat.com>
1559
1560         PR target/19747
1561         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1562
1563 2016-02-24  Renlin Li  <renlin.li@arm.com>
1564
1565         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1566         (print_insn_coprocessor): Support fp16 instructions.
1567
1568 2016-02-24  Renlin Li  <renlin.li@arm.com>
1569
1570         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1571         vminnm, vrint(mpna).
1572
1573 2016-02-24  Renlin Li  <renlin.li@arm.com>
1574
1575         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1576         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1577
1578 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1579
1580         * i386-dis.c (print_insn): Parenthesize expression to prevent
1581         truncated addresses.
1582         (OP_J): Likewise.
1583
1584 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1585             Janek van Oirschot  <jvanoirs@synopsys.com>
1586
1587         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1588         variable.
1589
1590 2016-02-04  Nick Clifton  <nickc@redhat.com>
1591
1592         PR target/19561
1593         * msp430-dis.c (print_insn_msp430): Add a special case for
1594         decoding an RRC instruction with the ZC bit set in the extension
1595         word.
1596
1597 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1598
1599         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1600         * epiphany-ibld.c: Regenerate.
1601         * fr30-ibld.c: Regenerate.
1602         * frv-ibld.c: Regenerate.
1603         * ip2k-ibld.c: Regenerate.
1604         * iq2000-ibld.c: Regenerate.
1605         * lm32-ibld.c: Regenerate.
1606         * m32c-ibld.c: Regenerate.
1607         * m32r-ibld.c: Regenerate.
1608         * mep-ibld.c: Regenerate.
1609         * mt-ibld.c: Regenerate.
1610         * or1k-ibld.c: Regenerate.
1611         * xc16x-ibld.c: Regenerate.
1612         * xstormy16-ibld.c: Regenerate.
1613
1614 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1615
1616         * epiphany-dis.c: Regenerated from latest cpu files.
1617
1618 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1619
1620         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1621         test bit.
1622
1623 2016-01-25  Renlin Li  <renlin.li@arm.com>
1624
1625         * arm-dis.c (mapping_symbol_for_insn): New function.
1626         (find_ifthen_state): Call mapping_symbol_for_insn().
1627
1628 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1629
1630         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1631         of MSR UAO immediate operand.
1632
1633 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1634
1635         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1636         instruction support.
1637
1638 2016-01-17  Alan Modra  <amodra@gmail.com>
1639
1640         * configure: Regenerate.
1641
1642 2016-01-14  Nick Clifton  <nickc@redhat.com>
1643
1644         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1645         instructions that can support stack pointer operations.
1646         * rl78-decode.c: Regenerate.
1647         * rl78-dis.c: Fix display of stack pointer in MOVW based
1648         instructions.
1649
1650 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1651
1652         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1653         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1654         erxtatus_el1 and erxaddr_el1.
1655
1656 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1657
1658         * arm-dis.c (arm_opcodes): Add "esb".
1659         (thumb_opcodes): Likewise.
1660
1661 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1662
1663         * ppc-opc.c <xscmpnedp>: Delete.
1664         <xvcmpnedp>: Likewise.
1665         <xvcmpnedp.>: Likewise.
1666         <xvcmpnesp>: Likewise.
1667         <xvcmpnesp.>: Likewise.
1668
1669 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1670
1671         PR gas/13050
1672         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1673         addition to ISA_A.
1674
1675 2016-01-01  Alan Modra  <amodra@gmail.com>
1676
1677         Update year range in copyright notice of all files.
1678
1679 For older changes see ChangeLog-2015
1680 \f
1681 Copyright (C) 2016 Free Software Foundation, Inc.
1682
1683 Copying and distribution of this file, with or without modification,
1684 are permitted in any medium without royalty provided the copyright
1685 notice and this notice are preserved.
1686
1687 Local Variables:
1688 mode: change-log
1689 left-margin: 8
1690 fill-column: 74
1691 version-control: never
1692 End: