opcodes/ChangeLog

   1 2016-10-07  Alan Modra  <amodra@gmail.com>
   2
   3         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
   4
   5 2016-10-06  Alan Modra  <amodra@gmail.com>
   6
   7         * aarch64-opc.c: Spell fall through comments consistently.
   8         * i386-dis.c: Likewise.
   9         * aarch64-dis.c: Add missing fall through comments.
  10         * aarch64-opc.c: Likewise.
  11         * arc-dis.c: Likewise.
  12         * arm-dis.c: Likewise.
  13         * i386-dis.c: Likewise.
  14         * m68k-dis.c: Likewise.
  15         * mep-asm.c: Likewise.
  16         * ns32k-dis.c: Likewise.
  17         * sh-dis.c: Likewise.
  18         * tic4x-dis.c: Likewise.
  19         * tic6x-dis.c: Likewise.
  20         * vax-dis.c: Likewise.
  21
  22 2016-10-06  Alan Modra  <amodra@gmail.com>
  23
  24         * arc-ext.c (create_map): Add missing break.
  25         * msp430-decode.opc (encode_as): Likewise.
  26         * msp430-decode.c: Regenerate.
  27
  28 2016-10-06  Alan Modra  <amodra@gmail.com>
  29
  30         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
  31         * crx-dis.c (print_insn_crx): Likewise.
  32
  33 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         PR binutils/20657
  36         * i386-dis.c (putop): Don't assign alt twice.
  37
  38 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
  39
  40         PR target/20553
  41         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
  42
  43 2016-09-29  Alan Modra  <amodra@gmail.com>
  44
  45         * ppc-opc.c (L): Make compulsory.
  46         (LOPT): New, optional form of L.
  47         (HTM_R): Define as LOPT.
  48         (L0, L1): Delete.
  49         (L32OPT): New, optional for 32-bit L.
  50         (L2OPT): New, 2-bit L for dcbf.
  51         (SVC_LEC): Update.
  52         (L2): Define.
  53         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
  54         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
  55         <dcbf>: Use L2OPT.
  56         <tlbiel, tlbie>: Use LOPT.
  57         <wclr, wclrall>: Use L2.
  58
  59 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
  60
  61         * Makefile.in: Regenerate.
  62         * configure: Likewise.
  63
  64 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
  65
  66         * arc-ext-tbl.h (EXTINSN2OPF): Define.
  67         (EXTINSN2OP): Use EXTINSN2OPF.
  68         (bspeekm, bspop, modapp): New extension instructions.
  69         * arc-opc.c (F_DNZ_ND): Define.
  70         (F_DNZ_D): Likewise.
  71         (F_SIZEB1): Changed.
  72         (C_DNZ_D): Define.
  73         (C_HARD): Changed.
  74         * arc-tbl.h (dbnz): New instruction.
  75         (prealloc): Allow it for ARC EM.
  76         (xbfu): Likewise.
  77
  78 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  79
  80         * aarch64-opc.c (print_immediate_offset_address): Print spaces
  81         after commas in addresses.
  82         (aarch64_print_operand): Likewise.
  83
  84 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  85
  86         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
  87         rather than "should be" or "expected to be" in error messages.
  88
  89 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  90
  91         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
  92         (print_mnemonic_name): ...here.
  93         (print_comment): New function.
  94         (print_aarch64_insn): Call it.
  95         * aarch64-opc.c (aarch64_conds): Add SVE names.
  96         (aarch64_print_operand): Print alternative condition names in
  97         a comment.
  98
  99 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 100
 101         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 102         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 103         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 104         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 105         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 106         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 107         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 108         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 109         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 110         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 111         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 112         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 113         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 114         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 115         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 116         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 117         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 118         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 119         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 120         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 121         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 122         (aarch64_feature_sve): New variable.
 123         (SVE): New macro.
 124         (_SVE_INSN): Likewise.
 125         (aarch64_opcode_table): Add SVE instructions.
 126         * aarch64-opc.h (extract_fields): Declare.
 127         * aarch64-opc-2.c: Regenerate.
 128         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 129         * aarch64-asm-2.c: Regenerate.
 130         * aarch64-dis.c (extract_fields): Make global.
 131         (do_misc_decoding): Handle the new SVE aarch64_ops.
 132         * aarch64-dis-2.c: Regenerate.
 133
 134 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 135
 136         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 137         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 138         aarch64_field_kinds.
 139         * aarch64-opc.c (fields): Add corresponding entries.
 140         * aarch64-asm.c (aarch64_get_variant): New function.
 141         (aarch64_encode_variant_using_iclass): Likewise.
 142         (aarch64_opcode_encode): Call it.
 143         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 144         (aarch64_opcode_decode): Call it.
 145
 146 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 147
 148         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 149         and FP register operands.
 150         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 151         (FLD_SVE_Vn): New aarch64_field_kinds.
 152         * aarch64-opc.c (fields): Add corresponding entries.
 153         (aarch64_print_operand): Handle the new SVE core and FP register
 154         operands.
 155         * aarch64-opc-2.c: Regenerate.
 156         * aarch64-asm-2.c: Likewise.
 157         * aarch64-dis-2.c: Likewise.
 158
 159 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 160
 161         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 162         immediate operands.
 163         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 164         * aarch64-opc.c (fields): Add corresponding entry.
 165         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 166         operands.
 167         (aarch64_print_operand): Likewise.
 168         * aarch64-opc-2.c: Regenerate.
 169         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 170         (ins_sve_float_zero_one): New inserters.
 171         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 172         (aarch64_ins_sve_float_half_two): Likewise.
 173         (aarch64_ins_sve_float_zero_one): Likewise.
 174         * aarch64-asm-2.c: Regenerate.
 175         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 176         (ext_sve_float_zero_one): New extractors.
 177         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 178         (aarch64_ext_sve_float_half_two): Likewise.
 179         (aarch64_ext_sve_float_zero_one): Likewise.
 180         * aarch64-dis-2.c: Regenerate.
 181
 182 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 183
 184         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 185         integer immediate operands.
 186         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 187         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 188         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 189         * aarch64-opc.c (fields): Add corresponding entries.
 190         (operand_general_constraint_met_p): Handle the new SVE integer
 191         immediate operands.
 192         (aarch64_print_operand): Likewise.
 193         (aarch64_sve_dupm_mov_immediate_p): New function.
 194         * aarch64-opc-2.c: Regenerate.
 195         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 196         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 197         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 198         (aarch64_ins_limm): ...here.
 199         (aarch64_ins_inv_limm): New function.
 200         (aarch64_ins_sve_aimm): Likewise.
 201         (aarch64_ins_sve_asimm): Likewise.
 202         (aarch64_ins_sve_limm_mov): Likewise.
 203         (aarch64_ins_sve_shlimm): Likewise.
 204         (aarch64_ins_sve_shrimm): Likewise.
 205         * aarch64-asm-2.c: Regenerate.
 206         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 207         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 208         * aarch64-dis.c (decode_limm): New function, split out from...
 209         (aarch64_ext_limm): ...here.
 210         (aarch64_ext_inv_limm): New function.
 211         (decode_sve_aimm): Likewise.
 212         (aarch64_ext_sve_aimm): Likewise.
 213         (aarch64_ext_sve_asimm): Likewise.
 214         (aarch64_ext_sve_limm_mov): Likewise.
 215         (aarch64_top_bit): Likewise.
 216         (aarch64_ext_sve_shlimm): Likewise.
 217         (aarch64_ext_sve_shrimm): Likewise.
 218         * aarch64-dis-2.c: Regenerate.
 219
 220 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 221
 222         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 223         operands.
 224         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 225         the AARCH64_MOD_MUL_VL entry.
 226         (value_aligned_p): Cope with non-power-of-two alignments.
 227         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 228         (print_immediate_offset_address): Likewise.
 229         (aarch64_print_operand): Likewise.
 230         * aarch64-opc-2.c: Regenerate.
 231         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 232         (ins_sve_addr_ri_s9xvl): New inserters.
 233         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 234         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 235         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 236         * aarch64-asm-2.c: Regenerate.
 237         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 238         (ext_sve_addr_ri_s9xvl): New extractors.
 239         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 240         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 241         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 242         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 243         * aarch64-dis-2.c: Regenerate.
 244
 245 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 246
 247         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 248         address operands.
 249         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 250         (FLD_SVE_xs_22): New aarch64_field_kinds.
 251         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 252         (get_operand_specific_data): New function.
 253         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 254         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 255         (operand_general_constraint_met_p): Handle the new SVE address
 256         operands.
 257         (sve_reg): New array.
 258         (get_addr_sve_reg_name): New function.
 259         (aarch64_print_operand): Handle the new SVE address operands.
 260         * aarch64-opc-2.c: Regenerate.
 261         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 262         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 263         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 264         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 265         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 266         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 267         (aarch64_ins_sve_addr_zi_u5): Likewise.
 268         (aarch64_ins_sve_addr_zz): Likewise.
 269         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 270         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 271         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 272         * aarch64-asm-2.c: Regenerate.
 273         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 274         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 275         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 276         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 277         (aarch64_ext_sve_addr_ri_u6): Likewise.
 278         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 279         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 280         (aarch64_ext_sve_addr_zi_u5): Likewise.
 281         (aarch64_ext_sve_addr_zz): Likewise.
 282         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 283         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 284         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 285         * aarch64-dis-2.c: Regenerate.
 286
 287 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 288
 289         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 290         AARCH64_OPND_SVE_PATTERN_SCALED.
 291         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 292         * aarch64-opc.c (fields): Add a corresponding entry.
 293         (set_multiplier_out_of_range_error): New function.
 294         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 295         (operand_general_constraint_met_p): Handle
 296         AARCH64_OPND_SVE_PATTERN_SCALED.
 297         (print_register_offset_address): Use PRIi64 to print the
 298         shift amount.
 299         (aarch64_print_operand): Likewise.  Handle
 300         AARCH64_OPND_SVE_PATTERN_SCALED.
 301         * aarch64-opc-2.c: Regenerate.
 302         * aarch64-asm.h (ins_sve_scale): New inserter.
 303         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 304         * aarch64-asm-2.c: Regenerate.
 305         * aarch64-dis.h (ext_sve_scale): New inserter.
 306         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 307         * aarch64-dis-2.c: Regenerate.
 308
 309 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 310
 311         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 312         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 313         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 314         (FLD_SVE_prfop): Likewise.
 315         * aarch64-opc.c: Include libiberty.h.
 316         (aarch64_sve_pattern_array): New variable.
 317         (aarch64_sve_prfop_array): Likewise.
 318         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 319         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 320         AARCH64_OPND_SVE_PRFOP.
 321         * aarch64-asm-2.c: Regenerate.
 322         * aarch64-dis-2.c: Likewise.
 323         * aarch64-opc-2.c: Likewise.
 324
 325 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 326
 327         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 328         AARCH64_OPND_QLF_P_[ZM].
 329         (aarch64_print_operand): Print /z and /m where appropriate.
 330
 331 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 332
 333         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 334         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 335         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 336         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 337         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 338         * aarch64-opc.c (fields): Add corresponding entries here.
 339         (operand_general_constraint_met_p): Check that SVE register lists
 340         have the correct length.  Check the ranges of SVE index registers.
 341         Check for cases where p8-p15 are used in 3-bit predicate fields.
 342         (aarch64_print_operand): Handle the new SVE operands.
 343         * aarch64-opc-2.c: Regenerate.
 344         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 345         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 346         (aarch64_ins_sve_reglist): Likewise.
 347         * aarch64-asm-2.c: Regenerate.
 348         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 349         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 350         (aarch64_ext_sve_reglist): Likewise.
 351         * aarch64-dis-2.c: Regenerate.
 352
 353 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 354
 355         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 356         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 357         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 358         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 359         tied operands.
 360
 361 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 362
 363         * aarch64-opc.c (get_offset_int_reg_name): New function.
 364         (print_immediate_offset_address): Likewise.
 365         (print_register_offset_address): Take the base and offset
 366         registers as parameters.
 367         (aarch64_print_operand): Update caller accordingly.  Use
 368         print_immediate_offset_address.
 369
 370 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 371
 372         * aarch64-opc.c (BANK): New macro.
 373         (R32, R64): Take a register number as argument
 374         (int_reg): Use BANK.
 375
 376 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 377
 378         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 379         (aarch64_print_operand): Update accordingly.
 380
 381 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 382
 383         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 384         for FPIMM.
 385         * aarch64-asm.h (ins_fpimm): New inserter.
 386         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 387         * aarch64-asm-2.c: Regenerate.
 388         * aarch64-dis.h (ext_fpimm): New extractor.
 389         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 390         (aarch64_ext_fpimm): New function.
 391         * aarch64-dis-2.c: Regenerate.
 392
 393 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 394
 395         * aarch64-asm.c: Include libiberty.h.
 396         (insert_fields): New function.
 397         (aarch64_ins_imm): Use it.
 398         * aarch64-dis.c (extract_fields): New function.
 399         (aarch64_ext_imm): Use it.
 400
 401 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 402
 403         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 404         with an esize parameter.
 405         (operand_general_constraint_met_p): Update accordingly.
 406         Fix misindented code.
 407         * aarch64-asm.c (aarch64_ins_limm): Update call to
 408         aarch64_logical_immediate_p.
 409
 410 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 411
 412         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 413
 414 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 415
 416         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 417
 418 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 419
 420         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 421
 422 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 423
 424         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 425         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 426         xor3>: Delete mnemonics.
 427         <cp_abort>: Rename mnemonic from ...
 428         <cpabort>: ...to this.
 429         <setb>: Change to a X form instruction.
 430         <sync>: Change to 1 operand form.
 431         <copy>: Delete mnemonic.
 432         <copy_first>: Rename mnemonic from ...
 433         <copy>: ...to this.
 434         <paste, paste.>: Delete mnemonics.
 435         <paste_last>: Rename mnemonic from ...
 436         <paste.>: ...to this.
 437
 438 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 439
 440         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 441
 442 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 443
 444         * s390-mkopc.c (main): Support alternate arch strings.
 445
 446 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 447
 448         * s390-opc.txt: Fix kmctr instruction type.
 449
 450 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 453         * i386-init.h: Regenerated.
 454
 455 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 456
 457         * opcodes/arc-dis.c (print_insn_arc): Changed.
 458
 459 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 460
 461         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 462         camellia_fl.
 463
 464 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 465
 466         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 467         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 468         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 469
 470 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 471
 472         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 473         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 474         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 475         PREFIX_MOD_3_0FAE_REG_4.
 476         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 477         PREFIX_MOD_3_0FAE_REG_4.
 478         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 479         (cpu_flags): Add CpuPTWRITE.
 480         * i386-opc.h (CpuPTWRITE): New.
 481         (i386_cpu_flags): Add cpuptwrite.
 482         * i386-opc.tbl: Add ptwrite instruction.
 483         * i386-init.h: Regenerated.
 484         * i386-tbl.h: Likewise.
 485
 486 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 487
 488         * arc-dis.h: Wrap around in extern "C".
 489
 490 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 491
 492         * aarch64-tbl.h (V8_2_INSN): New macro.
 493         (aarch64_opcode_table): Use it.
 494
 495 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 496
 497         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 498         CORE_INSN, __FP_INSN and SIMD_INSN.
 499
 500 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 501
 502         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 503         (aarch64_opcode_table): Update uses accordingly.
 504
 505 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 506         Kwok Cheung Yeung  <kcy@codesourcery.com>
 507
 508         opcodes/
 509         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 510         'e_cmplwi' to 'e_cmpli' instead.
 511         (OPVUPRT, OPVUPRT_MASK): Define.
 512         (powerpc_opcodes): Add E200Z4 insns.
 513         (vle_opcodes): Add context save/restore insns.
 514
 515 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 516
 517         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 518         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 519         "j".
 520
 521 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 522
 523         * arc-nps400-tbl.h: Change block comments to GNU format.
 524         * arc-dis.c: Add new globals addrtypenames,
 525         addrtypenames_max, and addtypeunknown.
 526         (get_addrtype): New function.
 527         (print_insn_arc): Print colons and address types when
 528         required.
 529         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 530         define insert and extract functions for all address types.
 531         (arc_operands): Add operands for colon and all address
 532         types.
 533         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 534         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 535         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 536         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 537         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 538         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 539
 540 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 541
 542         * configure: Regenerated.
 543
 544 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 545
 546         * arc-dis.c (skipclass): New structure.
 547         (decodelist): New variable.
 548         (is_compatible_p): New function.
 549         (new_element): Likewise.
 550         (skip_class_p): Likewise.
 551         (find_format_from_table): Use skip_class_p function.
 552         (find_format): Decode first the extension instructions.
 553         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 554         e_flags.
 555         (parse_option): New function.
 556         (parse_disassembler_options): Likewise.
 557         (print_arc_disassembler_options): Likewise.
 558         (print_insn_arc): Use parse_disassembler_options function.  Proper
 559         select ARCv2 cpu variant.
 560         * disassemble.c (disassembler_usage): Add ARC disassembler
 561         options.
 562
 563 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 564
 565         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 566         annotation from the "nal" entry and reorder it beyond "bltzal".
 567
 568 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 569
 570         * sparc-opc.c (ldtxa): New macro.
 571         (sparc_opcodes): Use the macro defined above to add entries for
 572         the LDTXA instructions.
 573         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 574         instruction.
 575
 576 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 577
 578         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 579         and "jmpc".
 580
 581 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 582
 583         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 584         (movzb): Adjust to cover all permitted suffixes.
 585         (movzw): New.
 586         * i386-tbl.h: Re-generate.
 587
 588 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 589
 590         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 591         (lgdt): Remove Tbyte from non-64-bit variant.
 592         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 593         xsaves64, xsavec64): Remove Disp16.
 594         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 595         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 596         64-bit variants.
 597         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 598         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 599         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 600         64-bit variants.
 601         * i386-tbl.h: Re-generate.
 602
 603 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 606         * i386-tbl.h: Re-generate.
 607
 608 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 609
 610         * arm-dis.c (print_insn): Fix typo in comment.
 611
 612 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 613
 614         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 615         range of ldst_elemlist operands.
 616         (print_register_list): Use PRIi64 to print the index.
 617         (aarch64_print_operand): Likewise.
 618
 619 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 620
 621         * mcore-opc.h: Remove sentinal.
 622         * mcore-dis.c (print_insn_mcore): Adjust.
 623
 624 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 625
 626         * arc-opc.c: Correct description of availability of NPS400
 627         features.
 628
 629 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 630
 631         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 632         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 633         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 634         xor3>: New mnemonics.
 635         <setb>: Change to a VX form instruction.
 636         (insert_sh6): Add support for rldixor.
 637         (extract_sh6): Likewise.
 638
 639 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 640
 641         * arc-ext.h: Wrap in extern C.
 642
 643 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 644
 645         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 646         Use same method for determining instruction length on ARC700 and
 647         NPS-400.
 648         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 649         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 650         with the NPS400 subclass.
 651         * arc-opc.c: Likewise.
 652
 653 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 654
 655         * sparc-opc.c (rdasr): New macro.
 656         (wrasr): Likewise.
 657         (rdpr): Likewise.
 658         (wrpr): Likewise.
 659         (rdhpr): Likewise.
 660         (wrhpr): Likewise.
 661         (sparc_opcodes): Use the macros above to fix and expand the
 662         definition of read/write instructions from/to
 663         asr/privileged/hyperprivileged instructions.
 664         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 665         %hva_mask_nz.  Prefer softint_set and softint_clear over
 666         set_softint and clear_softint.
 667         (print_insn_sparc): Support %ver in Rd.
 668
 669 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 670
 671         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 672         architecture according to the hardware capabilities they require.
 673
 674 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 675
 676         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 677         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 678         bfd_mach_sparc_v9{c,d,e,v,m}.
 679         * sparc-opc.c (MASK_V9C): Define.
 680         (MASK_V9D): Likewise.
 681         (MASK_V9E): Likewise.
 682         (MASK_V9V): Likewise.
 683         (MASK_V9M): Likewise.
 684         (v6): Add MASK_V9{C,D,E,V,M}.
 685         (v6notlet): Likewise.
 686         (v7): Likewise.
 687         (v8): Likewise.
 688         (v9): Likewise.
 689         (v9andleon): Likewise.
 690         (v9a): Likewise.
 691         (v9b): Likewise.
 692         (v9c): Define.
 693         (v9d): Likewise.
 694         (v9e): Likewise.
 695         (v9v): Likewise.
 696         (v9m): Likewise.
 697         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 698
 699 2016-06-15  Nick Clifton  <nickc@redhat.com>
 700
 701         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 702         constants to match expected behaviour.
 703         (nds32_parse_opcode): Likewise.  Also for whitespace.
 704
 705 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 706
 707         * arc-opc.c (extract_rhv1): Extract value from insn.
 708
 709 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 710
 711         * arc-nps400-tbl.h: Add ldbit instruction.
 712         * arc-opc.c: Add flag classes required for ldbit.
 713
 714 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 715
 716         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 717         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 718         support the above instructions.
 719
 720 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 721
 722         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 723         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 724         csma, cbba, zncv, and hofs.
 725         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 726         support the above instructions.
 727
 728 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 729
 730         * arc-nps400-tbl.h: Add andab and orab instructions.
 731
 732 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 733
 734         * arc-nps400-tbl.h: Add addl-like instructions.
 735
 736 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 737
 738         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 739
 740 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 741
 742         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 743         instructions.
 744
 745 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 746
 747         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 748         variable.
 749         (init_disasm): Handle new command line option "insnlength".
 750         (print_s390_disassembler_options): Mention new option in help
 751         output.
 752         (print_insn_s390): Use the encoded insn length when dumping
 753         unknown instructions.
 754
 755 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 756
 757         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 758          to the address and set as symbol address for LDS/ STS immediate operands.
 759
 760 2016-06-07  Alan Modra  <amodra@gmail.com>
 761
 762         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 763         cpu for "vle" to e500.
 764         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 765         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 766         (PPCNONE): Delete, substitute throughout.
 767         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 768         except for major opcode 4 and 31.
 769         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 770
 771 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 772
 773         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 774         ARM_EXT_RAS in relevant entries.
 775
 776 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 777
 778         PR binutils/20196
 779         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 780         opcodes for E6500.
 781
 782 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 783
 784         PR binutis/18386
 785         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 786         (indir_v_mode): New.
 787         Add comments for '&'.
 788         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 789         (putop): Handle '&'.
 790         (intel_operand_size): Handle indir_v_mode.
 791         (OP_E_register): Likewise.
 792         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 793         64-bit indirect call/jmp for AMD64.
 794         * i386-tbl.h: Regenerated
 795
 796 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 797
 798         * arc-dis.c (struct arc_operand_iterator): New structure.
 799         (find_format_from_table): All the old content from find_format,
 800         with some minor adjustments, and parameter renaming.
 801         (find_format_long_instructions): New function.
 802         (find_format): Rewritten.
 803         (arc_insn_length): Add LSB parameter.
 804         (extract_operand_value): New function.
 805         (operand_iterator_next): New function.
 806         (print_insn_arc): Use new functions to find opcode, and iterator
 807         over operands.
 808         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 809         (extract_nps_3bit_dst_short): New function.
 810         (insert_nps_3bit_src2_short): New function.
 811         (extract_nps_3bit_src2_short): New function.
 812         (insert_nps_bitop1_size): New function.
 813         (extract_nps_bitop1_size): New function.
 814         (insert_nps_bitop2_size): New function.
 815         (extract_nps_bitop2_size): New function.
 816         (insert_nps_bitop_mod4_msb): New function.
 817         (extract_nps_bitop_mod4_msb): New function.
 818         (insert_nps_bitop_mod4_lsb): New function.
 819         (extract_nps_bitop_mod4_lsb): New function.
 820         (insert_nps_bitop_dst_pos3_pos4): New function.
 821         (extract_nps_bitop_dst_pos3_pos4): New function.
 822         (insert_nps_bitop_ins_ext): New function.
 823         (extract_nps_bitop_ins_ext): New function.
 824         (arc_operands): Add new operands.
 825         (arc_long_opcodes): New global array.
 826         (arc_num_long_opcodes): New global.
 827         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 828
 829 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 830
 831         * nds32-asm.h: Add extern "C".
 832         * sh-opc.h: Likewise.
 833
 834 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 835
 836         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 837         0,b,limm to the rflt instruction.
 838
 839 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 840
 841         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 842         constant.
 843
 844 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 845
 846         PR gas/20145
 847         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 848         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 849         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 850         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 851         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 852         * i386-init.h: Regenerated.
 853
 854 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 855
 856         PR gas/20145
 857         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 858         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 859         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 860         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 861         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 862         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 863         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 864         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 865         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 866         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 867         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 868         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 869         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 870         CpuRegMask for AVX512.
 871         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 872         and CpuRegMask.
 873         (set_bitfield_from_cpu_flag_init): New function.
 874         (set_bitfield): Remove const on f.  Call
 875         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 876         * i386-opc.h (CpuRegMMX): New.
 877         (CpuRegXMM): Likewise.
 878         (CpuRegYMM): Likewise.
 879         (CpuRegZMM): Likewise.
 880         (CpuRegMask): Likewise.
 881         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 882         and cpuregmask.
 883         * i386-init.h: Regenerated.
 884         * i386-tbl.h: Likewise.
 885
 886 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 887
 888         PR gas/20154
 889         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 890         (opcode_modifiers): Add AMD64 and Intel64.
 891         (main): Properly verify CpuMax.
 892         * i386-opc.h (CpuAMD64): Removed.
 893         (CpuIntel64): Likewise.
 894         (CpuMax): Set to CpuNo64.
 895         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 896         (AMD64): New.
 897         (Intel64): Likewise.
 898         (i386_opcode_modifier): Add amd64 and intel64.
 899         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 900         on call and jmp.
 901         * i386-init.h: Regenerated.
 902         * i386-tbl.h: Likewise.
 903
 904 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 905
 906         PR gas/20154
 907         * i386-gen.c (main): Fail if CpuMax is incorrect.
 908         * i386-opc.h (CpuMax): Set to CpuIntel64.
 909         * i386-tbl.h: Regenerated.
 910
 911 2016-05-27  Nick Clifton  <nickc@redhat.com>
 912
 913         PR target/20150
 914         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 915         (msp430dis_opcode_unsigned): New function.
 916         (msp430dis_opcode_signed): New function.
 917         (msp430_singleoperand): Use the new opcode reading functions.
 918         Only disassenmble bytes if they were successfully read.
 919         (msp430_doubleoperand): Likewise.
 920         (msp430_branchinstr): Likewise.
 921         (msp430x_callx_instr): Likewise.
 922         (print_insn_msp430): Check that it is safe to read bytes before
 923         attempting disassembly.  Use the new opcode reading functions.
 924
 925 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 926
 927         * ppc-opc.c (CY): New define.  Document it.
 928         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 929
 930 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 931
 932         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 933         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 934         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 935         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 936         CPU_ANY_AVX_FLAGS.
 937         * i386-init.h: Regenerated.
 938
 939 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 940
 941         PR gas/20141
 942         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 943         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 944         * i386-init.h: Regenerated.
 945
 946 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 947
 948         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 949         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 950         * i386-init.h: Regenerated.
 951
 952 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 953
 954         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 955         information.
 956         (print_insn_arc): Set insn_type information.
 957         * arc-opc.c (C_CC): Add F_CLASS_COND.
 958         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 959         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 960         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 961         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 962         (brne, brne_s, jeq_s, jne_s): Likewise.
 963
 964 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 965
 966         * arc-tbl.h (neg): New instruction variant.
 967
 968 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 969
 970         * arc-dis.c (find_format, find_format, get_auxreg)
 971         (print_insn_arc): Changed.
 972         * arc-ext.h (INSERT_XOP): Likewise.
 973
 974 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 975
 976         * tic54x-dis.c (sprint_mmr): Adjust.
 977         * tic54x-opc.c: Likewise.
 978
 979 2016-05-19  Alan Modra  <amodra@gmail.com>
 980
 981         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 982
 983 2016-05-19  Alan Modra  <amodra@gmail.com>
 984
 985         * ppc-opc.c: Formatting.
 986         (NSISIGNOPT): Define.
 987         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 988
 989 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 990
 991         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 992         replacing references to `micromips_ase' throughout.
 993         (_print_insn_mips): Don't use file-level microMIPS annotation to
 994         determine the disassembly mode with the symbol table.
 995
 996 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 997
 998         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 999
1000 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1001
1002         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1003         mips64r6.
1004         * mips-opc.c (D34): New macro.
1005         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1006
1007 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1008
1009         * i386-dis.c (prefix_table): Add RDPID instruction.
1010         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1011         (cpu_flags): Add RDPID bitfield.
1012         * i386-opc.h (enum): Add RDPID element.
1013         (i386_cpu_flags): Add RDPID field.
1014         * i386-opc.tbl: Add RDPID instruction.
1015         * i386-init.h: Regenerate.
1016         * i386-tbl.h: Regenerate.
1017
1018 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1019
1020         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1021         branch type of a symbol.
1022         (print_insn): Likewise.
1023
1024 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1025
1026         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1027         Mainline Security Extensions instructions.
1028         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1029         Extensions instructions.
1030         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1031         instructions.
1032         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1033         special registers.
1034
1035 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1036
1037         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1038
1039 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1040
1041         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1042         (arcExtMap_genOpcode): Likewise.
1043         * arc-opc.c (arg_32bit_rc): Define new variable.
1044         (arg_32bit_u6): Likewise.
1045         (arg_32bit_limm): Likewise.
1046
1047 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1048
1049         * aarch64-gen.c (VERIFIER): Define.
1050         * aarch64-opc.c (VERIFIER): Define.
1051         (verify_ldpsw): Use static linkage.
1052         * aarch64-opc.h (verify_ldpsw): Remove.
1053         * aarch64-tbl.h: Use VERIFIER for verifiers.
1054
1055 2016-04-28  Nick Clifton  <nickc@redhat.com>
1056
1057         PR target/19722
1058         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1059         * aarch64-opc.c (verify_ldpsw): New function.
1060         * aarch64-opc.h (verify_ldpsw): New prototype.
1061         * aarch64-tbl.h: Add initialiser for verifier field.
1062         (LDPSW): Set verifier to verify_ldpsw.
1063
1064 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1065
1066         PR binutils/19983
1067         PR binutils/19984
1068         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1069         smaller than address size.
1070
1071 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1072
1073         * alpha-dis.c: Regenerate.
1074         * crx-dis.c: Likewise.
1075         * disassemble.c: Likewise.
1076         * epiphany-opc.c: Likewise.
1077         * fr30-opc.c: Likewise.
1078         * frv-opc.c: Likewise.
1079         * ip2k-opc.c: Likewise.
1080         * iq2000-opc.c: Likewise.
1081         * lm32-opc.c: Likewise.
1082         * lm32-opinst.c: Likewise.
1083         * m32c-opc.c: Likewise.
1084         * m32r-opc.c: Likewise.
1085         * m32r-opinst.c: Likewise.
1086         * mep-opc.c: Likewise.
1087         * mt-opc.c: Likewise.
1088         * or1k-opc.c: Likewise.
1089         * or1k-opinst.c: Likewise.
1090         * tic80-opc.c: Likewise.
1091         * xc16x-opc.c: Likewise.
1092         * xstormy16-opc.c: Likewise.
1093
1094 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1095
1096         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1097         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1098         calcsd, and calcxd instructions.
1099         * arc-opc.c (insert_nps_bitop_size): Delete.
1100         (extract_nps_bitop_size): Delete.
1101         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1102         (extract_nps_qcmp_m3): Define.
1103         (extract_nps_qcmp_m2): Define.
1104         (extract_nps_qcmp_m1): Define.
1105         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1106         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1107         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1108         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1109         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1110         NPS_QCMP_M3.
1111
1112 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1113
1114         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1115
1116 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1117
1118         * Makefile.in: Regenerated with automake 1.11.6.
1119         * aclocal.m4: Likewise.
1120
1121 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1122
1123         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1124         instructions.
1125         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1126         (extract_nps_cmem_uimm16): New function.
1127         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1128
1129 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1130
1131         * arc-dis.c (arc_insn_length): New function.
1132         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1133         (find_format): Change insnLen parameter to unsigned.
1134
1135 2016-04-13  Nick Clifton  <nickc@redhat.com>
1136
1137         PR target/19937
1138         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1139         the LD.B and LD.BU instructions.
1140
1141 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1142
1143         * arc-dis.c (find_format): Check for extension flags.
1144         (print_flags): New function.
1145         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1146         .extAuxRegister.
1147         * arc-ext.c (arcExtMap_coreRegName): Use
1148         LAST_EXTENSION_CORE_REGISTER.
1149         (arcExtMap_coreReadWrite): Likewise.
1150         (dump_ARC_extmap): Update printing.
1151         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1152         (arc_aux_regs): Add cpu field.
1153         * arc-regs.h: Add cpu field, lower case name aux registers.
1154
1155 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1156
1157         * arc-tbl.h: Add rtsc, sleep with no arguments.
1158
1159 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1160
1161         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1162         Initialize.
1163         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1164         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1165         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1166         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1167         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1168         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1169         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1170         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1171         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1172         (arc_opcode arc_opcodes): Null terminate the array.
1173         (arc_num_opcodes): Remove.
1174         * arc-ext.h (INSERT_XOP): Define.
1175         (extInstruction_t): Likewise.
1176         (arcExtMap_instName): Delete.
1177         (arcExtMap_insn): New function.
1178         (arcExtMap_genOpcode): Likewise.
1179         * arc-ext.c (ExtInstruction): Remove.
1180         (create_map): Zero initialize instruction fields.
1181         (arcExtMap_instName): Remove.
1182         (arcExtMap_insn): New function.
1183         (dump_ARC_extmap): More info while debuging.
1184         (arcExtMap_genOpcode): New function.
1185         * arc-dis.c (find_format): New function.
1186         (print_insn_arc): Use find_format.
1187         (arc_get_disassembler): Enable dump_ARC_extmap only when
1188         debugging.
1189
1190 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1191
1192         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1193         instruction bits out.
1194
1195 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1196
1197         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1198         * arc-opc.c (arc_flag_operands): Add new flags.
1199         (arc_flag_classes): Add new classes.
1200
1201 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1202
1203         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1204
1205 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1206
1207         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1208         encode1, rflt, crc16, and crc32 instructions.
1209         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1210         (arc_flag_classes): Add C_NPS_R.
1211         (insert_nps_bitop_size_2b): New function.
1212         (extract_nps_bitop_size_2b): Likewise.
1213         (insert_nps_bitop_uimm8): Likewise.
1214         (extract_nps_bitop_uimm8): Likewise.
1215         (arc_operands): Add new operand entries.
1216
1217 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1218
1219         * arc-regs.h: Add a new subclass field.  Add double assist
1220         accumulator register values.
1221         * arc-tbl.h: Use DPA subclass to mark the double assist
1222         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1223         * arc-opc.c (RSP): Define instead of SP.
1224         (arc_aux_regs): Add the subclass field.
1225
1226 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1227
1228         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1229
1230 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1231
1232         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1233         NPS_R_SRC1.
1234
1235 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1236
1237         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1238         issues.  No functional changes.
1239
1240 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1241
1242         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1243         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1244         (RTT): Remove duplicate.
1245         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1246         (PCT_CONFIG*): Remove.
1247         (D1L, D1H, D2H, D2L): Define.
1248
1249 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1250
1251         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1252
1253 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1254
1255         * arc-tbl.h (invld07): Remove.
1256         * arc-ext-tbl.h: New file.
1257         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1258         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1259
1260 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1261
1262         Fix -Wstack-usage warnings.
1263         * aarch64-dis.c (print_operands): Substitute size.
1264         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1265
1266 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1267
1268         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1269         to get a proper diagnostic when an invalid ASR register is used.
1270
1271 2016-03-22  Nick Clifton  <nickc@redhat.com>
1272
1273         * configure: Regenerate.
1274
1275 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1276
1277         * arc-nps400-tbl.h: New file.
1278         * arc-opc.c: Add top level comment.
1279         (insert_nps_3bit_dst): New function.
1280         (extract_nps_3bit_dst): New function.
1281         (insert_nps_3bit_src2): New function.
1282         (extract_nps_3bit_src2): New function.
1283         (insert_nps_bitop_size): New function.
1284         (extract_nps_bitop_size): New function.
1285         (arc_flag_operands): Add nps400 entries.
1286         (arc_flag_classes): Add nps400 entries.
1287         (arc_operands): Add nps400 entries.
1288         (arc_opcodes): Add nps400 include.
1289
1290 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1291
1292         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1293         the new class enum values.
1294
1295 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1296
1297         * arc-dis.c (print_insn_arc): Handle nps400.
1298
1299 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1300
1301         * arc-opc.c (BASE): Delete.
1302
1303 2016-03-18  Nick Clifton  <nickc@redhat.com>
1304
1305         PR target/19721
1306         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1307         of MOV insn that aliases an ORR insn.
1308
1309 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1310
1311         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1312
1313 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1314
1315         * mcore-opc.h: Add const qualifiers.
1316         * microblaze-opc.h (struct op_code_struct): Likewise.
1317         * sh-opc.h: Likewise.
1318         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1319         (tic4x_print_op): Likewise.
1320
1321 2016-03-02  Alan Modra  <amodra@gmail.com>
1322
1323         * or1k-desc.h: Regenerate.
1324         * fr30-ibld.c: Regenerate.
1325         * rl78-decode.c: Regenerate.
1326
1327 2016-03-01  Nick Clifton  <nickc@redhat.com>
1328
1329         PR target/19747
1330         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1331
1332 2016-02-24  Renlin Li  <renlin.li@arm.com>
1333
1334         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1335         (print_insn_coprocessor): Support fp16 instructions.
1336
1337 2016-02-24  Renlin Li  <renlin.li@arm.com>
1338
1339         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1340         vminnm, vrint(mpna).
1341
1342 2016-02-24  Renlin Li  <renlin.li@arm.com>
1343
1344         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1345         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1346
1347 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1348
1349         * i386-dis.c (print_insn): Parenthesize expression to prevent
1350         truncated addresses.
1351         (OP_J): Likewise.
1352
1353 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1354             Janek van Oirschot  <jvanoirs@synopsys.com>
1355
1356         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1357         variable.
1358
1359 2016-02-04  Nick Clifton  <nickc@redhat.com>
1360
1361         PR target/19561
1362         * msp430-dis.c (print_insn_msp430): Add a special case for
1363         decoding an RRC instruction with the ZC bit set in the extension
1364         word.
1365
1366 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1367
1368         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1369         * epiphany-ibld.c: Regenerate.
1370         * fr30-ibld.c: Regenerate.
1371         * frv-ibld.c: Regenerate.
1372         * ip2k-ibld.c: Regenerate.
1373         * iq2000-ibld.c: Regenerate.
1374         * lm32-ibld.c: Regenerate.
1375         * m32c-ibld.c: Regenerate.
1376         * m32r-ibld.c: Regenerate.
1377         * mep-ibld.c: Regenerate.
1378         * mt-ibld.c: Regenerate.
1379         * or1k-ibld.c: Regenerate.
1380         * xc16x-ibld.c: Regenerate.
1381         * xstormy16-ibld.c: Regenerate.
1382
1383 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1384
1385         * epiphany-dis.c: Regenerated from latest cpu files.
1386
1387 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1388
1389         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1390         test bit.
1391
1392 2016-01-25  Renlin Li  <renlin.li@arm.com>
1393
1394         * arm-dis.c (mapping_symbol_for_insn): New function.
1395         (find_ifthen_state): Call mapping_symbol_for_insn().
1396
1397 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1398
1399         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1400         of MSR UAO immediate operand.
1401
1402 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1403
1404         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1405         instruction support.
1406
1407 2016-01-17  Alan Modra  <amodra@gmail.com>
1408
1409         * configure: Regenerate.
1410
1411 2016-01-14  Nick Clifton  <nickc@redhat.com>
1412
1413         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1414         instructions that can support stack pointer operations.
1415         * rl78-decode.c: Regenerate.
1416         * rl78-dis.c: Fix display of stack pointer in MOVW based
1417         instructions.
1418
1419 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1420
1421         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1422         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1423         erxtatus_el1 and erxaddr_el1.
1424
1425 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1426
1427         * arm-dis.c (arm_opcodes): Add "esb".
1428         (thumb_opcodes): Likewise.
1429
1430 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1431
1432         * ppc-opc.c <xscmpnedp>: Delete.
1433         <xvcmpnedp>: Likewise.
1434         <xvcmpnedp.>: Likewise.
1435         <xvcmpnesp>: Likewise.
1436         <xvcmpnesp.>: Likewise.
1437
1438 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1439
1440         PR gas/13050
1441         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1442         addition to ISA_A.
1443
1444 2016-01-01  Alan Modra  <amodra@gmail.com>
1445
1446         Update year range in copyright notice of all files.
1447
1448 For older changes see ChangeLog-2015
1449 \f
1450 Copyright (C) 2016 Free Software Foundation, Inc.
1451
1452 Copying and distribution of this file, with or without modification,
1453 are permitted in any medium without royalty provided the copyright
1454 notice and this notice are preserved.
1455
1456 Local Variables:
1457 mode: change-log
1458 left-margin: 8
1459 fill-column: 74
1460 version-control: never
1461 End: