opcodes/ChangeLog

   1 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
   4         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
   5         aarch64_field_kinds.
   6         * aarch64-opc.c (fields): Add corresponding entries.
   7         * aarch64-asm.c (aarch64_get_variant): New function.
   8         (aarch64_encode_variant_using_iclass): Likewise.
   9         (aarch64_opcode_encode): Call it.
  10         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
  11         (aarch64_opcode_decode): Call it.
  12
  13 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  14
  15         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
  16         and FP register operands.
  17         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
  18         (FLD_SVE_Vn): New aarch64_field_kinds.
  19         * aarch64-opc.c (fields): Add corresponding entries.
  20         (aarch64_print_operand): Handle the new SVE core and FP register
  21         operands.
  22         * aarch64-opc-2.c: Regenerate.
  23         * aarch64-asm-2.c: Likewise.
  24         * aarch64-dis-2.c: Likewise.
  25
  26 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  27
  28         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
  29         immediate operands.
  30         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
  31         * aarch64-opc.c (fields): Add corresponding entry.
  32         (operand_general_constraint_met_p): Handle the new SVE FP immediate
  33         operands.
  34         (aarch64_print_operand): Likewise.
  35         * aarch64-opc-2.c: Regenerate.
  36         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
  37         (ins_sve_float_zero_one): New inserters.
  38         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
  39         (aarch64_ins_sve_float_half_two): Likewise.
  40         (aarch64_ins_sve_float_zero_one): Likewise.
  41         * aarch64-asm-2.c: Regenerate.
  42         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
  43         (ext_sve_float_zero_one): New extractors.
  44         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
  45         (aarch64_ext_sve_float_half_two): Likewise.
  46         (aarch64_ext_sve_float_zero_one): Likewise.
  47         * aarch64-dis-2.c: Regenerate.
  48
  49 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  50
  51         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
  52         integer immediate operands.
  53         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
  54         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
  55         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
  56         * aarch64-opc.c (fields): Add corresponding entries.
  57         (operand_general_constraint_met_p): Handle the new SVE integer
  58         immediate operands.
  59         (aarch64_print_operand): Likewise.
  60         (aarch64_sve_dupm_mov_immediate_p): New function.
  61         * aarch64-opc-2.c: Regenerate.
  62         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
  63         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
  64         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
  65         (aarch64_ins_limm): ...here.
  66         (aarch64_ins_inv_limm): New function.
  67         (aarch64_ins_sve_aimm): Likewise.
  68         (aarch64_ins_sve_asimm): Likewise.
  69         (aarch64_ins_sve_limm_mov): Likewise.
  70         (aarch64_ins_sve_shlimm): Likewise.
  71         (aarch64_ins_sve_shrimm): Likewise.
  72         * aarch64-asm-2.c: Regenerate.
  73         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
  74         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
  75         * aarch64-dis.c (decode_limm): New function, split out from...
  76         (aarch64_ext_limm): ...here.
  77         (aarch64_ext_inv_limm): New function.
  78         (decode_sve_aimm): Likewise.
  79         (aarch64_ext_sve_aimm): Likewise.
  80         (aarch64_ext_sve_asimm): Likewise.
  81         (aarch64_ext_sve_limm_mov): Likewise.
  82         (aarch64_top_bit): Likewise.
  83         (aarch64_ext_sve_shlimm): Likewise.
  84         (aarch64_ext_sve_shrimm): Likewise.
  85         * aarch64-dis-2.c: Regenerate.
  86
  87 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  88
  89         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
  90         operands.
  91         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
  92         the AARCH64_MOD_MUL_VL entry.
  93         (value_aligned_p): Cope with non-power-of-two alignments.
  94         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
  95         (print_immediate_offset_address): Likewise.
  96         (aarch64_print_operand): Likewise.
  97         * aarch64-opc-2.c: Regenerate.
  98         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
  99         (ins_sve_addr_ri_s9xvl): New inserters.
 100         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 101         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 102         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 103         * aarch64-asm-2.c: Regenerate.
 104         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 105         (ext_sve_addr_ri_s9xvl): New extractors.
 106         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 107         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 108         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 109         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 110         * aarch64-dis-2.c: Regenerate.
 111
 112 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 113
 114         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 115         address operands.
 116         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 117         (FLD_SVE_xs_22): New aarch64_field_kinds.
 118         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 119         (get_operand_specific_data): New function.
 120         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 121         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 122         (operand_general_constraint_met_p): Handle the new SVE address
 123         operands.
 124         (sve_reg): New array.
 125         (get_addr_sve_reg_name): New function.
 126         (aarch64_print_operand): Handle the new SVE address operands.
 127         * aarch64-opc-2.c: Regenerate.
 128         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 129         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 130         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 131         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 132         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 133         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 134         (aarch64_ins_sve_addr_zi_u5): Likewise.
 135         (aarch64_ins_sve_addr_zz): Likewise.
 136         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 137         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 138         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 139         * aarch64-asm-2.c: Regenerate.
 140         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 141         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 142         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 143         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 144         (aarch64_ext_sve_addr_ri_u6): Likewise.
 145         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 146         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 147         (aarch64_ext_sve_addr_zi_u5): Likewise.
 148         (aarch64_ext_sve_addr_zz): Likewise.
 149         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 150         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 151         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 152         * aarch64-dis-2.c: Regenerate.
 153
 154 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 155
 156         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 157         AARCH64_OPND_SVE_PATTERN_SCALED.
 158         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 159         * aarch64-opc.c (fields): Add a corresponding entry.
 160         (set_multiplier_out_of_range_error): New function.
 161         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 162         (operand_general_constraint_met_p): Handle
 163         AARCH64_OPND_SVE_PATTERN_SCALED.
 164         (print_register_offset_address): Use PRIi64 to print the
 165         shift amount.
 166         (aarch64_print_operand): Likewise.  Handle
 167         AARCH64_OPND_SVE_PATTERN_SCALED.
 168         * aarch64-opc-2.c: Regenerate.
 169         * aarch64-asm.h (ins_sve_scale): New inserter.
 170         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 171         * aarch64-asm-2.c: Regenerate.
 172         * aarch64-dis.h (ext_sve_scale): New inserter.
 173         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 174         * aarch64-dis-2.c: Regenerate.
 175
 176 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 177
 178         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 179         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 180         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 181         (FLD_SVE_prfop): Likewise.
 182         * aarch64-opc.c: Include libiberty.h.
 183         (aarch64_sve_pattern_array): New variable.
 184         (aarch64_sve_prfop_array): Likewise.
 185         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 186         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 187         AARCH64_OPND_SVE_PRFOP.
 188         * aarch64-asm-2.c: Regenerate.
 189         * aarch64-dis-2.c: Likewise.
 190         * aarch64-opc-2.c: Likewise.
 191
 192 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 193
 194         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 195         AARCH64_OPND_QLF_P_[ZM].
 196         (aarch64_print_operand): Print /z and /m where appropriate.
 197
 198 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 199
 200         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 201         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 202         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 203         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 204         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 205         * aarch64-opc.c (fields): Add corresponding entries here.
 206         (operand_general_constraint_met_p): Check that SVE register lists
 207         have the correct length.  Check the ranges of SVE index registers.
 208         Check for cases where p8-p15 are used in 3-bit predicate fields.
 209         (aarch64_print_operand): Handle the new SVE operands.
 210         * aarch64-opc-2.c: Regenerate.
 211         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 212         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 213         (aarch64_ins_sve_reglist): Likewise.
 214         * aarch64-asm-2.c: Regenerate.
 215         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 216         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 217         (aarch64_ext_sve_reglist): Likewise.
 218         * aarch64-dis-2.c: Regenerate.
 219
 220 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 221
 222         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 223         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 224         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 225         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 226         tied operands.
 227
 228 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 229
 230         * aarch64-opc.c (get_offset_int_reg_name): New function.
 231         (print_immediate_offset_address): Likewise.
 232         (print_register_offset_address): Take the base and offset
 233         registers as parameters.
 234         (aarch64_print_operand): Update caller accordingly.  Use
 235         print_immediate_offset_address.
 236
 237 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 238
 239         * aarch64-opc.c (BANK): New macro.
 240         (R32, R64): Take a register number as argument
 241         (int_reg): Use BANK.
 242
 243 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 244
 245         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 246         (aarch64_print_operand): Update accordingly.
 247
 248 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 249
 250         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 251         for FPIMM.
 252         * aarch64-asm.h (ins_fpimm): New inserter.
 253         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 254         * aarch64-asm-2.c: Regenerate.
 255         * aarch64-dis.h (ext_fpimm): New extractor.
 256         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 257         (aarch64_ext_fpimm): New function.
 258         * aarch64-dis-2.c: Regenerate.
 259
 260 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 261
 262         * aarch64-asm.c: Include libiberty.h.
 263         (insert_fields): New function.
 264         (aarch64_ins_imm): Use it.
 265         * aarch64-dis.c (extract_fields): New function.
 266         (aarch64_ext_imm): Use it.
 267
 268 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 269
 270         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 271         with an esize parameter.
 272         (operand_general_constraint_met_p): Update accordingly.
 273         Fix misindented code.
 274         * aarch64-asm.c (aarch64_ins_limm): Update call to
 275         aarch64_logical_immediate_p.
 276
 277 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 278
 279         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 280
 281 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 282
 283         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 284
 285 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 286
 287         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 288
 289 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 290
 291         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 292         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 293         xor3>: Delete mnemonics.
 294         <cp_abort>: Rename mnemonic from ...
 295         <cpabort>: ...to this.
 296         <setb>: Change to a X form instruction.
 297         <sync>: Change to 1 operand form.
 298         <copy>: Delete mnemonic.
 299         <copy_first>: Rename mnemonic from ...
 300         <copy>: ...to this.
 301         <paste, paste.>: Delete mnemonics.
 302         <paste_last>: Rename mnemonic from ...
 303         <paste.>: ...to this.
 304
 305 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 306
 307         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 308
 309 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 310
 311         * s390-mkopc.c (main): Support alternate arch strings.
 312
 313 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 314
 315         * s390-opc.txt: Fix kmctr instruction type.
 316
 317 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 320         * i386-init.h: Regenerated.
 321
 322 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 323
 324         * opcodes/arc-dis.c (print_insn_arc): Changed.
 325
 326 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 327
 328         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 329         camellia_fl.
 330
 331 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 332
 333         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 334         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 335         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 336
 337 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 338
 339         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 340         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 341         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 342         PREFIX_MOD_3_0FAE_REG_4.
 343         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 344         PREFIX_MOD_3_0FAE_REG_4.
 345         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 346         (cpu_flags): Add CpuPTWRITE.
 347         * i386-opc.h (CpuPTWRITE): New.
 348         (i386_cpu_flags): Add cpuptwrite.
 349         * i386-opc.tbl: Add ptwrite instruction.
 350         * i386-init.h: Regenerated.
 351         * i386-tbl.h: Likewise.
 352
 353 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 354
 355         * arc-dis.h: Wrap around in extern "C".
 356
 357 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 358
 359         * aarch64-tbl.h (V8_2_INSN): New macro.
 360         (aarch64_opcode_table): Use it.
 361
 362 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 363
 364         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 365         CORE_INSN, __FP_INSN and SIMD_INSN.
 366
 367 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 368
 369         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 370         (aarch64_opcode_table): Update uses accordingly.
 371
 372 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 373         Kwok Cheung Yeung  <kcy@codesourcery.com>
 374
 375         opcodes/
 376         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 377         'e_cmplwi' to 'e_cmpli' instead.
 378         (OPVUPRT, OPVUPRT_MASK): Define.
 379         (powerpc_opcodes): Add E200Z4 insns.
 380         (vle_opcodes): Add context save/restore insns.
 381
 382 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 383
 384         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 385         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 386         "j".
 387
 388 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 389
 390         * arc-nps400-tbl.h: Change block comments to GNU format.
 391         * arc-dis.c: Add new globals addrtypenames,
 392         addrtypenames_max, and addtypeunknown.
 393         (get_addrtype): New function.
 394         (print_insn_arc): Print colons and address types when
 395         required.
 396         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 397         define insert and extract functions for all address types.
 398         (arc_operands): Add operands for colon and all address
 399         types.
 400         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 401         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 402         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 403         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 404         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 405         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 406
 407 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 408
 409         * configure: Regenerated.
 410
 411 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 412
 413         * arc-dis.c (skipclass): New structure.
 414         (decodelist): New variable.
 415         (is_compatible_p): New function.
 416         (new_element): Likewise.
 417         (skip_class_p): Likewise.
 418         (find_format_from_table): Use skip_class_p function.
 419         (find_format): Decode first the extension instructions.
 420         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 421         e_flags.
 422         (parse_option): New function.
 423         (parse_disassembler_options): Likewise.
 424         (print_arc_disassembler_options): Likewise.
 425         (print_insn_arc): Use parse_disassembler_options function.  Proper
 426         select ARCv2 cpu variant.
 427         * disassemble.c (disassembler_usage): Add ARC disassembler
 428         options.
 429
 430 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 431
 432         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 433         annotation from the "nal" entry and reorder it beyond "bltzal".
 434
 435 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 436
 437         * sparc-opc.c (ldtxa): New macro.
 438         (sparc_opcodes): Use the macro defined above to add entries for
 439         the LDTXA instructions.
 440         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 441         instruction.
 442
 443 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 444
 445         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 446         and "jmpc".
 447
 448 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 449
 450         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 451         (movzb): Adjust to cover all permitted suffixes.
 452         (movzw): New.
 453         * i386-tbl.h: Re-generate.
 454
 455 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 456
 457         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 458         (lgdt): Remove Tbyte from non-64-bit variant.
 459         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 460         xsaves64, xsavec64): Remove Disp16.
 461         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 462         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 463         64-bit variants.
 464         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 465         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 466         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 467         64-bit variants.
 468         * i386-tbl.h: Re-generate.
 469
 470 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 473         * i386-tbl.h: Re-generate.
 474
 475 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 476
 477         * arm-dis.c (print_insn): Fix typo in comment.
 478
 479 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 480
 481         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 482         range of ldst_elemlist operands.
 483         (print_register_list): Use PRIi64 to print the index.
 484         (aarch64_print_operand): Likewise.
 485
 486 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 487
 488         * mcore-opc.h: Remove sentinal.
 489         * mcore-dis.c (print_insn_mcore): Adjust.
 490
 491 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 492
 493         * arc-opc.c: Correct description of availability of NPS400
 494         features.
 495
 496 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 497
 498         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 499         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 500         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 501         xor3>: New mnemonics.
 502         <setb>: Change to a VX form instruction.
 503         (insert_sh6): Add support for rldixor.
 504         (extract_sh6): Likewise.
 505
 506 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 507
 508         * arc-ext.h: Wrap in extern C.
 509
 510 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 511
 512         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 513         Use same method for determining instruction length on ARC700 and
 514         NPS-400.
 515         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 516         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 517         with the NPS400 subclass.
 518         * arc-opc.c: Likewise.
 519
 520 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 521
 522         * sparc-opc.c (rdasr): New macro.
 523         (wrasr): Likewise.
 524         (rdpr): Likewise.
 525         (wrpr): Likewise.
 526         (rdhpr): Likewise.
 527         (wrhpr): Likewise.
 528         (sparc_opcodes): Use the macros above to fix and expand the
 529         definition of read/write instructions from/to
 530         asr/privileged/hyperprivileged instructions.
 531         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 532         %hva_mask_nz.  Prefer softint_set and softint_clear over
 533         set_softint and clear_softint.
 534         (print_insn_sparc): Support %ver in Rd.
 535
 536 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 537
 538         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 539         architecture according to the hardware capabilities they require.
 540
 541 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 542
 543         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 544         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 545         bfd_mach_sparc_v9{c,d,e,v,m}.
 546         * sparc-opc.c (MASK_V9C): Define.
 547         (MASK_V9D): Likewise.
 548         (MASK_V9E): Likewise.
 549         (MASK_V9V): Likewise.
 550         (MASK_V9M): Likewise.
 551         (v6): Add MASK_V9{C,D,E,V,M}.
 552         (v6notlet): Likewise.
 553         (v7): Likewise.
 554         (v8): Likewise.
 555         (v9): Likewise.
 556         (v9andleon): Likewise.
 557         (v9a): Likewise.
 558         (v9b): Likewise.
 559         (v9c): Define.
 560         (v9d): Likewise.
 561         (v9e): Likewise.
 562         (v9v): Likewise.
 563         (v9m): Likewise.
 564         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 565
 566 2016-06-15  Nick Clifton  <nickc@redhat.com>
 567
 568         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 569         constants to match expected behaviour.
 570         (nds32_parse_opcode): Likewise.  Also for whitespace.
 571
 572 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 573
 574         * arc-opc.c (extract_rhv1): Extract value from insn.
 575
 576 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 577
 578         * arc-nps400-tbl.h: Add ldbit instruction.
 579         * arc-opc.c: Add flag classes required for ldbit.
 580
 581 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 582
 583         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 584         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 585         support the above instructions.
 586
 587 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 588
 589         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 590         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 591         csma, cbba, zncv, and hofs.
 592         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 593         support the above instructions.
 594
 595 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 596
 597         * arc-nps400-tbl.h: Add andab and orab instructions.
 598
 599 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 600
 601         * arc-nps400-tbl.h: Add addl-like instructions.
 602
 603 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 604
 605         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 606
 607 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 608
 609         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 610         instructions.
 611
 612 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 613
 614         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 615         variable.
 616         (init_disasm): Handle new command line option "insnlength".
 617         (print_s390_disassembler_options): Mention new option in help
 618         output.
 619         (print_insn_s390): Use the encoded insn length when dumping
 620         unknown instructions.
 621
 622 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 623
 624         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 625          to the address and set as symbol address for LDS/ STS immediate operands.
 626
 627 2016-06-07  Alan Modra  <amodra@gmail.com>
 628
 629         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 630         cpu for "vle" to e500.
 631         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 632         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 633         (PPCNONE): Delete, substitute throughout.
 634         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 635         except for major opcode 4 and 31.
 636         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 637
 638 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 639
 640         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 641         ARM_EXT_RAS in relevant entries.
 642
 643 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 644
 645         PR binutils/20196
 646         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 647         opcodes for E6500.
 648
 649 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 650
 651         PR binutis/18386
 652         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 653         (indir_v_mode): New.
 654         Add comments for '&'.
 655         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 656         (putop): Handle '&'.
 657         (intel_operand_size): Handle indir_v_mode.
 658         (OP_E_register): Likewise.
 659         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 660         64-bit indirect call/jmp for AMD64.
 661         * i386-tbl.h: Regenerated
 662
 663 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 664
 665         * arc-dis.c (struct arc_operand_iterator): New structure.
 666         (find_format_from_table): All the old content from find_format,
 667         with some minor adjustments, and parameter renaming.
 668         (find_format_long_instructions): New function.
 669         (find_format): Rewritten.
 670         (arc_insn_length): Add LSB parameter.
 671         (extract_operand_value): New function.
 672         (operand_iterator_next): New function.
 673         (print_insn_arc): Use new functions to find opcode, and iterator
 674         over operands.
 675         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 676         (extract_nps_3bit_dst_short): New function.
 677         (insert_nps_3bit_src2_short): New function.
 678         (extract_nps_3bit_src2_short): New function.
 679         (insert_nps_bitop1_size): New function.
 680         (extract_nps_bitop1_size): New function.
 681         (insert_nps_bitop2_size): New function.
 682         (extract_nps_bitop2_size): New function.
 683         (insert_nps_bitop_mod4_msb): New function.
 684         (extract_nps_bitop_mod4_msb): New function.
 685         (insert_nps_bitop_mod4_lsb): New function.
 686         (extract_nps_bitop_mod4_lsb): New function.
 687         (insert_nps_bitop_dst_pos3_pos4): New function.
 688         (extract_nps_bitop_dst_pos3_pos4): New function.
 689         (insert_nps_bitop_ins_ext): New function.
 690         (extract_nps_bitop_ins_ext): New function.
 691         (arc_operands): Add new operands.
 692         (arc_long_opcodes): New global array.
 693         (arc_num_long_opcodes): New global.
 694         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 695
 696 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 697
 698         * nds32-asm.h: Add extern "C".
 699         * sh-opc.h: Likewise.
 700
 701 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 702
 703         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 704         0,b,limm to the rflt instruction.
 705
 706 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 707
 708         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 709         constant.
 710
 711 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 712
 713         PR gas/20145
 714         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 715         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 716         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 717         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 718         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 719         * i386-init.h: Regenerated.
 720
 721 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 722
 723         PR gas/20145
 724         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 725         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 726         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 727         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 728         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 729         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 730         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 731         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 732         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 733         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 734         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 735         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 736         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 737         CpuRegMask for AVX512.
 738         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 739         and CpuRegMask.
 740         (set_bitfield_from_cpu_flag_init): New function.
 741         (set_bitfield): Remove const on f.  Call
 742         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 743         * i386-opc.h (CpuRegMMX): New.
 744         (CpuRegXMM): Likewise.
 745         (CpuRegYMM): Likewise.
 746         (CpuRegZMM): Likewise.
 747         (CpuRegMask): Likewise.
 748         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 749         and cpuregmask.
 750         * i386-init.h: Regenerated.
 751         * i386-tbl.h: Likewise.
 752
 753 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 754
 755         PR gas/20154
 756         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 757         (opcode_modifiers): Add AMD64 and Intel64.
 758         (main): Properly verify CpuMax.
 759         * i386-opc.h (CpuAMD64): Removed.
 760         (CpuIntel64): Likewise.
 761         (CpuMax): Set to CpuNo64.
 762         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 763         (AMD64): New.
 764         (Intel64): Likewise.
 765         (i386_opcode_modifier): Add amd64 and intel64.
 766         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 767         on call and jmp.
 768         * i386-init.h: Regenerated.
 769         * i386-tbl.h: Likewise.
 770
 771 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 772
 773         PR gas/20154
 774         * i386-gen.c (main): Fail if CpuMax is incorrect.
 775         * i386-opc.h (CpuMax): Set to CpuIntel64.
 776         * i386-tbl.h: Regenerated.
 777
 778 2016-05-27  Nick Clifton  <nickc@redhat.com>
 779
 780         PR target/20150
 781         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 782         (msp430dis_opcode_unsigned): New function.
 783         (msp430dis_opcode_signed): New function.
 784         (msp430_singleoperand): Use the new opcode reading functions.
 785         Only disassenmble bytes if they were successfully read.
 786         (msp430_doubleoperand): Likewise.
 787         (msp430_branchinstr): Likewise.
 788         (msp430x_callx_instr): Likewise.
 789         (print_insn_msp430): Check that it is safe to read bytes before
 790         attempting disassembly.  Use the new opcode reading functions.
 791
 792 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 793
 794         * ppc-opc.c (CY): New define.  Document it.
 795         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 796
 797 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 798
 799         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 800         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 801         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 802         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 803         CPU_ANY_AVX_FLAGS.
 804         * i386-init.h: Regenerated.
 805
 806 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 807
 808         PR gas/20141
 809         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 810         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 811         * i386-init.h: Regenerated.
 812
 813 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 814
 815         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 816         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 817         * i386-init.h: Regenerated.
 818
 819 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 820
 821         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 822         information.
 823         (print_insn_arc): Set insn_type information.
 824         * arc-opc.c (C_CC): Add F_CLASS_COND.
 825         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 826         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 827         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 828         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 829         (brne, brne_s, jeq_s, jne_s): Likewise.
 830
 831 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 832
 833         * arc-tbl.h (neg): New instruction variant.
 834
 835 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 836
 837         * arc-dis.c (find_format, find_format, get_auxreg)
 838         (print_insn_arc): Changed.
 839         * arc-ext.h (INSERT_XOP): Likewise.
 840
 841 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 842
 843         * tic54x-dis.c (sprint_mmr): Adjust.
 844         * tic54x-opc.c: Likewise.
 845
 846 2016-05-19  Alan Modra  <amodra@gmail.com>
 847
 848         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 849
 850 2016-05-19  Alan Modra  <amodra@gmail.com>
 851
 852         * ppc-opc.c: Formatting.
 853         (NSISIGNOPT): Define.
 854         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 855
 856 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 857
 858         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 859         replacing references to `micromips_ase' throughout.
 860         (_print_insn_mips): Don't use file-level microMIPS annotation to
 861         determine the disassembly mode with the symbol table.
 862
 863 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 864
 865         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 866
 867 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 868
 869         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 870         mips64r6.
 871         * mips-opc.c (D34): New macro.
 872         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 873
 874 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 875
 876         * i386-dis.c (prefix_table): Add RDPID instruction.
 877         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 878         (cpu_flags): Add RDPID bitfield.
 879         * i386-opc.h (enum): Add RDPID element.
 880         (i386_cpu_flags): Add RDPID field.
 881         * i386-opc.tbl: Add RDPID instruction.
 882         * i386-init.h: Regenerate.
 883         * i386-tbl.h: Regenerate.
 884
 885 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 886
 887         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 888         branch type of a symbol.
 889         (print_insn): Likewise.
 890
 891 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 892
 893         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 894         Mainline Security Extensions instructions.
 895         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 896         Extensions instructions.
 897         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 898         instructions.
 899         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 900         special registers.
 901
 902 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 903
 904         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 905
 906 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 907
 908         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 909         (arcExtMap_genOpcode): Likewise.
 910         * arc-opc.c (arg_32bit_rc): Define new variable.
 911         (arg_32bit_u6): Likewise.
 912         (arg_32bit_limm): Likewise.
 913
 914 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 915
 916         * aarch64-gen.c (VERIFIER): Define.
 917         * aarch64-opc.c (VERIFIER): Define.
 918         (verify_ldpsw): Use static linkage.
 919         * aarch64-opc.h (verify_ldpsw): Remove.
 920         * aarch64-tbl.h: Use VERIFIER for verifiers.
 921
 922 2016-04-28  Nick Clifton  <nickc@redhat.com>
 923
 924         PR target/19722
 925         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 926         * aarch64-opc.c (verify_ldpsw): New function.
 927         * aarch64-opc.h (verify_ldpsw): New prototype.
 928         * aarch64-tbl.h: Add initialiser for verifier field.
 929         (LDPSW): Set verifier to verify_ldpsw.
 930
 931 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 932
 933         PR binutils/19983
 934         PR binutils/19984
 935         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 936         smaller than address size.
 937
 938 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 939
 940         * alpha-dis.c: Regenerate.
 941         * crx-dis.c: Likewise.
 942         * disassemble.c: Likewise.
 943         * epiphany-opc.c: Likewise.
 944         * fr30-opc.c: Likewise.
 945         * frv-opc.c: Likewise.
 946         * ip2k-opc.c: Likewise.
 947         * iq2000-opc.c: Likewise.
 948         * lm32-opc.c: Likewise.
 949         * lm32-opinst.c: Likewise.
 950         * m32c-opc.c: Likewise.
 951         * m32r-opc.c: Likewise.
 952         * m32r-opinst.c: Likewise.
 953         * mep-opc.c: Likewise.
 954         * mt-opc.c: Likewise.
 955         * or1k-opc.c: Likewise.
 956         * or1k-opinst.c: Likewise.
 957         * tic80-opc.c: Likewise.
 958         * xc16x-opc.c: Likewise.
 959         * xstormy16-opc.c: Likewise.
 960
 961 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 962
 963         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 964         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 965         calcsd, and calcxd instructions.
 966         * arc-opc.c (insert_nps_bitop_size): Delete.
 967         (extract_nps_bitop_size): Delete.
 968         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 969         (extract_nps_qcmp_m3): Define.
 970         (extract_nps_qcmp_m2): Define.
 971         (extract_nps_qcmp_m1): Define.
 972         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 973         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 974         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 975         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 976         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 977         NPS_QCMP_M3.
 978
 979 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 980
 981         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 982
 983 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 984
 985         * Makefile.in: Regenerated with automake 1.11.6.
 986         * aclocal.m4: Likewise.
 987
 988 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 989
 990         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 991         instructions.
 992         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 993         (extract_nps_cmem_uimm16): New function.
 994         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 995
 996 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 997
 998         * arc-dis.c (arc_insn_length): New function.
 999         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1000         (find_format): Change insnLen parameter to unsigned.
1001
1002 2016-04-13  Nick Clifton  <nickc@redhat.com>
1003
1004         PR target/19937
1005         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1006         the LD.B and LD.BU instructions.
1007
1008 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1009
1010         * arc-dis.c (find_format): Check for extension flags.
1011         (print_flags): New function.
1012         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1013         .extAuxRegister.
1014         * arc-ext.c (arcExtMap_coreRegName): Use
1015         LAST_EXTENSION_CORE_REGISTER.
1016         (arcExtMap_coreReadWrite): Likewise.
1017         (dump_ARC_extmap): Update printing.
1018         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1019         (arc_aux_regs): Add cpu field.
1020         * arc-regs.h: Add cpu field, lower case name aux registers.
1021
1022 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1023
1024         * arc-tbl.h: Add rtsc, sleep with no arguments.
1025
1026 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1027
1028         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1029         Initialize.
1030         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1031         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1032         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1033         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1034         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1035         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1036         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1037         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1038         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1039         (arc_opcode arc_opcodes): Null terminate the array.
1040         (arc_num_opcodes): Remove.
1041         * arc-ext.h (INSERT_XOP): Define.
1042         (extInstruction_t): Likewise.
1043         (arcExtMap_instName): Delete.
1044         (arcExtMap_insn): New function.
1045         (arcExtMap_genOpcode): Likewise.
1046         * arc-ext.c (ExtInstruction): Remove.
1047         (create_map): Zero initialize instruction fields.
1048         (arcExtMap_instName): Remove.
1049         (arcExtMap_insn): New function.
1050         (dump_ARC_extmap): More info while debuging.
1051         (arcExtMap_genOpcode): New function.
1052         * arc-dis.c (find_format): New function.
1053         (print_insn_arc): Use find_format.
1054         (arc_get_disassembler): Enable dump_ARC_extmap only when
1055         debugging.
1056
1057 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1058
1059         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1060         instruction bits out.
1061
1062 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1063
1064         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1065         * arc-opc.c (arc_flag_operands): Add new flags.
1066         (arc_flag_classes): Add new classes.
1067
1068 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1069
1070         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1071
1072 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1073
1074         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1075         encode1, rflt, crc16, and crc32 instructions.
1076         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1077         (arc_flag_classes): Add C_NPS_R.
1078         (insert_nps_bitop_size_2b): New function.
1079         (extract_nps_bitop_size_2b): Likewise.
1080         (insert_nps_bitop_uimm8): Likewise.
1081         (extract_nps_bitop_uimm8): Likewise.
1082         (arc_operands): Add new operand entries.
1083
1084 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1085
1086         * arc-regs.h: Add a new subclass field.  Add double assist
1087         accumulator register values.
1088         * arc-tbl.h: Use DPA subclass to mark the double assist
1089         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1090         * arc-opc.c (RSP): Define instead of SP.
1091         (arc_aux_regs): Add the subclass field.
1092
1093 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1094
1095         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1096
1097 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1098
1099         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1100         NPS_R_SRC1.
1101
1102 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1103
1104         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1105         issues.  No functional changes.
1106
1107 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1108
1109         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1110         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1111         (RTT): Remove duplicate.
1112         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1113         (PCT_CONFIG*): Remove.
1114         (D1L, D1H, D2H, D2L): Define.
1115
1116 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1117
1118         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1119
1120 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1121
1122         * arc-tbl.h (invld07): Remove.
1123         * arc-ext-tbl.h: New file.
1124         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1125         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1126
1127 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1128
1129         Fix -Wstack-usage warnings.
1130         * aarch64-dis.c (print_operands): Substitute size.
1131         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1132
1133 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1134
1135         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1136         to get a proper diagnostic when an invalid ASR register is used.
1137
1138 2016-03-22  Nick Clifton  <nickc@redhat.com>
1139
1140         * configure: Regenerate.
1141
1142 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1143
1144         * arc-nps400-tbl.h: New file.
1145         * arc-opc.c: Add top level comment.
1146         (insert_nps_3bit_dst): New function.
1147         (extract_nps_3bit_dst): New function.
1148         (insert_nps_3bit_src2): New function.
1149         (extract_nps_3bit_src2): New function.
1150         (insert_nps_bitop_size): New function.
1151         (extract_nps_bitop_size): New function.
1152         (arc_flag_operands): Add nps400 entries.
1153         (arc_flag_classes): Add nps400 entries.
1154         (arc_operands): Add nps400 entries.
1155         (arc_opcodes): Add nps400 include.
1156
1157 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1158
1159         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1160         the new class enum values.
1161
1162 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1163
1164         * arc-dis.c (print_insn_arc): Handle nps400.
1165
1166 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1167
1168         * arc-opc.c (BASE): Delete.
1169
1170 2016-03-18  Nick Clifton  <nickc@redhat.com>
1171
1172         PR target/19721
1173         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1174         of MOV insn that aliases an ORR insn.
1175
1176 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1177
1178         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1179
1180 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1181
1182         * mcore-opc.h: Add const qualifiers.
1183         * microblaze-opc.h (struct op_code_struct): Likewise.
1184         * sh-opc.h: Likewise.
1185         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1186         (tic4x_print_op): Likewise.
1187
1188 2016-03-02  Alan Modra  <amodra@gmail.com>
1189
1190         * or1k-desc.h: Regenerate.
1191         * fr30-ibld.c: Regenerate.
1192         * rl78-decode.c: Regenerate.
1193
1194 2016-03-01  Nick Clifton  <nickc@redhat.com>
1195
1196         PR target/19747
1197         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1198
1199 2016-02-24  Renlin Li  <renlin.li@arm.com>
1200
1201         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1202         (print_insn_coprocessor): Support fp16 instructions.
1203
1204 2016-02-24  Renlin Li  <renlin.li@arm.com>
1205
1206         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1207         vminnm, vrint(mpna).
1208
1209 2016-02-24  Renlin Li  <renlin.li@arm.com>
1210
1211         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1212         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1213
1214 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1215
1216         * i386-dis.c (print_insn): Parenthesize expression to prevent
1217         truncated addresses.
1218         (OP_J): Likewise.
1219
1220 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1221             Janek van Oirschot  <jvanoirs@synopsys.com>
1222
1223         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1224         variable.
1225
1226 2016-02-04  Nick Clifton  <nickc@redhat.com>
1227
1228         PR target/19561
1229         * msp430-dis.c (print_insn_msp430): Add a special case for
1230         decoding an RRC instruction with the ZC bit set in the extension
1231         word.
1232
1233 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1234
1235         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1236         * epiphany-ibld.c: Regenerate.
1237         * fr30-ibld.c: Regenerate.
1238         * frv-ibld.c: Regenerate.
1239         * ip2k-ibld.c: Regenerate.
1240         * iq2000-ibld.c: Regenerate.
1241         * lm32-ibld.c: Regenerate.
1242         * m32c-ibld.c: Regenerate.
1243         * m32r-ibld.c: Regenerate.
1244         * mep-ibld.c: Regenerate.
1245         * mt-ibld.c: Regenerate.
1246         * or1k-ibld.c: Regenerate.
1247         * xc16x-ibld.c: Regenerate.
1248         * xstormy16-ibld.c: Regenerate.
1249
1250 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1251
1252         * epiphany-dis.c: Regenerated from latest cpu files.
1253
1254 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1255
1256         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1257         test bit.
1258
1259 2016-01-25  Renlin Li  <renlin.li@arm.com>
1260
1261         * arm-dis.c (mapping_symbol_for_insn): New function.
1262         (find_ifthen_state): Call mapping_symbol_for_insn().
1263
1264 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1265
1266         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1267         of MSR UAO immediate operand.
1268
1269 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1270
1271         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1272         instruction support.
1273
1274 2016-01-17  Alan Modra  <amodra@gmail.com>
1275
1276         * configure: Regenerate.
1277
1278 2016-01-14  Nick Clifton  <nickc@redhat.com>
1279
1280         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1281         instructions that can support stack pointer operations.
1282         * rl78-decode.c: Regenerate.
1283         * rl78-dis.c: Fix display of stack pointer in MOVW based
1284         instructions.
1285
1286 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1287
1288         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1289         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1290         erxtatus_el1 and erxaddr_el1.
1291
1292 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1293
1294         * arm-dis.c (arm_opcodes): Add "esb".
1295         (thumb_opcodes): Likewise.
1296
1297 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1298
1299         * ppc-opc.c <xscmpnedp>: Delete.
1300         <xvcmpnedp>: Likewise.
1301         <xvcmpnedp.>: Likewise.
1302         <xvcmpnesp>: Likewise.
1303         <xvcmpnesp.>: Likewise.
1304
1305 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1306
1307         PR gas/13050
1308         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1309         addition to ISA_A.
1310
1311 2016-01-01  Alan Modra  <amodra@gmail.com>
1312
1313         Update year range in copyright notice of all files.
1314
1315 For older changes see ChangeLog-2015
1316 \f
1317 Copyright (C) 2016 Free Software Foundation, Inc.
1318
1319 Copying and distribution of this file, with or without modification,
1320 are permitted in any medium without royalty provided the copyright
1321 notice and this notice are preserved.
1322
1323 Local Variables:
1324 mode: change-log
1325 left-margin: 8
1326 fill-column: 74
1327 version-control: never
1328 End: