opcodes/ChangeLog

   1 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
   4         ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
   5         (print_insn_mips16): Check opcode entries for validity against
   6         the ISA level and ASE set selected.
   7
   8 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
   9
  10         * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
  11         `insn' together, with `extend' as the high-order 16 bits.
  12         (match_kind): New enum.
  13         (print_insn_mips16): Rework for 32-bit instruction matching.
  14         Do not dump EXTEND prefixes here.
  15         * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
  16         Recode `match' and `mask' fields as 32-bit in absolute "jal" and
  17         "jalx" entries.
  18
  19 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  20
  21         * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
  22         than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
  23         INSN_MACRO entries.
  24
  25 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  26
  27         * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
  28         than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
  29         opcode).
  30
  31 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  32
  33         * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
  34         "*.aqrl".
  35
  36 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  37
  38         * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
  39         INSN_ALIAS.
  40
  41 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  42
  43         * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
  44         format.
  45
  46 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  47
  48         * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
  49         XLEN when none is provided.
  50
  51 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  52
  53         * riscv-opc.c: Formatting fixes.
  54
  55 2016-12-20  Alan Modra  <amodra@gmail.com>
  56
  57         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
  58         * Makefile.in: Regenerate.
  59         * po/POTFILES.in: Regenerate.
  60
  61 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
  62
  63         * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
  64         Only examine ELF file structures here.
  65
  66 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
  67
  68         * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
  69         `bfd_mips_elf_get_abiflags' here.
  70
  71 2016-12-16  Nick Clifton  <nickc@redhat.com>
  72
  73         * arm-dis.c (print_insn_thumb32): Fix compile time warning
  74         computing value_in_comment.
  75
  76 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  77
  78         * mips-dis.c (mips_convert_abiflags_ases): New function.
  79         (set_default_mips_dis_options): Also infer ASE flags from ELF
  80         file structures.
  81
  82 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  83
  84         * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
  85         header flag interpretation code.
  86
  87 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  88
  89         * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
  90         `pinfo2' with SP-relative "sd" entries.
  91
  92 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  93
  94         * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
  95         compact jumps.
  96
  97 2016-12-13 Renlin Li <renlin.li@arm.com>
  98
  99         * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
 100         qualifier.
 101         (operand_general_constraint_met_p): Remove case for CP_REG.
 102         (aarch64_print_operand): Print CRn, CRm operand using imm field.
 103         * aarch64-tbl.h (QL_SYS): Use CR qualifier.
 104         (QL_SYSL): Likewise.
 105         (aarch64_opcode_table): Change CRn, CRm operand class and type.
 106         * aarch64-opc-2.c : Regenerate.
 107         * aarch64-asm-2.c : Likewise.
 108         * aarch64-dis-2.c : Likewise.
 109
 110 2016-12-12  Yao Qi  <yao.qi@linaro.org>
 111
 112         * rx-dis.c: Include <setjmp.h>
 113         (struct private): New.
 114         (rx_get_byte): Check return value of read_memory_func, and
 115         call memory_error_func and OPCODES_SIGLONGJMP on error.
 116         (print_insn_rx): Call OPCODES_SIGSETJMP.
 117
 118 2016-12-12  Yao Qi  <yao.qi@linaro.org>
 119
 120         * rl78-dis.c: Include <setjmp.h>.
 121         (struct private): New.
 122         (rl78_get_byte): Check return value of read_memory_func, and
 123         call memory_error_func and OPCODES_SIGLONGJMP on error.
 124         (print_insn_rl78_common): Call OPCODES_SIGJMP.
 125
 126 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 127
 128         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
 129
 130 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 131
 132         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
 133         than UINT.
 134
 135 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 136
 137         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
 138         to separate `extend' and its uninterpreted argument output.
 139         Separate hexadecimal halves of undecoded extended instructions
 140         output.
 141
 142 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 143
 144         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
 145         indentation space across.
 146
 147 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 148
 149         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
 150         adjustment for PC-relative operations following MIPS16e compact
 151         jumps or undefined RR/J(AL)R(C) encodings.
 152
 153 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 154
 155         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
 156         variable to `reglane_index'.
 157
 158 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
 159
 160         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
 161
 162 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 163
 164         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
 165
 166 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 167
 168         * mips16-opc.c (mips16_opcodes): Update comment naming structure
 169         members.
 170
 171 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 172
 173         * mips-dis.c (print_mips_disassembler_options): Reformat output.
 174
 175 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 176
 177         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
 178         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
 179
 180 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 181
 182         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
 183
 184 2016-12-01  Nick Clifton  <nickc@redhat.com>
 185
 186         PR binutils/20893
 187         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
 188         opcode designator.
 189
 190 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 191
 192         * arc-opc.c (insert_ra_chk): New function.
 193         (insert_rb_chk): Likewise.
 194         (insert_rad): Update text error message.
 195         (insert_rcd): Likewise.
 196         (insert_rhv2): Likewise.
 197         (insert_r0): Likewise.
 198         (insert_r1): Likewise.
 199         (insert_r2): Likewise.
 200         (insert_r3): Likewise.
 201         (insert_sp): Likewise.
 202         (insert_gp): Likewise.
 203         (insert_pcl): Likewise.
 204         (insert_blink): Likewise.
 205         (insert_ilink1): Likewise.
 206         (insert_ilink2): Likewise.
 207         (insert_ras): Likewise.
 208         (insert_rbs): Likewise.
 209         (insert_rcs): Likewise.
 210         (insert_simm3s): Likewise.
 211         (insert_rrange): Likewise.
 212         (insert_fpel): Likewise.
 213         (insert_blinkel): Likewise.
 214         (insert_pcel): Likewise.
 215         (insert_nps_3bit_dst): Likewise.
 216         (insert_nps_3bit_dst_short): Likewise.
 217         (insert_nps_3bit_src2_short): Likewise.
 218         (insert_nps_bitop_size_2b): Likewise.
 219         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 220         (RA_CHK): Define.
 221         (RB): Adjust.
 222         (RB_CHK): Define.
 223         (RC): Adjust.
 224         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 225         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 226         Change first insn argument to check for LP_COUNT usage.
 227         (rem): Likewise.
 228         (ld, ldd): All instructions are LOAD class.  Change first insn
 229         argument to check for LP_COUNT usage.
 230         (st, std): All instructions are STORE class.
 231         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 232         Change first insn argument to check for LP_COUNT usage.
 233         (mov): All instructions are MOVE class.  Change first insn
 234         argument to check for LP_COUNT usage.
 235
 236 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 237
 238         * arc-dis.c (is_compatible_p): Remove function.
 239         (skip_this_opcode): Don't add any decoding class to decode list.
 240         Remove warning.
 241         (find_format_from_table): Go through all opcodes, and warn if we
 242         use a guessed mnemonic.
 243
 244 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 245             Amit Pawar  <amit.pawar@amd.com>
 246
 247         PR binutils/20637
 248         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 249         instructions.
 250
 251 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 252
 253         * configure: Regenerate.
 254
 255 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 256
 257         * sparc-opc.c (HWS_V8): Definition moved from
 258         gas/config/tc-sparc.c.
 259         (HWS_V9): Likewise.
 260         (HWS_VA): Likewise.
 261         (HWS_VB): Likewise.
 262         (HWS_VC): Likewise.
 263         (HWS_VD): Likewise.
 264         (HWS_VE): Likewise.
 265         (HWS_VV): Likewise.
 266         (HWS_VM): Likewise.
 267         (HWS2_VM): Likewise.
 268         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 269         existing entries.
 270
 271 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 272
 273         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 274         instructions.
 275
 276 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 277
 278         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 279         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 280         (aarch64_opcode_table): Add fcmla and fcadd.
 281         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 282         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 283         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 284         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 285         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 286         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 287         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 288         (operand_general_constraint_met_p): Rotate and index range check.
 289         (aarch64_print_operand): Handle rotate operand.
 290         * aarch64-asm-2.c: Regenerate.
 291         * aarch64-dis-2.c: Likewise.
 292         * aarch64-opc-2.c: Likewise.
 293
 294 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 295
 296         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 297         * aarch64-asm-2.c: Regenerate.
 298         * aarch64-dis-2.c: Regenerate.
 299         * aarch64-opc-2.c: Regenerate.
 300
 301 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 302
 303         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 304         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 305         * aarch64-asm-2.c: Regenerate.
 306         * aarch64-dis-2.c: Regenerate.
 307         * aarch64-opc-2.c: Regenerate.
 308
 309 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 310
 311         * aarch64-tbl.h (QL_X1NIL): New.
 312         (arch64_opcode_table): Add ldraa, ldrab.
 313         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 314         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 315         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 316         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 317         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 318         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 319         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 320         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 321         (aarch64_print_operand): Likewise.
 322         * aarch64-asm-2.c: Regenerate.
 323         * aarch64-dis-2.c: Regenerate.
 324         * aarch64-opc-2.c: Regenerate.
 325
 326 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 327
 328         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 329         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 330         * aarch64-asm-2.c: Regenerate.
 331         * aarch64-dis-2.c: Regenerate.
 332         * aarch64-opc-2.c: Regenerate.
 333
 334 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 335
 336         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 337         (AARCH64_OPERANDS): Add Rm_SP.
 338         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 339         * aarch64-asm-2.c: Regenerate.
 340         * aarch64-dis-2.c: Regenerate.
 341         * aarch64-opc-2.c: Regenerate.
 342
 343 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 344
 345         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 346         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 347         autdzb, xpaci, xpacd.
 348         * aarch64-asm-2.c: Regenerate.
 349         * aarch64-dis-2.c: Regenerate.
 350         * aarch64-opc-2.c: Regenerate.
 351
 352 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 353
 354         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 355         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 356         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 357         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 358
 359 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 360
 361         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 362         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 363         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 364         autibsp.
 365         * aarch64-asm-2.c: Regenerate.
 366         * aarch64-dis-2.c: Regenerate.
 367
 368 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 369
 370         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 371
 372 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 373
 374         PR binutils/20799
 375         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 376         * i386-dis.c (EdqwS): Removed.
 377         (dqw_swap_mode): Likewise.
 378         (intel_operand_size): Don't check dqw_swap_mode.
 379         (OP_E_register): Likewise.
 380         (OP_E_memory): Likewise.
 381         (OP_G): Likewise.
 382         (OP_EX): Likewise.
 383         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 384         * i386-tbl.h: Regerated.
 385
 386 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 387
 388         * i386-opc.tbl: Merge AVX512F vmovq.
 389         * i386-tbl.h: Regerated.
 390
 391 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 392
 393         PR binutils/20701
 394         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 395         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 396         (three_byte_table): Remove THREE_BYTE_0F7A.
 397
 398 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 399
 400         PR binutils/20775
 401         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 402         (FGRPd9_4): Replace 1 with 2.
 403         (FGRPd9_5): Replace 2 with 3.
 404         (FGRPd9_6): Replace 3 with 4.
 405         (FGRPd9_7): Replace 4 with 5.
 406         (FGRPda_5): Replace 5 with 6.
 407         (FGRPdb_4): Replace 6 with 7.
 408         (FGRPde_3): Replace 7 with 8.
 409         (FGRPdf_4): Replace 8 with 9.
 410         (fgrps): Add an entry for Bad_Opcode.
 411
 412 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 413
 414         * arc-opc.c (arc_flag_operands): Add F_DI14.
 415         (arc_flag_classes): Add C_DI14.
 416         * arc-nps400-tbl.h: Add new exc instructions.
 417
 418 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 419
 420         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 421         major opcode 0xa.
 422         * arc-nps-400-tbl.h: Add dcmac instruction.
 423         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 424         (insert_nps_rbdouble_64): Added.
 425         (extract_nps_rbdouble_64): Added.
 426         (insert_nps_proto_size): Added.
 427         (extract_nps_proto_size): Added.
 428
 429 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 430
 431         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 432         relating to long instruction processing, add new limm field.
 433         (OPCODE): Rename to...
 434         (OPCODE_32BIT_INSN): ...this.
 435         (OPCODE_AC): Delete.
 436         (skip_this_opcode): Handle different instruction lengths, update
 437         macro name.
 438         (special_flag_p): Update parameter type.
 439         (find_format_from_table): Update for more instruction lengths.
 440         (find_format_long_instructions): Delete.
 441         (find_format): Update for more instruction lengths.
 442         (arc_insn_length): Likewise.
 443         (extract_operand_value): Update for more instruction lengths.
 444         (operand_iterator_next): Remove code relating to long
 445         instructions.
 446         (arc_opcode_to_insn_type): New function.
 447         (print_insn_arc):Update for more instructions lengths.
 448         * arc-ext.c (extInstruction_t): Change argument type.
 449         * arc-ext.h (extInstruction_t): Change argument type.
 450         * arc-fxi.h: Change type unsigned to unsigned long long
 451         extensively throughout.
 452         * arc-nps400-tbl.h: Add long instructions taken from
 453         arc_long_opcodes table in arc-opc.c.
 454         * arc-opc.c: Update parameter types on insert/extract handlers.
 455         (arc_long_opcodes): Delete.
 456         (arc_num_long_opcodes): Delete.
 457         (arc_opcode_len): Update for more instruction lengths.
 458
 459 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 460
 461         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 462
 463 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 464
 465         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 466         with arc_opcode_len.
 467         (find_format_long_instructions): Likewise.
 468         * arc-opc.c (arc_opcode_len): New function.
 469
 470 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 471
 472         * arc-nps400-tbl.h: Fix some instruction masks.
 473
 474 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 475
 476         * i386-dis.c (REG_82): Removed.
 477         (X86_64_82_REG_0): Likewise.
 478         (X86_64_82_REG_1): Likewise.
 479         (X86_64_82_REG_2): Likewise.
 480         (X86_64_82_REG_3): Likewise.
 481         (X86_64_82_REG_4): Likewise.
 482         (X86_64_82_REG_5): Likewise.
 483         (X86_64_82_REG_6): Likewise.
 484         (X86_64_82_REG_7): Likewise.
 485         (X86_64_82): New.
 486         (dis386): Use X86_64_82 instead of REG_82.
 487         (reg_table): Remove REG_82.
 488         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 489         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 490         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 491         X86_64_82_REG_7.
 492
 493 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 494
 495         PR binutils/20754
 496         * i386-dis.c (REG_82): New.
 497         (X86_64_82_REG_0): Likewise.
 498         (X86_64_82_REG_1): Likewise.
 499         (X86_64_82_REG_2): Likewise.
 500         (X86_64_82_REG_3): Likewise.
 501         (X86_64_82_REG_4): Likewise.
 502         (X86_64_82_REG_5): Likewise.
 503         (X86_64_82_REG_6): Likewise.
 504         (X86_64_82_REG_7): Likewise.
 505         (dis386): Use REG_82.
 506         (reg_table): Add REG_82.
 507         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 508         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 509         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 510
 511 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 512
 513         * i386-dis.c (REG_82): Renamed to ...
 514         (REG_83): This.
 515         (dis386): Updated.
 516         (reg_table): Likewise.
 517
 518 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 519
 520         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 521         * i386-dis-evex.h (evex_table): Updated.
 522         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 523         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 524         (cpu_flags): Add CpuAVX512_4VNNIW.
 525         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 526         (i386_cpu_flags): Add cpuavx512_4vnniw.
 527         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 528         * i386-init.h: Regenerate.
 529         * i386-tbl.h: Ditto.
 530
 531 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 532
 533         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 534         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 535         * i386-dis-evex.h (evex_table): Updated.
 536         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 537         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 538         (cpu_flags): Add CpuAVX512_4FMAPS.
 539         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 540         * i386-opc.h (AVX512_4FMAP): New.
 541         (i386_cpu_flags): Add cpuavx512_4fmaps.
 542         (ImplicitQuadGroup): New.
 543         (i386_opcode_modifier): Add implicitquadgroup.
 544         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 545         * i386-init.h: Regenerate.
 546         * i386-tbl.h: Ditto.
 547
 548 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 549             Andrew Waterman <andrew@sifive.com>
 550
 551         Add support for RISC-V architecture.
 552         * configure.ac: Add entry for bfd_riscv_arch.
 553         * configure: Regenerate.
 554         * disassemble.c (disassembler): Add support for riscv.
 555         (disassembler_usage): Likewise.
 556         * riscv-dis.c: New file.
 557         * riscv-opc.c: New file.
 558
 559 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 560
 561         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 562         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 563         (rm_table): Update the RM_0FAE_REG_7 entry.
 564         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 565         (cpu_flags): Remove CpuPCOMMIT.
 566         * i386-opc.h (CpuPCOMMIT): Removed.
 567         (i386_cpu_flags): Remove cpupcommit.
 568         * i386-opc.tbl: Remove pcommit.
 569         * i386-init.h: Regenerated.
 570         * i386-tbl.h: Likewise.
 571
 572 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 573
 574         PR binutis/20705
 575         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 576         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 577         32-bit mode.  Don't check vex.register_specifier in 32-bit
 578         mode.
 579         (OP_VEX): Check for invalid mask registers.
 580
 581 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 582
 583         PR binutis/20699
 584         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 585         sizeflag.
 586
 587 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 588
 589         PR binutis/20704
 590         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 591
 592 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 593
 594         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 595         local variable to `index_regno'.
 596
 597 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 598
 599         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 600
 601 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 602
 603         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 604         usage on ISA basis.
 605
 606 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 607
 608         PR target/20666
 609         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 610
 611 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 612
 613         PR target/20667
 614         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 615         available.
 616
 617 2016-10-07  Alan Modra  <amodra@gmail.com>
 618
 619         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 620
 621 2016-10-06  Alan Modra  <amodra@gmail.com>
 622
 623         * aarch64-opc.c: Spell fall through comments consistently.
 624         * i386-dis.c: Likewise.
 625         * aarch64-dis.c: Add missing fall through comments.
 626         * aarch64-opc.c: Likewise.
 627         * arc-dis.c: Likewise.
 628         * arm-dis.c: Likewise.
 629         * i386-dis.c: Likewise.
 630         * m68k-dis.c: Likewise.
 631         * mep-asm.c: Likewise.
 632         * ns32k-dis.c: Likewise.
 633         * sh-dis.c: Likewise.
 634         * tic4x-dis.c: Likewise.
 635         * tic6x-dis.c: Likewise.
 636         * vax-dis.c: Likewise.
 637
 638 2016-10-06  Alan Modra  <amodra@gmail.com>
 639
 640         * arc-ext.c (create_map): Add missing break.
 641         * msp430-decode.opc (encode_as): Likewise.
 642         * msp430-decode.c: Regenerate.
 643
 644 2016-10-06  Alan Modra  <amodra@gmail.com>
 645
 646         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 647         * crx-dis.c (print_insn_crx): Likewise.
 648
 649 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 650
 651         PR binutils/20657
 652         * i386-dis.c (putop): Don't assign alt twice.
 653
 654 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 655
 656         PR target/20553
 657         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 658
 659 2016-09-29  Alan Modra  <amodra@gmail.com>
 660
 661         * ppc-opc.c (L): Make compulsory.
 662         (LOPT): New, optional form of L.
 663         (HTM_R): Define as LOPT.
 664         (L0, L1): Delete.
 665         (L32OPT): New, optional for 32-bit L.
 666         (L2OPT): New, 2-bit L for dcbf.
 667         (SVC_LEC): Update.
 668         (L2): Define.
 669         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 670         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 671         <dcbf>: Use L2OPT.
 672         <tlbiel, tlbie>: Use LOPT.
 673         <wclr, wclrall>: Use L2.
 674
 675 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 676
 677         * Makefile.in: Regenerate.
 678         * configure: Likewise.
 679
 680 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 681
 682         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 683         (EXTINSN2OP): Use EXTINSN2OPF.
 684         (bspeekm, bspop, modapp): New extension instructions.
 685         * arc-opc.c (F_DNZ_ND): Define.
 686         (F_DNZ_D): Likewise.
 687         (F_SIZEB1): Changed.
 688         (C_DNZ_D): Define.
 689         (C_HARD): Changed.
 690         * arc-tbl.h (dbnz): New instruction.
 691         (prealloc): Allow it for ARC EM.
 692         (xbfu): Likewise.
 693
 694 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 695
 696         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 697         after commas in addresses.
 698         (aarch64_print_operand): Likewise.
 699
 700 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 701
 702         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 703         rather than "should be" or "expected to be" in error messages.
 704
 705 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 706
 707         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 708         (print_mnemonic_name): ...here.
 709         (print_comment): New function.
 710         (print_aarch64_insn): Call it.
 711         * aarch64-opc.c (aarch64_conds): Add SVE names.
 712         (aarch64_print_operand): Print alternative condition names in
 713         a comment.
 714
 715 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 716
 717         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 718         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 719         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 720         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 721         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 722         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 723         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 724         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 725         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 726         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 727         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 728         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 729         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 730         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 731         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 732         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 733         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 734         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 735         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 736         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 737         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 738         (aarch64_feature_sve): New variable.
 739         (SVE): New macro.
 740         (_SVE_INSN): Likewise.
 741         (aarch64_opcode_table): Add SVE instructions.
 742         * aarch64-opc.h (extract_fields): Declare.
 743         * aarch64-opc-2.c: Regenerate.
 744         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 745         * aarch64-asm-2.c: Regenerate.
 746         * aarch64-dis.c (extract_fields): Make global.
 747         (do_misc_decoding): Handle the new SVE aarch64_ops.
 748         * aarch64-dis-2.c: Regenerate.
 749
 750 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 751
 752         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 753         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 754         aarch64_field_kinds.
 755         * aarch64-opc.c (fields): Add corresponding entries.
 756         * aarch64-asm.c (aarch64_get_variant): New function.
 757         (aarch64_encode_variant_using_iclass): Likewise.
 758         (aarch64_opcode_encode): Call it.
 759         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 760         (aarch64_opcode_decode): Call it.
 761
 762 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 763
 764         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 765         and FP register operands.
 766         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 767         (FLD_SVE_Vn): New aarch64_field_kinds.
 768         * aarch64-opc.c (fields): Add corresponding entries.
 769         (aarch64_print_operand): Handle the new SVE core and FP register
 770         operands.
 771         * aarch64-opc-2.c: Regenerate.
 772         * aarch64-asm-2.c: Likewise.
 773         * aarch64-dis-2.c: Likewise.
 774
 775 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 776
 777         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 778         immediate operands.
 779         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 780         * aarch64-opc.c (fields): Add corresponding entry.
 781         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 782         operands.
 783         (aarch64_print_operand): Likewise.
 784         * aarch64-opc-2.c: Regenerate.
 785         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 786         (ins_sve_float_zero_one): New inserters.
 787         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 788         (aarch64_ins_sve_float_half_two): Likewise.
 789         (aarch64_ins_sve_float_zero_one): Likewise.
 790         * aarch64-asm-2.c: Regenerate.
 791         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 792         (ext_sve_float_zero_one): New extractors.
 793         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 794         (aarch64_ext_sve_float_half_two): Likewise.
 795         (aarch64_ext_sve_float_zero_one): Likewise.
 796         * aarch64-dis-2.c: Regenerate.
 797
 798 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 799
 800         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 801         integer immediate operands.
 802         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 803         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 804         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 805         * aarch64-opc.c (fields): Add corresponding entries.
 806         (operand_general_constraint_met_p): Handle the new SVE integer
 807         immediate operands.
 808         (aarch64_print_operand): Likewise.
 809         (aarch64_sve_dupm_mov_immediate_p): New function.
 810         * aarch64-opc-2.c: Regenerate.
 811         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 812         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 813         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 814         (aarch64_ins_limm): ...here.
 815         (aarch64_ins_inv_limm): New function.
 816         (aarch64_ins_sve_aimm): Likewise.
 817         (aarch64_ins_sve_asimm): Likewise.
 818         (aarch64_ins_sve_limm_mov): Likewise.
 819         (aarch64_ins_sve_shlimm): Likewise.
 820         (aarch64_ins_sve_shrimm): Likewise.
 821         * aarch64-asm-2.c: Regenerate.
 822         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 823         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 824         * aarch64-dis.c (decode_limm): New function, split out from...
 825         (aarch64_ext_limm): ...here.
 826         (aarch64_ext_inv_limm): New function.
 827         (decode_sve_aimm): Likewise.
 828         (aarch64_ext_sve_aimm): Likewise.
 829         (aarch64_ext_sve_asimm): Likewise.
 830         (aarch64_ext_sve_limm_mov): Likewise.
 831         (aarch64_top_bit): Likewise.
 832         (aarch64_ext_sve_shlimm): Likewise.
 833         (aarch64_ext_sve_shrimm): Likewise.
 834         * aarch64-dis-2.c: Regenerate.
 835
 836 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 837
 838         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 839         operands.
 840         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 841         the AARCH64_MOD_MUL_VL entry.
 842         (value_aligned_p): Cope with non-power-of-two alignments.
 843         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 844         (print_immediate_offset_address): Likewise.
 845         (aarch64_print_operand): Likewise.
 846         * aarch64-opc-2.c: Regenerate.
 847         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 848         (ins_sve_addr_ri_s9xvl): New inserters.
 849         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 850         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 851         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 852         * aarch64-asm-2.c: Regenerate.
 853         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 854         (ext_sve_addr_ri_s9xvl): New extractors.
 855         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 856         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 857         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 858         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 859         * aarch64-dis-2.c: Regenerate.
 860
 861 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 862
 863         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 864         address operands.
 865         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 866         (FLD_SVE_xs_22): New aarch64_field_kinds.
 867         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 868         (get_operand_specific_data): New function.
 869         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 870         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 871         (operand_general_constraint_met_p): Handle the new SVE address
 872         operands.
 873         (sve_reg): New array.
 874         (get_addr_sve_reg_name): New function.
 875         (aarch64_print_operand): Handle the new SVE address operands.
 876         * aarch64-opc-2.c: Regenerate.
 877         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 878         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 879         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 880         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 881         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 882         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 883         (aarch64_ins_sve_addr_zi_u5): Likewise.
 884         (aarch64_ins_sve_addr_zz): Likewise.
 885         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 886         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 887         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 888         * aarch64-asm-2.c: Regenerate.
 889         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 890         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 891         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 892         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 893         (aarch64_ext_sve_addr_ri_u6): Likewise.
 894         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 895         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 896         (aarch64_ext_sve_addr_zi_u5): Likewise.
 897         (aarch64_ext_sve_addr_zz): Likewise.
 898         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 899         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 900         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 901         * aarch64-dis-2.c: Regenerate.
 902
 903 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 904
 905         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 906         AARCH64_OPND_SVE_PATTERN_SCALED.
 907         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 908         * aarch64-opc.c (fields): Add a corresponding entry.
 909         (set_multiplier_out_of_range_error): New function.
 910         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 911         (operand_general_constraint_met_p): Handle
 912         AARCH64_OPND_SVE_PATTERN_SCALED.
 913         (print_register_offset_address): Use PRIi64 to print the
 914         shift amount.
 915         (aarch64_print_operand): Likewise.  Handle
 916         AARCH64_OPND_SVE_PATTERN_SCALED.
 917         * aarch64-opc-2.c: Regenerate.
 918         * aarch64-asm.h (ins_sve_scale): New inserter.
 919         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 920         * aarch64-asm-2.c: Regenerate.
 921         * aarch64-dis.h (ext_sve_scale): New inserter.
 922         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 923         * aarch64-dis-2.c: Regenerate.
 924
 925 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 926
 927         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 928         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 929         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 930         (FLD_SVE_prfop): Likewise.
 931         * aarch64-opc.c: Include libiberty.h.
 932         (aarch64_sve_pattern_array): New variable.
 933         (aarch64_sve_prfop_array): Likewise.
 934         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 935         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 936         AARCH64_OPND_SVE_PRFOP.
 937         * aarch64-asm-2.c: Regenerate.
 938         * aarch64-dis-2.c: Likewise.
 939         * aarch64-opc-2.c: Likewise.
 940
 941 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 942
 943         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 944         AARCH64_OPND_QLF_P_[ZM].
 945         (aarch64_print_operand): Print /z and /m where appropriate.
 946
 947 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 948
 949         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 950         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 951         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 952         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 953         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 954         * aarch64-opc.c (fields): Add corresponding entries here.
 955         (operand_general_constraint_met_p): Check that SVE register lists
 956         have the correct length.  Check the ranges of SVE index registers.
 957         Check for cases where p8-p15 are used in 3-bit predicate fields.
 958         (aarch64_print_operand): Handle the new SVE operands.
 959         * aarch64-opc-2.c: Regenerate.
 960         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 961         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 962         (aarch64_ins_sve_reglist): Likewise.
 963         * aarch64-asm-2.c: Regenerate.
 964         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 965         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 966         (aarch64_ext_sve_reglist): Likewise.
 967         * aarch64-dis-2.c: Regenerate.
 968
 969 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 970
 971         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 972         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 973         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 974         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 975         tied operands.
 976
 977 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 978
 979         * aarch64-opc.c (get_offset_int_reg_name): New function.
 980         (print_immediate_offset_address): Likewise.
 981         (print_register_offset_address): Take the base and offset
 982         registers as parameters.
 983         (aarch64_print_operand): Update caller accordingly.  Use
 984         print_immediate_offset_address.
 985
 986 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 987
 988         * aarch64-opc.c (BANK): New macro.
 989         (R32, R64): Take a register number as argument
 990         (int_reg): Use BANK.
 991
 992 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 993
 994         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 995         (aarch64_print_operand): Update accordingly.
 996
 997 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 998
 999         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1000         for FPIMM.
1001         * aarch64-asm.h (ins_fpimm): New inserter.
1002         * aarch64-asm.c (aarch64_ins_fpimm): New function.
1003         * aarch64-asm-2.c: Regenerate.
1004         * aarch64-dis.h (ext_fpimm): New extractor.
1005         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1006         (aarch64_ext_fpimm): New function.
1007         * aarch64-dis-2.c: Regenerate.
1008
1009 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1010
1011         * aarch64-asm.c: Include libiberty.h.
1012         (insert_fields): New function.
1013         (aarch64_ins_imm): Use it.
1014         * aarch64-dis.c (extract_fields): New function.
1015         (aarch64_ext_imm): Use it.
1016
1017 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1018
1019         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1020         with an esize parameter.
1021         (operand_general_constraint_met_p): Update accordingly.
1022         Fix misindented code.
1023         * aarch64-asm.c (aarch64_ins_limm): Update call to
1024         aarch64_logical_immediate_p.
1025
1026 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1027
1028         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1029
1030 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1031
1032         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1033
1034 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
1035
1036         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1037
1038 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
1039
1040         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1041         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1042         xor3>: Delete mnemonics.
1043         <cp_abort>: Rename mnemonic from ...
1044         <cpabort>: ...to this.
1045         <setb>: Change to a X form instruction.
1046         <sync>: Change to 1 operand form.
1047         <copy>: Delete mnemonic.
1048         <copy_first>: Rename mnemonic from ...
1049         <copy>: ...to this.
1050         <paste, paste.>: Delete mnemonics.
1051         <paste_last>: Rename mnemonic from ...
1052         <paste.>: ...to this.
1053
1054 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1055
1056         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1057
1058 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1059
1060         * s390-mkopc.c (main): Support alternate arch strings.
1061
1062 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
1063
1064         * s390-opc.txt: Fix kmctr instruction type.
1065
1066 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
1067
1068         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1069         * i386-init.h: Regenerated.
1070
1071 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
1072
1073         * opcodes/arc-dis.c (print_insn_arc): Changed.
1074
1075 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
1076
1077         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1078         camellia_fl.
1079
1080 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1081
1082         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
1083         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1084         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1085
1086 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
1087
1088         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1089         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1090         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1091         PREFIX_MOD_3_0FAE_REG_4.
1092         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1093         PREFIX_MOD_3_0FAE_REG_4.
1094         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1095         (cpu_flags): Add CpuPTWRITE.
1096         * i386-opc.h (CpuPTWRITE): New.
1097         (i386_cpu_flags): Add cpuptwrite.
1098         * i386-opc.tbl: Add ptwrite instruction.
1099         * i386-init.h: Regenerated.
1100         * i386-tbl.h: Likewise.
1101
1102 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1103
1104         * arc-dis.h: Wrap around in extern "C".
1105
1106 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1107
1108         * aarch64-tbl.h (V8_2_INSN): New macro.
1109         (aarch64_opcode_table): Use it.
1110
1111 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1112
1113         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1114         CORE_INSN, __FP_INSN and SIMD_INSN.
1115
1116 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1117
1118         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1119         (aarch64_opcode_table): Update uses accordingly.
1120
1121 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1122         Kwok Cheung Yeung  <kcy@codesourcery.com>
1123
1124         opcodes/
1125         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1126         'e_cmplwi' to 'e_cmpli' instead.
1127         (OPVUPRT, OPVUPRT_MASK): Define.
1128         (powerpc_opcodes): Add E200Z4 insns.
1129         (vle_opcodes): Add context save/restore insns.
1130
1131 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1132
1133         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1134         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1135         "j".
1136
1137 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1138
1139         * arc-nps400-tbl.h: Change block comments to GNU format.
1140         * arc-dis.c: Add new globals addrtypenames,
1141         addrtypenames_max, and addtypeunknown.
1142         (get_addrtype): New function.
1143         (print_insn_arc): Print colons and address types when
1144         required.
1145         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1146         define insert and extract functions for all address types.
1147         (arc_operands): Add operands for colon and all address
1148         types.
1149         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1150         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1151         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1152         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1153         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1154         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1155
1156 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1157
1158         * configure: Regenerated.
1159
1160 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1161
1162         * arc-dis.c (skipclass): New structure.
1163         (decodelist): New variable.
1164         (is_compatible_p): New function.
1165         (new_element): Likewise.
1166         (skip_class_p): Likewise.
1167         (find_format_from_table): Use skip_class_p function.
1168         (find_format): Decode first the extension instructions.
1169         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1170         e_flags.
1171         (parse_option): New function.
1172         (parse_disassembler_options): Likewise.
1173         (print_arc_disassembler_options): Likewise.
1174         (print_insn_arc): Use parse_disassembler_options function.  Proper
1175         select ARCv2 cpu variant.
1176         * disassemble.c (disassembler_usage): Add ARC disassembler
1177         options.
1178
1179 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1180
1181         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1182         annotation from the "nal" entry and reorder it beyond "bltzal".
1183
1184 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1185
1186         * sparc-opc.c (ldtxa): New macro.
1187         (sparc_opcodes): Use the macro defined above to add entries for
1188         the LDTXA instructions.
1189         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1190         instruction.
1191
1192 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1193
1194         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1195         and "jmpc".
1196
1197 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1198
1199         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1200         (movzb): Adjust to cover all permitted suffixes.
1201         (movzw): New.
1202         * i386-tbl.h: Re-generate.
1203
1204 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1205
1206         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1207         (lgdt): Remove Tbyte from non-64-bit variant.
1208         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1209         xsaves64, xsavec64): Remove Disp16.
1210         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1211         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1212         64-bit variants.
1213         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1214         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1215         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1216         64-bit variants.
1217         * i386-tbl.h: Re-generate.
1218
1219 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1220
1221         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1222         * i386-tbl.h: Re-generate.
1223
1224 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1225
1226         * arm-dis.c (print_insn): Fix typo in comment.
1227
1228 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1229
1230         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1231         range of ldst_elemlist operands.
1232         (print_register_list): Use PRIi64 to print the index.
1233         (aarch64_print_operand): Likewise.
1234
1235 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1236
1237         * mcore-opc.h: Remove sentinal.
1238         * mcore-dis.c (print_insn_mcore): Adjust.
1239
1240 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1241
1242         * arc-opc.c: Correct description of availability of NPS400
1243         features.
1244
1245 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1246
1247         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1248         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1249         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1250         xor3>: New mnemonics.
1251         <setb>: Change to a VX form instruction.
1252         (insert_sh6): Add support for rldixor.
1253         (extract_sh6): Likewise.
1254
1255 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1256
1257         * arc-ext.h: Wrap in extern C.
1258
1259 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1260
1261         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1262         Use same method for determining instruction length on ARC700 and
1263         NPS-400.
1264         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1265         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1266         with the NPS400 subclass.
1267         * arc-opc.c: Likewise.
1268
1269 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1270
1271         * sparc-opc.c (rdasr): New macro.
1272         (wrasr): Likewise.
1273         (rdpr): Likewise.
1274         (wrpr): Likewise.
1275         (rdhpr): Likewise.
1276         (wrhpr): Likewise.
1277         (sparc_opcodes): Use the macros above to fix and expand the
1278         definition of read/write instructions from/to
1279         asr/privileged/hyperprivileged instructions.
1280         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1281         %hva_mask_nz.  Prefer softint_set and softint_clear over
1282         set_softint and clear_softint.
1283         (print_insn_sparc): Support %ver in Rd.
1284
1285 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1286
1287         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1288         architecture according to the hardware capabilities they require.
1289
1290 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1291
1292         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1293         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1294         bfd_mach_sparc_v9{c,d,e,v,m}.
1295         * sparc-opc.c (MASK_V9C): Define.
1296         (MASK_V9D): Likewise.
1297         (MASK_V9E): Likewise.
1298         (MASK_V9V): Likewise.
1299         (MASK_V9M): Likewise.
1300         (v6): Add MASK_V9{C,D,E,V,M}.
1301         (v6notlet): Likewise.
1302         (v7): Likewise.
1303         (v8): Likewise.
1304         (v9): Likewise.
1305         (v9andleon): Likewise.
1306         (v9a): Likewise.
1307         (v9b): Likewise.
1308         (v9c): Define.
1309         (v9d): Likewise.
1310         (v9e): Likewise.
1311         (v9v): Likewise.
1312         (v9m): Likewise.
1313         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1314
1315 2016-06-15  Nick Clifton  <nickc@redhat.com>
1316
1317         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1318         constants to match expected behaviour.
1319         (nds32_parse_opcode): Likewise.  Also for whitespace.
1320
1321 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1322
1323         * arc-opc.c (extract_rhv1): Extract value from insn.
1324
1325 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1326
1327         * arc-nps400-tbl.h: Add ldbit instruction.
1328         * arc-opc.c: Add flag classes required for ldbit.
1329
1330 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1331
1332         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1333         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1334         support the above instructions.
1335
1336 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1337
1338         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1339         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1340         csma, cbba, zncv, and hofs.
1341         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1342         support the above instructions.
1343
1344 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1345
1346         * arc-nps400-tbl.h: Add andab and orab instructions.
1347
1348 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1349
1350         * arc-nps400-tbl.h: Add addl-like instructions.
1351
1352 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1353
1354         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1355
1356 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1357
1358         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1359         instructions.
1360
1361 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1362
1363         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1364         variable.
1365         (init_disasm): Handle new command line option "insnlength".
1366         (print_s390_disassembler_options): Mention new option in help
1367         output.
1368         (print_insn_s390): Use the encoded insn length when dumping
1369         unknown instructions.
1370
1371 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1372
1373         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1374          to the address and set as symbol address for LDS/ STS immediate operands.
1375
1376 2016-06-07  Alan Modra  <amodra@gmail.com>
1377
1378         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1379         cpu for "vle" to e500.
1380         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1381         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1382         (PPCNONE): Delete, substitute throughout.
1383         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1384         except for major opcode 4 and 31.
1385         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1386
1387 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1388
1389         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1390         ARM_EXT_RAS in relevant entries.
1391
1392 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1393
1394         PR binutils/20196
1395         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1396         opcodes for E6500.
1397
1398 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1399
1400         PR binutis/18386
1401         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1402         (indir_v_mode): New.
1403         Add comments for '&'.
1404         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1405         (putop): Handle '&'.
1406         (intel_operand_size): Handle indir_v_mode.
1407         (OP_E_register): Likewise.
1408         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1409         64-bit indirect call/jmp for AMD64.
1410         * i386-tbl.h: Regenerated
1411
1412 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1413
1414         * arc-dis.c (struct arc_operand_iterator): New structure.
1415         (find_format_from_table): All the old content from find_format,
1416         with some minor adjustments, and parameter renaming.
1417         (find_format_long_instructions): New function.
1418         (find_format): Rewritten.
1419         (arc_insn_length): Add LSB parameter.
1420         (extract_operand_value): New function.
1421         (operand_iterator_next): New function.
1422         (print_insn_arc): Use new functions to find opcode, and iterator
1423         over operands.
1424         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1425         (extract_nps_3bit_dst_short): New function.
1426         (insert_nps_3bit_src2_short): New function.
1427         (extract_nps_3bit_src2_short): New function.
1428         (insert_nps_bitop1_size): New function.
1429         (extract_nps_bitop1_size): New function.
1430         (insert_nps_bitop2_size): New function.
1431         (extract_nps_bitop2_size): New function.
1432         (insert_nps_bitop_mod4_msb): New function.
1433         (extract_nps_bitop_mod4_msb): New function.
1434         (insert_nps_bitop_mod4_lsb): New function.
1435         (extract_nps_bitop_mod4_lsb): New function.
1436         (insert_nps_bitop_dst_pos3_pos4): New function.
1437         (extract_nps_bitop_dst_pos3_pos4): New function.
1438         (insert_nps_bitop_ins_ext): New function.
1439         (extract_nps_bitop_ins_ext): New function.
1440         (arc_operands): Add new operands.
1441         (arc_long_opcodes): New global array.
1442         (arc_num_long_opcodes): New global.
1443         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1444
1445 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1446
1447         * nds32-asm.h: Add extern "C".
1448         * sh-opc.h: Likewise.
1449
1450 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1451
1452         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1453         0,b,limm to the rflt instruction.
1454
1455 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1456
1457         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1458         constant.
1459
1460 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1461
1462         PR gas/20145
1463         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1464         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1465         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1466         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1467         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1468         * i386-init.h: Regenerated.
1469
1470 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1471
1472         PR gas/20145
1473         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1474         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1475         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1476         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1477         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1478         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1479         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1480         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1481         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1482         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1483         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1484         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1485         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1486         CpuRegMask for AVX512.
1487         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1488         and CpuRegMask.
1489         (set_bitfield_from_cpu_flag_init): New function.
1490         (set_bitfield): Remove const on f.  Call
1491         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1492         * i386-opc.h (CpuRegMMX): New.
1493         (CpuRegXMM): Likewise.
1494         (CpuRegYMM): Likewise.
1495         (CpuRegZMM): Likewise.
1496         (CpuRegMask): Likewise.
1497         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1498         and cpuregmask.
1499         * i386-init.h: Regenerated.
1500         * i386-tbl.h: Likewise.
1501
1502 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1503
1504         PR gas/20154
1505         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1506         (opcode_modifiers): Add AMD64 and Intel64.
1507         (main): Properly verify CpuMax.
1508         * i386-opc.h (CpuAMD64): Removed.
1509         (CpuIntel64): Likewise.
1510         (CpuMax): Set to CpuNo64.
1511         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1512         (AMD64): New.
1513         (Intel64): Likewise.
1514         (i386_opcode_modifier): Add amd64 and intel64.
1515         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1516         on call and jmp.
1517         * i386-init.h: Regenerated.
1518         * i386-tbl.h: Likewise.
1519
1520 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1521
1522         PR gas/20154
1523         * i386-gen.c (main): Fail if CpuMax is incorrect.
1524         * i386-opc.h (CpuMax): Set to CpuIntel64.
1525         * i386-tbl.h: Regenerated.
1526
1527 2016-05-27  Nick Clifton  <nickc@redhat.com>
1528
1529         PR target/20150
1530         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1531         (msp430dis_opcode_unsigned): New function.
1532         (msp430dis_opcode_signed): New function.
1533         (msp430_singleoperand): Use the new opcode reading functions.
1534         Only disassenmble bytes if they were successfully read.
1535         (msp430_doubleoperand): Likewise.
1536         (msp430_branchinstr): Likewise.
1537         (msp430x_callx_instr): Likewise.
1538         (print_insn_msp430): Check that it is safe to read bytes before
1539         attempting disassembly.  Use the new opcode reading functions.
1540
1541 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1542
1543         * ppc-opc.c (CY): New define.  Document it.
1544         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1545
1546 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1547
1548         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1549         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1550         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1551         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1552         CPU_ANY_AVX_FLAGS.
1553         * i386-init.h: Regenerated.
1554
1555 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1556
1557         PR gas/20141
1558         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1559         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1560         * i386-init.h: Regenerated.
1561
1562 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1563
1564         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1565         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1566         * i386-init.h: Regenerated.
1567
1568 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1569
1570         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1571         information.
1572         (print_insn_arc): Set insn_type information.
1573         * arc-opc.c (C_CC): Add F_CLASS_COND.
1574         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1575         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1576         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1577         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1578         (brne, brne_s, jeq_s, jne_s): Likewise.
1579
1580 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1581
1582         * arc-tbl.h (neg): New instruction variant.
1583
1584 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1585
1586         * arc-dis.c (find_format, find_format, get_auxreg)
1587         (print_insn_arc): Changed.
1588         * arc-ext.h (INSERT_XOP): Likewise.
1589
1590 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1591
1592         * tic54x-dis.c (sprint_mmr): Adjust.
1593         * tic54x-opc.c: Likewise.
1594
1595 2016-05-19  Alan Modra  <amodra@gmail.com>
1596
1597         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1598
1599 2016-05-19  Alan Modra  <amodra@gmail.com>
1600
1601         * ppc-opc.c: Formatting.
1602         (NSISIGNOPT): Define.
1603         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1604
1605 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1606
1607         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1608         replacing references to `micromips_ase' throughout.
1609         (_print_insn_mips): Don't use file-level microMIPS annotation to
1610         determine the disassembly mode with the symbol table.
1611
1612 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1613
1614         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1615
1616 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1617
1618         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1619         mips64r6.
1620         * mips-opc.c (D34): New macro.
1621         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1622
1623 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1624
1625         * i386-dis.c (prefix_table): Add RDPID instruction.
1626         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1627         (cpu_flags): Add RDPID bitfield.
1628         * i386-opc.h (enum): Add RDPID element.
1629         (i386_cpu_flags): Add RDPID field.
1630         * i386-opc.tbl: Add RDPID instruction.
1631         * i386-init.h: Regenerate.
1632         * i386-tbl.h: Regenerate.
1633
1634 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1635
1636         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1637         branch type of a symbol.
1638         (print_insn): Likewise.
1639
1640 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1641
1642         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1643         Mainline Security Extensions instructions.
1644         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1645         Extensions instructions.
1646         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1647         instructions.
1648         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1649         special registers.
1650
1651 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1652
1653         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1654
1655 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1656
1657         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1658         (arcExtMap_genOpcode): Likewise.
1659         * arc-opc.c (arg_32bit_rc): Define new variable.
1660         (arg_32bit_u6): Likewise.
1661         (arg_32bit_limm): Likewise.
1662
1663 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1664
1665         * aarch64-gen.c (VERIFIER): Define.
1666         * aarch64-opc.c (VERIFIER): Define.
1667         (verify_ldpsw): Use static linkage.
1668         * aarch64-opc.h (verify_ldpsw): Remove.
1669         * aarch64-tbl.h: Use VERIFIER for verifiers.
1670
1671 2016-04-28  Nick Clifton  <nickc@redhat.com>
1672
1673         PR target/19722
1674         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1675         * aarch64-opc.c (verify_ldpsw): New function.
1676         * aarch64-opc.h (verify_ldpsw): New prototype.
1677         * aarch64-tbl.h: Add initialiser for verifier field.
1678         (LDPSW): Set verifier to verify_ldpsw.
1679
1680 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1681
1682         PR binutils/19983
1683         PR binutils/19984
1684         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1685         smaller than address size.
1686
1687 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1688
1689         * alpha-dis.c: Regenerate.
1690         * crx-dis.c: Likewise.
1691         * disassemble.c: Likewise.
1692         * epiphany-opc.c: Likewise.
1693         * fr30-opc.c: Likewise.
1694         * frv-opc.c: Likewise.
1695         * ip2k-opc.c: Likewise.
1696         * iq2000-opc.c: Likewise.
1697         * lm32-opc.c: Likewise.
1698         * lm32-opinst.c: Likewise.
1699         * m32c-opc.c: Likewise.
1700         * m32r-opc.c: Likewise.
1701         * m32r-opinst.c: Likewise.
1702         * mep-opc.c: Likewise.
1703         * mt-opc.c: Likewise.
1704         * or1k-opc.c: Likewise.
1705         * or1k-opinst.c: Likewise.
1706         * tic80-opc.c: Likewise.
1707         * xc16x-opc.c: Likewise.
1708         * xstormy16-opc.c: Likewise.
1709
1710 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1711
1712         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1713         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1714         calcsd, and calcxd instructions.
1715         * arc-opc.c (insert_nps_bitop_size): Delete.
1716         (extract_nps_bitop_size): Delete.
1717         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1718         (extract_nps_qcmp_m3): Define.
1719         (extract_nps_qcmp_m2): Define.
1720         (extract_nps_qcmp_m1): Define.
1721         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1722         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1723         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1724         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1725         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1726         NPS_QCMP_M3.
1727
1728 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1729
1730         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1731
1732 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1733
1734         * Makefile.in: Regenerated with automake 1.11.6.
1735         * aclocal.m4: Likewise.
1736
1737 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1738
1739         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1740         instructions.
1741         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1742         (extract_nps_cmem_uimm16): New function.
1743         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1744
1745 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1746
1747         * arc-dis.c (arc_insn_length): New function.
1748         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1749         (find_format): Change insnLen parameter to unsigned.
1750
1751 2016-04-13  Nick Clifton  <nickc@redhat.com>
1752
1753         PR target/19937
1754         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1755         the LD.B and LD.BU instructions.
1756
1757 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1758
1759         * arc-dis.c (find_format): Check for extension flags.
1760         (print_flags): New function.
1761         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1762         .extAuxRegister.
1763         * arc-ext.c (arcExtMap_coreRegName): Use
1764         LAST_EXTENSION_CORE_REGISTER.
1765         (arcExtMap_coreReadWrite): Likewise.
1766         (dump_ARC_extmap): Update printing.
1767         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1768         (arc_aux_regs): Add cpu field.
1769         * arc-regs.h: Add cpu field, lower case name aux registers.
1770
1771 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1772
1773         * arc-tbl.h: Add rtsc, sleep with no arguments.
1774
1775 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1776
1777         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1778         Initialize.
1779         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1780         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1781         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1782         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1783         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1784         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1785         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1786         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1787         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1788         (arc_opcode arc_opcodes): Null terminate the array.
1789         (arc_num_opcodes): Remove.
1790         * arc-ext.h (INSERT_XOP): Define.
1791         (extInstruction_t): Likewise.
1792         (arcExtMap_instName): Delete.
1793         (arcExtMap_insn): New function.
1794         (arcExtMap_genOpcode): Likewise.
1795         * arc-ext.c (ExtInstruction): Remove.
1796         (create_map): Zero initialize instruction fields.
1797         (arcExtMap_instName): Remove.
1798         (arcExtMap_insn): New function.
1799         (dump_ARC_extmap): More info while debuging.
1800         (arcExtMap_genOpcode): New function.
1801         * arc-dis.c (find_format): New function.
1802         (print_insn_arc): Use find_format.
1803         (arc_get_disassembler): Enable dump_ARC_extmap only when
1804         debugging.
1805
1806 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1807
1808         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1809         instruction bits out.
1810
1811 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1812
1813         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1814         * arc-opc.c (arc_flag_operands): Add new flags.
1815         (arc_flag_classes): Add new classes.
1816
1817 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1818
1819         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1820
1821 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1822
1823         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1824         encode1, rflt, crc16, and crc32 instructions.
1825         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1826         (arc_flag_classes): Add C_NPS_R.
1827         (insert_nps_bitop_size_2b): New function.
1828         (extract_nps_bitop_size_2b): Likewise.
1829         (insert_nps_bitop_uimm8): Likewise.
1830         (extract_nps_bitop_uimm8): Likewise.
1831         (arc_operands): Add new operand entries.
1832
1833 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1834
1835         * arc-regs.h: Add a new subclass field.  Add double assist
1836         accumulator register values.
1837         * arc-tbl.h: Use DPA subclass to mark the double assist
1838         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1839         * arc-opc.c (RSP): Define instead of SP.
1840         (arc_aux_regs): Add the subclass field.
1841
1842 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1843
1844         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1845
1846 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1847
1848         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1849         NPS_R_SRC1.
1850
1851 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1852
1853         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1854         issues.  No functional changes.
1855
1856 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1857
1858         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1859         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1860         (RTT): Remove duplicate.
1861         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1862         (PCT_CONFIG*): Remove.
1863         (D1L, D1H, D2H, D2L): Define.
1864
1865 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1866
1867         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1868
1869 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1870
1871         * arc-tbl.h (invld07): Remove.
1872         * arc-ext-tbl.h: New file.
1873         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1874         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1875
1876 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1877
1878         Fix -Wstack-usage warnings.
1879         * aarch64-dis.c (print_operands): Substitute size.
1880         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1881
1882 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1883
1884         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1885         to get a proper diagnostic when an invalid ASR register is used.
1886
1887 2016-03-22  Nick Clifton  <nickc@redhat.com>
1888
1889         * configure: Regenerate.
1890
1891 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1892
1893         * arc-nps400-tbl.h: New file.
1894         * arc-opc.c: Add top level comment.
1895         (insert_nps_3bit_dst): New function.
1896         (extract_nps_3bit_dst): New function.
1897         (insert_nps_3bit_src2): New function.
1898         (extract_nps_3bit_src2): New function.
1899         (insert_nps_bitop_size): New function.
1900         (extract_nps_bitop_size): New function.
1901         (arc_flag_operands): Add nps400 entries.
1902         (arc_flag_classes): Add nps400 entries.
1903         (arc_operands): Add nps400 entries.
1904         (arc_opcodes): Add nps400 include.
1905
1906 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1907
1908         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1909         the new class enum values.
1910
1911 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1912
1913         * arc-dis.c (print_insn_arc): Handle nps400.
1914
1915 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1916
1917         * arc-opc.c (BASE): Delete.
1918
1919 2016-03-18  Nick Clifton  <nickc@redhat.com>
1920
1921         PR target/19721
1922         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1923         of MOV insn that aliases an ORR insn.
1924
1925 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1926
1927         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1928
1929 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1930
1931         * mcore-opc.h: Add const qualifiers.
1932         * microblaze-opc.h (struct op_code_struct): Likewise.
1933         * sh-opc.h: Likewise.
1934         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1935         (tic4x_print_op): Likewise.
1936
1937 2016-03-02  Alan Modra  <amodra@gmail.com>
1938
1939         * or1k-desc.h: Regenerate.
1940         * fr30-ibld.c: Regenerate.
1941         * rl78-decode.c: Regenerate.
1942
1943 2016-03-01  Nick Clifton  <nickc@redhat.com>
1944
1945         PR target/19747
1946         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1947
1948 2016-02-24  Renlin Li  <renlin.li@arm.com>
1949
1950         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1951         (print_insn_coprocessor): Support fp16 instructions.
1952
1953 2016-02-24  Renlin Li  <renlin.li@arm.com>
1954
1955         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1956         vminnm, vrint(mpna).
1957
1958 2016-02-24  Renlin Li  <renlin.li@arm.com>
1959
1960         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1961         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1962
1963 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1964
1965         * i386-dis.c (print_insn): Parenthesize expression to prevent
1966         truncated addresses.
1967         (OP_J): Likewise.
1968
1969 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1970             Janek van Oirschot  <jvanoirs@synopsys.com>
1971
1972         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1973         variable.
1974
1975 2016-02-04  Nick Clifton  <nickc@redhat.com>
1976
1977         PR target/19561
1978         * msp430-dis.c (print_insn_msp430): Add a special case for
1979         decoding an RRC instruction with the ZC bit set in the extension
1980         word.
1981
1982 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1983
1984         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1985         * epiphany-ibld.c: Regenerate.
1986         * fr30-ibld.c: Regenerate.
1987         * frv-ibld.c: Regenerate.
1988         * ip2k-ibld.c: Regenerate.
1989         * iq2000-ibld.c: Regenerate.
1990         * lm32-ibld.c: Regenerate.
1991         * m32c-ibld.c: Regenerate.
1992         * m32r-ibld.c: Regenerate.
1993         * mep-ibld.c: Regenerate.
1994         * mt-ibld.c: Regenerate.
1995         * or1k-ibld.c: Regenerate.
1996         * xc16x-ibld.c: Regenerate.
1997         * xstormy16-ibld.c: Regenerate.
1998
1999 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
2000
2001         * epiphany-dis.c: Regenerated from latest cpu files.
2002
2003 2016-02-01  Michael McConville  <mmcco@mykolab.com>
2004
2005         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2006         test bit.
2007
2008 2016-01-25  Renlin Li  <renlin.li@arm.com>
2009
2010         * arm-dis.c (mapping_symbol_for_insn): New function.
2011         (find_ifthen_state): Call mapping_symbol_for_insn().
2012
2013 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
2014
2015         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2016         of MSR UAO immediate operand.
2017
2018 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
2019
2020         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2021         instruction support.
2022
2023 2016-01-17  Alan Modra  <amodra@gmail.com>
2024
2025         * configure: Regenerate.
2026
2027 2016-01-14  Nick Clifton  <nickc@redhat.com>
2028
2029         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2030         instructions that can support stack pointer operations.
2031         * rl78-decode.c: Regenerate.
2032         * rl78-dis.c: Fix display of stack pointer in MOVW based
2033         instructions.
2034
2035 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
2036
2037         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2038         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
2039         erxtatus_el1 and erxaddr_el1.
2040
2041 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
2042
2043         * arm-dis.c (arm_opcodes): Add "esb".
2044         (thumb_opcodes): Likewise.
2045
2046 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
2047
2048         * ppc-opc.c <xscmpnedp>: Delete.
2049         <xvcmpnedp>: Likewise.
2050         <xvcmpnedp.>: Likewise.
2051         <xvcmpnesp>: Likewise.
2052         <xvcmpnesp.>: Likewise.
2053
2054 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
2055
2056         PR gas/13050
2057         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2058         addition to ISA_A.
2059
2060 2016-01-01  Alan Modra  <amodra@gmail.com>
2061
2062         Update year range in copyright notice of all files.
2063
2064 For older changes see ChangeLog-2015
2065 \f
2066 Copyright (C) 2016 Free Software Foundation, Inc.
2067
2068 Copying and distribution of this file, with or without modification,
2069 are permitted in any medium without royalty provided the copyright
2070 notice and this notice are preserved.
2071
2072 Local Variables:
2073 mode: change-log
2074 left-margin: 8
2075 fill-column: 74
2076 version-control: never
2077 End: