opcodes/ChangeLog

   1 2018-11-29  Jim Wilson  <jimw@sifive.com>
   2
   3         * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
   4         (c.unimp): New.
   5
   6 2018-11-27  Jim Wilson  <jimw@sifive.com>
   7
   8         * riscv-opc.c (ciw): Fix whitespace to align columns.
   9         (ca): New.
  10
  11 2018-11-21  John Darrington  <john@darrington.wattle.id.au>
  12
  13         * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
  14         if the postbyte matches the appropriate pattern.
  15
  16 2018-11-13  Francois H. Theron <francois.theron@netronome.com>
  17
  18         * nfp-dis.c: Fix crc[] disassembly if operands are swapped.
  19
  20 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  21
  22         * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
  23         IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
  24         IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
  25         CIGDVAC and GZVA.
  26         (aarch64_sys_ins_reg_supported_p): New check for above.
  27
  28 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  29
  30         * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
  31         TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
  32         RGSR_EL1 and GCR_EL1.
  33         (aarch64_sys_reg_supported_p): New check for above.
  34         (aarch64_pstatefields): New entry for TCO.
  35         (aarch64_pstatefield_supported_p): New check for above.
  36
  37 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  38
  39         * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
  40         * aarch64-asm.h (ins_addr_simple_2): Declare the above.
  41         * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
  42         * aarch64-dis.h (ext_addr_simple_2): Declare the above.
  43         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
  44         AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
  45         (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
  46         * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
  47         (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
  48         * aarch64-asm-2.c: Regenerated.
  49         * aarch64-dis-2.c: Regenerated.
  50         * aarch64-opc-2.c: Regenerated.
  51
  52 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  53
  54         * aarch64-tbl.h (QL_LDG): New.
  55         (aarch64_opcode_table): Add ldg.
  56         * aarch64-asm-2.c: Regenerated.
  57         * aarch64-dis-2.c: Regenerated.
  58         * aarch64-opc-2.c: Regenerated.
  59
  60 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  61
  62         * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
  63         for AARCH64_OPND_QLF_imm_tag.
  64         (operand_general_constraint_met_p): Add case for
  65         AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
  66         (aarch64_print_operand): Likewise.
  67         * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
  68         (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
  69         for both offset and pre/post indexed versions.
  70         (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
  71         * aarch64-asm-2.c: Regenerated.
  72         * aarch64-dis-2.c: Regenerated.
  73         * aarch64-opc-2.c: Regenerated.
  74
  75 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  76
  77         * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
  78         * aarch64-asm-2.c: Regenerated.
  79         * aarch64-dis-2.c: Regenerated.
  80         * aarch64-opc-2.c: Regenerated.
  81
  82 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  83
  84         * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
  85         (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
  86         * aarch64-opc.c (fields): Add entry for imm4_3.
  87         (operand_general_constraint_met_p): Add cases for
  88         AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
  89         (aarch64_print_operand): Likewise.
  90         * aarch64-tbl.h (QL_ADDG): New.
  91         (aarch64_opcode_table): Add addg, subg, irg and gmi.
  92         (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
  93         * aarch64-asm.c (aarch64_ins_imm): Add case for
  94         operand_need_shift_by_four.
  95         * aarch64-asm-2.c: Regenerated.
  96         * aarch64-dis-2.c: Regenerated.
  97         * aarch64-opc-2.c: Regenerated.
  98
  99 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
 100
 101         * aarch64-tbl.h (aarch64_feature_memtag): New.
 102         (MEMTAG, MEMTAG_INSN): New.
 103
 104 2018-11-06  Sudakshina Das  <sudi.das@arm.com>
 105
 106         * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
 107         with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
 108
 109 2018-11-06  Alan Modra  <amodra@gmail.com>
 110
 111         * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
 112         (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
 113         (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
 114         (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
 115         Don't return zero on error, insert mask bits instead.
 116         (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
 117         (insert_sh6, extract_sh6): Delete dead code.
 118         (insert_sprbat, insert_sprg): Use unsigned comparisions.
 119         (powerpc_operands <OIMM>): Set shift count rather than using
 120         PPC_OPSHIFT_INV.
 121         <SE_SDH, SE_SDW>: Likewise.  Don't use insert/extract functions.
 122
 123 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
 126         vpbroadcast{d,q} with GPR operand.
 127
 128 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 129
 130         * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
 131         * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
 132         cases up one level in the hierarchy.
 133
 134 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 135
 136         * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
 137         MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
 138         (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
 139         into MOD_VEX_0F93_P_3_LEN_0.
 140         (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
 141         operand cases up one level in the hierarchy.
 142
 143 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
 146         VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
 147         EVEX_W_0F3A22_P_2): Delete.
 148         (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
 149         entries up one level in the hierarchy.
 150         (OP_E_memory): Handle dq_mode when determining Disp8 shift
 151         value.
 152         * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
 153         entries up one level in the hierarchy.
 154         * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
 155         VexWIG for AVX flavors.
 156         * i386-tbl.h: Re-generate.
 157
 158 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 159
 160         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
 161         vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
 162         vcvtusi2ss, kmovd): Drop VexW=1.
 163         * i386-tbl.h: Re-generate.
 164
 165 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 166
 167         * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
 168         EVex512, EVexLIG, EVexDYN): New.
 169         (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
 170         insns): Use Vex128 instead of Vex=3 (aka VexLIG).
 171         (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
 172         of EVex=4 (aka EVexLIG).
 173         * i386-tbl.h: Re-generate.
 174
 175 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 176
 177         * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
 178         (vpmaxub): Re-order attributes on AVX512BW flavor.
 179         * i386-tbl.h: Re-generate.
 180
 181 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
 184         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
 185         Vex=1 on AVX / AVX2 flavors.
 186         (vpmaxub): Re-order attributes on AVX512BW flavor.
 187         * i386-tbl.h: Re-generate.
 188
 189 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-opc.tbl (VexW0, VexW1): New.
 192         (vphadd*, vphsub*): Use VexW0 on XOP variants.
 193         * i386-tbl.h: Re-generate.
 194
 195 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
 196
 197         * s12z-dis.c (decode_possible_symbol): Add fallback case.
 198         (rel_15_7): Likewise.
 199
 200 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
 201
 202         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
 203         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
 204         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
 205
 206 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
 207
 208         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
 209         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
 210
 211 2018-10-10  Jan Beulich  <jbeulich@suse.com>
 212
 213         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
 214         Size64. Add Size.
 215         * i386-opc.h (Size16, Size32, Size64): Delete.
 216         (Size): New.
 217         (SIZE16, SIZE32, SIZE64): Define.
 218         (struct i386_opcode_modifier): Drop size16, size32, and size64.
 219         Add size.
 220         * i386-opc.tbl (Size16, Size32, Size64): Define.
 221         * i386-tbl.h: Re-generate.
 222
 223 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 224
 225         * aarch64-opc.c (operand_general_constraint_met_p): Add
 226         SSBS in the check for one-bit immediate.
 227         (aarch64_sys_regs): New entry for SSBS.
 228         (aarch64_sys_reg_supported_p): New check for above.
 229         (aarch64_pstatefields): New entry for SSBS.
 230         (aarch64_pstatefield_supported_p): New check for above.
 231
 232 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 233
 234         * aarch64-opc.c (aarch64_sys_regs): New entries for
 235         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
 236         (aarch64_sys_reg_supported_p): New checks for above.
 237
 238 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 239
 240         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
 241         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
 242         with the hint immediate.
 243         * aarch64-opc.c (aarch64_hint_options): New entries for
 244         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
 245         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
 246         while checking for HINT_OPD_F_NOPRINT flag.
 247         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
 248         extract value.
 249         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
 250         (aarch64_opcode_table): Add entry for BTI.
 251         (AARCH64_OPERANDS): Add new description for BTI targets.
 252         * aarch64-asm-2.c: Regenerate.
 253         * aarch64-dis-2.c: Regenerate.
 254         * aarch64-opc-2.c: Regenerate.
 255
 256 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 257
 258         * aarch64-opc.c (aarch64_sys_regs): New entries for
 259         rndr and rndrrs.
 260         (aarch64_sys_reg_supported_p): New check for above.
 261
 262 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 263
 264         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
 265         (aarch64_sys_ins_reg_supported_p): New check for above.
 266
 267 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 268
 269         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
 270         AARCH64_OPND_SYSREG_SR.
 271         * aarch64-opc.c (aarch64_print_operand): Likewise.
 272         (aarch64_sys_regs_sr): Define table.
 273         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
 274         AARCH64_FEATURE_PREDRES.
 275         * aarch64-tbl.h (aarch64_feature_predres): New.
 276         (PREDRES, PREDRES_INSN): New.
 277         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
 278         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
 279         * aarch64-asm-2.c: Regenerate.
 280         * aarch64-dis-2.c: Regenerate.
 281         * aarch64-opc-2.c: Regenerate.
 282
 283 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 284
 285         * aarch64-tbl.h (aarch64_feature_sb): New.
 286         (SB, SB_INSN): New.
 287         (aarch64_opcode_table): Add entry for sb.
 288         * aarch64-asm-2.c: Regenerate.
 289         * aarch64-dis-2.c: Regenerate.
 290         * aarch64-opc-2.c: Regenerate.
 291
 292 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 293
 294         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 295         (aarch64_feature_frintts): New.
 296         (FLAGMANIP, FRINTTS): New.
 297         (aarch64_opcode_table): Add entries for xaflag, axflag
 298         and frint[32,64][x,z] instructions.
 299         * aarch64-asm-2.c: Regenerate.
 300         * aarch64-dis-2.c: Regenerate.
 301         * aarch64-opc-2.c: Regenerate.
 302
 303 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 304
 305         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 306         (ARMV8_5, V8_5_INSN): New.
 307
 308 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 309
 310         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 311
 312 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 313
 314         * i386-dis.c (rm_table): Add enclv.
 315         * i386-opc.tbl: Add enclv.
 316         * i386-tbl.h: Regenerated.
 317
 318 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 319
 320         * arm-dis.c (arm_opcodes): Add sb.
 321         (thumb32_opcodes): Likewise.
 322
 323 2018-10-05  Richard Henderson  <rth@twiddle.net>
 324             Stafford Horne  <shorne@gmail.com>
 325
 326         * or1k-desc.c: Regenerate.
 327         * or1k-desc.h: Regenerate.
 328         * or1k-opc.c: Regenerate.
 329         * or1k-opc.h: Regenerate.
 330         * or1k-opinst.c: Regenerate.
 331
 332 2018-10-05  Richard Henderson  <rth@twiddle.net>
 333
 334         * or1k-asm.c: Regenerated.
 335         * or1k-desc.c: Regenerated.
 336         * or1k-desc.h: Regenerated.
 337         * or1k-dis.c: Regenerated.
 338         * or1k-ibld.c: Regenerated.
 339         * or1k-opc.c: Regenerated.
 340         * or1k-opc.h: Regenerated.
 341         * or1k-opinst.c: Regenerated.
 342
 343 2018-10-05  Richard Henderson  <rth@twiddle.net>
 344
 345         * or1k-asm.c: Regenerate.
 346
 347 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 348
 349         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 350         * aarch64-dis.c (print_operands): Refactor to take notes.
 351         (print_verifier_notes): New.
 352         (print_aarch64_insn): Apply constraint verifier.
 353         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 354         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 355
 356 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 357
 358         * aarch64-opc.c (init_insn_block): New.
 359         (verify_constraints, aarch64_is_destructive_by_operands): New.
 360         * aarch64-opc.h (verify_constraints): New.
 361
 362 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 363
 364         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 365         * aarch64-opc.c (verify_ldpsw): Update arguments.
 366
 367 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 368
 369         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 370         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 371
 372 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 373
 374         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 375         * aarch64-dis.c (insn_sequence): New.
 376
 377 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 378
 379         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 380         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 381         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 382         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 383         constraints.
 384         (_SVE_INSNC): New.
 385         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 386         constraints.
 387         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 388         F_SCAN flags.
 389         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 390         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 391         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 392         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 393         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 394         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 395         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 396
 397 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 398
 399         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 400
 401 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 402
 403         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 404         are used when extracting signed fields and converting them to
 405         potentially 64-bit types.
 406
 407 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 408
 409         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 410         * Makefile.in: Re-generate.
 411         * aclocal.m4: Re-generate.
 412         * configure: Re-generate.
 413         * configure.ac: Remove check for -Wno-missing-field-initializers.
 414         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 415         (csky_v2_opcodes): Likewise.
 416
 417 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 418
 419         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 420
 421 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 422
 423         * nds32-asm.c (operand_fields): Remove the unused fields.
 424         (nds32_opcodes): Remove the unused instructions.
 425         * nds32-dis.c (nds32_ex9_info): Removed.
 426         (nds32_parse_opcode): Updated.
 427         (print_insn_nds32): Likewise.
 428         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 429         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 430         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 431         build_opcode_hash_table): New functions.
 432         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 433         nds32_opcode_table): New.
 434         (hw_ktabs): Declare it to a pointer rather than an array.
 435         (build_hash_table): Removed.
 436         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 437         SYN_ROPT and upadte HW_GPR and HW_INT.
 438         * nds32-dis.c (keywords): Remove const.
 439         (match_field): New function.
 440         (nds32_parse_opcode): Updated.
 441         * disassemble.c (disassemble_init_for_target):
 442         Add disassemble_init_nds32.
 443         * nds32-dis.c (eum map_type): New.
 444         (nds32_private_data): Likewise.
 445         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 446         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 447         (print_insn_nds32): Updated.
 448         * nds32-asm.c (parse_aext_reg): Add new parameter.
 449         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 450         are allowed to use.
 451         All callers changed.
 452         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 453         (operand_fields): Add new fields.
 454         (nds32_opcodes): Add new instructions.
 455         (keyword_aridxi_mx): New keyword.
 456         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 457         and NASM_ATTR_ZOL.
 458         (ALU2_1, ALU2_2, ALU2_3): New macros.
 459         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 460
 461 2018-09-17  Kito Cheng  <kito@andestech.com>
 462
 463         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 464
 465 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 466
 467         PR gas/23670
 468         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 469         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 470         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 471         (EVEX_LEN_0F7E_P_1): Likewise.
 472         (EVEX_LEN_0F7E_P_2): Likewise.
 473         (EVEX_LEN_0FD6_P_2): Likewise.
 474         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 475         (EVEX_LEN_TABLE): Likewise.
 476         (EVEX_LEN_0F6E_P_2): New enum.
 477         (EVEX_LEN_0F7E_P_1): Likewise.
 478         (EVEX_LEN_0F7E_P_2): Likewise.
 479         (EVEX_LEN_0FD6_P_2): Likewise.
 480         (evex_len_table): New.
 481         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 482         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 483         * i386-tbl.h: Regenerated.
 484
 485 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 486
 487         PR gas/23665
 488         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 489         VEX_LEN_0F7E_P_2 entries.
 490         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 491         * i386-tbl.h: Regenerated.
 492
 493 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 494
 495         * i386-dis.c (VZERO_Fixup): Removed.
 496         (VZERO): Likewise.
 497         (VEX_LEN_0F10_P_1): Likewise.
 498         (VEX_LEN_0F10_P_3): Likewise.
 499         (VEX_LEN_0F11_P_1): Likewise.
 500         (VEX_LEN_0F11_P_3): Likewise.
 501         (VEX_LEN_0F2E_P_0): Likewise.
 502         (VEX_LEN_0F2E_P_2): Likewise.
 503         (VEX_LEN_0F2F_P_0): Likewise.
 504         (VEX_LEN_0F2F_P_2): Likewise.
 505         (VEX_LEN_0F51_P_1): Likewise.
 506         (VEX_LEN_0F51_P_3): Likewise.
 507         (VEX_LEN_0F52_P_1): Likewise.
 508         (VEX_LEN_0F53_P_1): Likewise.
 509         (VEX_LEN_0F58_P_1): Likewise.
 510         (VEX_LEN_0F58_P_3): Likewise.
 511         (VEX_LEN_0F59_P_1): Likewise.
 512         (VEX_LEN_0F59_P_3): Likewise.
 513         (VEX_LEN_0F5A_P_1): Likewise.
 514         (VEX_LEN_0F5A_P_3): Likewise.
 515         (VEX_LEN_0F5C_P_1): Likewise.
 516         (VEX_LEN_0F5C_P_3): Likewise.
 517         (VEX_LEN_0F5D_P_1): Likewise.
 518         (VEX_LEN_0F5D_P_3): Likewise.
 519         (VEX_LEN_0F5E_P_1): Likewise.
 520         (VEX_LEN_0F5E_P_3): Likewise.
 521         (VEX_LEN_0F5F_P_1): Likewise.
 522         (VEX_LEN_0F5F_P_3): Likewise.
 523         (VEX_LEN_0FC2_P_1): Likewise.
 524         (VEX_LEN_0FC2_P_3): Likewise.
 525         (VEX_LEN_0F3A0A_P_2): Likewise.
 526         (VEX_LEN_0F3A0B_P_2): Likewise.
 527         (VEX_W_0F10_P_0): Likewise.
 528         (VEX_W_0F10_P_1): Likewise.
 529         (VEX_W_0F10_P_2): Likewise.
 530         (VEX_W_0F10_P_3): Likewise.
 531         (VEX_W_0F11_P_0): Likewise.
 532         (VEX_W_0F11_P_1): Likewise.
 533         (VEX_W_0F11_P_2): Likewise.
 534         (VEX_W_0F11_P_3): Likewise.
 535         (VEX_W_0F12_P_0_M_0): Likewise.
 536         (VEX_W_0F12_P_0_M_1): Likewise.
 537         (VEX_W_0F12_P_1): Likewise.
 538         (VEX_W_0F12_P_2): Likewise.
 539         (VEX_W_0F12_P_3): Likewise.
 540         (VEX_W_0F13_M_0): Likewise.
 541         (VEX_W_0F14): Likewise.
 542         (VEX_W_0F15): Likewise.
 543         (VEX_W_0F16_P_0_M_0): Likewise.
 544         (VEX_W_0F16_P_0_M_1): Likewise.
 545         (VEX_W_0F16_P_1): Likewise.
 546         (VEX_W_0F16_P_2): Likewise.
 547         (VEX_W_0F17_M_0): Likewise.
 548         (VEX_W_0F28): Likewise.
 549         (VEX_W_0F29): Likewise.
 550         (VEX_W_0F2B_M_0): Likewise.
 551         (VEX_W_0F2E_P_0): Likewise.
 552         (VEX_W_0F2E_P_2): Likewise.
 553         (VEX_W_0F2F_P_0): Likewise.
 554         (VEX_W_0F2F_P_2): Likewise.
 555         (VEX_W_0F50_M_0): Likewise.
 556         (VEX_W_0F51_P_0): Likewise.
 557         (VEX_W_0F51_P_1): Likewise.
 558         (VEX_W_0F51_P_2): Likewise.
 559         (VEX_W_0F51_P_3): Likewise.
 560         (VEX_W_0F52_P_0): Likewise.
 561         (VEX_W_0F52_P_1): Likewise.
 562         (VEX_W_0F53_P_0): Likewise.
 563         (VEX_W_0F53_P_1): Likewise.
 564         (VEX_W_0F58_P_0): Likewise.
 565         (VEX_W_0F58_P_1): Likewise.
 566         (VEX_W_0F58_P_2): Likewise.
 567         (VEX_W_0F58_P_3): Likewise.
 568         (VEX_W_0F59_P_0): Likewise.
 569         (VEX_W_0F59_P_1): Likewise.
 570         (VEX_W_0F59_P_2): Likewise.
 571         (VEX_W_0F59_P_3): Likewise.
 572         (VEX_W_0F5A_P_0): Likewise.
 573         (VEX_W_0F5A_P_1): Likewise.
 574         (VEX_W_0F5A_P_3): Likewise.
 575         (VEX_W_0F5B_P_0): Likewise.
 576         (VEX_W_0F5B_P_1): Likewise.
 577         (VEX_W_0F5B_P_2): Likewise.
 578         (VEX_W_0F5C_P_0): Likewise.
 579         (VEX_W_0F5C_P_1): Likewise.
 580         (VEX_W_0F5C_P_2): Likewise.
 581         (VEX_W_0F5C_P_3): Likewise.
 582         (VEX_W_0F5D_P_0): Likewise.
 583         (VEX_W_0F5D_P_1): Likewise.
 584         (VEX_W_0F5D_P_2): Likewise.
 585         (VEX_W_0F5D_P_3): Likewise.
 586         (VEX_W_0F5E_P_0): Likewise.
 587         (VEX_W_0F5E_P_1): Likewise.
 588         (VEX_W_0F5E_P_2): Likewise.
 589         (VEX_W_0F5E_P_3): Likewise.
 590         (VEX_W_0F5F_P_0): Likewise.
 591         (VEX_W_0F5F_P_1): Likewise.
 592         (VEX_W_0F5F_P_2): Likewise.
 593         (VEX_W_0F5F_P_3): Likewise.
 594         (VEX_W_0F60_P_2): Likewise.
 595         (VEX_W_0F61_P_2): Likewise.
 596         (VEX_W_0F62_P_2): Likewise.
 597         (VEX_W_0F63_P_2): Likewise.
 598         (VEX_W_0F64_P_2): Likewise.
 599         (VEX_W_0F65_P_2): Likewise.
 600         (VEX_W_0F66_P_2): Likewise.
 601         (VEX_W_0F67_P_2): Likewise.
 602         (VEX_W_0F68_P_2): Likewise.
 603         (VEX_W_0F69_P_2): Likewise.
 604         (VEX_W_0F6A_P_2): Likewise.
 605         (VEX_W_0F6B_P_2): Likewise.
 606         (VEX_W_0F6C_P_2): Likewise.
 607         (VEX_W_0F6D_P_2): Likewise.
 608         (VEX_W_0F6F_P_1): Likewise.
 609         (VEX_W_0F6F_P_2): Likewise.
 610         (VEX_W_0F70_P_1): Likewise.
 611         (VEX_W_0F70_P_2): Likewise.
 612         (VEX_W_0F70_P_3): Likewise.
 613         (VEX_W_0F71_R_2_P_2): Likewise.
 614         (VEX_W_0F71_R_4_P_2): Likewise.
 615         (VEX_W_0F71_R_6_P_2): Likewise.
 616         (VEX_W_0F72_R_2_P_2): Likewise.
 617         (VEX_W_0F72_R_4_P_2): Likewise.
 618         (VEX_W_0F72_R_6_P_2): Likewise.
 619         (VEX_W_0F73_R_2_P_2): Likewise.
 620         (VEX_W_0F73_R_3_P_2): Likewise.
 621         (VEX_W_0F73_R_6_P_2): Likewise.
 622         (VEX_W_0F73_R_7_P_2): Likewise.
 623         (VEX_W_0F74_P_2): Likewise.
 624         (VEX_W_0F75_P_2): Likewise.
 625         (VEX_W_0F76_P_2): Likewise.
 626         (VEX_W_0F77_P_0): Likewise.
 627         (VEX_W_0F7C_P_2): Likewise.
 628         (VEX_W_0F7C_P_3): Likewise.
 629         (VEX_W_0F7D_P_2): Likewise.
 630         (VEX_W_0F7D_P_3): Likewise.
 631         (VEX_W_0F7E_P_1): Likewise.
 632         (VEX_W_0F7F_P_1): Likewise.
 633         (VEX_W_0F7F_P_2): Likewise.
 634         (VEX_W_0FAE_R_2_M_0): Likewise.
 635         (VEX_W_0FAE_R_3_M_0): Likewise.
 636         (VEX_W_0FC2_P_0): Likewise.
 637         (VEX_W_0FC2_P_1): Likewise.
 638         (VEX_W_0FC2_P_2): Likewise.
 639         (VEX_W_0FC2_P_3): Likewise.
 640         (VEX_W_0FD0_P_2): Likewise.
 641         (VEX_W_0FD0_P_3): Likewise.
 642         (VEX_W_0FD1_P_2): Likewise.
 643         (VEX_W_0FD2_P_2): Likewise.
 644         (VEX_W_0FD3_P_2): Likewise.
 645         (VEX_W_0FD4_P_2): Likewise.
 646         (VEX_W_0FD5_P_2): Likewise.
 647         (VEX_W_0FD6_P_2): Likewise.
 648         (VEX_W_0FD7_P_2_M_1): Likewise.
 649         (VEX_W_0FD8_P_2): Likewise.
 650         (VEX_W_0FD9_P_2): Likewise.
 651         (VEX_W_0FDA_P_2): Likewise.
 652         (VEX_W_0FDB_P_2): Likewise.
 653         (VEX_W_0FDC_P_2): Likewise.
 654         (VEX_W_0FDD_P_2): Likewise.
 655         (VEX_W_0FDE_P_2): Likewise.
 656         (VEX_W_0FDF_P_2): Likewise.
 657         (VEX_W_0FE0_P_2): Likewise.
 658         (VEX_W_0FE1_P_2): Likewise.
 659         (VEX_W_0FE2_P_2): Likewise.
 660         (VEX_W_0FE3_P_2): Likewise.
 661         (VEX_W_0FE4_P_2): Likewise.
 662         (VEX_W_0FE5_P_2): Likewise.
 663         (VEX_W_0FE6_P_1): Likewise.
 664         (VEX_W_0FE6_P_2): Likewise.
 665         (VEX_W_0FE6_P_3): Likewise.
 666         (VEX_W_0FE7_P_2_M_0): Likewise.
 667         (VEX_W_0FE8_P_2): Likewise.
 668         (VEX_W_0FE9_P_2): Likewise.
 669         (VEX_W_0FEA_P_2): Likewise.
 670         (VEX_W_0FEB_P_2): Likewise.
 671         (VEX_W_0FEC_P_2): Likewise.
 672         (VEX_W_0FED_P_2): Likewise.
 673         (VEX_W_0FEE_P_2): Likewise.
 674         (VEX_W_0FEF_P_2): Likewise.
 675         (VEX_W_0FF0_P_3_M_0): Likewise.
 676         (VEX_W_0FF1_P_2): Likewise.
 677         (VEX_W_0FF2_P_2): Likewise.
 678         (VEX_W_0FF3_P_2): Likewise.
 679         (VEX_W_0FF4_P_2): Likewise.
 680         (VEX_W_0FF5_P_2): Likewise.
 681         (VEX_W_0FF6_P_2): Likewise.
 682         (VEX_W_0FF7_P_2): Likewise.
 683         (VEX_W_0FF8_P_2): Likewise.
 684         (VEX_W_0FF9_P_2): Likewise.
 685         (VEX_W_0FFA_P_2): Likewise.
 686         (VEX_W_0FFB_P_2): Likewise.
 687         (VEX_W_0FFC_P_2): Likewise.
 688         (VEX_W_0FFD_P_2): Likewise.
 689         (VEX_W_0FFE_P_2): Likewise.
 690         (VEX_W_0F3800_P_2): Likewise.
 691         (VEX_W_0F3801_P_2): Likewise.
 692         (VEX_W_0F3802_P_2): Likewise.
 693         (VEX_W_0F3803_P_2): Likewise.
 694         (VEX_W_0F3804_P_2): Likewise.
 695         (VEX_W_0F3805_P_2): Likewise.
 696         (VEX_W_0F3806_P_2): Likewise.
 697         (VEX_W_0F3807_P_2): Likewise.
 698         (VEX_W_0F3808_P_2): Likewise.
 699         (VEX_W_0F3809_P_2): Likewise.
 700         (VEX_W_0F380A_P_2): Likewise.
 701         (VEX_W_0F380B_P_2): Likewise.
 702         (VEX_W_0F3817_P_2): Likewise.
 703         (VEX_W_0F381C_P_2): Likewise.
 704         (VEX_W_0F381D_P_2): Likewise.
 705         (VEX_W_0F381E_P_2): Likewise.
 706         (VEX_W_0F3820_P_2): Likewise.
 707         (VEX_W_0F3821_P_2): Likewise.
 708         (VEX_W_0F3822_P_2): Likewise.
 709         (VEX_W_0F3823_P_2): Likewise.
 710         (VEX_W_0F3824_P_2): Likewise.
 711         (VEX_W_0F3825_P_2): Likewise.
 712         (VEX_W_0F3828_P_2): Likewise.
 713         (VEX_W_0F3829_P_2): Likewise.
 714         (VEX_W_0F382A_P_2_M_0): Likewise.
 715         (VEX_W_0F382B_P_2): Likewise.
 716         (VEX_W_0F3830_P_2): Likewise.
 717         (VEX_W_0F3831_P_2): Likewise.
 718         (VEX_W_0F3832_P_2): Likewise.
 719         (VEX_W_0F3833_P_2): Likewise.
 720         (VEX_W_0F3834_P_2): Likewise.
 721         (VEX_W_0F3835_P_2): Likewise.
 722         (VEX_W_0F3837_P_2): Likewise.
 723         (VEX_W_0F3838_P_2): Likewise.
 724         (VEX_W_0F3839_P_2): Likewise.
 725         (VEX_W_0F383A_P_2): Likewise.
 726         (VEX_W_0F383B_P_2): Likewise.
 727         (VEX_W_0F383C_P_2): Likewise.
 728         (VEX_W_0F383D_P_2): Likewise.
 729         (VEX_W_0F383E_P_2): Likewise.
 730         (VEX_W_0F383F_P_2): Likewise.
 731         (VEX_W_0F3840_P_2): Likewise.
 732         (VEX_W_0F3841_P_2): Likewise.
 733         (VEX_W_0F38DB_P_2): Likewise.
 734         (VEX_W_0F3A08_P_2): Likewise.
 735         (VEX_W_0F3A09_P_2): Likewise.
 736         (VEX_W_0F3A0A_P_2): Likewise.
 737         (VEX_W_0F3A0B_P_2): Likewise.
 738         (VEX_W_0F3A0C_P_2): Likewise.
 739         (VEX_W_0F3A0D_P_2): Likewise.
 740         (VEX_W_0F3A0E_P_2): Likewise.
 741         (VEX_W_0F3A0F_P_2): Likewise.
 742         (VEX_W_0F3A21_P_2): Likewise.
 743         (VEX_W_0F3A40_P_2): Likewise.
 744         (VEX_W_0F3A41_P_2): Likewise.
 745         (VEX_W_0F3A42_P_2): Likewise.
 746         (VEX_W_0F3A62_P_2): Likewise.
 747         (VEX_W_0F3A63_P_2): Likewise.
 748         (VEX_W_0F3ADF_P_2): Likewise.
 749         (VEX_LEN_0F77_P_0): New.
 750         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 751         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 752         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 753         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 754         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 755         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 756         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 757         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 758         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 759         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 760         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 761         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 762         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 763         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 764         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 765         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 766         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 767         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 768         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 769         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 770         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 771         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 772         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 773         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 774         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 775         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 776         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 777         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 778         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 779         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 780         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 781         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 782         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 783         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 784         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 785         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 786         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 787         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 788         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 789         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 790         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 791         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 792         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 793         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 794         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 795         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 796         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 797         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 798         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 799         (vex_table): Update VEX 0F28 and 0F29 entries.
 800         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 801         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 802         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 803         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 804         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 805         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 806         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 807         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 808         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 809         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 810         VEX_LEN_0F3A0B_P_2 entries.
 811         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 812         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 813         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 814         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 815         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 816         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 817         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 818         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 819         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 820         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 821         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 822         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 823         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 824         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 825         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 826         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 827         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 828         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 829         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 830         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 831         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 832         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 833         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 834         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 835         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 836         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 837         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 838         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 839         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 840         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 841         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 842         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 843         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 844         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 845         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 846         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 847         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 848         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 849         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 850         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 851         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 852         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 853         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 854         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 855         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 856         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 857         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 858         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 859         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 860         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 861         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 862         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 863         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 864         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 865         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 866         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 867         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 868         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 869         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 870         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 871         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 872         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 873         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 874         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 875         VEX_W_0F3ADF_P_2 entries.
 876         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 877         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 878         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 879
 880 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 881
 882         * i386-opc.tbl (VexWIG): New.
 883         Replace VexW=3 with VexWIG.
 884
 885 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 886
 887         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 888         * i386-tbl.h: Regenerated.
 889
 890 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 891
 892         PR gas/23665
 893         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 894         VEX_LEN_0FD6_P_2 entries.
 895         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 896         * i386-tbl.h: Regenerated.
 897
 898 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 899
 900         PR gas/23642
 901         * i386-opc.h (VEXWIG): New.
 902         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 903         * i386-tbl.h: Regenerated.
 904
 905 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 906
 907         PR binutils/23655
 908         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 909         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 910         * i386-dis.c (EXxEVexR64): New.
 911         (evex_rounding_64_mode): Likewise.
 912         (OP_Rounding): Handle evex_rounding_64_mode.
 913
 914 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 915
 916         PR binutils/23655
 917         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 918         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 919         * i386-dis.c (Edqa): New.
 920         (dqa_mode): Likewise.
 921         (intel_operand_size): Handle dqa_mode as m_mode.
 922         (OP_E_register): Handle dqa_mode as dq_mode.
 923         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 924
 925 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 926
 927         * i386-dis.c (OP_E_memory): Reformat.
 928
 929 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 930
 931         * i386-opc.tbl (crc32): Fold byte and word forms.
 932         * i386-tbl.h: Re-generate.
 933
 934 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 935
 936         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 937         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 938         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 939         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 940         * i386-tbl.h: Regenerated.
 941
 942 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 943
 944         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 945         meaningless.
 946         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 947         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 948         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 949         * i386-tbl.h: Re-generate.
 950
 951 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 952
 953         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 954         AVX512_4VNNIW insns.
 955         * i386-tbl.h: Re-generate.
 956
 957 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 958
 959         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 960         meaningless.
 961         * i386-tbl.h: Re-generate.
 962
 963 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 964
 965         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 966         meaningless.
 967         * i386-tbl.h: Re-generate.
 968
 969 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 970
 971         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 972         meaningless.
 973         * i386-tbl.h: Re-generate.
 974
 975 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 976
 977         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 978         meaningless.
 979         * i386-tbl.h: Re-generate.
 980
 981 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 982
 983         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 984         meaningless.
 985         * i386-tbl.h: Re-generate.
 986
 987 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 990         * i386-tbl.h: Re-generate.
 991
 992 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 993
 994         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 995         * i386-tbl.h: Re-generate.
 996
 997 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 998
 999         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
1000         meaningless.
1001         * i386-tbl.h: Re-generate.
1002
1003 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1004
1005         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
1006         meaningless.
1007         * i386-tbl.h: Re-generate.
1008
1009 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1010
1011         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
1012         * i386-tbl.h: Re-generate.
1013
1014 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1015
1016         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
1017         * i386-tbl.h: Re-generate.
1018
1019 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
1022         * i386-tbl.h: Re-generate.
1023
1024 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1025
1026         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
1027         meaningless.
1028         * i386-tbl.h: Re-generate.
1029
1030 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1031
1032         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
1033         meaningless.
1034         * i386-tbl.h: Re-generate.
1035
1036 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1037
1038         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1039         meaningless.
1040         * i386-tbl.h: Re-generate.
1041
1042 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1043
1044         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1045         * i386-tbl.h: Re-generate.
1046
1047 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1048
1049         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1050         * i386-tbl.h: Re-generate.
1051
1052 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1053
1054         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1055         * i386-tbl.h: Re-generate.
1056
1057 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1058
1059         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1060         (vpbroadcastw, rdpid): Drop NoRex64.
1061         * i386-tbl.h: Re-generate.
1062
1063 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1066         store templates, adding D.
1067         * i386-tbl.h: Re-generate.
1068
1069 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1070
1071         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1072         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1073         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1074         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1075         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1076         Fold load and store templates where possible, adding D. Drop
1077         IgnoreSize where it was pointlessly present. Drop redundant
1078         *word.
1079         * i386-tbl.h: Re-generate.
1080
1081 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1082
1083         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1084         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1085         (intel_operand_size): Handle v_bndmk_mode.
1086         (OP_E_memory): Likewise. Produce (bad) when also riprel.
1087
1088 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
1089
1090         * disassemble.c (ARCH_s12z): Define if ARCH_all.
1091
1092 2018-08-31  Kito Cheng  <kito@andestech.com>
1093
1094         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1095         compressed floating point instructions.
1096
1097 2018-08-30  Kito Cheng  <kito@andestech.com>
1098
1099         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1100         riscv_opcode.xlen_requirement.
1101         * riscv-opc.c (riscv_opcodes): Update for struct change.
1102
1103 2018-08-29  Martin Aberg  <maberg@gaisler.com>
1104
1105         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1106         psr (PWRPSR) instruction.
1107
1108 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1109
1110         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1111
1112 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1113
1114         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1115
1116 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1117
1118         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1119         loongson3a as an alias of gs464 for compatibility.
1120         * mips-opc.c (mips_opcodes): Change Comments.
1121
1122 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1123
1124         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1125         option.
1126         (print_mips_disassembler_options): Document -M loongson-ext.
1127         * mips-opc.c (LEXT2): New macro.
1128         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1129
1130 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1131
1132          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1133          descriptors.
1134          (parse_mips_ase_option): Handle -M loongson-ext option.
1135          (print_mips_disassembler_options): Document -M loongson-ext.
1136          * mips-opc.c (IL3A): Delete.
1137          * mips-opc.c (LEXT): New macro.
1138          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1139          instructions.
1140
1141 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1142
1143         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1144         descriptors.
1145         (parse_mips_ase_option): Handle -M loongson-cam option.
1146         (print_mips_disassembler_options): Document -M loongson-cam.
1147         * mips-opc.c (LCAM): New macro.
1148         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1149         instructions.
1150
1151 2018-08-21  Alan Modra  <amodra@gmail.com>
1152
1153         * ppc-dis.c (operand_value_powerpc): Init "invalid".
1154         (skip_optional_operands): Count optional operands, and update
1155         ppc_optional_operand_value call.
1156         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1157         (extract_vlensi): Likewise.
1158         (extract_fxm): Return default value for missing optional operand.
1159         (extract_ls, extract_raq, extract_tbr): Likewise.
1160         (insert_sxl, extract_sxl): New functions.
1161         (insert_esync, extract_esync): Remove Power9 handling and simplify.
1162         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1163         flag and extra entry.
1164         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1165         extract_sxl.
1166
1167 2018-08-20  Alan Modra  <amodra@gmail.com>
1168
1169         * sh-opc.h (MASK): Simplify.
1170
1171 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1172
1173         * s12z-dis.c (bm_decode): Deal with cases where the mode is
1174         BM_RESERVED0 or BM_RESERVED1
1175         (bm_rel_decode, bm_n_bytes): Ditto.
1176
1177 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1178
1179         * s12z.h: Delete.
1180
1181 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1182
1183         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1184         address with the addr32 prefix and without base nor index
1185         registers.
1186
1187 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1188
1189         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1190         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1191         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1192         (cpu_flags): Add CpuCMOV and CpuFXSR.
1193         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1194         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1195         * i386-init.h: Regenerated.
1196         * i386-tbl.h: Likewise.
1197
1198 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1199
1200         * arc-regs.h: Update auxiliary registers.
1201
1202 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1203
1204         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1205         (RegIP, RegIZ): Define.
1206         * i386-reg.tbl: Adjust comments.
1207         (rip): Use Qword instead of BaseIndex. Use RegIP.
1208         (eip): Use Dword instead of BaseIndex. Use RegIP.
1209         (riz): Add Qword. Use RegIZ.
1210         (eiz): Add Dword. Use RegIZ.
1211         * i386-tbl.h: Re-generate.
1212
1213 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1214
1215         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1216         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1217         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1218         * i386-tbl.h: Re-generate.
1219
1220 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1221
1222         * i386-gen.c (operand_types): Remove Mem field.
1223         * i386-opc.h (union i386_operand_type): Remove mem field.
1224         * i386-init.h, i386-tbl.h: Re-generate.
1225
1226 2018-08-01  Alan Modra  <amodra@gmail.com>
1227
1228         * po/POTFILES.in: Regenerate.
1229
1230 2018-07-31  Nick Clifton  <nickc@redhat.com>
1231
1232         * po/sv.po: Updated Swedish translation.
1233
1234 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1235
1236         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1237         * i386-init.h, i386-tbl.h: Re-generate.
1238
1239 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1240
1241         * i386-opc.h (ZEROING_MASKING) Rename to ...
1242         (DYNAMIC_MASKING): ... this. Adjust comment.
1243         * i386-opc.tbl (MaskingMorZ): Define.
1244         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1245         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1246         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1247         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1248         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1249         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1250         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1251         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1252         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1253
1254 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1255
1256         * i386-opc.tbl: Use element rather than vector size for AVX512*
1257         scatter/gather insns.
1258         * i386-tbl.h: Re-generate.
1259
1260 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1261
1262         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1263         (cpu_flags): Drop CpuVREX.
1264         * i386-opc.h (CpuVREX): Delete.
1265         (union i386_cpu_flags): Remove cpuvrex.
1266         * i386-init.h, i386-tbl.h: Re-generate.
1267
1268 2018-07-30  Jim Wilson  <jimw@sifive.com>
1269
1270         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1271         fields.
1272         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1273
1274 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1275
1276         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1277         * Makefile.in: Regenerated.
1278         * configure.ac: Add C-SKY.
1279         * configure: Regenerated.
1280         * csky-dis.c: New file.
1281         * csky-opc.h: New file.
1282         * disassemble.c (ARCH_csky): Define.
1283         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1284         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1285
1286 2018-07-27  Alan Modra  <amodra@gmail.com>
1287
1288         * ppc-opc.c (insert_sprbat): Correct function parameter and
1289         return type.
1290         (extract_sprbat): Likewise, variable too.
1291
1292 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1293             Alan Modra  <amodra@gmail.com>
1294
1295         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1296         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1297         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1298         support disjointed BAT.
1299         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1300         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1301         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1302
1303 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1304             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1305
1306         * i386-gen.c (adjust_broadcast_modifier): New function.
1307         (process_i386_opcode_modifier): Add an argument for operands.
1308         Adjust the Broadcast value based on operands.
1309         (output_i386_opcode): Pass operand_types to
1310         process_i386_opcode_modifier.
1311         (process_i386_opcodes): Pass NULL as operands to
1312         process_i386_opcode_modifier.
1313         * i386-opc.h (BYTE_BROADCAST): New.
1314         (WORD_BROADCAST): Likewise.
1315         (DWORD_BROADCAST): Likewise.
1316         (QWORD_BROADCAST): Likewise.
1317         (i386_opcode_modifier): Expand broadcast to 3 bits.
1318         * i386-tbl.h: Regenerated.
1319
1320 2018-07-24  Alan Modra  <amodra@gmail.com>
1321
1322         PR 23430
1323         * or1k-desc.h: Regenerate.
1324
1325 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1326
1327         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1328         vcvtusi2ss, and vcvtusi2sd.
1329         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1330         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1331         * i386-tbl.h: Re-generate.
1332
1333 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1334
1335         * arc-opc.c (extract_w6): Fix extending the sign.
1336
1337 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1338
1339         * arc-tbl.h (vewt): Allow it for ARC EM family.
1340
1341 2018-07-23  Alan Modra  <amodra@gmail.com>
1342
1343         PR 23419
1344         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1345         opcode variants for mtspr/mfspr encodings.
1346
1347 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1348             Maciej W. Rozycki  <macro@mips.com>
1349
1350         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1351         loongson3a descriptors.
1352         (parse_mips_ase_option): Handle -M loongson-mmi option.
1353         (print_mips_disassembler_options): Document -M loongson-mmi.
1354         * mips-opc.c (LMMI): New macro.
1355         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1356         instructions.
1357
1358 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1359
1360         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1361         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1362         IgnoreSize and [XYZ]MMword where applicable.
1363         * i386-tbl.h: Re-generate.
1364
1365 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1366
1367         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1368         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1369         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1370         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1371         * i386-tbl.h: Re-generate.
1372
1373 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1374
1375         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1376         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1377         VPCLMULQDQ templates into their respective AVX512VL counterparts
1378         where possible, using Disp8ShiftVL and CheckRegSize instead of
1379         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1380         * i386-tbl.h: Re-generate.
1381
1382 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1383
1384         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1385         AVX512VL counterparts where possible, using Disp8ShiftVL and
1386         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1387         IgnoreSize) as appropriate.
1388         * i386-tbl.h: Re-generate.
1389
1390 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1391
1392         * i386-opc.tbl: Fold AVX512BW templates into their respective
1393         AVX512VL counterparts where possible, using Disp8ShiftVL and
1394         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1395         IgnoreSize) as appropriate.
1396         * i386-tbl.h: Re-generate.
1397
1398 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1399
1400         * i386-opc.tbl: Fold AVX512CD templates into their respective
1401         AVX512VL counterparts where possible, using Disp8ShiftVL and
1402         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1403         IgnoreSize) as appropriate.
1404         * i386-tbl.h: Re-generate.
1405
1406 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1407
1408         * i386-opc.h (DISP8_SHIFT_VL): New.
1409         * i386-opc.tbl (Disp8ShiftVL):  Define.
1410         (various): Fold AVX512VL templates into their respective
1411         AVX512F counterparts where possible, using Disp8ShiftVL and
1412         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1413         IgnoreSize) as appropriate.
1414         * i386-tbl.h: Re-generate.
1415
1416 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1417
1418         * Makefile.am: Change dependencies and rule for
1419         $(srcdir)/i386-init.h.
1420         * Makefile.in: Re-generate.
1421         * i386-gen.c (process_i386_opcodes): New local variable
1422         "marker". Drop opening of input file. Recognize marker and line
1423         number directives.
1424         * i386-opc.tbl (OPCODE_I386_H): Define.
1425         (i386-opc.h): Include it.
1426         (None): Undefine.
1427
1428 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1429
1430         PR gas/23418
1431         * i386-opc.h (Byte): Update comments.
1432         (Word): Likewise.
1433         (Dword): Likewise.
1434         (Fword): Likewise.
1435         (Qword): Likewise.
1436         (Tbyte): Likewise.
1437         (Xmmword): Likewise.
1438         (Ymmword): Likewise.
1439         (Zmmword): Likewise.
1440         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1441         vcvttps2uqq.
1442         * i386-tbl.h: Regenerated.
1443
1444 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1445
1446         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1447         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1448         * aarch64-asm-2.c: Regenerate.
1449         * aarch64-dis-2.c: Regenerate.
1450         * aarch64-opc-2.c: Regenerate.
1451
1452 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1453
1454         PR binutils/23192
1455         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1456         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1457         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1458         sqdmulh, sqrdmulh): Use Em16.
1459
1460 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1461
1462         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1463         csdb together with them.
1464         (thumb32_opcodes): Likewise.
1465
1466 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1467
1468         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1469         requiring 32-bit registers as operands 2 and 3. Improve
1470         comments.
1471         (mwait, mwaitx): Fold templates. Improve comments.
1472         OPERAND_TYPE_INOUTPORTREG.
1473         * i386-tbl.h: Re-generate.
1474
1475 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1476
1477         * i386-gen.c (operand_type_init): Remove
1478         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1479         OPERAND_TYPE_INOUTPORTREG.
1480         * i386-init.h: Re-generate.
1481
1482 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1483
1484         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1485         (wrssq, wrussq): Add Qword.
1486         * i386-tbl.h: Re-generate.
1487
1488 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1489
1490         * i386-opc.h: Rename OTMax to OTNum.
1491         (OTNumOfUints): Adjust calculation.
1492         (OTUnused): Directly alias to OTNum.
1493
1494 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1495
1496         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1497         `reg_xys'.
1498         (lea_reg_xys): Likewise.
1499         (print_insn_loop_primitive): Rename `reg' local variable to
1500         `reg_dxy'.
1501
1502 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1503
1504         PR binutils/23242
1505         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1506
1507 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1508
1509         PR binutils/23369
1510         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1511         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1512
1513 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1514
1515         PR tdep/8282
1516         * mips-dis.c (mips_option_arg_t): New enumeration.
1517         (mips_options): New variable.
1518         (disassembler_options_mips): New function.
1519         (print_mips_disassembler_options): Reimplement in terms of
1520         `disassembler_options_mips'.
1521         * arm-dis.c (disassembler_options_arm): Adapt to using the
1522         `disasm_options_and_args_t' structure.
1523         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1524         * s390-dis.c (disassembler_options_s390): Likewise.
1525
1526 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1527
1528         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1529         expected result.
1530         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1531         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1532         * testsuite/ld-arm/tls-longplt.d: Likewise.
1533
1534 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1535
1536         PR binutils/23192
1537         * aarch64-asm-2.c: Regenerate.
1538         * aarch64-dis-2.c: Likewise.
1539         * aarch64-opc-2.c: Likewise.
1540         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1541         * aarch64-opc.c (operand_general_constraint_met_p,
1542         aarch64_print_operand): Likewise.
1543         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1544         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1545         fmlal2, fmlsl2.
1546         (AARCH64_OPERANDS): Add Em2.
1547
1548 2018-06-26  Nick Clifton  <nickc@redhat.com>
1549
1550         * po/uk.po: Updated Ukranian translation.
1551         * po/de.po: Updated German translation.
1552         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1553
1554 2018-06-26  Nick Clifton  <nickc@redhat.com>
1555
1556         * nfp-dis.c: Fix spelling mistake.
1557
1558 2018-06-24  Nick Clifton  <nickc@redhat.com>
1559
1560         * configure: Regenerate.
1561         * po/opcodes.pot: Regenerate.
1562
1563 2018-06-24  Nick Clifton  <nickc@redhat.com>
1564
1565         2.31 branch created.
1566
1567 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1568
1569         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1570         * aarch64-asm-2.c: Regenerate.
1571         * aarch64-dis-2.c: Likewise.
1572
1573 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1574
1575         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1576         `-M ginv' option description.
1577
1578 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1579
1580         PR gas/23305
1581         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1582         la and lla.
1583
1584 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1585
1586         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1587         * configure.ac: Remove AC_PREREQ.
1588         * Makefile.in: Re-generate.
1589         * aclocal.m4: Re-generate.
1590         * configure: Re-generate.
1591
1592 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1593
1594         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1595         mips64r6 descriptors.
1596         (parse_mips_ase_option): Handle -Mginv option.
1597         (print_mips_disassembler_options): Document -Mginv.
1598         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1599         (GINV): New macro.
1600         (mips_opcodes): Define ginvi and ginvt.
1601
1602 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1603             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1604
1605         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1606         * mips-opc.c (CRC, CRC64): New macros.
1607         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1608         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1609         crc32cd for CRC64.
1610
1611 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1612
1613         PR 20319
1614         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1615         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1616
1617 2018-06-06  Alan Modra  <amodra@gmail.com>
1618
1619         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1620         setjmp.  Move init for some other vars later too.
1621
1622 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1623
1624         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1625         (dis_private): Add new fields for property section tracking.
1626         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1627         (xtensa_instruction_fits): New functions.
1628         (fetch_data): Bump minimal fetch size to 4.
1629         (print_insn_xtensa): Make struct dis_private static.
1630         Load and prepare property table on section change.
1631         Don't disassemble literals. Don't disassemble instructions that
1632         cross property table boundaries.
1633
1634 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1635
1636         * configure: Regenerated.
1637
1638 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1639
1640         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1641         * i386-tbl.h: Re-generate.
1642
1643 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1644
1645         * i386-opc.tbl (sldt, str): Add NoRex64.
1646         * i386-tbl.h: Re-generate.
1647
1648 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1649
1650         * i386-opc.tbl (invpcid): Add Oword.
1651         * i386-tbl.h: Re-generate.
1652
1653 2018-06-01  Alan Modra  <amodra@gmail.com>
1654
1655         * sysdep.h (_bfd_error_handler): Don't declare.
1656         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1657         * rl78-decode.opc: Likewise.
1658         * msp430-decode.c: Regenerate.
1659         * rl78-decode.c: Regenerate.
1660
1661 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1662
1663         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1664         * i386-init.h : Regenerated.
1665
1666 2018-05-25  Alan Modra  <amodra@gmail.com>
1667
1668         * Makefile.in: Regenerate.
1669         * po/POTFILES.in: Regenerate.
1670
1671 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1672
1673         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1674         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1675         (insert_bab, extract_bab, insert_btab, extract_btab,
1676         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1677         (BAT, BBA VBA RBS XB6S): Delete macros.
1678         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1679         (BB, BD, RBX, XC6): Update for new macros.
1680         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1681         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1682         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1683         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1684
1685 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1686
1687         * Makefile.am: Add support for s12z architecture.
1688         * configure.ac: Likewise.
1689         * disassemble.c: Likewise.
1690         * disassemble.h: Likewise.
1691         * Makefile.in: Regenerate.
1692         * configure: Regenerate.
1693         * s12z-dis.c: New file.
1694         * s12z.h: New file.
1695
1696 2018-05-18  Alan Modra  <amodra@gmail.com>
1697
1698         * nfp-dis.c: Don't #include libbfd.h.
1699         (init_nfp3200_priv): Use bfd_get_section_contents.
1700         (nit_nfp6000_mecsr_sec): Likewise.
1701
1702 2018-05-17  Nick Clifton  <nickc@redhat.com>
1703
1704         * po/zh_CN.po: Updated simplified Chinese translation.
1705
1706 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1707
1708         PR binutils/23109
1709         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1710         * aarch64-dis-2.c: Regenerate.
1711
1712 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1713
1714         PR binutils/21446
1715         * aarch64-asm.c (opintl.h): Include.
1716         (aarch64_ins_sysreg): Enforce read/write constraints.
1717         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1718         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1719         (F_REG_READ, F_REG_WRITE): New.
1720         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1721         AARCH64_OPND_SYSREG.
1722         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1723         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1724         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1725         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1726         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1727         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1728         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1729         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1730         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1731         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1732         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1733         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1734         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1735         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1736         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1737         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1738         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1739
1740 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1741
1742         PR binutils/21446
1743         * aarch64-dis.c (no_notes: New.
1744         (parse_aarch64_dis_option): Support notes.
1745         (aarch64_decode_insn, print_operands): Likewise.
1746         (print_aarch64_disassembler_options): Document notes.
1747         * aarch64-opc.c (aarch64_print_operand): Support notes.
1748
1749 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1750
1751         PR binutils/21446
1752         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1753         and take error struct.
1754         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1755         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1756         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1757         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1758         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1759         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1760         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1761         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1762         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1763         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1764         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1765         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1766         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1767         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1768         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1769         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1770         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1771         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1772         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1773         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1774         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1775         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1776         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1777         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1778         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1779         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1780         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1781         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1782         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1783         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1784         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1785         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1786         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1787         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1788         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1789         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1790         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1791         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1792         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1793         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1794         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1795         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1796         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1797         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1798         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1799         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1800         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1801         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1802         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1803         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1804         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1805         (determine_disassembling_preference, aarch64_decode_insn,
1806         print_insn_aarch64_word, print_insn_data): Take errors struct.
1807         (print_insn_aarch64): Use errors.
1808         * aarch64-asm-2.c: Regenerate.
1809         * aarch64-dis-2.c: Regenerate.
1810         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1811         boolean in aarch64_insert_operan.
1812         (print_operand_extractor): Likewise.
1813         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1814
1815 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1816
1817         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1818
1819 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1820
1821         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1822
1823 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1824
1825         * cr16-opc.c (cr16_instruction): Comment typo fix.
1826         * hppa-dis.c (print_insn_hppa): Likewise.
1827
1828 2018-05-08  Jim Wilson  <jimw@sifive.com>
1829
1830         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1831         (match_c_slli64, match_srxi_as_c_srxi): New.
1832         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1833         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1834         <c.slli, c.srli, c.srai>: Use match_s_slli.
1835         <c.slli64, c.srli64, c.srai64>: New.
1836
1837 2018-05-08  Alan Modra  <amodra@gmail.com>
1838
1839         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1840         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1841         partition opcode space for index lookup.
1842
1843 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1844
1845         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1846         <insn_length>: ...with this.  Update usage.
1847         Remove duplicate call to *info->memory_error_func.
1848
1849 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1850             H.J. Lu  <hongjiu.lu@intel.com>
1851
1852         * i386-dis.c (Gva): New.
1853         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1854         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1855         (prefix_table): New instructions (see prefix above).
1856         (mod_table): New instructions (see prefix above).
1857         (OP_G): Handle va_mode.
1858         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1859         CPU_MOVDIR64B_FLAGS.
1860         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1861         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1862         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1863         * i386-opc.tbl: Add movidir{i,64b}.
1864         * i386-init.h: Regenerated.
1865         * i386-tbl.h: Likewise.
1866
1867 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1868
1869         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1870         AddrPrefixOpReg.
1871         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1872         (AddrPrefixOpReg): This.
1873         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1874         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1875
1876 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1877
1878         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1879         (vle_num_opcodes): Likewise.
1880         (spe2_num_opcodes): Likewise.
1881         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1882         initialization loop.
1883         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1884         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1885         only once.
1886
1887 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1888
1889         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1890
1891 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1892
1893         Makefile.am: Added nfp-dis.c.
1894         configure.ac: Added bfd_nfp_arch.
1895         disassemble.h: Added print_insn_nfp prototype.
1896         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1897         nfp-dis.c: New, for NFP support.
1898         po/POTFILES.in: Added nfp-dis.c to the list.
1899         Makefile.in: Regenerate.
1900         configure: Regenerate.
1901
1902 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1903
1904         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1905         templates into their base ones.
1906         * i386-tlb.h: Re-generate.
1907
1908 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1909
1910         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1911         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1912         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1913         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1914         * i386-init.h: Re-generate.
1915
1916 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1917
1918         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1919         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1920         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1921         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1922         comment.
1923         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1924         and CpuRegMask.
1925         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1926         CpuRegMask: Delete.
1927         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1928         cpuregzmm, and cpuregmask.
1929         * i386-init.h: Re-generate.
1930         * i386-tbl.h: Re-generate.
1931
1932 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1933
1934         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1935         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1936         * i386-init.h: Re-generate.
1937
1938 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1939
1940         * i386-gen.c (VexImmExt): Delete.
1941         * i386-opc.h (VexImmExt, veximmext): Delete.
1942         * i386-opc.tbl: Drop all VexImmExt uses.
1943         * i386-tlb.h: Re-generate.
1944
1945 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1946
1947         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1948         register-only forms.
1949         * i386-tlb.h: Re-generate.
1950
1951 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1952
1953         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1954
1955 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1956
1957         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1958         PREFIX_0F1C.
1959         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1960         (cpu_flags): Add CpuCLDEMOTE.
1961         * i386-init.h: Regenerate.
1962         * i386-opc.h (enum): Add CpuCLDEMOTE,
1963         (i386_cpu_flags): Add cpucldemote.
1964         * i386-opc.tbl: Add cldemote.
1965         * i386-tbl.h: Regenerate.
1966
1967 2018-04-16  Alan Modra  <amodra@gmail.com>
1968
1969         * Makefile.am: Remove sh5 and sh64 support.
1970         * configure.ac: Likewise.
1971         * disassemble.c: Likewise.
1972         * disassemble.h: Likewise.
1973         * sh-dis.c: Likewise.
1974         * sh64-dis.c: Delete.
1975         * sh64-opc.c: Delete.
1976         * sh64-opc.h: Delete.
1977         * Makefile.in: Regenerate.
1978         * configure: Regenerate.
1979         * po/POTFILES.in: Regenerate.
1980
1981 2018-04-16  Alan Modra  <amodra@gmail.com>
1982
1983         * Makefile.am: Remove w65 support.
1984         * configure.ac: Likewise.
1985         * disassemble.c: Likewise.
1986         * disassemble.h: Likewise.
1987         * w65-dis.c: Delete.
1988         * w65-opc.h: Delete.
1989         * Makefile.in: Regenerate.
1990         * configure: Regenerate.
1991         * po/POTFILES.in: Regenerate.
1992
1993 2018-04-16  Alan Modra  <amodra@gmail.com>
1994
1995         * configure.ac: Remove we32k support.
1996         * configure: Regenerate.
1997
1998 2018-04-16  Alan Modra  <amodra@gmail.com>
1999
2000         * Makefile.am: Remove m88k support.
2001         * configure.ac: Likewise.
2002         * disassemble.c: Likewise.
2003         * disassemble.h: Likewise.
2004         * m88k-dis.c: Delete.
2005         * Makefile.in: Regenerate.
2006         * configure: Regenerate.
2007         * po/POTFILES.in: Regenerate.
2008
2009 2018-04-16  Alan Modra  <amodra@gmail.com>
2010
2011         * Makefile.am: Remove i370 support.
2012         * configure.ac: Likewise.
2013         * disassemble.c: Likewise.
2014         * disassemble.h: Likewise.
2015         * i370-dis.c: Delete.
2016         * i370-opc.c: Delete.
2017         * Makefile.in: Regenerate.
2018         * configure: Regenerate.
2019         * po/POTFILES.in: Regenerate.
2020
2021 2018-04-16  Alan Modra  <amodra@gmail.com>
2022
2023         * Makefile.am: Remove h8500 support.
2024         * configure.ac: Likewise.
2025         * disassemble.c: Likewise.
2026         * disassemble.h: Likewise.
2027         * h8500-dis.c: Delete.
2028         * h8500-opc.h: Delete.
2029         * Makefile.in: Regenerate.
2030         * configure: Regenerate.
2031         * po/POTFILES.in: Regenerate.
2032
2033 2018-04-16  Alan Modra  <amodra@gmail.com>
2034
2035         * configure.ac: Remove tahoe support.
2036         * configure: Regenerate.
2037
2038 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
2039
2040         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2041         umwait.
2042         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2043         64-bit mode.
2044         * i386-tbl.h: Regenerated.
2045
2046 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2047
2048         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2049         PREFIX_MOD_1_0FAE_REG_6.
2050         (va_mode): New.
2051         (OP_E_register): Use va_mode.
2052         * i386-dis-evex.h (prefix_table):
2053         New instructions (see prefixes above).
2054         * i386-gen.c (cpu_flag_init): Add WAITPKG.
2055         (cpu_flags): Likewise.
2056         * i386-opc.h (enum): Likewise.
2057         (i386_cpu_flags): Likewise.
2058         * i386-opc.tbl: Add umonitor, umwait, tpause.
2059         * i386-init.h: Regenerate.
2060         * i386-tbl.h: Likewise.
2061
2062 2018-04-11  Alan Modra  <amodra@gmail.com>
2063
2064         * opcodes/i860-dis.c: Delete.
2065         * opcodes/i960-dis.c: Delete.
2066         * Makefile.am: Remove i860 and i960 support.
2067         * configure.ac: Likewise.
2068         * disassemble.c: Likewise.
2069         * disassemble.h: Likewise.
2070         * Makefile.in: Regenerate.
2071         * configure: Regenerate.
2072         * po/POTFILES.in: Regenerate.
2073
2074 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
2075
2076         PR binutils/23025
2077         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2078         to 0.
2079         (print_insn): Clear vex instead of vex.evex.
2080
2081 2018-04-04  Nick Clifton  <nickc@redhat.com>
2082
2083         * po/es.po: Updated Spanish translation.
2084
2085 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2086
2087         * i386-gen.c (opcode_modifiers): Delete VecESize.
2088         * i386-opc.h (VecESize): Delete.
2089         (struct i386_opcode_modifier): Delete vecesize.
2090         * i386-opc.tbl: Drop VecESize.
2091         * i386-tlb.h: Re-generate.
2092
2093 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2094
2095         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2096         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2097         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2098         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2099         * i386-tlb.h: Re-generate.
2100
2101 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2102
2103         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2104         Fold AVX512 forms
2105         * i386-tlb.h: Re-generate.
2106
2107 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2108
2109         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2110         (vex_len_table): Drop Y for vcvt*2si.
2111         (putop): Replace plain 'Y' handling by abort().
2112
2113 2018-03-28  Nick Clifton  <nickc@redhat.com>
2114
2115         PR 22988
2116         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2117         instructions with only a base address register.
2118         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2119         handle AARHC64_OPND_SVE_ADDR_R.
2120         (aarch64_print_operand): Likewise.
2121         * aarch64-asm-2.c: Regenerate.
2122         * aarch64_dis-2.c: Regenerate.
2123         * aarch64-opc-2.c: Regenerate.
2124
2125 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2126
2127         * i386-opc.tbl: Drop VecESize from register only insn forms and
2128         memory forms not allowing broadcast.
2129         * i386-tlb.h: Re-generate.
2130
2131 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2132
2133         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2134         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2135         sha256*): Drop Disp<N>.
2136
2137 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2138
2139         * i386-dis.c (EbndS, bnd_swap_mode): New.
2140         (prefix_table): Use EbndS.
2141         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2142         * i386-opc.tbl (bndmov): Move misplaced Load.
2143         * i386-tlb.h: Re-generate.
2144
2145 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2146
2147         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2148         templates allowing memory operands and folded ones for register
2149         only flavors.
2150         * i386-tlb.h: Re-generate.
2151
2152 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2153
2154         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2155         256-bit templates. Drop redundant leftover Disp<N>.
2156         * i386-tlb.h: Re-generate.
2157
2158 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
2159
2160         * riscv-opc.c (riscv_insn_types): New.
2161
2162 2018-03-13  Nick Clifton  <nickc@redhat.com>
2163
2164         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2165
2166 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2167
2168         * i386-opc.tbl: Add Optimize to clr.
2169         * i386-tbl.h: Regenerated.
2170
2171 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2172
2173         * i386-gen.c (opcode_modifiers): Remove OldGcc.
2174         * i386-opc.h (OldGcc): Removed.
2175         (i386_opcode_modifier): Remove oldgcc.
2176         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2177         instructions for old (<= 2.8.1) versions of gcc.
2178         * i386-tbl.h: Regenerated.
2179
2180 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2181
2182         * i386-opc.h (EVEXDYN): New.
2183         * i386-opc.tbl: Fold various AVX512VL templates.
2184         * i386-tlb.h: Re-generate.
2185
2186 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2187
2188         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2189         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2190         vpexpandd, vpexpandq): Fold AFX512VF templates.
2191         * i386-tlb.h: Re-generate.
2192
2193 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2194
2195         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2196         Fold 128- and 256-bit VEX-encoded templates.
2197         * i386-tlb.h: Re-generate.
2198
2199 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2200
2201         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2202         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2203         vpexpandd, vpexpandq): Fold AVX512F templates.
2204         * i386-tlb.h: Re-generate.
2205
2206 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2207
2208         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2209         64-bit templates. Drop Disp<N>.
2210         * i386-tlb.h: Re-generate.
2211
2212 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2213
2214         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2215         and 256-bit templates.
2216         * i386-tlb.h: Re-generate.
2217
2218 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2219
2220         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2221         * i386-tlb.h: Re-generate.
2222
2223 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2224
2225         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2226         Drop NoAVX.
2227         * i386-tlb.h: Re-generate.
2228
2229 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2230
2231         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2232         * i386-tlb.h: Re-generate.
2233
2234 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2235
2236         * i386-gen.c (opcode_modifiers): Delete FloatD.
2237         * i386-opc.h (FloatD): Delete.
2238         (struct i386_opcode_modifier): Delete floatd.
2239         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2240         FloatD by D.
2241         * i386-tlb.h: Re-generate.
2242
2243 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2244
2245         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2246
2247 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2248
2249         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2250         * i386-tlb.h: Re-generate.
2251
2252 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2253
2254         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2255         forms.
2256         * i386-tlb.h: Re-generate.
2257
2258 2018-03-07  Alan Modra  <amodra@gmail.com>
2259
2260         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2261         bfd_arch_rs6000.
2262         * disassemble.h (print_insn_rs6000): Delete.
2263         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2264         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2265         (print_insn_rs6000): Delete.
2266
2267 2018-03-03  Alan Modra  <amodra@gmail.com>
2268
2269         * sysdep.h (opcodes_error_handler): Define.
2270         (_bfd_error_handler): Declare.
2271         * Makefile.am: Remove stray #.
2272         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2273         EDIT" comment.
2274         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2275         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2276         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2277         opcodes_error_handler to print errors.  Standardize error messages.
2278         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2279         and include opintl.h.
2280         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2281         * i386-gen.c: Standardize error messages.
2282         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2283         * Makefile.in: Regenerate.
2284         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2285         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2286         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2287         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2288         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2289         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2290         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2291         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2292         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2293         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2294         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2295         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2296         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2297
2298 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2299
2300         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2301         vpsub[bwdq] instructions.
2302         * i386-tbl.h: Regenerated.
2303
2304 2018-03-01  Alan Modra  <amodra@gmail.com>
2305
2306         * configure.ac (ALL_LINGUAS): Sort.
2307         * configure: Regenerate.
2308
2309 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2310
2311         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2312         macro by assignements.
2313
2314 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2315
2316         PR gas/22871
2317         * i386-gen.c (opcode_modifiers): Add Optimize.
2318         * i386-opc.h (Optimize): New enum.
2319         (i386_opcode_modifier): Add optimize.
2320         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2321         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2322         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2323         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2324         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2325         vpxord and vpxorq.
2326         * i386-tbl.h: Regenerated.
2327
2328 2018-02-26  Alan Modra  <amodra@gmail.com>
2329
2330         * crx-dis.c (getregliststring): Allocate a large enough buffer
2331         to silence false positive gcc8 warning.
2332
2333 2018-02-22  Shea Levy <shea@shealevy.com>
2334
2335         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2336
2337 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2338
2339         * i386-opc.tbl: Add {rex},
2340         * i386-tbl.h: Regenerated.
2341
2342 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2343
2344         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2345         (mips16_opcodes): Replace `M' with `m' for "restore".
2346
2347 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2348
2349         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2350
2351 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2352
2353         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2354         variable to `function_index'.
2355
2356 2018-02-13  Nick Clifton  <nickc@redhat.com>
2357
2358         PR 22823
2359         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2360         about truncation of printing.
2361
2362 2018-02-12  Henry Wong <henry@stuffedcow.net>
2363
2364         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2365
2366 2018-02-05  Nick Clifton  <nickc@redhat.com>
2367
2368         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2369
2370 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2371
2372         * i386-dis.c (enum): Add pconfig.
2373         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2374         (cpu_flags): Add CpuPCONFIG.
2375         * i386-opc.h (enum): Add CpuPCONFIG.
2376         (i386_cpu_flags): Add cpupconfig.
2377         * i386-opc.tbl: Add PCONFIG instruction.
2378         * i386-init.h: Regenerate.
2379         * i386-tbl.h: Likewise.
2380
2381 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2382
2383         * i386-dis.c (enum): Add PREFIX_0F09.
2384         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2385         (cpu_flags): Add CpuWBNOINVD.
2386         * i386-opc.h (enum): Add CpuWBNOINVD.
2387         (i386_cpu_flags): Add cpuwbnoinvd.
2388         * i386-opc.tbl: Add WBNOINVD instruction.
2389         * i386-init.h: Regenerate.
2390         * i386-tbl.h: Likewise.
2391
2392 2018-01-17  Jim Wilson  <jimw@sifive.com>
2393
2394         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2395
2396 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2397
2398         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2399         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2400         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2401         (cpu_flags): Add CpuIBT, CpuSHSTK.
2402         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2403         (i386_cpu_flags): Add cpuibt, cpushstk.
2404         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2405         * i386-init.h: Regenerate.
2406         * i386-tbl.h: Likewise.
2407
2408 2018-01-16  Nick Clifton  <nickc@redhat.com>
2409
2410         * po/pt_BR.po: Updated Brazilian Portugese translation.
2411         * po/de.po: Updated German translation.
2412
2413 2018-01-15  Jim Wilson  <jimw@sifive.com>
2414
2415         * riscv-opc.c (match_c_nop): New.
2416         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2417
2418 2018-01-15  Nick Clifton  <nickc@redhat.com>
2419
2420         * po/uk.po: Updated Ukranian translation.
2421
2422 2018-01-13  Nick Clifton  <nickc@redhat.com>
2423
2424         * po/opcodes.pot: Regenerated.
2425
2426 2018-01-13  Nick Clifton  <nickc@redhat.com>
2427
2428         * configure: Regenerate.
2429
2430 2018-01-13  Nick Clifton  <nickc@redhat.com>
2431
2432         2.30 branch created.
2433
2434 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2435
2436         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2437         * i386-tbl.h: Regenerate.
2438
2439 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2440
2441         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2442         * i386-tbl.h: Re-generate.
2443
2444 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2445
2446         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2447         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2448         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2449         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2450         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2451         Disp8MemShift of AVX512VL forms.
2452         * i386-tbl.h: Re-generate.
2453
2454 2018-01-09  Jim Wilson  <jimw@sifive.com>
2455
2456         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2457         then the hi_addr value is zero.
2458
2459 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2460
2461         * arm-dis.c (arm_opcodes): Add csdb.
2462         (thumb32_opcodes): Add csdb.
2463
2464 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2465
2466         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2467         * aarch64-asm-2.c: Regenerate.
2468         * aarch64-dis-2.c: Regenerate.
2469         * aarch64-opc-2.c: Regenerate.
2470
2471 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2472
2473         PR gas/22681
2474         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2475         Remove AVX512 vmovd with 64-bit operands.
2476         * i386-tbl.h: Regenerated.
2477
2478 2018-01-05  Jim Wilson  <jimw@sifive.com>
2479
2480         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2481         jalr.
2482
2483 2018-01-03  Alan Modra  <amodra@gmail.com>
2484
2485         Update year range in copyright notice of all files.
2486
2487 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2488
2489         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2490         and OPERAND_TYPE_REGZMM entries.
2491
2492 For older changes see ChangeLog-2017
2493 \f
2494 Copyright (C) 2018 Free Software Foundation, Inc.
2495
2496 Copying and distribution of this file, with or without modification,
2497 are permitted in any medium without royalty provided the copyright
2498 notice and this notice are preserved.
2499
2500 Local Variables:
2501 mode: change-log
2502 left-margin: 8
2503 fill-column: 74
2504 version-control: never
2505 End: