opcodes/ChangeLog

   1 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
   4         (aarch64_feature_frintts): New.
   5         (FLAGMANIP, FRINTTS): New.
   6         (aarch64_opcode_table): Add entries for xaflag, axflag
   7         and frint[32,64][x,z] instructions.
   8         * aarch64-asm-2.c: Regenerate.
   9         * aarch64-dis-2.c: Regenerate.
  10         * aarch64-opc-2.c: Regenerate.
  11
  12 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  13
  14         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
  15         (ARMV8_5, V8_5_INSN): New.
  16
  17 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
  18
  19         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
  20
  21 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         * i386-dis.c (rm_table): Add enclv.
  24         * i386-opc.tbl: Add enclv.
  25         * i386-tbl.h: Regenerated.
  26
  27 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
  28
  29         * arm-dis.c (arm_opcodes): Add sb.
  30         (thumb32_opcodes): Likewise.
  31
  32 2018-10-05  Richard Henderson  <rth@twiddle.net>
  33             Stafford Horne  <shorne@gmail.com>
  34
  35         * or1k-desc.c: Regenerate.
  36         * or1k-desc.h: Regenerate.
  37         * or1k-opc.c: Regenerate.
  38         * or1k-opc.h: Regenerate.
  39         * or1k-opinst.c: Regenerate.
  40
  41 2018-10-05  Richard Henderson  <rth@twiddle.net>
  42
  43         * or1k-asm.c: Regenerated.
  44         * or1k-desc.c: Regenerated.
  45         * or1k-desc.h: Regenerated.
  46         * or1k-dis.c: Regenerated.
  47         * or1k-ibld.c: Regenerated.
  48         * or1k-opc.c: Regenerated.
  49         * or1k-opc.h: Regenerated.
  50         * or1k-opinst.c: Regenerated.
  51
  52 2018-10-05  Richard Henderson  <rth@twiddle.net>
  53
  54         * or1k-asm.c: Regenerate.
  55
  56 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  57
  58         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
  59         * aarch64-dis.c (print_operands): Refactor to take notes.
  60         (print_verifier_notes): New.
  61         (print_aarch64_insn): Apply constraint verifier.
  62         (print_insn_aarch64_word): Update call to print_aarch64_insn.
  63         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
  64
  65 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  66
  67         * aarch64-opc.c (init_insn_block): New.
  68         (verify_constraints, aarch64_is_destructive_by_operands): New.
  69         * aarch64-opc.h (verify_constraints): New.
  70
  71 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  72
  73         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
  74         * aarch64-opc.c (verify_ldpsw): Update arguments.
  75
  76 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  77
  78         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
  79         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
  80
  81 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  82
  83         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
  84         * aarch64-dis.c (insn_sequence): New.
  85
  86 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  87
  88         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
  89         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
  90         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
  91         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
  92         constraints.
  93         (_SVE_INSNC): New.
  94         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
  95         constraints.
  96         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
  97         F_SCAN flags.
  98         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
  99         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 100         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 101         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 102         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 103         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 104         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 105
 106 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 107
 108         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 109
 110 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 111
 112         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 113         are used when extracting signed fields and converting them to
 114         potentially 64-bit types.
 115
 116 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 117
 118         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 119         * Makefile.in: Re-generate.
 120         * aclocal.m4: Re-generate.
 121         * configure: Re-generate.
 122         * configure.ac: Remove check for -Wno-missing-field-initializers.
 123         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 124         (csky_v2_opcodes): Likewise.
 125
 126 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 127
 128         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 129
 130 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 131
 132         * nds32-asm.c (operand_fields): Remove the unused fields.
 133         (nds32_opcodes): Remove the unused instructions.
 134         * nds32-dis.c (nds32_ex9_info): Removed.
 135         (nds32_parse_opcode): Updated.
 136         (print_insn_nds32): Likewise.
 137         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 138         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 139         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 140         build_opcode_hash_table): New functions.
 141         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 142         nds32_opcode_table): New.
 143         (hw_ktabs): Declare it to a pointer rather than an array.
 144         (build_hash_table): Removed.
 145         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 146         SYN_ROPT and upadte HW_GPR and HW_INT.
 147         * nds32-dis.c (keywords): Remove const.
 148         (match_field): New function.
 149         (nds32_parse_opcode): Updated.
 150         * disassemble.c (disassemble_init_for_target):
 151         Add disassemble_init_nds32.
 152         * nds32-dis.c (eum map_type): New.
 153         (nds32_private_data): Likewise.
 154         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 155         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 156         (print_insn_nds32): Updated.
 157         * nds32-asm.c (parse_aext_reg): Add new parameter.
 158         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 159         are allowed to use.
 160         All callers changed.
 161         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 162         (operand_fields): Add new fields.
 163         (nds32_opcodes): Add new instructions.
 164         (keyword_aridxi_mx): New keyword.
 165         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 166         and NASM_ATTR_ZOL.
 167         (ALU2_1, ALU2_2, ALU2_3): New macros.
 168         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 169
 170 2018-09-17  Kito Cheng  <kito@andestech.com>
 171
 172         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 173
 174 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 175
 176         PR gas/23670
 177         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 178         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 179         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 180         (EVEX_LEN_0F7E_P_1): Likewise.
 181         (EVEX_LEN_0F7E_P_2): Likewise.
 182         (EVEX_LEN_0FD6_P_2): Likewise.
 183         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 184         (EVEX_LEN_TABLE): Likewise.
 185         (EVEX_LEN_0F6E_P_2): New enum.
 186         (EVEX_LEN_0F7E_P_1): Likewise.
 187         (EVEX_LEN_0F7E_P_2): Likewise.
 188         (EVEX_LEN_0FD6_P_2): Likewise.
 189         (evex_len_table): New.
 190         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 191         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 192         * i386-tbl.h: Regenerated.
 193
 194 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 195
 196         PR gas/23665
 197         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 198         VEX_LEN_0F7E_P_2 entries.
 199         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 200         * i386-tbl.h: Regenerated.
 201
 202 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 203
 204         * i386-dis.c (VZERO_Fixup): Removed.
 205         (VZERO): Likewise.
 206         (VEX_LEN_0F10_P_1): Likewise.
 207         (VEX_LEN_0F10_P_3): Likewise.
 208         (VEX_LEN_0F11_P_1): Likewise.
 209         (VEX_LEN_0F11_P_3): Likewise.
 210         (VEX_LEN_0F2E_P_0): Likewise.
 211         (VEX_LEN_0F2E_P_2): Likewise.
 212         (VEX_LEN_0F2F_P_0): Likewise.
 213         (VEX_LEN_0F2F_P_2): Likewise.
 214         (VEX_LEN_0F51_P_1): Likewise.
 215         (VEX_LEN_0F51_P_3): Likewise.
 216         (VEX_LEN_0F52_P_1): Likewise.
 217         (VEX_LEN_0F53_P_1): Likewise.
 218         (VEX_LEN_0F58_P_1): Likewise.
 219         (VEX_LEN_0F58_P_3): Likewise.
 220         (VEX_LEN_0F59_P_1): Likewise.
 221         (VEX_LEN_0F59_P_3): Likewise.
 222         (VEX_LEN_0F5A_P_1): Likewise.
 223         (VEX_LEN_0F5A_P_3): Likewise.
 224         (VEX_LEN_0F5C_P_1): Likewise.
 225         (VEX_LEN_0F5C_P_3): Likewise.
 226         (VEX_LEN_0F5D_P_1): Likewise.
 227         (VEX_LEN_0F5D_P_3): Likewise.
 228         (VEX_LEN_0F5E_P_1): Likewise.
 229         (VEX_LEN_0F5E_P_3): Likewise.
 230         (VEX_LEN_0F5F_P_1): Likewise.
 231         (VEX_LEN_0F5F_P_3): Likewise.
 232         (VEX_LEN_0FC2_P_1): Likewise.
 233         (VEX_LEN_0FC2_P_3): Likewise.
 234         (VEX_LEN_0F3A0A_P_2): Likewise.
 235         (VEX_LEN_0F3A0B_P_2): Likewise.
 236         (VEX_W_0F10_P_0): Likewise.
 237         (VEX_W_0F10_P_1): Likewise.
 238         (VEX_W_0F10_P_2): Likewise.
 239         (VEX_W_0F10_P_3): Likewise.
 240         (VEX_W_0F11_P_0): Likewise.
 241         (VEX_W_0F11_P_1): Likewise.
 242         (VEX_W_0F11_P_2): Likewise.
 243         (VEX_W_0F11_P_3): Likewise.
 244         (VEX_W_0F12_P_0_M_0): Likewise.
 245         (VEX_W_0F12_P_0_M_1): Likewise.
 246         (VEX_W_0F12_P_1): Likewise.
 247         (VEX_W_0F12_P_2): Likewise.
 248         (VEX_W_0F12_P_3): Likewise.
 249         (VEX_W_0F13_M_0): Likewise.
 250         (VEX_W_0F14): Likewise.
 251         (VEX_W_0F15): Likewise.
 252         (VEX_W_0F16_P_0_M_0): Likewise.
 253         (VEX_W_0F16_P_0_M_1): Likewise.
 254         (VEX_W_0F16_P_1): Likewise.
 255         (VEX_W_0F16_P_2): Likewise.
 256         (VEX_W_0F17_M_0): Likewise.
 257         (VEX_W_0F28): Likewise.
 258         (VEX_W_0F29): Likewise.
 259         (VEX_W_0F2B_M_0): Likewise.
 260         (VEX_W_0F2E_P_0): Likewise.
 261         (VEX_W_0F2E_P_2): Likewise.
 262         (VEX_W_0F2F_P_0): Likewise.
 263         (VEX_W_0F2F_P_2): Likewise.
 264         (VEX_W_0F50_M_0): Likewise.
 265         (VEX_W_0F51_P_0): Likewise.
 266         (VEX_W_0F51_P_1): Likewise.
 267         (VEX_W_0F51_P_2): Likewise.
 268         (VEX_W_0F51_P_3): Likewise.
 269         (VEX_W_0F52_P_0): Likewise.
 270         (VEX_W_0F52_P_1): Likewise.
 271         (VEX_W_0F53_P_0): Likewise.
 272         (VEX_W_0F53_P_1): Likewise.
 273         (VEX_W_0F58_P_0): Likewise.
 274         (VEX_W_0F58_P_1): Likewise.
 275         (VEX_W_0F58_P_2): Likewise.
 276         (VEX_W_0F58_P_3): Likewise.
 277         (VEX_W_0F59_P_0): Likewise.
 278         (VEX_W_0F59_P_1): Likewise.
 279         (VEX_W_0F59_P_2): Likewise.
 280         (VEX_W_0F59_P_3): Likewise.
 281         (VEX_W_0F5A_P_0): Likewise.
 282         (VEX_W_0F5A_P_1): Likewise.
 283         (VEX_W_0F5A_P_3): Likewise.
 284         (VEX_W_0F5B_P_0): Likewise.
 285         (VEX_W_0F5B_P_1): Likewise.
 286         (VEX_W_0F5B_P_2): Likewise.
 287         (VEX_W_0F5C_P_0): Likewise.
 288         (VEX_W_0F5C_P_1): Likewise.
 289         (VEX_W_0F5C_P_2): Likewise.
 290         (VEX_W_0F5C_P_3): Likewise.
 291         (VEX_W_0F5D_P_0): Likewise.
 292         (VEX_W_0F5D_P_1): Likewise.
 293         (VEX_W_0F5D_P_2): Likewise.
 294         (VEX_W_0F5D_P_3): Likewise.
 295         (VEX_W_0F5E_P_0): Likewise.
 296         (VEX_W_0F5E_P_1): Likewise.
 297         (VEX_W_0F5E_P_2): Likewise.
 298         (VEX_W_0F5E_P_3): Likewise.
 299         (VEX_W_0F5F_P_0): Likewise.
 300         (VEX_W_0F5F_P_1): Likewise.
 301         (VEX_W_0F5F_P_2): Likewise.
 302         (VEX_W_0F5F_P_3): Likewise.
 303         (VEX_W_0F60_P_2): Likewise.
 304         (VEX_W_0F61_P_2): Likewise.
 305         (VEX_W_0F62_P_2): Likewise.
 306         (VEX_W_0F63_P_2): Likewise.
 307         (VEX_W_0F64_P_2): Likewise.
 308         (VEX_W_0F65_P_2): Likewise.
 309         (VEX_W_0F66_P_2): Likewise.
 310         (VEX_W_0F67_P_2): Likewise.
 311         (VEX_W_0F68_P_2): Likewise.
 312         (VEX_W_0F69_P_2): Likewise.
 313         (VEX_W_0F6A_P_2): Likewise.
 314         (VEX_W_0F6B_P_2): Likewise.
 315         (VEX_W_0F6C_P_2): Likewise.
 316         (VEX_W_0F6D_P_2): Likewise.
 317         (VEX_W_0F6F_P_1): Likewise.
 318         (VEX_W_0F6F_P_2): Likewise.
 319         (VEX_W_0F70_P_1): Likewise.
 320         (VEX_W_0F70_P_2): Likewise.
 321         (VEX_W_0F70_P_3): Likewise.
 322         (VEX_W_0F71_R_2_P_2): Likewise.
 323         (VEX_W_0F71_R_4_P_2): Likewise.
 324         (VEX_W_0F71_R_6_P_2): Likewise.
 325         (VEX_W_0F72_R_2_P_2): Likewise.
 326         (VEX_W_0F72_R_4_P_2): Likewise.
 327         (VEX_W_0F72_R_6_P_2): Likewise.
 328         (VEX_W_0F73_R_2_P_2): Likewise.
 329         (VEX_W_0F73_R_3_P_2): Likewise.
 330         (VEX_W_0F73_R_6_P_2): Likewise.
 331         (VEX_W_0F73_R_7_P_2): Likewise.
 332         (VEX_W_0F74_P_2): Likewise.
 333         (VEX_W_0F75_P_2): Likewise.
 334         (VEX_W_0F76_P_2): Likewise.
 335         (VEX_W_0F77_P_0): Likewise.
 336         (VEX_W_0F7C_P_2): Likewise.
 337         (VEX_W_0F7C_P_3): Likewise.
 338         (VEX_W_0F7D_P_2): Likewise.
 339         (VEX_W_0F7D_P_3): Likewise.
 340         (VEX_W_0F7E_P_1): Likewise.
 341         (VEX_W_0F7F_P_1): Likewise.
 342         (VEX_W_0F7F_P_2): Likewise.
 343         (VEX_W_0FAE_R_2_M_0): Likewise.
 344         (VEX_W_0FAE_R_3_M_0): Likewise.
 345         (VEX_W_0FC2_P_0): Likewise.
 346         (VEX_W_0FC2_P_1): Likewise.
 347         (VEX_W_0FC2_P_2): Likewise.
 348         (VEX_W_0FC2_P_3): Likewise.
 349         (VEX_W_0FD0_P_2): Likewise.
 350         (VEX_W_0FD0_P_3): Likewise.
 351         (VEX_W_0FD1_P_2): Likewise.
 352         (VEX_W_0FD2_P_2): Likewise.
 353         (VEX_W_0FD3_P_2): Likewise.
 354         (VEX_W_0FD4_P_2): Likewise.
 355         (VEX_W_0FD5_P_2): Likewise.
 356         (VEX_W_0FD6_P_2): Likewise.
 357         (VEX_W_0FD7_P_2_M_1): Likewise.
 358         (VEX_W_0FD8_P_2): Likewise.
 359         (VEX_W_0FD9_P_2): Likewise.
 360         (VEX_W_0FDA_P_2): Likewise.
 361         (VEX_W_0FDB_P_2): Likewise.
 362         (VEX_W_0FDC_P_2): Likewise.
 363         (VEX_W_0FDD_P_2): Likewise.
 364         (VEX_W_0FDE_P_2): Likewise.
 365         (VEX_W_0FDF_P_2): Likewise.
 366         (VEX_W_0FE0_P_2): Likewise.
 367         (VEX_W_0FE1_P_2): Likewise.
 368         (VEX_W_0FE2_P_2): Likewise.
 369         (VEX_W_0FE3_P_2): Likewise.
 370         (VEX_W_0FE4_P_2): Likewise.
 371         (VEX_W_0FE5_P_2): Likewise.
 372         (VEX_W_0FE6_P_1): Likewise.
 373         (VEX_W_0FE6_P_2): Likewise.
 374         (VEX_W_0FE6_P_3): Likewise.
 375         (VEX_W_0FE7_P_2_M_0): Likewise.
 376         (VEX_W_0FE8_P_2): Likewise.
 377         (VEX_W_0FE9_P_2): Likewise.
 378         (VEX_W_0FEA_P_2): Likewise.
 379         (VEX_W_0FEB_P_2): Likewise.
 380         (VEX_W_0FEC_P_2): Likewise.
 381         (VEX_W_0FED_P_2): Likewise.
 382         (VEX_W_0FEE_P_2): Likewise.
 383         (VEX_W_0FEF_P_2): Likewise.
 384         (VEX_W_0FF0_P_3_M_0): Likewise.
 385         (VEX_W_0FF1_P_2): Likewise.
 386         (VEX_W_0FF2_P_2): Likewise.
 387         (VEX_W_0FF3_P_2): Likewise.
 388         (VEX_W_0FF4_P_2): Likewise.
 389         (VEX_W_0FF5_P_2): Likewise.
 390         (VEX_W_0FF6_P_2): Likewise.
 391         (VEX_W_0FF7_P_2): Likewise.
 392         (VEX_W_0FF8_P_2): Likewise.
 393         (VEX_W_0FF9_P_2): Likewise.
 394         (VEX_W_0FFA_P_2): Likewise.
 395         (VEX_W_0FFB_P_2): Likewise.
 396         (VEX_W_0FFC_P_2): Likewise.
 397         (VEX_W_0FFD_P_2): Likewise.
 398         (VEX_W_0FFE_P_2): Likewise.
 399         (VEX_W_0F3800_P_2): Likewise.
 400         (VEX_W_0F3801_P_2): Likewise.
 401         (VEX_W_0F3802_P_2): Likewise.
 402         (VEX_W_0F3803_P_2): Likewise.
 403         (VEX_W_0F3804_P_2): Likewise.
 404         (VEX_W_0F3805_P_2): Likewise.
 405         (VEX_W_0F3806_P_2): Likewise.
 406         (VEX_W_0F3807_P_2): Likewise.
 407         (VEX_W_0F3808_P_2): Likewise.
 408         (VEX_W_0F3809_P_2): Likewise.
 409         (VEX_W_0F380A_P_2): Likewise.
 410         (VEX_W_0F380B_P_2): Likewise.
 411         (VEX_W_0F3817_P_2): Likewise.
 412         (VEX_W_0F381C_P_2): Likewise.
 413         (VEX_W_0F381D_P_2): Likewise.
 414         (VEX_W_0F381E_P_2): Likewise.
 415         (VEX_W_0F3820_P_2): Likewise.
 416         (VEX_W_0F3821_P_2): Likewise.
 417         (VEX_W_0F3822_P_2): Likewise.
 418         (VEX_W_0F3823_P_2): Likewise.
 419         (VEX_W_0F3824_P_2): Likewise.
 420         (VEX_W_0F3825_P_2): Likewise.
 421         (VEX_W_0F3828_P_2): Likewise.
 422         (VEX_W_0F3829_P_2): Likewise.
 423         (VEX_W_0F382A_P_2_M_0): Likewise.
 424         (VEX_W_0F382B_P_2): Likewise.
 425         (VEX_W_0F3830_P_2): Likewise.
 426         (VEX_W_0F3831_P_2): Likewise.
 427         (VEX_W_0F3832_P_2): Likewise.
 428         (VEX_W_0F3833_P_2): Likewise.
 429         (VEX_W_0F3834_P_2): Likewise.
 430         (VEX_W_0F3835_P_2): Likewise.
 431         (VEX_W_0F3837_P_2): Likewise.
 432         (VEX_W_0F3838_P_2): Likewise.
 433         (VEX_W_0F3839_P_2): Likewise.
 434         (VEX_W_0F383A_P_2): Likewise.
 435         (VEX_W_0F383B_P_2): Likewise.
 436         (VEX_W_0F383C_P_2): Likewise.
 437         (VEX_W_0F383D_P_2): Likewise.
 438         (VEX_W_0F383E_P_2): Likewise.
 439         (VEX_W_0F383F_P_2): Likewise.
 440         (VEX_W_0F3840_P_2): Likewise.
 441         (VEX_W_0F3841_P_2): Likewise.
 442         (VEX_W_0F38DB_P_2): Likewise.
 443         (VEX_W_0F3A08_P_2): Likewise.
 444         (VEX_W_0F3A09_P_2): Likewise.
 445         (VEX_W_0F3A0A_P_2): Likewise.
 446         (VEX_W_0F3A0B_P_2): Likewise.
 447         (VEX_W_0F3A0C_P_2): Likewise.
 448         (VEX_W_0F3A0D_P_2): Likewise.
 449         (VEX_W_0F3A0E_P_2): Likewise.
 450         (VEX_W_0F3A0F_P_2): Likewise.
 451         (VEX_W_0F3A21_P_2): Likewise.
 452         (VEX_W_0F3A40_P_2): Likewise.
 453         (VEX_W_0F3A41_P_2): Likewise.
 454         (VEX_W_0F3A42_P_2): Likewise.
 455         (VEX_W_0F3A62_P_2): Likewise.
 456         (VEX_W_0F3A63_P_2): Likewise.
 457         (VEX_W_0F3ADF_P_2): Likewise.
 458         (VEX_LEN_0F77_P_0): New.
 459         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 460         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 461         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 462         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 463         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 464         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 465         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 466         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 467         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 468         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 469         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 470         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 471         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 472         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 473         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 474         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 475         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 476         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 477         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 478         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 479         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 480         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 481         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 482         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 483         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 484         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 485         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 486         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 487         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 488         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 489         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 490         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 491         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 492         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 493         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 494         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 495         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 496         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 497         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 498         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 499         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 500         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 501         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 502         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 503         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 504         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 505         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 506         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 507         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 508         (vex_table): Update VEX 0F28 and 0F29 entries.
 509         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 510         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 511         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 512         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 513         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 514         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 515         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 516         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 517         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 518         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 519         VEX_LEN_0F3A0B_P_2 entries.
 520         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 521         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 522         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 523         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 524         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 525         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 526         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 527         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 528         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 529         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 530         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 531         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 532         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 533         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 534         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 535         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 536         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 537         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 538         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 539         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 540         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 541         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 542         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 543         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 544         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 545         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 546         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 547         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 548         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 549         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 550         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 551         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 552         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 553         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 554         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 555         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 556         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 557         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 558         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 559         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 560         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 561         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 562         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 563         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 564         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 565         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 566         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 567         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 568         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 569         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 570         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 571         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 572         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 573         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 574         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 575         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 576         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 577         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 578         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 579         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 580         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 581         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 582         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 583         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 584         VEX_W_0F3ADF_P_2 entries.
 585         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 586         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 587         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 588
 589 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 590
 591         * i386-opc.tbl (VexWIG): New.
 592         Replace VexW=3 with VexWIG.
 593
 594 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 597         * i386-tbl.h: Regenerated.
 598
 599 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 600
 601         PR gas/23665
 602         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 603         VEX_LEN_0FD6_P_2 entries.
 604         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 605         * i386-tbl.h: Regenerated.
 606
 607 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 608
 609         PR gas/23642
 610         * i386-opc.h (VEXWIG): New.
 611         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 612         * i386-tbl.h: Regenerated.
 613
 614 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 615
 616         PR binutils/23655
 617         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 618         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 619         * i386-dis.c (EXxEVexR64): New.
 620         (evex_rounding_64_mode): Likewise.
 621         (OP_Rounding): Handle evex_rounding_64_mode.
 622
 623 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         PR binutils/23655
 626         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 627         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 628         * i386-dis.c (Edqa): New.
 629         (dqa_mode): Likewise.
 630         (intel_operand_size): Handle dqa_mode as m_mode.
 631         (OP_E_register): Handle dqa_mode as dq_mode.
 632         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 633
 634 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 635
 636         * i386-dis.c (OP_E_memory): Reformat.
 637
 638 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 639
 640         * i386-opc.tbl (crc32): Fold byte and word forms.
 641         * i386-tbl.h: Re-generate.
 642
 643 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 644
 645         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 646         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 647         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 648         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 649         * i386-tbl.h: Regenerated.
 650
 651 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 652
 653         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 654         meaningless.
 655         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 656         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 657         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 658         * i386-tbl.h: Re-generate.
 659
 660 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 661
 662         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 663         AVX512_4VNNIW insns.
 664         * i386-tbl.h: Re-generate.
 665
 666 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 667
 668         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 669         meaningless.
 670         * i386-tbl.h: Re-generate.
 671
 672 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 673
 674         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 675         meaningless.
 676         * i386-tbl.h: Re-generate.
 677
 678 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 679
 680         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 681         meaningless.
 682         * i386-tbl.h: Re-generate.
 683
 684 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 685
 686         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 687         meaningless.
 688         * i386-tbl.h: Re-generate.
 689
 690 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 691
 692         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 693         meaningless.
 694         * i386-tbl.h: Re-generate.
 695
 696 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 699         * i386-tbl.h: Re-generate.
 700
 701 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 702
 703         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 704         * i386-tbl.h: Re-generate.
 705
 706 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 707
 708         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 709         meaningless.
 710         * i386-tbl.h: Re-generate.
 711
 712 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 715         meaningless.
 716         * i386-tbl.h: Re-generate.
 717
 718 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 719
 720         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 721         * i386-tbl.h: Re-generate.
 722
 723 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 724
 725         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 726         * i386-tbl.h: Re-generate.
 727
 728 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 729
 730         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 731         * i386-tbl.h: Re-generate.
 732
 733 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 734
 735         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 736         meaningless.
 737         * i386-tbl.h: Re-generate.
 738
 739 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 740
 741         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 742         meaningless.
 743         * i386-tbl.h: Re-generate.
 744
 745 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 746
 747         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 748         meaningless.
 749         * i386-tbl.h: Re-generate.
 750
 751 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 754         * i386-tbl.h: Re-generate.
 755
 756 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 757
 758         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 759         * i386-tbl.h: Re-generate.
 760
 761 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 764         * i386-tbl.h: Re-generate.
 765
 766 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 767
 768         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 769         (vpbroadcastw, rdpid): Drop NoRex64.
 770         * i386-tbl.h: Re-generate.
 771
 772 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 773
 774         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 775         store templates, adding D.
 776         * i386-tbl.h: Re-generate.
 777
 778 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 779
 780         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 781         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 782         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 783         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 784         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 785         Fold load and store templates where possible, adding D. Drop
 786         IgnoreSize where it was pointlessly present. Drop redundant
 787         *word.
 788         * i386-tbl.h: Re-generate.
 789
 790 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 791
 792         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 793         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 794         (intel_operand_size): Handle v_bndmk_mode.
 795         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 796
 797 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 798
 799         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 800
 801 2018-08-31  Kito Cheng  <kito@andestech.com>
 802
 803         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 804         compressed floating point instructions.
 805
 806 2018-08-30  Kito Cheng  <kito@andestech.com>
 807
 808         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 809         riscv_opcode.xlen_requirement.
 810         * riscv-opc.c (riscv_opcodes): Update for struct change.
 811
 812 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 813
 814         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 815         psr (PWRPSR) instruction.
 816
 817 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 818
 819         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 820
 821 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 822
 823         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 824
 825 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 826
 827         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 828         loongson3a as an alias of gs464 for compatibility.
 829         * mips-opc.c (mips_opcodes): Change Comments.
 830
 831 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 832
 833         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 834         option.
 835         (print_mips_disassembler_options): Document -M loongson-ext.
 836         * mips-opc.c (LEXT2): New macro.
 837         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 838
 839 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 840
 841          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 842          descriptors.
 843          (parse_mips_ase_option): Handle -M loongson-ext option.
 844          (print_mips_disassembler_options): Document -M loongson-ext.
 845          * mips-opc.c (IL3A): Delete.
 846          * mips-opc.c (LEXT): New macro.
 847          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 848          instructions.
 849
 850 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 851
 852         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 853         descriptors.
 854         (parse_mips_ase_option): Handle -M loongson-cam option.
 855         (print_mips_disassembler_options): Document -M loongson-cam.
 856         * mips-opc.c (LCAM): New macro.
 857         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 858         instructions.
 859
 860 2018-08-21  Alan Modra  <amodra@gmail.com>
 861
 862         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 863         (skip_optional_operands): Count optional operands, and update
 864         ppc_optional_operand_value call.
 865         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 866         (extract_vlensi): Likewise.
 867         (extract_fxm): Return default value for missing optional operand.
 868         (extract_ls, extract_raq, extract_tbr): Likewise.
 869         (insert_sxl, extract_sxl): New functions.
 870         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 871         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 872         flag and extra entry.
 873         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 874         extract_sxl.
 875
 876 2018-08-20  Alan Modra  <amodra@gmail.com>
 877
 878         * sh-opc.h (MASK): Simplify.
 879
 880 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 881
 882         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 883         BM_RESERVED0 or BM_RESERVED1
 884         (bm_rel_decode, bm_n_bytes): Ditto.
 885
 886 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 887
 888         * s12z.h: Delete.
 889
 890 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 891
 892         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 893         address with the addr32 prefix and without base nor index
 894         registers.
 895
 896 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 897
 898         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 899         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 900         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 901         (cpu_flags): Add CpuCMOV and CpuFXSR.
 902         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 903         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 904         * i386-init.h: Regenerated.
 905         * i386-tbl.h: Likewise.
 906
 907 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 908
 909         * arc-regs.h: Update auxiliary registers.
 910
 911 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 912
 913         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 914         (RegIP, RegIZ): Define.
 915         * i386-reg.tbl: Adjust comments.
 916         (rip): Use Qword instead of BaseIndex. Use RegIP.
 917         (eip): Use Dword instead of BaseIndex. Use RegIP.
 918         (riz): Add Qword. Use RegIZ.
 919         (eiz): Add Dword. Use RegIZ.
 920         * i386-tbl.h: Re-generate.
 921
 922 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 923
 924         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 925         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 926         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 927         * i386-tbl.h: Re-generate.
 928
 929 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 930
 931         * i386-gen.c (operand_types): Remove Mem field.
 932         * i386-opc.h (union i386_operand_type): Remove mem field.
 933         * i386-init.h, i386-tbl.h: Re-generate.
 934
 935 2018-08-01  Alan Modra  <amodra@gmail.com>
 936
 937         * po/POTFILES.in: Regenerate.
 938
 939 2018-07-31  Nick Clifton  <nickc@redhat.com>
 940
 941         * po/sv.po: Updated Swedish translation.
 942
 943 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 944
 945         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 946         * i386-init.h, i386-tbl.h: Re-generate.
 947
 948 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 949
 950         * i386-opc.h (ZEROING_MASKING) Rename to ...
 951         (DYNAMIC_MASKING): ... this. Adjust comment.
 952         * i386-opc.tbl (MaskingMorZ): Define.
 953         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 954         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 955         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 956         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 957         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 958         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 959         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 960         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 961         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 962
 963 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 964
 965         * i386-opc.tbl: Use element rather than vector size for AVX512*
 966         scatter/gather insns.
 967         * i386-tbl.h: Re-generate.
 968
 969 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 970
 971         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 972         (cpu_flags): Drop CpuVREX.
 973         * i386-opc.h (CpuVREX): Delete.
 974         (union i386_cpu_flags): Remove cpuvrex.
 975         * i386-init.h, i386-tbl.h: Re-generate.
 976
 977 2018-07-30  Jim Wilson  <jimw@sifive.com>
 978
 979         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 980         fields.
 981         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 982
 983 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 984
 985         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 986         * Makefile.in: Regenerated.
 987         * configure.ac: Add C-SKY.
 988         * configure: Regenerated.
 989         * csky-dis.c: New file.
 990         * csky-opc.h: New file.
 991         * disassemble.c (ARCH_csky): Define.
 992         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 993         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 994
 995 2018-07-27  Alan Modra  <amodra@gmail.com>
 996
 997         * ppc-opc.c (insert_sprbat): Correct function parameter and
 998         return type.
 999         (extract_sprbat): Likewise, variable too.
1000
1001 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1002             Alan Modra  <amodra@gmail.com>
1003
1004         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1005         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1006         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1007         support disjointed BAT.
1008         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1009         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1010         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1011
1012 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1013             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1014
1015         * i386-gen.c (adjust_broadcast_modifier): New function.
1016         (process_i386_opcode_modifier): Add an argument for operands.
1017         Adjust the Broadcast value based on operands.
1018         (output_i386_opcode): Pass operand_types to
1019         process_i386_opcode_modifier.
1020         (process_i386_opcodes): Pass NULL as operands to
1021         process_i386_opcode_modifier.
1022         * i386-opc.h (BYTE_BROADCAST): New.
1023         (WORD_BROADCAST): Likewise.
1024         (DWORD_BROADCAST): Likewise.
1025         (QWORD_BROADCAST): Likewise.
1026         (i386_opcode_modifier): Expand broadcast to 3 bits.
1027         * i386-tbl.h: Regenerated.
1028
1029 2018-07-24  Alan Modra  <amodra@gmail.com>
1030
1031         PR 23430
1032         * or1k-desc.h: Regenerate.
1033
1034 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1035
1036         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1037         vcvtusi2ss, and vcvtusi2sd.
1038         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1039         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1040         * i386-tbl.h: Re-generate.
1041
1042 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1043
1044         * arc-opc.c (extract_w6): Fix extending the sign.
1045
1046 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1047
1048         * arc-tbl.h (vewt): Allow it for ARC EM family.
1049
1050 2018-07-23  Alan Modra  <amodra@gmail.com>
1051
1052         PR 23419
1053         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1054         opcode variants for mtspr/mfspr encodings.
1055
1056 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1057             Maciej W. Rozycki  <macro@mips.com>
1058
1059         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1060         loongson3a descriptors.
1061         (parse_mips_ase_option): Handle -M loongson-mmi option.
1062         (print_mips_disassembler_options): Document -M loongson-mmi.
1063         * mips-opc.c (LMMI): New macro.
1064         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1065         instructions.
1066
1067 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1068
1069         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1070         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1071         IgnoreSize and [XYZ]MMword where applicable.
1072         * i386-tbl.h: Re-generate.
1073
1074 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1075
1076         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1077         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1078         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1079         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1080         * i386-tbl.h: Re-generate.
1081
1082 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1083
1084         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1085         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1086         VPCLMULQDQ templates into their respective AVX512VL counterparts
1087         where possible, using Disp8ShiftVL and CheckRegSize instead of
1088         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1089         * i386-tbl.h: Re-generate.
1090
1091 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1092
1093         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1094         AVX512VL counterparts where possible, using Disp8ShiftVL and
1095         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1096         IgnoreSize) as appropriate.
1097         * i386-tbl.h: Re-generate.
1098
1099 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1100
1101         * i386-opc.tbl: Fold AVX512BW templates into their respective
1102         AVX512VL counterparts where possible, using Disp8ShiftVL and
1103         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1104         IgnoreSize) as appropriate.
1105         * i386-tbl.h: Re-generate.
1106
1107 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1108
1109         * i386-opc.tbl: Fold AVX512CD templates into their respective
1110         AVX512VL counterparts where possible, using Disp8ShiftVL and
1111         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1112         IgnoreSize) as appropriate.
1113         * i386-tbl.h: Re-generate.
1114
1115 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1116
1117         * i386-opc.h (DISP8_SHIFT_VL): New.
1118         * i386-opc.tbl (Disp8ShiftVL):  Define.
1119         (various): Fold AVX512VL templates into their respective
1120         AVX512F counterparts where possible, using Disp8ShiftVL and
1121         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1122         IgnoreSize) as appropriate.
1123         * i386-tbl.h: Re-generate.
1124
1125 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1126
1127         * Makefile.am: Change dependencies and rule for
1128         $(srcdir)/i386-init.h.
1129         * Makefile.in: Re-generate.
1130         * i386-gen.c (process_i386_opcodes): New local variable
1131         "marker". Drop opening of input file. Recognize marker and line
1132         number directives.
1133         * i386-opc.tbl (OPCODE_I386_H): Define.
1134         (i386-opc.h): Include it.
1135         (None): Undefine.
1136
1137 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1138
1139         PR gas/23418
1140         * i386-opc.h (Byte): Update comments.
1141         (Word): Likewise.
1142         (Dword): Likewise.
1143         (Fword): Likewise.
1144         (Qword): Likewise.
1145         (Tbyte): Likewise.
1146         (Xmmword): Likewise.
1147         (Ymmword): Likewise.
1148         (Zmmword): Likewise.
1149         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1150         vcvttps2uqq.
1151         * i386-tbl.h: Regenerated.
1152
1153 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1154
1155         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1156         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1157         * aarch64-asm-2.c: Regenerate.
1158         * aarch64-dis-2.c: Regenerate.
1159         * aarch64-opc-2.c: Regenerate.
1160
1161 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1162
1163         PR binutils/23192
1164         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1165         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1166         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1167         sqdmulh, sqrdmulh): Use Em16.
1168
1169 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1170
1171         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1172         csdb together with them.
1173         (thumb32_opcodes): Likewise.
1174
1175 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1176
1177         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1178         requiring 32-bit registers as operands 2 and 3. Improve
1179         comments.
1180         (mwait, mwaitx): Fold templates. Improve comments.
1181         OPERAND_TYPE_INOUTPORTREG.
1182         * i386-tbl.h: Re-generate.
1183
1184 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1185
1186         * i386-gen.c (operand_type_init): Remove
1187         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1188         OPERAND_TYPE_INOUTPORTREG.
1189         * i386-init.h: Re-generate.
1190
1191 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1192
1193         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1194         (wrssq, wrussq): Add Qword.
1195         * i386-tbl.h: Re-generate.
1196
1197 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1198
1199         * i386-opc.h: Rename OTMax to OTNum.
1200         (OTNumOfUints): Adjust calculation.
1201         (OTUnused): Directly alias to OTNum.
1202
1203 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1204
1205         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1206         `reg_xys'.
1207         (lea_reg_xys): Likewise.
1208         (print_insn_loop_primitive): Rename `reg' local variable to
1209         `reg_dxy'.
1210
1211 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1212
1213         PR binutils/23242
1214         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1215
1216 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1217
1218         PR binutils/23369
1219         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1220         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1221
1222 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1223
1224         PR tdep/8282
1225         * mips-dis.c (mips_option_arg_t): New enumeration.
1226         (mips_options): New variable.
1227         (disassembler_options_mips): New function.
1228         (print_mips_disassembler_options): Reimplement in terms of
1229         `disassembler_options_mips'.
1230         * arm-dis.c (disassembler_options_arm): Adapt to using the
1231         `disasm_options_and_args_t' structure.
1232         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1233         * s390-dis.c (disassembler_options_s390): Likewise.
1234
1235 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1236
1237         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1238         expected result.
1239         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1240         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1241         * testsuite/ld-arm/tls-longplt.d: Likewise.
1242
1243 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1244
1245         PR binutils/23192
1246         * aarch64-asm-2.c: Regenerate.
1247         * aarch64-dis-2.c: Likewise.
1248         * aarch64-opc-2.c: Likewise.
1249         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1250         * aarch64-opc.c (operand_general_constraint_met_p,
1251         aarch64_print_operand): Likewise.
1252         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1253         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1254         fmlal2, fmlsl2.
1255         (AARCH64_OPERANDS): Add Em2.
1256
1257 2018-06-26  Nick Clifton  <nickc@redhat.com>
1258
1259         * po/uk.po: Updated Ukranian translation.
1260         * po/de.po: Updated German translation.
1261         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1262
1263 2018-06-26  Nick Clifton  <nickc@redhat.com>
1264
1265         * nfp-dis.c: Fix spelling mistake.
1266
1267 2018-06-24  Nick Clifton  <nickc@redhat.com>
1268
1269         * configure: Regenerate.
1270         * po/opcodes.pot: Regenerate.
1271
1272 2018-06-24  Nick Clifton  <nickc@redhat.com>
1273
1274         2.31 branch created.
1275
1276 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1277
1278         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1279         * aarch64-asm-2.c: Regenerate.
1280         * aarch64-dis-2.c: Likewise.
1281
1282 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1283
1284         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1285         `-M ginv' option description.
1286
1287 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1288
1289         PR gas/23305
1290         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1291         la and lla.
1292
1293 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1294
1295         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1296         * configure.ac: Remove AC_PREREQ.
1297         * Makefile.in: Re-generate.
1298         * aclocal.m4: Re-generate.
1299         * configure: Re-generate.
1300
1301 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1302
1303         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1304         mips64r6 descriptors.
1305         (parse_mips_ase_option): Handle -Mginv option.
1306         (print_mips_disassembler_options): Document -Mginv.
1307         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1308         (GINV): New macro.
1309         (mips_opcodes): Define ginvi and ginvt.
1310
1311 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1312             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1313
1314         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1315         * mips-opc.c (CRC, CRC64): New macros.
1316         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1317         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1318         crc32cd for CRC64.
1319
1320 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1321
1322         PR 20319
1323         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1324         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1325
1326 2018-06-06  Alan Modra  <amodra@gmail.com>
1327
1328         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1329         setjmp.  Move init for some other vars later too.
1330
1331 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1332
1333         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1334         (dis_private): Add new fields for property section tracking.
1335         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1336         (xtensa_instruction_fits): New functions.
1337         (fetch_data): Bump minimal fetch size to 4.
1338         (print_insn_xtensa): Make struct dis_private static.
1339         Load and prepare property table on section change.
1340         Don't disassemble literals. Don't disassemble instructions that
1341         cross property table boundaries.
1342
1343 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1344
1345         * configure: Regenerated.
1346
1347 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1348
1349         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1350         * i386-tbl.h: Re-generate.
1351
1352 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1353
1354         * i386-opc.tbl (sldt, str): Add NoRex64.
1355         * i386-tbl.h: Re-generate.
1356
1357 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1358
1359         * i386-opc.tbl (invpcid): Add Oword.
1360         * i386-tbl.h: Re-generate.
1361
1362 2018-06-01  Alan Modra  <amodra@gmail.com>
1363
1364         * sysdep.h (_bfd_error_handler): Don't declare.
1365         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1366         * rl78-decode.opc: Likewise.
1367         * msp430-decode.c: Regenerate.
1368         * rl78-decode.c: Regenerate.
1369
1370 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1371
1372         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1373         * i386-init.h : Regenerated.
1374
1375 2018-05-25  Alan Modra  <amodra@gmail.com>
1376
1377         * Makefile.in: Regenerate.
1378         * po/POTFILES.in: Regenerate.
1379
1380 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1381
1382         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1383         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1384         (insert_bab, extract_bab, insert_btab, extract_btab,
1385         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1386         (BAT, BBA VBA RBS XB6S): Delete macros.
1387         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1388         (BB, BD, RBX, XC6): Update for new macros.
1389         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1390         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1391         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1392         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1393
1394 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1395
1396         * Makefile.am: Add support for s12z architecture.
1397         * configure.ac: Likewise.
1398         * disassemble.c: Likewise.
1399         * disassemble.h: Likewise.
1400         * Makefile.in: Regenerate.
1401         * configure: Regenerate.
1402         * s12z-dis.c: New file.
1403         * s12z.h: New file.
1404
1405 2018-05-18  Alan Modra  <amodra@gmail.com>
1406
1407         * nfp-dis.c: Don't #include libbfd.h.
1408         (init_nfp3200_priv): Use bfd_get_section_contents.
1409         (nit_nfp6000_mecsr_sec): Likewise.
1410
1411 2018-05-17  Nick Clifton  <nickc@redhat.com>
1412
1413         * po/zh_CN.po: Updated simplified Chinese translation.
1414
1415 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1416
1417         PR binutils/23109
1418         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1419         * aarch64-dis-2.c: Regenerate.
1420
1421 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1422
1423         PR binutils/21446
1424         * aarch64-asm.c (opintl.h): Include.
1425         (aarch64_ins_sysreg): Enforce read/write constraints.
1426         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1427         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1428         (F_REG_READ, F_REG_WRITE): New.
1429         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1430         AARCH64_OPND_SYSREG.
1431         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1432         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1433         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1434         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1435         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1436         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1437         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1438         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1439         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1440         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1441         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1442         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1443         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1444         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1445         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1446         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1447         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1448
1449 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1450
1451         PR binutils/21446
1452         * aarch64-dis.c (no_notes: New.
1453         (parse_aarch64_dis_option): Support notes.
1454         (aarch64_decode_insn, print_operands): Likewise.
1455         (print_aarch64_disassembler_options): Document notes.
1456         * aarch64-opc.c (aarch64_print_operand): Support notes.
1457
1458 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1459
1460         PR binutils/21446
1461         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1462         and take error struct.
1463         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1464         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1465         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1466         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1467         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1468         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1469         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1470         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1471         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1472         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1473         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1474         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1475         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1476         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1477         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1478         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1479         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1480         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1481         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1482         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1483         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1484         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1485         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1486         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1487         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1488         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1489         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1490         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1491         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1492         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1493         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1494         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1495         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1496         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1497         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1498         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1499         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1500         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1501         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1502         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1503         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1504         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1505         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1506         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1507         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1508         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1509         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1510         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1511         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1512         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1513         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1514         (determine_disassembling_preference, aarch64_decode_insn,
1515         print_insn_aarch64_word, print_insn_data): Take errors struct.
1516         (print_insn_aarch64): Use errors.
1517         * aarch64-asm-2.c: Regenerate.
1518         * aarch64-dis-2.c: Regenerate.
1519         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1520         boolean in aarch64_insert_operan.
1521         (print_operand_extractor): Likewise.
1522         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1523
1524 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1525
1526         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1527
1528 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1529
1530         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1531
1532 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1533
1534         * cr16-opc.c (cr16_instruction): Comment typo fix.
1535         * hppa-dis.c (print_insn_hppa): Likewise.
1536
1537 2018-05-08  Jim Wilson  <jimw@sifive.com>
1538
1539         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1540         (match_c_slli64, match_srxi_as_c_srxi): New.
1541         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1542         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1543         <c.slli, c.srli, c.srai>: Use match_s_slli.
1544         <c.slli64, c.srli64, c.srai64>: New.
1545
1546 2018-05-08  Alan Modra  <amodra@gmail.com>
1547
1548         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1549         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1550         partition opcode space for index lookup.
1551
1552 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1553
1554         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1555         <insn_length>: ...with this.  Update usage.
1556         Remove duplicate call to *info->memory_error_func.
1557
1558 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1559             H.J. Lu  <hongjiu.lu@intel.com>
1560
1561         * i386-dis.c (Gva): New.
1562         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1563         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1564         (prefix_table): New instructions (see prefix above).
1565         (mod_table): New instructions (see prefix above).
1566         (OP_G): Handle va_mode.
1567         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1568         CPU_MOVDIR64B_FLAGS.
1569         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1570         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1571         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1572         * i386-opc.tbl: Add movidir{i,64b}.
1573         * i386-init.h: Regenerated.
1574         * i386-tbl.h: Likewise.
1575
1576 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1577
1578         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1579         AddrPrefixOpReg.
1580         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1581         (AddrPrefixOpReg): This.
1582         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1583         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1584
1585 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1586
1587         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1588         (vle_num_opcodes): Likewise.
1589         (spe2_num_opcodes): Likewise.
1590         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1591         initialization loop.
1592         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1593         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1594         only once.
1595
1596 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1597
1598         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1599
1600 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1601
1602         Makefile.am: Added nfp-dis.c.
1603         configure.ac: Added bfd_nfp_arch.
1604         disassemble.h: Added print_insn_nfp prototype.
1605         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1606         nfp-dis.c: New, for NFP support.
1607         po/POTFILES.in: Added nfp-dis.c to the list.
1608         Makefile.in: Regenerate.
1609         configure: Regenerate.
1610
1611 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1612
1613         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1614         templates into their base ones.
1615         * i386-tlb.h: Re-generate.
1616
1617 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1618
1619         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1620         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1621         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1622         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1623         * i386-init.h: Re-generate.
1624
1625 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1626
1627         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1628         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1629         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1630         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1631         comment.
1632         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1633         and CpuRegMask.
1634         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1635         CpuRegMask: Delete.
1636         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1637         cpuregzmm, and cpuregmask.
1638         * i386-init.h: Re-generate.
1639         * i386-tbl.h: Re-generate.
1640
1641 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1642
1643         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1644         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1645         * i386-init.h: Re-generate.
1646
1647 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1648
1649         * i386-gen.c (VexImmExt): Delete.
1650         * i386-opc.h (VexImmExt, veximmext): Delete.
1651         * i386-opc.tbl: Drop all VexImmExt uses.
1652         * i386-tlb.h: Re-generate.
1653
1654 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1655
1656         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1657         register-only forms.
1658         * i386-tlb.h: Re-generate.
1659
1660 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1661
1662         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1663
1664 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1665
1666         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1667         PREFIX_0F1C.
1668         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1669         (cpu_flags): Add CpuCLDEMOTE.
1670         * i386-init.h: Regenerate.
1671         * i386-opc.h (enum): Add CpuCLDEMOTE,
1672         (i386_cpu_flags): Add cpucldemote.
1673         * i386-opc.tbl: Add cldemote.
1674         * i386-tbl.h: Regenerate.
1675
1676 2018-04-16  Alan Modra  <amodra@gmail.com>
1677
1678         * Makefile.am: Remove sh5 and sh64 support.
1679         * configure.ac: Likewise.
1680         * disassemble.c: Likewise.
1681         * disassemble.h: Likewise.
1682         * sh-dis.c: Likewise.
1683         * sh64-dis.c: Delete.
1684         * sh64-opc.c: Delete.
1685         * sh64-opc.h: Delete.
1686         * Makefile.in: Regenerate.
1687         * configure: Regenerate.
1688         * po/POTFILES.in: Regenerate.
1689
1690 2018-04-16  Alan Modra  <amodra@gmail.com>
1691
1692         * Makefile.am: Remove w65 support.
1693         * configure.ac: Likewise.
1694         * disassemble.c: Likewise.
1695         * disassemble.h: Likewise.
1696         * w65-dis.c: Delete.
1697         * w65-opc.h: Delete.
1698         * Makefile.in: Regenerate.
1699         * configure: Regenerate.
1700         * po/POTFILES.in: Regenerate.
1701
1702 2018-04-16  Alan Modra  <amodra@gmail.com>
1703
1704         * configure.ac: Remove we32k support.
1705         * configure: Regenerate.
1706
1707 2018-04-16  Alan Modra  <amodra@gmail.com>
1708
1709         * Makefile.am: Remove m88k support.
1710         * configure.ac: Likewise.
1711         * disassemble.c: Likewise.
1712         * disassemble.h: Likewise.
1713         * m88k-dis.c: Delete.
1714         * Makefile.in: Regenerate.
1715         * configure: Regenerate.
1716         * po/POTFILES.in: Regenerate.
1717
1718 2018-04-16  Alan Modra  <amodra@gmail.com>
1719
1720         * Makefile.am: Remove i370 support.
1721         * configure.ac: Likewise.
1722         * disassemble.c: Likewise.
1723         * disassemble.h: Likewise.
1724         * i370-dis.c: Delete.
1725         * i370-opc.c: Delete.
1726         * Makefile.in: Regenerate.
1727         * configure: Regenerate.
1728         * po/POTFILES.in: Regenerate.
1729
1730 2018-04-16  Alan Modra  <amodra@gmail.com>
1731
1732         * Makefile.am: Remove h8500 support.
1733         * configure.ac: Likewise.
1734         * disassemble.c: Likewise.
1735         * disassemble.h: Likewise.
1736         * h8500-dis.c: Delete.
1737         * h8500-opc.h: Delete.
1738         * Makefile.in: Regenerate.
1739         * configure: Regenerate.
1740         * po/POTFILES.in: Regenerate.
1741
1742 2018-04-16  Alan Modra  <amodra@gmail.com>
1743
1744         * configure.ac: Remove tahoe support.
1745         * configure: Regenerate.
1746
1747 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1748
1749         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1750         umwait.
1751         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1752         64-bit mode.
1753         * i386-tbl.h: Regenerated.
1754
1755 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1756
1757         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1758         PREFIX_MOD_1_0FAE_REG_6.
1759         (va_mode): New.
1760         (OP_E_register): Use va_mode.
1761         * i386-dis-evex.h (prefix_table):
1762         New instructions (see prefixes above).
1763         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1764         (cpu_flags): Likewise.
1765         * i386-opc.h (enum): Likewise.
1766         (i386_cpu_flags): Likewise.
1767         * i386-opc.tbl: Add umonitor, umwait, tpause.
1768         * i386-init.h: Regenerate.
1769         * i386-tbl.h: Likewise.
1770
1771 2018-04-11  Alan Modra  <amodra@gmail.com>
1772
1773         * opcodes/i860-dis.c: Delete.
1774         * opcodes/i960-dis.c: Delete.
1775         * Makefile.am: Remove i860 and i960 support.
1776         * configure.ac: Likewise.
1777         * disassemble.c: Likewise.
1778         * disassemble.h: Likewise.
1779         * Makefile.in: Regenerate.
1780         * configure: Regenerate.
1781         * po/POTFILES.in: Regenerate.
1782
1783 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1784
1785         PR binutils/23025
1786         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1787         to 0.
1788         (print_insn): Clear vex instead of vex.evex.
1789
1790 2018-04-04  Nick Clifton  <nickc@redhat.com>
1791
1792         * po/es.po: Updated Spanish translation.
1793
1794 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1795
1796         * i386-gen.c (opcode_modifiers): Delete VecESize.
1797         * i386-opc.h (VecESize): Delete.
1798         (struct i386_opcode_modifier): Delete vecesize.
1799         * i386-opc.tbl: Drop VecESize.
1800         * i386-tlb.h: Re-generate.
1801
1802 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1803
1804         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1805         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1806         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1807         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1808         * i386-tlb.h: Re-generate.
1809
1810 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1811
1812         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1813         Fold AVX512 forms
1814         * i386-tlb.h: Re-generate.
1815
1816 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1817
1818         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1819         (vex_len_table): Drop Y for vcvt*2si.
1820         (putop): Replace plain 'Y' handling by abort().
1821
1822 2018-03-28  Nick Clifton  <nickc@redhat.com>
1823
1824         PR 22988
1825         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1826         instructions with only a base address register.
1827         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1828         handle AARHC64_OPND_SVE_ADDR_R.
1829         (aarch64_print_operand): Likewise.
1830         * aarch64-asm-2.c: Regenerate.
1831         * aarch64_dis-2.c: Regenerate.
1832         * aarch64-opc-2.c: Regenerate.
1833
1834 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1835
1836         * i386-opc.tbl: Drop VecESize from register only insn forms and
1837         memory forms not allowing broadcast.
1838         * i386-tlb.h: Re-generate.
1839
1840 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1841
1842         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1843         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1844         sha256*): Drop Disp<N>.
1845
1846 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1847
1848         * i386-dis.c (EbndS, bnd_swap_mode): New.
1849         (prefix_table): Use EbndS.
1850         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1851         * i386-opc.tbl (bndmov): Move misplaced Load.
1852         * i386-tlb.h: Re-generate.
1853
1854 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1855
1856         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1857         templates allowing memory operands and folded ones for register
1858         only flavors.
1859         * i386-tlb.h: Re-generate.
1860
1861 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1862
1863         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1864         256-bit templates. Drop redundant leftover Disp<N>.
1865         * i386-tlb.h: Re-generate.
1866
1867 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1868
1869         * riscv-opc.c (riscv_insn_types): New.
1870
1871 2018-03-13  Nick Clifton  <nickc@redhat.com>
1872
1873         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1874
1875 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1876
1877         * i386-opc.tbl: Add Optimize to clr.
1878         * i386-tbl.h: Regenerated.
1879
1880 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1881
1882         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1883         * i386-opc.h (OldGcc): Removed.
1884         (i386_opcode_modifier): Remove oldgcc.
1885         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1886         instructions for old (<= 2.8.1) versions of gcc.
1887         * i386-tbl.h: Regenerated.
1888
1889 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1890
1891         * i386-opc.h (EVEXDYN): New.
1892         * i386-opc.tbl: Fold various AVX512VL templates.
1893         * i386-tlb.h: Re-generate.
1894
1895 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1896
1897         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1898         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1899         vpexpandd, vpexpandq): Fold AFX512VF templates.
1900         * i386-tlb.h: Re-generate.
1901
1902 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1903
1904         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1905         Fold 128- and 256-bit VEX-encoded templates.
1906         * i386-tlb.h: Re-generate.
1907
1908 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1909
1910         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1911         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1912         vpexpandd, vpexpandq): Fold AVX512F templates.
1913         * i386-tlb.h: Re-generate.
1914
1915 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1916
1917         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1918         64-bit templates. Drop Disp<N>.
1919         * i386-tlb.h: Re-generate.
1920
1921 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1922
1923         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1924         and 256-bit templates.
1925         * i386-tlb.h: Re-generate.
1926
1927 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1928
1929         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1930         * i386-tlb.h: Re-generate.
1931
1932 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1933
1934         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1935         Drop NoAVX.
1936         * i386-tlb.h: Re-generate.
1937
1938 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1939
1940         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1941         * i386-tlb.h: Re-generate.
1942
1943 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1944
1945         * i386-gen.c (opcode_modifiers): Delete FloatD.
1946         * i386-opc.h (FloatD): Delete.
1947         (struct i386_opcode_modifier): Delete floatd.
1948         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1949         FloatD by D.
1950         * i386-tlb.h: Re-generate.
1951
1952 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1953
1954         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1955
1956 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1957
1958         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1959         * i386-tlb.h: Re-generate.
1960
1961 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1962
1963         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1964         forms.
1965         * i386-tlb.h: Re-generate.
1966
1967 2018-03-07  Alan Modra  <amodra@gmail.com>
1968
1969         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1970         bfd_arch_rs6000.
1971         * disassemble.h (print_insn_rs6000): Delete.
1972         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1973         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1974         (print_insn_rs6000): Delete.
1975
1976 2018-03-03  Alan Modra  <amodra@gmail.com>
1977
1978         * sysdep.h (opcodes_error_handler): Define.
1979         (_bfd_error_handler): Declare.
1980         * Makefile.am: Remove stray #.
1981         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1982         EDIT" comment.
1983         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1984         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1985         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1986         opcodes_error_handler to print errors.  Standardize error messages.
1987         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1988         and include opintl.h.
1989         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1990         * i386-gen.c: Standardize error messages.
1991         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1992         * Makefile.in: Regenerate.
1993         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1994         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1995         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1996         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1997         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1998         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1999         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2000         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2001         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2002         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2003         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2004         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2005         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2006
2007 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2008
2009         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2010         vpsub[bwdq] instructions.
2011         * i386-tbl.h: Regenerated.
2012
2013 2018-03-01  Alan Modra  <amodra@gmail.com>
2014
2015         * configure.ac (ALL_LINGUAS): Sort.
2016         * configure: Regenerate.
2017
2018 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2019
2020         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2021         macro by assignements.
2022
2023 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2024
2025         PR gas/22871
2026         * i386-gen.c (opcode_modifiers): Add Optimize.
2027         * i386-opc.h (Optimize): New enum.
2028         (i386_opcode_modifier): Add optimize.
2029         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2030         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2031         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2032         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2033         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2034         vpxord and vpxorq.
2035         * i386-tbl.h: Regenerated.
2036
2037 2018-02-26  Alan Modra  <amodra@gmail.com>
2038
2039         * crx-dis.c (getregliststring): Allocate a large enough buffer
2040         to silence false positive gcc8 warning.
2041
2042 2018-02-22  Shea Levy <shea@shealevy.com>
2043
2044         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2045
2046 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2047
2048         * i386-opc.tbl: Add {rex},
2049         * i386-tbl.h: Regenerated.
2050
2051 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2052
2053         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2054         (mips16_opcodes): Replace `M' with `m' for "restore".
2055
2056 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2057
2058         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2059
2060 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2061
2062         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2063         variable to `function_index'.
2064
2065 2018-02-13  Nick Clifton  <nickc@redhat.com>
2066
2067         PR 22823
2068         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2069         about truncation of printing.
2070
2071 2018-02-12  Henry Wong <henry@stuffedcow.net>
2072
2073         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2074
2075 2018-02-05  Nick Clifton  <nickc@redhat.com>
2076
2077         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2078
2079 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2080
2081         * i386-dis.c (enum): Add pconfig.
2082         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2083         (cpu_flags): Add CpuPCONFIG.
2084         * i386-opc.h (enum): Add CpuPCONFIG.
2085         (i386_cpu_flags): Add cpupconfig.
2086         * i386-opc.tbl: Add PCONFIG instruction.
2087         * i386-init.h: Regenerate.
2088         * i386-tbl.h: Likewise.
2089
2090 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2091
2092         * i386-dis.c (enum): Add PREFIX_0F09.
2093         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2094         (cpu_flags): Add CpuWBNOINVD.
2095         * i386-opc.h (enum): Add CpuWBNOINVD.
2096         (i386_cpu_flags): Add cpuwbnoinvd.
2097         * i386-opc.tbl: Add WBNOINVD instruction.
2098         * i386-init.h: Regenerate.
2099         * i386-tbl.h: Likewise.
2100
2101 2018-01-17  Jim Wilson  <jimw@sifive.com>
2102
2103         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2104
2105 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2106
2107         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2108         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2109         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2110         (cpu_flags): Add CpuIBT, CpuSHSTK.
2111         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2112         (i386_cpu_flags): Add cpuibt, cpushstk.
2113         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2114         * i386-init.h: Regenerate.
2115         * i386-tbl.h: Likewise.
2116
2117 2018-01-16  Nick Clifton  <nickc@redhat.com>
2118
2119         * po/pt_BR.po: Updated Brazilian Portugese translation.
2120         * po/de.po: Updated German translation.
2121
2122 2018-01-15  Jim Wilson  <jimw@sifive.com>
2123
2124         * riscv-opc.c (match_c_nop): New.
2125         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2126
2127 2018-01-15  Nick Clifton  <nickc@redhat.com>
2128
2129         * po/uk.po: Updated Ukranian translation.
2130
2131 2018-01-13  Nick Clifton  <nickc@redhat.com>
2132
2133         * po/opcodes.pot: Regenerated.
2134
2135 2018-01-13  Nick Clifton  <nickc@redhat.com>
2136
2137         * configure: Regenerate.
2138
2139 2018-01-13  Nick Clifton  <nickc@redhat.com>
2140
2141         2.30 branch created.
2142
2143 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2144
2145         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2146         * i386-tbl.h: Regenerate.
2147
2148 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2149
2150         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2151         * i386-tbl.h: Re-generate.
2152
2153 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2154
2155         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2156         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2157         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2158         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2159         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2160         Disp8MemShift of AVX512VL forms.
2161         * i386-tbl.h: Re-generate.
2162
2163 2018-01-09  Jim Wilson  <jimw@sifive.com>
2164
2165         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2166         then the hi_addr value is zero.
2167
2168 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2169
2170         * arm-dis.c (arm_opcodes): Add csdb.
2171         (thumb32_opcodes): Add csdb.
2172
2173 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2174
2175         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2176         * aarch64-asm-2.c: Regenerate.
2177         * aarch64-dis-2.c: Regenerate.
2178         * aarch64-opc-2.c: Regenerate.
2179
2180 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2181
2182         PR gas/22681
2183         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2184         Remove AVX512 vmovd with 64-bit operands.
2185         * i386-tbl.h: Regenerated.
2186
2187 2018-01-05  Jim Wilson  <jimw@sifive.com>
2188
2189         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2190         jalr.
2191
2192 2018-01-03  Alan Modra  <amodra@gmail.com>
2193
2194         Update year range in copyright notice of all files.
2195
2196 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2197
2198         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2199         and OPERAND_TYPE_REGZMM entries.
2200
2201 For older changes see ChangeLog-2017
2202 \f
2203 Copyright (C) 2018 Free Software Foundation, Inc.
2204
2205 Copying and distribution of this file, with or without modification,
2206 are permitted in any medium without royalty provided the copyright
2207 notice and this notice are preserved.
2208
2209 Local Variables:
2210 mode: change-log
2211 left-margin: 8
2212 fill-column: 74
2213 version-control: never
2214 End: