opcodes/ChangeLog

   1 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
   4         immediate operands.
   5         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
   6         * aarch64-opc.c (fields): Add corresponding entry.
   7         (operand_general_constraint_met_p): Handle the new SVE FP immediate
   8         operands.
   9         (aarch64_print_operand): Likewise.
  10         * aarch64-opc-2.c: Regenerate.
  11         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
  12         (ins_sve_float_zero_one): New inserters.
  13         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
  14         (aarch64_ins_sve_float_half_two): Likewise.
  15         (aarch64_ins_sve_float_zero_one): Likewise.
  16         * aarch64-asm-2.c: Regenerate.
  17         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
  18         (ext_sve_float_zero_one): New extractors.
  19         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
  20         (aarch64_ext_sve_float_half_two): Likewise.
  21         (aarch64_ext_sve_float_zero_one): Likewise.
  22         * aarch64-dis-2.c: Regenerate.
  23
  24 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  25
  26         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
  27         integer immediate operands.
  28         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
  29         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
  30         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
  31         * aarch64-opc.c (fields): Add corresponding entries.
  32         (operand_general_constraint_met_p): Handle the new SVE integer
  33         immediate operands.
  34         (aarch64_print_operand): Likewise.
  35         (aarch64_sve_dupm_mov_immediate_p): New function.
  36         * aarch64-opc-2.c: Regenerate.
  37         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
  38         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
  39         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
  40         (aarch64_ins_limm): ...here.
  41         (aarch64_ins_inv_limm): New function.
  42         (aarch64_ins_sve_aimm): Likewise.
  43         (aarch64_ins_sve_asimm): Likewise.
  44         (aarch64_ins_sve_limm_mov): Likewise.
  45         (aarch64_ins_sve_shlimm): Likewise.
  46         (aarch64_ins_sve_shrimm): Likewise.
  47         * aarch64-asm-2.c: Regenerate.
  48         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
  49         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
  50         * aarch64-dis.c (decode_limm): New function, split out from...
  51         (aarch64_ext_limm): ...here.
  52         (aarch64_ext_inv_limm): New function.
  53         (decode_sve_aimm): Likewise.
  54         (aarch64_ext_sve_aimm): Likewise.
  55         (aarch64_ext_sve_asimm): Likewise.
  56         (aarch64_ext_sve_limm_mov): Likewise.
  57         (aarch64_top_bit): Likewise.
  58         (aarch64_ext_sve_shlimm): Likewise.
  59         (aarch64_ext_sve_shrimm): Likewise.
  60         * aarch64-dis-2.c: Regenerate.
  61
  62 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  63
  64         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
  65         operands.
  66         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
  67         the AARCH64_MOD_MUL_VL entry.
  68         (value_aligned_p): Cope with non-power-of-two alignments.
  69         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
  70         (print_immediate_offset_address): Likewise.
  71         (aarch64_print_operand): Likewise.
  72         * aarch64-opc-2.c: Regenerate.
  73         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
  74         (ins_sve_addr_ri_s9xvl): New inserters.
  75         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
  76         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
  77         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
  78         * aarch64-asm-2.c: Regenerate.
  79         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
  80         (ext_sve_addr_ri_s9xvl): New extractors.
  81         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
  82         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
  83         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
  84         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
  85         * aarch64-dis-2.c: Regenerate.
  86
  87 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  88
  89         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
  90         address operands.
  91         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
  92         (FLD_SVE_xs_22): New aarch64_field_kinds.
  93         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
  94         (get_operand_specific_data): New function.
  95         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
  96         FLD_SVE_xs_14 and FLD_SVE_xs_22.
  97         (operand_general_constraint_met_p): Handle the new SVE address
  98         operands.
  99         (sve_reg): New array.
 100         (get_addr_sve_reg_name): New function.
 101         (aarch64_print_operand): Handle the new SVE address operands.
 102         * aarch64-opc-2.c: Regenerate.
 103         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 104         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 105         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 106         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 107         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 108         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 109         (aarch64_ins_sve_addr_zi_u5): Likewise.
 110         (aarch64_ins_sve_addr_zz): Likewise.
 111         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 112         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 113         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 114         * aarch64-asm-2.c: Regenerate.
 115         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 116         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 117         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 118         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 119         (aarch64_ext_sve_addr_ri_u6): Likewise.
 120         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 121         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 122         (aarch64_ext_sve_addr_zi_u5): Likewise.
 123         (aarch64_ext_sve_addr_zz): Likewise.
 124         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 125         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 126         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 127         * aarch64-dis-2.c: Regenerate.
 128
 129 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 130
 131         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 132         AARCH64_OPND_SVE_PATTERN_SCALED.
 133         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 134         * aarch64-opc.c (fields): Add a corresponding entry.
 135         (set_multiplier_out_of_range_error): New function.
 136         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 137         (operand_general_constraint_met_p): Handle
 138         AARCH64_OPND_SVE_PATTERN_SCALED.
 139         (print_register_offset_address): Use PRIi64 to print the
 140         shift amount.
 141         (aarch64_print_operand): Likewise.  Handle
 142         AARCH64_OPND_SVE_PATTERN_SCALED.
 143         * aarch64-opc-2.c: Regenerate.
 144         * aarch64-asm.h (ins_sve_scale): New inserter.
 145         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 146         * aarch64-asm-2.c: Regenerate.
 147         * aarch64-dis.h (ext_sve_scale): New inserter.
 148         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 149         * aarch64-dis-2.c: Regenerate.
 150
 151 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 152
 153         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 154         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 155         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 156         (FLD_SVE_prfop): Likewise.
 157         * aarch64-opc.c: Include libiberty.h.
 158         (aarch64_sve_pattern_array): New variable.
 159         (aarch64_sve_prfop_array): Likewise.
 160         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 161         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 162         AARCH64_OPND_SVE_PRFOP.
 163         * aarch64-asm-2.c: Regenerate.
 164         * aarch64-dis-2.c: Likewise.
 165         * aarch64-opc-2.c: Likewise.
 166
 167 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 168
 169         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 170         AARCH64_OPND_QLF_P_[ZM].
 171         (aarch64_print_operand): Print /z and /m where appropriate.
 172
 173 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 174
 175         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 176         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 177         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 178         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 179         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 180         * aarch64-opc.c (fields): Add corresponding entries here.
 181         (operand_general_constraint_met_p): Check that SVE register lists
 182         have the correct length.  Check the ranges of SVE index registers.
 183         Check for cases where p8-p15 are used in 3-bit predicate fields.
 184         (aarch64_print_operand): Handle the new SVE operands.
 185         * aarch64-opc-2.c: Regenerate.
 186         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 187         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 188         (aarch64_ins_sve_reglist): Likewise.
 189         * aarch64-asm-2.c: Regenerate.
 190         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 191         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 192         (aarch64_ext_sve_reglist): Likewise.
 193         * aarch64-dis-2.c: Regenerate.
 194
 195 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 196
 197         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 198         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 199         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 200         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 201         tied operands.
 202
 203 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 204
 205         * aarch64-opc.c (get_offset_int_reg_name): New function.
 206         (print_immediate_offset_address): Likewise.
 207         (print_register_offset_address): Take the base and offset
 208         registers as parameters.
 209         (aarch64_print_operand): Update caller accordingly.  Use
 210         print_immediate_offset_address.
 211
 212 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 213
 214         * aarch64-opc.c (BANK): New macro.
 215         (R32, R64): Take a register number as argument
 216         (int_reg): Use BANK.
 217
 218 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 219
 220         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 221         (aarch64_print_operand): Update accordingly.
 222
 223 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 224
 225         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 226         for FPIMM.
 227         * aarch64-asm.h (ins_fpimm): New inserter.
 228         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 229         * aarch64-asm-2.c: Regenerate.
 230         * aarch64-dis.h (ext_fpimm): New extractor.
 231         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 232         (aarch64_ext_fpimm): New function.
 233         * aarch64-dis-2.c: Regenerate.
 234
 235 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 236
 237         * aarch64-asm.c: Include libiberty.h.
 238         (insert_fields): New function.
 239         (aarch64_ins_imm): Use it.
 240         * aarch64-dis.c (extract_fields): New function.
 241         (aarch64_ext_imm): Use it.
 242
 243 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 244
 245         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 246         with an esize parameter.
 247         (operand_general_constraint_met_p): Update accordingly.
 248         Fix misindented code.
 249         * aarch64-asm.c (aarch64_ins_limm): Update call to
 250         aarch64_logical_immediate_p.
 251
 252 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 253
 254         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 255
 256 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 257
 258         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 259
 260 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 261
 262         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 263
 264 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 265
 266         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 267         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 268         xor3>: Delete mnemonics.
 269         <cp_abort>: Rename mnemonic from ...
 270         <cpabort>: ...to this.
 271         <setb>: Change to a X form instruction.
 272         <sync>: Change to 1 operand form.
 273         <copy>: Delete mnemonic.
 274         <copy_first>: Rename mnemonic from ...
 275         <copy>: ...to this.
 276         <paste, paste.>: Delete mnemonics.
 277         <paste_last>: Rename mnemonic from ...
 278         <paste.>: ...to this.
 279
 280 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 281
 282         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 283
 284 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 285
 286         * s390-mkopc.c (main): Support alternate arch strings.
 287
 288 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 289
 290         * s390-opc.txt: Fix kmctr instruction type.
 291
 292 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 295         * i386-init.h: Regenerated.
 296
 297 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 298
 299         * opcodes/arc-dis.c (print_insn_arc): Changed.
 300
 301 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 302
 303         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 304         camellia_fl.
 305
 306 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 307
 308         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 309         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 310         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 311
 312 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 313
 314         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 315         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 316         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 317         PREFIX_MOD_3_0FAE_REG_4.
 318         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 319         PREFIX_MOD_3_0FAE_REG_4.
 320         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 321         (cpu_flags): Add CpuPTWRITE.
 322         * i386-opc.h (CpuPTWRITE): New.
 323         (i386_cpu_flags): Add cpuptwrite.
 324         * i386-opc.tbl: Add ptwrite instruction.
 325         * i386-init.h: Regenerated.
 326         * i386-tbl.h: Likewise.
 327
 328 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 329
 330         * arc-dis.h: Wrap around in extern "C".
 331
 332 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 333
 334         * aarch64-tbl.h (V8_2_INSN): New macro.
 335         (aarch64_opcode_table): Use it.
 336
 337 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 338
 339         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 340         CORE_INSN, __FP_INSN and SIMD_INSN.
 341
 342 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 343
 344         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 345         (aarch64_opcode_table): Update uses accordingly.
 346
 347 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 348         Kwok Cheung Yeung  <kcy@codesourcery.com>
 349
 350         opcodes/
 351         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 352         'e_cmplwi' to 'e_cmpli' instead.
 353         (OPVUPRT, OPVUPRT_MASK): Define.
 354         (powerpc_opcodes): Add E200Z4 insns.
 355         (vle_opcodes): Add context save/restore insns.
 356
 357 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 358
 359         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 360         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 361         "j".
 362
 363 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 364
 365         * arc-nps400-tbl.h: Change block comments to GNU format.
 366         * arc-dis.c: Add new globals addrtypenames,
 367         addrtypenames_max, and addtypeunknown.
 368         (get_addrtype): New function.
 369         (print_insn_arc): Print colons and address types when
 370         required.
 371         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 372         define insert and extract functions for all address types.
 373         (arc_operands): Add operands for colon and all address
 374         types.
 375         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 376         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 377         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 378         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 379         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 380         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 381
 382 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         * configure: Regenerated.
 385
 386 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 387
 388         * arc-dis.c (skipclass): New structure.
 389         (decodelist): New variable.
 390         (is_compatible_p): New function.
 391         (new_element): Likewise.
 392         (skip_class_p): Likewise.
 393         (find_format_from_table): Use skip_class_p function.
 394         (find_format): Decode first the extension instructions.
 395         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 396         e_flags.
 397         (parse_option): New function.
 398         (parse_disassembler_options): Likewise.
 399         (print_arc_disassembler_options): Likewise.
 400         (print_insn_arc): Use parse_disassembler_options function.  Proper
 401         select ARCv2 cpu variant.
 402         * disassemble.c (disassembler_usage): Add ARC disassembler
 403         options.
 404
 405 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 406
 407         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 408         annotation from the "nal" entry and reorder it beyond "bltzal".
 409
 410 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 411
 412         * sparc-opc.c (ldtxa): New macro.
 413         (sparc_opcodes): Use the macro defined above to add entries for
 414         the LDTXA instructions.
 415         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 416         instruction.
 417
 418 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 419
 420         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 421         and "jmpc".
 422
 423 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 424
 425         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 426         (movzb): Adjust to cover all permitted suffixes.
 427         (movzw): New.
 428         * i386-tbl.h: Re-generate.
 429
 430 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 431
 432         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 433         (lgdt): Remove Tbyte from non-64-bit variant.
 434         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 435         xsaves64, xsavec64): Remove Disp16.
 436         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 437         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 438         64-bit variants.
 439         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 440         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 441         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 442         64-bit variants.
 443         * i386-tbl.h: Re-generate.
 444
 445 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 446
 447         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 448         * i386-tbl.h: Re-generate.
 449
 450 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 451
 452         * arm-dis.c (print_insn): Fix typo in comment.
 453
 454 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 455
 456         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 457         range of ldst_elemlist operands.
 458         (print_register_list): Use PRIi64 to print the index.
 459         (aarch64_print_operand): Likewise.
 460
 461 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 462
 463         * mcore-opc.h: Remove sentinal.
 464         * mcore-dis.c (print_insn_mcore): Adjust.
 465
 466 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 467
 468         * arc-opc.c: Correct description of availability of NPS400
 469         features.
 470
 471 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 472
 473         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 474         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 475         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 476         xor3>: New mnemonics.
 477         <setb>: Change to a VX form instruction.
 478         (insert_sh6): Add support for rldixor.
 479         (extract_sh6): Likewise.
 480
 481 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 482
 483         * arc-ext.h: Wrap in extern C.
 484
 485 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 486
 487         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 488         Use same method for determining instruction length on ARC700 and
 489         NPS-400.
 490         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 491         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 492         with the NPS400 subclass.
 493         * arc-opc.c: Likewise.
 494
 495 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 496
 497         * sparc-opc.c (rdasr): New macro.
 498         (wrasr): Likewise.
 499         (rdpr): Likewise.
 500         (wrpr): Likewise.
 501         (rdhpr): Likewise.
 502         (wrhpr): Likewise.
 503         (sparc_opcodes): Use the macros above to fix and expand the
 504         definition of read/write instructions from/to
 505         asr/privileged/hyperprivileged instructions.
 506         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 507         %hva_mask_nz.  Prefer softint_set and softint_clear over
 508         set_softint and clear_softint.
 509         (print_insn_sparc): Support %ver in Rd.
 510
 511 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 512
 513         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 514         architecture according to the hardware capabilities they require.
 515
 516 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 517
 518         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 519         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 520         bfd_mach_sparc_v9{c,d,e,v,m}.
 521         * sparc-opc.c (MASK_V9C): Define.
 522         (MASK_V9D): Likewise.
 523         (MASK_V9E): Likewise.
 524         (MASK_V9V): Likewise.
 525         (MASK_V9M): Likewise.
 526         (v6): Add MASK_V9{C,D,E,V,M}.
 527         (v6notlet): Likewise.
 528         (v7): Likewise.
 529         (v8): Likewise.
 530         (v9): Likewise.
 531         (v9andleon): Likewise.
 532         (v9a): Likewise.
 533         (v9b): Likewise.
 534         (v9c): Define.
 535         (v9d): Likewise.
 536         (v9e): Likewise.
 537         (v9v): Likewise.
 538         (v9m): Likewise.
 539         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 540
 541 2016-06-15  Nick Clifton  <nickc@redhat.com>
 542
 543         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 544         constants to match expected behaviour.
 545         (nds32_parse_opcode): Likewise.  Also for whitespace.
 546
 547 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 548
 549         * arc-opc.c (extract_rhv1): Extract value from insn.
 550
 551 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 552
 553         * arc-nps400-tbl.h: Add ldbit instruction.
 554         * arc-opc.c: Add flag classes required for ldbit.
 555
 556 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 557
 558         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 559         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 560         support the above instructions.
 561
 562 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 563
 564         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 565         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 566         csma, cbba, zncv, and hofs.
 567         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 568         support the above instructions.
 569
 570 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 571
 572         * arc-nps400-tbl.h: Add andab and orab instructions.
 573
 574 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 575
 576         * arc-nps400-tbl.h: Add addl-like instructions.
 577
 578 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 579
 580         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 581
 582 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 583
 584         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 585         instructions.
 586
 587 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 588
 589         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 590         variable.
 591         (init_disasm): Handle new command line option "insnlength".
 592         (print_s390_disassembler_options): Mention new option in help
 593         output.
 594         (print_insn_s390): Use the encoded insn length when dumping
 595         unknown instructions.
 596
 597 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 598
 599         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 600          to the address and set as symbol address for LDS/ STS immediate operands.
 601
 602 2016-06-07  Alan Modra  <amodra@gmail.com>
 603
 604         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 605         cpu for "vle" to e500.
 606         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 607         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 608         (PPCNONE): Delete, substitute throughout.
 609         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 610         except for major opcode 4 and 31.
 611         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 612
 613 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 614
 615         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 616         ARM_EXT_RAS in relevant entries.
 617
 618 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 619
 620         PR binutils/20196
 621         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 622         opcodes for E6500.
 623
 624 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 625
 626         PR binutis/18386
 627         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 628         (indir_v_mode): New.
 629         Add comments for '&'.
 630         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 631         (putop): Handle '&'.
 632         (intel_operand_size): Handle indir_v_mode.
 633         (OP_E_register): Likewise.
 634         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 635         64-bit indirect call/jmp for AMD64.
 636         * i386-tbl.h: Regenerated
 637
 638 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 639
 640         * arc-dis.c (struct arc_operand_iterator): New structure.
 641         (find_format_from_table): All the old content from find_format,
 642         with some minor adjustments, and parameter renaming.
 643         (find_format_long_instructions): New function.
 644         (find_format): Rewritten.
 645         (arc_insn_length): Add LSB parameter.
 646         (extract_operand_value): New function.
 647         (operand_iterator_next): New function.
 648         (print_insn_arc): Use new functions to find opcode, and iterator
 649         over operands.
 650         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 651         (extract_nps_3bit_dst_short): New function.
 652         (insert_nps_3bit_src2_short): New function.
 653         (extract_nps_3bit_src2_short): New function.
 654         (insert_nps_bitop1_size): New function.
 655         (extract_nps_bitop1_size): New function.
 656         (insert_nps_bitop2_size): New function.
 657         (extract_nps_bitop2_size): New function.
 658         (insert_nps_bitop_mod4_msb): New function.
 659         (extract_nps_bitop_mod4_msb): New function.
 660         (insert_nps_bitop_mod4_lsb): New function.
 661         (extract_nps_bitop_mod4_lsb): New function.
 662         (insert_nps_bitop_dst_pos3_pos4): New function.
 663         (extract_nps_bitop_dst_pos3_pos4): New function.
 664         (insert_nps_bitop_ins_ext): New function.
 665         (extract_nps_bitop_ins_ext): New function.
 666         (arc_operands): Add new operands.
 667         (arc_long_opcodes): New global array.
 668         (arc_num_long_opcodes): New global.
 669         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 670
 671 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 672
 673         * nds32-asm.h: Add extern "C".
 674         * sh-opc.h: Likewise.
 675
 676 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 677
 678         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 679         0,b,limm to the rflt instruction.
 680
 681 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 682
 683         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 684         constant.
 685
 686 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 687
 688         PR gas/20145
 689         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 690         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 691         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 692         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 693         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 694         * i386-init.h: Regenerated.
 695
 696 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 697
 698         PR gas/20145
 699         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 700         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 701         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 702         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 703         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 704         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 705         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 706         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 707         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 708         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 709         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 710         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 711         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 712         CpuRegMask for AVX512.
 713         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 714         and CpuRegMask.
 715         (set_bitfield_from_cpu_flag_init): New function.
 716         (set_bitfield): Remove const on f.  Call
 717         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 718         * i386-opc.h (CpuRegMMX): New.
 719         (CpuRegXMM): Likewise.
 720         (CpuRegYMM): Likewise.
 721         (CpuRegZMM): Likewise.
 722         (CpuRegMask): Likewise.
 723         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 724         and cpuregmask.
 725         * i386-init.h: Regenerated.
 726         * i386-tbl.h: Likewise.
 727
 728 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 729
 730         PR gas/20154
 731         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 732         (opcode_modifiers): Add AMD64 and Intel64.
 733         (main): Properly verify CpuMax.
 734         * i386-opc.h (CpuAMD64): Removed.
 735         (CpuIntel64): Likewise.
 736         (CpuMax): Set to CpuNo64.
 737         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 738         (AMD64): New.
 739         (Intel64): Likewise.
 740         (i386_opcode_modifier): Add amd64 and intel64.
 741         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 742         on call and jmp.
 743         * i386-init.h: Regenerated.
 744         * i386-tbl.h: Likewise.
 745
 746 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 747
 748         PR gas/20154
 749         * i386-gen.c (main): Fail if CpuMax is incorrect.
 750         * i386-opc.h (CpuMax): Set to CpuIntel64.
 751         * i386-tbl.h: Regenerated.
 752
 753 2016-05-27  Nick Clifton  <nickc@redhat.com>
 754
 755         PR target/20150
 756         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 757         (msp430dis_opcode_unsigned): New function.
 758         (msp430dis_opcode_signed): New function.
 759         (msp430_singleoperand): Use the new opcode reading functions.
 760         Only disassenmble bytes if they were successfully read.
 761         (msp430_doubleoperand): Likewise.
 762         (msp430_branchinstr): Likewise.
 763         (msp430x_callx_instr): Likewise.
 764         (print_insn_msp430): Check that it is safe to read bytes before
 765         attempting disassembly.  Use the new opcode reading functions.
 766
 767 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 768
 769         * ppc-opc.c (CY): New define.  Document it.
 770         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 771
 772 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 773
 774         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 775         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 776         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 777         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 778         CPU_ANY_AVX_FLAGS.
 779         * i386-init.h: Regenerated.
 780
 781 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 782
 783         PR gas/20141
 784         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 785         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 786         * i386-init.h: Regenerated.
 787
 788 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 789
 790         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 791         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 792         * i386-init.h: Regenerated.
 793
 794 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 795
 796         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 797         information.
 798         (print_insn_arc): Set insn_type information.
 799         * arc-opc.c (C_CC): Add F_CLASS_COND.
 800         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 801         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 802         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 803         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 804         (brne, brne_s, jeq_s, jne_s): Likewise.
 805
 806 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 807
 808         * arc-tbl.h (neg): New instruction variant.
 809
 810 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 811
 812         * arc-dis.c (find_format, find_format, get_auxreg)
 813         (print_insn_arc): Changed.
 814         * arc-ext.h (INSERT_XOP): Likewise.
 815
 816 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 817
 818         * tic54x-dis.c (sprint_mmr): Adjust.
 819         * tic54x-opc.c: Likewise.
 820
 821 2016-05-19  Alan Modra  <amodra@gmail.com>
 822
 823         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 824
 825 2016-05-19  Alan Modra  <amodra@gmail.com>
 826
 827         * ppc-opc.c: Formatting.
 828         (NSISIGNOPT): Define.
 829         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 830
 831 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 832
 833         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 834         replacing references to `micromips_ase' throughout.
 835         (_print_insn_mips): Don't use file-level microMIPS annotation to
 836         determine the disassembly mode with the symbol table.
 837
 838 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 839
 840         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 841
 842 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 843
 844         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 845         mips64r6.
 846         * mips-opc.c (D34): New macro.
 847         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 848
 849 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 850
 851         * i386-dis.c (prefix_table): Add RDPID instruction.
 852         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 853         (cpu_flags): Add RDPID bitfield.
 854         * i386-opc.h (enum): Add RDPID element.
 855         (i386_cpu_flags): Add RDPID field.
 856         * i386-opc.tbl: Add RDPID instruction.
 857         * i386-init.h: Regenerate.
 858         * i386-tbl.h: Regenerate.
 859
 860 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 861
 862         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 863         branch type of a symbol.
 864         (print_insn): Likewise.
 865
 866 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 867
 868         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 869         Mainline Security Extensions instructions.
 870         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 871         Extensions instructions.
 872         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 873         instructions.
 874         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 875         special registers.
 876
 877 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 878
 879         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 880
 881 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 882
 883         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 884         (arcExtMap_genOpcode): Likewise.
 885         * arc-opc.c (arg_32bit_rc): Define new variable.
 886         (arg_32bit_u6): Likewise.
 887         (arg_32bit_limm): Likewise.
 888
 889 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 890
 891         * aarch64-gen.c (VERIFIER): Define.
 892         * aarch64-opc.c (VERIFIER): Define.
 893         (verify_ldpsw): Use static linkage.
 894         * aarch64-opc.h (verify_ldpsw): Remove.
 895         * aarch64-tbl.h: Use VERIFIER for verifiers.
 896
 897 2016-04-28  Nick Clifton  <nickc@redhat.com>
 898
 899         PR target/19722
 900         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 901         * aarch64-opc.c (verify_ldpsw): New function.
 902         * aarch64-opc.h (verify_ldpsw): New prototype.
 903         * aarch64-tbl.h: Add initialiser for verifier field.
 904         (LDPSW): Set verifier to verify_ldpsw.
 905
 906 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 907
 908         PR binutils/19983
 909         PR binutils/19984
 910         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 911         smaller than address size.
 912
 913 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 914
 915         * alpha-dis.c: Regenerate.
 916         * crx-dis.c: Likewise.
 917         * disassemble.c: Likewise.
 918         * epiphany-opc.c: Likewise.
 919         * fr30-opc.c: Likewise.
 920         * frv-opc.c: Likewise.
 921         * ip2k-opc.c: Likewise.
 922         * iq2000-opc.c: Likewise.
 923         * lm32-opc.c: Likewise.
 924         * lm32-opinst.c: Likewise.
 925         * m32c-opc.c: Likewise.
 926         * m32r-opc.c: Likewise.
 927         * m32r-opinst.c: Likewise.
 928         * mep-opc.c: Likewise.
 929         * mt-opc.c: Likewise.
 930         * or1k-opc.c: Likewise.
 931         * or1k-opinst.c: Likewise.
 932         * tic80-opc.c: Likewise.
 933         * xc16x-opc.c: Likewise.
 934         * xstormy16-opc.c: Likewise.
 935
 936 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 937
 938         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 939         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 940         calcsd, and calcxd instructions.
 941         * arc-opc.c (insert_nps_bitop_size): Delete.
 942         (extract_nps_bitop_size): Delete.
 943         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 944         (extract_nps_qcmp_m3): Define.
 945         (extract_nps_qcmp_m2): Define.
 946         (extract_nps_qcmp_m1): Define.
 947         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 948         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 949         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 950         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 951         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 952         NPS_QCMP_M3.
 953
 954 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 955
 956         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 957
 958 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 959
 960         * Makefile.in: Regenerated with automake 1.11.6.
 961         * aclocal.m4: Likewise.
 962
 963 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 964
 965         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 966         instructions.
 967         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 968         (extract_nps_cmem_uimm16): New function.
 969         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 970
 971 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 972
 973         * arc-dis.c (arc_insn_length): New function.
 974         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 975         (find_format): Change insnLen parameter to unsigned.
 976
 977 2016-04-13  Nick Clifton  <nickc@redhat.com>
 978
 979         PR target/19937
 980         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 981         the LD.B and LD.BU instructions.
 982
 983 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 984
 985         * arc-dis.c (find_format): Check for extension flags.
 986         (print_flags): New function.
 987         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 988         .extAuxRegister.
 989         * arc-ext.c (arcExtMap_coreRegName): Use
 990         LAST_EXTENSION_CORE_REGISTER.
 991         (arcExtMap_coreReadWrite): Likewise.
 992         (dump_ARC_extmap): Update printing.
 993         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 994         (arc_aux_regs): Add cpu field.
 995         * arc-regs.h: Add cpu field, lower case name aux registers.
 996
 997 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 998
 999         * arc-tbl.h: Add rtsc, sleep with no arguments.
1000
1001 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1002
1003         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1004         Initialize.
1005         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1006         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1007         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1008         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1009         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1010         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1011         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1012         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1013         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1014         (arc_opcode arc_opcodes): Null terminate the array.
1015         (arc_num_opcodes): Remove.
1016         * arc-ext.h (INSERT_XOP): Define.
1017         (extInstruction_t): Likewise.
1018         (arcExtMap_instName): Delete.
1019         (arcExtMap_insn): New function.
1020         (arcExtMap_genOpcode): Likewise.
1021         * arc-ext.c (ExtInstruction): Remove.
1022         (create_map): Zero initialize instruction fields.
1023         (arcExtMap_instName): Remove.
1024         (arcExtMap_insn): New function.
1025         (dump_ARC_extmap): More info while debuging.
1026         (arcExtMap_genOpcode): New function.
1027         * arc-dis.c (find_format): New function.
1028         (print_insn_arc): Use find_format.
1029         (arc_get_disassembler): Enable dump_ARC_extmap only when
1030         debugging.
1031
1032 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1033
1034         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1035         instruction bits out.
1036
1037 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1038
1039         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1040         * arc-opc.c (arc_flag_operands): Add new flags.
1041         (arc_flag_classes): Add new classes.
1042
1043 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1044
1045         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1046
1047 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1048
1049         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1050         encode1, rflt, crc16, and crc32 instructions.
1051         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1052         (arc_flag_classes): Add C_NPS_R.
1053         (insert_nps_bitop_size_2b): New function.
1054         (extract_nps_bitop_size_2b): Likewise.
1055         (insert_nps_bitop_uimm8): Likewise.
1056         (extract_nps_bitop_uimm8): Likewise.
1057         (arc_operands): Add new operand entries.
1058
1059 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1060
1061         * arc-regs.h: Add a new subclass field.  Add double assist
1062         accumulator register values.
1063         * arc-tbl.h: Use DPA subclass to mark the double assist
1064         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1065         * arc-opc.c (RSP): Define instead of SP.
1066         (arc_aux_regs): Add the subclass field.
1067
1068 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1069
1070         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1071
1072 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1073
1074         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1075         NPS_R_SRC1.
1076
1077 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1078
1079         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1080         issues.  No functional changes.
1081
1082 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1083
1084         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1085         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1086         (RTT): Remove duplicate.
1087         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1088         (PCT_CONFIG*): Remove.
1089         (D1L, D1H, D2H, D2L): Define.
1090
1091 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1092
1093         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1094
1095 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1096
1097         * arc-tbl.h (invld07): Remove.
1098         * arc-ext-tbl.h: New file.
1099         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1100         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1101
1102 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1103
1104         Fix -Wstack-usage warnings.
1105         * aarch64-dis.c (print_operands): Substitute size.
1106         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1107
1108 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1109
1110         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1111         to get a proper diagnostic when an invalid ASR register is used.
1112
1113 2016-03-22  Nick Clifton  <nickc@redhat.com>
1114
1115         * configure: Regenerate.
1116
1117 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1118
1119         * arc-nps400-tbl.h: New file.
1120         * arc-opc.c: Add top level comment.
1121         (insert_nps_3bit_dst): New function.
1122         (extract_nps_3bit_dst): New function.
1123         (insert_nps_3bit_src2): New function.
1124         (extract_nps_3bit_src2): New function.
1125         (insert_nps_bitop_size): New function.
1126         (extract_nps_bitop_size): New function.
1127         (arc_flag_operands): Add nps400 entries.
1128         (arc_flag_classes): Add nps400 entries.
1129         (arc_operands): Add nps400 entries.
1130         (arc_opcodes): Add nps400 include.
1131
1132 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1133
1134         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1135         the new class enum values.
1136
1137 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1138
1139         * arc-dis.c (print_insn_arc): Handle nps400.
1140
1141 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1142
1143         * arc-opc.c (BASE): Delete.
1144
1145 2016-03-18  Nick Clifton  <nickc@redhat.com>
1146
1147         PR target/19721
1148         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1149         of MOV insn that aliases an ORR insn.
1150
1151 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1152
1153         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1154
1155 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1156
1157         * mcore-opc.h: Add const qualifiers.
1158         * microblaze-opc.h (struct op_code_struct): Likewise.
1159         * sh-opc.h: Likewise.
1160         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1161         (tic4x_print_op): Likewise.
1162
1163 2016-03-02  Alan Modra  <amodra@gmail.com>
1164
1165         * or1k-desc.h: Regenerate.
1166         * fr30-ibld.c: Regenerate.
1167         * rl78-decode.c: Regenerate.
1168
1169 2016-03-01  Nick Clifton  <nickc@redhat.com>
1170
1171         PR target/19747
1172         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1173
1174 2016-02-24  Renlin Li  <renlin.li@arm.com>
1175
1176         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1177         (print_insn_coprocessor): Support fp16 instructions.
1178
1179 2016-02-24  Renlin Li  <renlin.li@arm.com>
1180
1181         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1182         vminnm, vrint(mpna).
1183
1184 2016-02-24  Renlin Li  <renlin.li@arm.com>
1185
1186         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1187         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1188
1189 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1190
1191         * i386-dis.c (print_insn): Parenthesize expression to prevent
1192         truncated addresses.
1193         (OP_J): Likewise.
1194
1195 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1196             Janek van Oirschot  <jvanoirs@synopsys.com>
1197
1198         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1199         variable.
1200
1201 2016-02-04  Nick Clifton  <nickc@redhat.com>
1202
1203         PR target/19561
1204         * msp430-dis.c (print_insn_msp430): Add a special case for
1205         decoding an RRC instruction with the ZC bit set in the extension
1206         word.
1207
1208 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1209
1210         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1211         * epiphany-ibld.c: Regenerate.
1212         * fr30-ibld.c: Regenerate.
1213         * frv-ibld.c: Regenerate.
1214         * ip2k-ibld.c: Regenerate.
1215         * iq2000-ibld.c: Regenerate.
1216         * lm32-ibld.c: Regenerate.
1217         * m32c-ibld.c: Regenerate.
1218         * m32r-ibld.c: Regenerate.
1219         * mep-ibld.c: Regenerate.
1220         * mt-ibld.c: Regenerate.
1221         * or1k-ibld.c: Regenerate.
1222         * xc16x-ibld.c: Regenerate.
1223         * xstormy16-ibld.c: Regenerate.
1224
1225 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1226
1227         * epiphany-dis.c: Regenerated from latest cpu files.
1228
1229 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1230
1231         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1232         test bit.
1233
1234 2016-01-25  Renlin Li  <renlin.li@arm.com>
1235
1236         * arm-dis.c (mapping_symbol_for_insn): New function.
1237         (find_ifthen_state): Call mapping_symbol_for_insn().
1238
1239 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1240
1241         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1242         of MSR UAO immediate operand.
1243
1244 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1245
1246         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1247         instruction support.
1248
1249 2016-01-17  Alan Modra  <amodra@gmail.com>
1250
1251         * configure: Regenerate.
1252
1253 2016-01-14  Nick Clifton  <nickc@redhat.com>
1254
1255         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1256         instructions that can support stack pointer operations.
1257         * rl78-decode.c: Regenerate.
1258         * rl78-dis.c: Fix display of stack pointer in MOVW based
1259         instructions.
1260
1261 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1262
1263         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1264         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1265         erxtatus_el1 and erxaddr_el1.
1266
1267 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1268
1269         * arm-dis.c (arm_opcodes): Add "esb".
1270         (thumb_opcodes): Likewise.
1271
1272 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1273
1274         * ppc-opc.c <xscmpnedp>: Delete.
1275         <xvcmpnedp>: Likewise.
1276         <xvcmpnedp.>: Likewise.
1277         <xvcmpnesp>: Likewise.
1278         <xvcmpnesp.>: Likewise.
1279
1280 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1281
1282         PR gas/13050
1283         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1284         addition to ISA_A.
1285
1286 2016-01-01  Alan Modra  <amodra@gmail.com>
1287
1288         Update year range in copyright notice of all files.
1289
1290 For older changes see ChangeLog-2015
1291 \f
1292 Copyright (C) 2016 Free Software Foundation, Inc.
1293
1294 Copying and distribution of this file, with or without modification,
1295 are permitted in any medium without royalty provided the copyright
1296 notice and this notice are preserved.
1297
1298 Local Variables:
1299 mode: change-log
1300 left-margin: 8
1301 fill-column: 74
1302 version-control: never
1303 End: