opcodes/ChangeLog

   1 2016-12-20  Andrew Waterman  <andrew@sifive.com>
   2
   3         * riscv-opc.c: Formatting fixes.
   4
   5 2016-12-20  Alan Modra  <amodra@gmail.com>
   6
   7         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
   8         * Makefile.in: Regenerate.
   9         * po/POTFILES.in: Regenerate.
  10
  11 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
  12
  13         * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
  14         Only examine ELF file structures here.
  15
  16 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
  17
  18         * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
  19         `bfd_mips_elf_get_abiflags' here.
  20
  21 2016-12-16  Nick Clifton  <nickc@redhat.com>
  22
  23         * arm-dis.c (print_insn_thumb32): Fix compile time warning
  24         computing value_in_comment.
  25
  26 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  27
  28         * mips-dis.c (mips_convert_abiflags_ases): New function.
  29         (set_default_mips_dis_options): Also infer ASE flags from ELF
  30         file structures.
  31
  32 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  33
  34         * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
  35         header flag interpretation code.
  36
  37 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  38
  39         * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
  40         `pinfo2' with SP-relative "sd" entries.
  41
  42 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  43
  44         * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
  45         compact jumps.
  46
  47 2016-12-13 Renlin Li <renlin.li@arm.com>
  48
  49         * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
  50         qualifier.
  51         (operand_general_constraint_met_p): Remove case for CP_REG.
  52         (aarch64_print_operand): Print CRn, CRm operand using imm field.
  53         * aarch64-tbl.h (QL_SYS): Use CR qualifier.
  54         (QL_SYSL): Likewise.
  55         (aarch64_opcode_table): Change CRn, CRm operand class and type.
  56         * aarch64-opc-2.c : Regenerate.
  57         * aarch64-asm-2.c : Likewise.
  58         * aarch64-dis-2.c : Likewise.
  59
  60 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  61
  62         * rx-dis.c: Include <setjmp.h>
  63         (struct private): New.
  64         (rx_get_byte): Check return value of read_memory_func, and
  65         call memory_error_func and OPCODES_SIGLONGJMP on error.
  66         (print_insn_rx): Call OPCODES_SIGSETJMP.
  67
  68 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  69
  70         * rl78-dis.c: Include <setjmp.h>.
  71         (struct private): New.
  72         (rl78_get_byte): Check return value of read_memory_func, and
  73         call memory_error_func and OPCODES_SIGLONGJMP on error.
  74         (print_insn_rl78_common): Call OPCODES_SIGJMP.
  75
  76 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  77
  78         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
  79
  80 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  81
  82         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
  83         than UINT.
  84
  85 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  86
  87         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
  88         to separate `extend' and its uninterpreted argument output.
  89         Separate hexadecimal halves of undecoded extended instructions
  90         output.
  91
  92 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  93
  94         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
  95         indentation space across.
  96
  97 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  98
  99         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
 100         adjustment for PC-relative operations following MIPS16e compact
 101         jumps or undefined RR/J(AL)R(C) encodings.
 102
 103 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 104
 105         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
 106         variable to `reglane_index'.
 107
 108 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
 109
 110         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
 111
 112 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 113
 114         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
 115
 116 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 117
 118         * mips16-opc.c (mips16_opcodes): Update comment naming structure
 119         members.
 120
 121 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 122
 123         * mips-dis.c (print_mips_disassembler_options): Reformat output.
 124
 125 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 126
 127         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
 128         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
 129
 130 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 131
 132         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
 133
 134 2016-12-01  Nick Clifton  <nickc@redhat.com>
 135
 136         PR binutils/20893
 137         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
 138         opcode designator.
 139
 140 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 141
 142         * arc-opc.c (insert_ra_chk): New function.
 143         (insert_rb_chk): Likewise.
 144         (insert_rad): Update text error message.
 145         (insert_rcd): Likewise.
 146         (insert_rhv2): Likewise.
 147         (insert_r0): Likewise.
 148         (insert_r1): Likewise.
 149         (insert_r2): Likewise.
 150         (insert_r3): Likewise.
 151         (insert_sp): Likewise.
 152         (insert_gp): Likewise.
 153         (insert_pcl): Likewise.
 154         (insert_blink): Likewise.
 155         (insert_ilink1): Likewise.
 156         (insert_ilink2): Likewise.
 157         (insert_ras): Likewise.
 158         (insert_rbs): Likewise.
 159         (insert_rcs): Likewise.
 160         (insert_simm3s): Likewise.
 161         (insert_rrange): Likewise.
 162         (insert_fpel): Likewise.
 163         (insert_blinkel): Likewise.
 164         (insert_pcel): Likewise.
 165         (insert_nps_3bit_dst): Likewise.
 166         (insert_nps_3bit_dst_short): Likewise.
 167         (insert_nps_3bit_src2_short): Likewise.
 168         (insert_nps_bitop_size_2b): Likewise.
 169         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 170         (RA_CHK): Define.
 171         (RB): Adjust.
 172         (RB_CHK): Define.
 173         (RC): Adjust.
 174         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 175         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 176         Change first insn argument to check for LP_COUNT usage.
 177         (rem): Likewise.
 178         (ld, ldd): All instructions are LOAD class.  Change first insn
 179         argument to check for LP_COUNT usage.
 180         (st, std): All instructions are STORE class.
 181         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 182         Change first insn argument to check for LP_COUNT usage.
 183         (mov): All instructions are MOVE class.  Change first insn
 184         argument to check for LP_COUNT usage.
 185
 186 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 187
 188         * arc-dis.c (is_compatible_p): Remove function.
 189         (skip_this_opcode): Don't add any decoding class to decode list.
 190         Remove warning.
 191         (find_format_from_table): Go through all opcodes, and warn if we
 192         use a guessed mnemonic.
 193
 194 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 195             Amit Pawar  <amit.pawar@amd.com>
 196
 197         PR binutils/20637
 198         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 199         instructions.
 200
 201 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 202
 203         * configure: Regenerate.
 204
 205 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 206
 207         * sparc-opc.c (HWS_V8): Definition moved from
 208         gas/config/tc-sparc.c.
 209         (HWS_V9): Likewise.
 210         (HWS_VA): Likewise.
 211         (HWS_VB): Likewise.
 212         (HWS_VC): Likewise.
 213         (HWS_VD): Likewise.
 214         (HWS_VE): Likewise.
 215         (HWS_VV): Likewise.
 216         (HWS_VM): Likewise.
 217         (HWS2_VM): Likewise.
 218         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 219         existing entries.
 220
 221 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 222
 223         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 224         instructions.
 225
 226 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 227
 228         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 229         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 230         (aarch64_opcode_table): Add fcmla and fcadd.
 231         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 232         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 233         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 234         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 235         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 236         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 237         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 238         (operand_general_constraint_met_p): Rotate and index range check.
 239         (aarch64_print_operand): Handle rotate operand.
 240         * aarch64-asm-2.c: Regenerate.
 241         * aarch64-dis-2.c: Likewise.
 242         * aarch64-opc-2.c: Likewise.
 243
 244 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 245
 246         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 247         * aarch64-asm-2.c: Regenerate.
 248         * aarch64-dis-2.c: Regenerate.
 249         * aarch64-opc-2.c: Regenerate.
 250
 251 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 252
 253         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 254         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 255         * aarch64-asm-2.c: Regenerate.
 256         * aarch64-dis-2.c: Regenerate.
 257         * aarch64-opc-2.c: Regenerate.
 258
 259 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 260
 261         * aarch64-tbl.h (QL_X1NIL): New.
 262         (arch64_opcode_table): Add ldraa, ldrab.
 263         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 264         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 265         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 266         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 267         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 268         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 269         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 270         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 271         (aarch64_print_operand): Likewise.
 272         * aarch64-asm-2.c: Regenerate.
 273         * aarch64-dis-2.c: Regenerate.
 274         * aarch64-opc-2.c: Regenerate.
 275
 276 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 277
 278         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 279         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 280         * aarch64-asm-2.c: Regenerate.
 281         * aarch64-dis-2.c: Regenerate.
 282         * aarch64-opc-2.c: Regenerate.
 283
 284 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 285
 286         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 287         (AARCH64_OPERANDS): Add Rm_SP.
 288         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 289         * aarch64-asm-2.c: Regenerate.
 290         * aarch64-dis-2.c: Regenerate.
 291         * aarch64-opc-2.c: Regenerate.
 292
 293 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 294
 295         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 296         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 297         autdzb, xpaci, xpacd.
 298         * aarch64-asm-2.c: Regenerate.
 299         * aarch64-dis-2.c: Regenerate.
 300         * aarch64-opc-2.c: Regenerate.
 301
 302 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 303
 304         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 305         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 306         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 307         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 308
 309 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 310
 311         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 312         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 313         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 314         autibsp.
 315         * aarch64-asm-2.c: Regenerate.
 316         * aarch64-dis-2.c: Regenerate.
 317
 318 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 319
 320         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 321
 322 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 323
 324         PR binutils/20799
 325         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 326         * i386-dis.c (EdqwS): Removed.
 327         (dqw_swap_mode): Likewise.
 328         (intel_operand_size): Don't check dqw_swap_mode.
 329         (OP_E_register): Likewise.
 330         (OP_E_memory): Likewise.
 331         (OP_G): Likewise.
 332         (OP_EX): Likewise.
 333         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 334         * i386-tbl.h: Regerated.
 335
 336 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 337
 338         * i386-opc.tbl: Merge AVX512F vmovq.
 339         * i386-tbl.h: Regerated.
 340
 341 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 342
 343         PR binutils/20701
 344         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 345         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 346         (three_byte_table): Remove THREE_BYTE_0F7A.
 347
 348 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 349
 350         PR binutils/20775
 351         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 352         (FGRPd9_4): Replace 1 with 2.
 353         (FGRPd9_5): Replace 2 with 3.
 354         (FGRPd9_6): Replace 3 with 4.
 355         (FGRPd9_7): Replace 4 with 5.
 356         (FGRPda_5): Replace 5 with 6.
 357         (FGRPdb_4): Replace 6 with 7.
 358         (FGRPde_3): Replace 7 with 8.
 359         (FGRPdf_4): Replace 8 with 9.
 360         (fgrps): Add an entry for Bad_Opcode.
 361
 362 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 363
 364         * arc-opc.c (arc_flag_operands): Add F_DI14.
 365         (arc_flag_classes): Add C_DI14.
 366         * arc-nps400-tbl.h: Add new exc instructions.
 367
 368 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 369
 370         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 371         major opcode 0xa.
 372         * arc-nps-400-tbl.h: Add dcmac instruction.
 373         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 374         (insert_nps_rbdouble_64): Added.
 375         (extract_nps_rbdouble_64): Added.
 376         (insert_nps_proto_size): Added.
 377         (extract_nps_proto_size): Added.
 378
 379 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 380
 381         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 382         relating to long instruction processing, add new limm field.
 383         (OPCODE): Rename to...
 384         (OPCODE_32BIT_INSN): ...this.
 385         (OPCODE_AC): Delete.
 386         (skip_this_opcode): Handle different instruction lengths, update
 387         macro name.
 388         (special_flag_p): Update parameter type.
 389         (find_format_from_table): Update for more instruction lengths.
 390         (find_format_long_instructions): Delete.
 391         (find_format): Update for more instruction lengths.
 392         (arc_insn_length): Likewise.
 393         (extract_operand_value): Update for more instruction lengths.
 394         (operand_iterator_next): Remove code relating to long
 395         instructions.
 396         (arc_opcode_to_insn_type): New function.
 397         (print_insn_arc):Update for more instructions lengths.
 398         * arc-ext.c (extInstruction_t): Change argument type.
 399         * arc-ext.h (extInstruction_t): Change argument type.
 400         * arc-fxi.h: Change type unsigned to unsigned long long
 401         extensively throughout.
 402         * arc-nps400-tbl.h: Add long instructions taken from
 403         arc_long_opcodes table in arc-opc.c.
 404         * arc-opc.c: Update parameter types on insert/extract handlers.
 405         (arc_long_opcodes): Delete.
 406         (arc_num_long_opcodes): Delete.
 407         (arc_opcode_len): Update for more instruction lengths.
 408
 409 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 410
 411         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 412
 413 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 414
 415         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 416         with arc_opcode_len.
 417         (find_format_long_instructions): Likewise.
 418         * arc-opc.c (arc_opcode_len): New function.
 419
 420 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 421
 422         * arc-nps400-tbl.h: Fix some instruction masks.
 423
 424 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 425
 426         * i386-dis.c (REG_82): Removed.
 427         (X86_64_82_REG_0): Likewise.
 428         (X86_64_82_REG_1): Likewise.
 429         (X86_64_82_REG_2): Likewise.
 430         (X86_64_82_REG_3): Likewise.
 431         (X86_64_82_REG_4): Likewise.
 432         (X86_64_82_REG_5): Likewise.
 433         (X86_64_82_REG_6): Likewise.
 434         (X86_64_82_REG_7): Likewise.
 435         (X86_64_82): New.
 436         (dis386): Use X86_64_82 instead of REG_82.
 437         (reg_table): Remove REG_82.
 438         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 439         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 440         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 441         X86_64_82_REG_7.
 442
 443 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 444
 445         PR binutils/20754
 446         * i386-dis.c (REG_82): New.
 447         (X86_64_82_REG_0): Likewise.
 448         (X86_64_82_REG_1): Likewise.
 449         (X86_64_82_REG_2): Likewise.
 450         (X86_64_82_REG_3): Likewise.
 451         (X86_64_82_REG_4): Likewise.
 452         (X86_64_82_REG_5): Likewise.
 453         (X86_64_82_REG_6): Likewise.
 454         (X86_64_82_REG_7): Likewise.
 455         (dis386): Use REG_82.
 456         (reg_table): Add REG_82.
 457         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 458         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 459         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 460
 461 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 462
 463         * i386-dis.c (REG_82): Renamed to ...
 464         (REG_83): This.
 465         (dis386): Updated.
 466         (reg_table): Likewise.
 467
 468 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 469
 470         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 471         * i386-dis-evex.h (evex_table): Updated.
 472         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 473         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 474         (cpu_flags): Add CpuAVX512_4VNNIW.
 475         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 476         (i386_cpu_flags): Add cpuavx512_4vnniw.
 477         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 478         * i386-init.h: Regenerate.
 479         * i386-tbl.h: Ditto.
 480
 481 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 482
 483         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 484         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 485         * i386-dis-evex.h (evex_table): Updated.
 486         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 487         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 488         (cpu_flags): Add CpuAVX512_4FMAPS.
 489         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 490         * i386-opc.h (AVX512_4FMAP): New.
 491         (i386_cpu_flags): Add cpuavx512_4fmaps.
 492         (ImplicitQuadGroup): New.
 493         (i386_opcode_modifier): Add implicitquadgroup.
 494         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 495         * i386-init.h: Regenerate.
 496         * i386-tbl.h: Ditto.
 497
 498 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 499             Andrew Waterman <andrew@sifive.com>
 500
 501         Add support for RISC-V architecture.
 502         * configure.ac: Add entry for bfd_riscv_arch.
 503         * configure: Regenerate.
 504         * disassemble.c (disassembler): Add support for riscv.
 505         (disassembler_usage): Likewise.
 506         * riscv-dis.c: New file.
 507         * riscv-opc.c: New file.
 508
 509 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 510
 511         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 512         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 513         (rm_table): Update the RM_0FAE_REG_7 entry.
 514         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 515         (cpu_flags): Remove CpuPCOMMIT.
 516         * i386-opc.h (CpuPCOMMIT): Removed.
 517         (i386_cpu_flags): Remove cpupcommit.
 518         * i386-opc.tbl: Remove pcommit.
 519         * i386-init.h: Regenerated.
 520         * i386-tbl.h: Likewise.
 521
 522 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 523
 524         PR binutis/20705
 525         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 526         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 527         32-bit mode.  Don't check vex.register_specifier in 32-bit
 528         mode.
 529         (OP_VEX): Check for invalid mask registers.
 530
 531 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 532
 533         PR binutis/20699
 534         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 535         sizeflag.
 536
 537 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 538
 539         PR binutis/20704
 540         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 541
 542 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 543
 544         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 545         local variable to `index_regno'.
 546
 547 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 548
 549         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 550
 551 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 552
 553         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 554         usage on ISA basis.
 555
 556 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 557
 558         PR target/20666
 559         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 560
 561 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 562
 563         PR target/20667
 564         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 565         available.
 566
 567 2016-10-07  Alan Modra  <amodra@gmail.com>
 568
 569         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 570
 571 2016-10-06  Alan Modra  <amodra@gmail.com>
 572
 573         * aarch64-opc.c: Spell fall through comments consistently.
 574         * i386-dis.c: Likewise.
 575         * aarch64-dis.c: Add missing fall through comments.
 576         * aarch64-opc.c: Likewise.
 577         * arc-dis.c: Likewise.
 578         * arm-dis.c: Likewise.
 579         * i386-dis.c: Likewise.
 580         * m68k-dis.c: Likewise.
 581         * mep-asm.c: Likewise.
 582         * ns32k-dis.c: Likewise.
 583         * sh-dis.c: Likewise.
 584         * tic4x-dis.c: Likewise.
 585         * tic6x-dis.c: Likewise.
 586         * vax-dis.c: Likewise.
 587
 588 2016-10-06  Alan Modra  <amodra@gmail.com>
 589
 590         * arc-ext.c (create_map): Add missing break.
 591         * msp430-decode.opc (encode_as): Likewise.
 592         * msp430-decode.c: Regenerate.
 593
 594 2016-10-06  Alan Modra  <amodra@gmail.com>
 595
 596         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 597         * crx-dis.c (print_insn_crx): Likewise.
 598
 599 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 600
 601         PR binutils/20657
 602         * i386-dis.c (putop): Don't assign alt twice.
 603
 604 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 605
 606         PR target/20553
 607         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 608
 609 2016-09-29  Alan Modra  <amodra@gmail.com>
 610
 611         * ppc-opc.c (L): Make compulsory.
 612         (LOPT): New, optional form of L.
 613         (HTM_R): Define as LOPT.
 614         (L0, L1): Delete.
 615         (L32OPT): New, optional for 32-bit L.
 616         (L2OPT): New, 2-bit L for dcbf.
 617         (SVC_LEC): Update.
 618         (L2): Define.
 619         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 620         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 621         <dcbf>: Use L2OPT.
 622         <tlbiel, tlbie>: Use LOPT.
 623         <wclr, wclrall>: Use L2.
 624
 625 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 626
 627         * Makefile.in: Regenerate.
 628         * configure: Likewise.
 629
 630 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 631
 632         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 633         (EXTINSN2OP): Use EXTINSN2OPF.
 634         (bspeekm, bspop, modapp): New extension instructions.
 635         * arc-opc.c (F_DNZ_ND): Define.
 636         (F_DNZ_D): Likewise.
 637         (F_SIZEB1): Changed.
 638         (C_DNZ_D): Define.
 639         (C_HARD): Changed.
 640         * arc-tbl.h (dbnz): New instruction.
 641         (prealloc): Allow it for ARC EM.
 642         (xbfu): Likewise.
 643
 644 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 645
 646         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 647         after commas in addresses.
 648         (aarch64_print_operand): Likewise.
 649
 650 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 651
 652         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 653         rather than "should be" or "expected to be" in error messages.
 654
 655 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 656
 657         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 658         (print_mnemonic_name): ...here.
 659         (print_comment): New function.
 660         (print_aarch64_insn): Call it.
 661         * aarch64-opc.c (aarch64_conds): Add SVE names.
 662         (aarch64_print_operand): Print alternative condition names in
 663         a comment.
 664
 665 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 666
 667         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 668         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 669         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 670         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 671         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 672         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 673         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 674         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 675         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 676         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 677         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 678         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 679         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 680         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 681         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 682         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 683         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 684         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 685         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 686         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 687         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 688         (aarch64_feature_sve): New variable.
 689         (SVE): New macro.
 690         (_SVE_INSN): Likewise.
 691         (aarch64_opcode_table): Add SVE instructions.
 692         * aarch64-opc.h (extract_fields): Declare.
 693         * aarch64-opc-2.c: Regenerate.
 694         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 695         * aarch64-asm-2.c: Regenerate.
 696         * aarch64-dis.c (extract_fields): Make global.
 697         (do_misc_decoding): Handle the new SVE aarch64_ops.
 698         * aarch64-dis-2.c: Regenerate.
 699
 700 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 701
 702         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 703         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 704         aarch64_field_kinds.
 705         * aarch64-opc.c (fields): Add corresponding entries.
 706         * aarch64-asm.c (aarch64_get_variant): New function.
 707         (aarch64_encode_variant_using_iclass): Likewise.
 708         (aarch64_opcode_encode): Call it.
 709         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 710         (aarch64_opcode_decode): Call it.
 711
 712 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 713
 714         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 715         and FP register operands.
 716         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 717         (FLD_SVE_Vn): New aarch64_field_kinds.
 718         * aarch64-opc.c (fields): Add corresponding entries.
 719         (aarch64_print_operand): Handle the new SVE core and FP register
 720         operands.
 721         * aarch64-opc-2.c: Regenerate.
 722         * aarch64-asm-2.c: Likewise.
 723         * aarch64-dis-2.c: Likewise.
 724
 725 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 726
 727         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 728         immediate operands.
 729         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 730         * aarch64-opc.c (fields): Add corresponding entry.
 731         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 732         operands.
 733         (aarch64_print_operand): Likewise.
 734         * aarch64-opc-2.c: Regenerate.
 735         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 736         (ins_sve_float_zero_one): New inserters.
 737         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 738         (aarch64_ins_sve_float_half_two): Likewise.
 739         (aarch64_ins_sve_float_zero_one): Likewise.
 740         * aarch64-asm-2.c: Regenerate.
 741         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 742         (ext_sve_float_zero_one): New extractors.
 743         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 744         (aarch64_ext_sve_float_half_two): Likewise.
 745         (aarch64_ext_sve_float_zero_one): Likewise.
 746         * aarch64-dis-2.c: Regenerate.
 747
 748 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 749
 750         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 751         integer immediate operands.
 752         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 753         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 754         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 755         * aarch64-opc.c (fields): Add corresponding entries.
 756         (operand_general_constraint_met_p): Handle the new SVE integer
 757         immediate operands.
 758         (aarch64_print_operand): Likewise.
 759         (aarch64_sve_dupm_mov_immediate_p): New function.
 760         * aarch64-opc-2.c: Regenerate.
 761         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 762         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 763         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 764         (aarch64_ins_limm): ...here.
 765         (aarch64_ins_inv_limm): New function.
 766         (aarch64_ins_sve_aimm): Likewise.
 767         (aarch64_ins_sve_asimm): Likewise.
 768         (aarch64_ins_sve_limm_mov): Likewise.
 769         (aarch64_ins_sve_shlimm): Likewise.
 770         (aarch64_ins_sve_shrimm): Likewise.
 771         * aarch64-asm-2.c: Regenerate.
 772         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 773         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 774         * aarch64-dis.c (decode_limm): New function, split out from...
 775         (aarch64_ext_limm): ...here.
 776         (aarch64_ext_inv_limm): New function.
 777         (decode_sve_aimm): Likewise.
 778         (aarch64_ext_sve_aimm): Likewise.
 779         (aarch64_ext_sve_asimm): Likewise.
 780         (aarch64_ext_sve_limm_mov): Likewise.
 781         (aarch64_top_bit): Likewise.
 782         (aarch64_ext_sve_shlimm): Likewise.
 783         (aarch64_ext_sve_shrimm): Likewise.
 784         * aarch64-dis-2.c: Regenerate.
 785
 786 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 787
 788         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 789         operands.
 790         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 791         the AARCH64_MOD_MUL_VL entry.
 792         (value_aligned_p): Cope with non-power-of-two alignments.
 793         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 794         (print_immediate_offset_address): Likewise.
 795         (aarch64_print_operand): Likewise.
 796         * aarch64-opc-2.c: Regenerate.
 797         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 798         (ins_sve_addr_ri_s9xvl): New inserters.
 799         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 800         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 801         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 802         * aarch64-asm-2.c: Regenerate.
 803         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 804         (ext_sve_addr_ri_s9xvl): New extractors.
 805         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 806         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 807         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 808         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 809         * aarch64-dis-2.c: Regenerate.
 810
 811 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 812
 813         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 814         address operands.
 815         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 816         (FLD_SVE_xs_22): New aarch64_field_kinds.
 817         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 818         (get_operand_specific_data): New function.
 819         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 820         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 821         (operand_general_constraint_met_p): Handle the new SVE address
 822         operands.
 823         (sve_reg): New array.
 824         (get_addr_sve_reg_name): New function.
 825         (aarch64_print_operand): Handle the new SVE address operands.
 826         * aarch64-opc-2.c: Regenerate.
 827         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 828         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 829         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 830         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 831         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 832         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 833         (aarch64_ins_sve_addr_zi_u5): Likewise.
 834         (aarch64_ins_sve_addr_zz): Likewise.
 835         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 836         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 837         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 838         * aarch64-asm-2.c: Regenerate.
 839         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 840         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 841         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 842         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 843         (aarch64_ext_sve_addr_ri_u6): Likewise.
 844         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 845         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 846         (aarch64_ext_sve_addr_zi_u5): Likewise.
 847         (aarch64_ext_sve_addr_zz): Likewise.
 848         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 849         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 850         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 851         * aarch64-dis-2.c: Regenerate.
 852
 853 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 854
 855         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 856         AARCH64_OPND_SVE_PATTERN_SCALED.
 857         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 858         * aarch64-opc.c (fields): Add a corresponding entry.
 859         (set_multiplier_out_of_range_error): New function.
 860         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 861         (operand_general_constraint_met_p): Handle
 862         AARCH64_OPND_SVE_PATTERN_SCALED.
 863         (print_register_offset_address): Use PRIi64 to print the
 864         shift amount.
 865         (aarch64_print_operand): Likewise.  Handle
 866         AARCH64_OPND_SVE_PATTERN_SCALED.
 867         * aarch64-opc-2.c: Regenerate.
 868         * aarch64-asm.h (ins_sve_scale): New inserter.
 869         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 870         * aarch64-asm-2.c: Regenerate.
 871         * aarch64-dis.h (ext_sve_scale): New inserter.
 872         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 873         * aarch64-dis-2.c: Regenerate.
 874
 875 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 876
 877         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 878         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 879         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 880         (FLD_SVE_prfop): Likewise.
 881         * aarch64-opc.c: Include libiberty.h.
 882         (aarch64_sve_pattern_array): New variable.
 883         (aarch64_sve_prfop_array): Likewise.
 884         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 885         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 886         AARCH64_OPND_SVE_PRFOP.
 887         * aarch64-asm-2.c: Regenerate.
 888         * aarch64-dis-2.c: Likewise.
 889         * aarch64-opc-2.c: Likewise.
 890
 891 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 892
 893         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 894         AARCH64_OPND_QLF_P_[ZM].
 895         (aarch64_print_operand): Print /z and /m where appropriate.
 896
 897 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 898
 899         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 900         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 901         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 902         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 903         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 904         * aarch64-opc.c (fields): Add corresponding entries here.
 905         (operand_general_constraint_met_p): Check that SVE register lists
 906         have the correct length.  Check the ranges of SVE index registers.
 907         Check for cases where p8-p15 are used in 3-bit predicate fields.
 908         (aarch64_print_operand): Handle the new SVE operands.
 909         * aarch64-opc-2.c: Regenerate.
 910         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 911         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 912         (aarch64_ins_sve_reglist): Likewise.
 913         * aarch64-asm-2.c: Regenerate.
 914         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 915         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 916         (aarch64_ext_sve_reglist): Likewise.
 917         * aarch64-dis-2.c: Regenerate.
 918
 919 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 920
 921         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 922         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 923         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 924         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 925         tied operands.
 926
 927 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 928
 929         * aarch64-opc.c (get_offset_int_reg_name): New function.
 930         (print_immediate_offset_address): Likewise.
 931         (print_register_offset_address): Take the base and offset
 932         registers as parameters.
 933         (aarch64_print_operand): Update caller accordingly.  Use
 934         print_immediate_offset_address.
 935
 936 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 937
 938         * aarch64-opc.c (BANK): New macro.
 939         (R32, R64): Take a register number as argument
 940         (int_reg): Use BANK.
 941
 942 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 943
 944         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 945         (aarch64_print_operand): Update accordingly.
 946
 947 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 948
 949         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 950         for FPIMM.
 951         * aarch64-asm.h (ins_fpimm): New inserter.
 952         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 953         * aarch64-asm-2.c: Regenerate.
 954         * aarch64-dis.h (ext_fpimm): New extractor.
 955         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 956         (aarch64_ext_fpimm): New function.
 957         * aarch64-dis-2.c: Regenerate.
 958
 959 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 960
 961         * aarch64-asm.c: Include libiberty.h.
 962         (insert_fields): New function.
 963         (aarch64_ins_imm): Use it.
 964         * aarch64-dis.c (extract_fields): New function.
 965         (aarch64_ext_imm): Use it.
 966
 967 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 968
 969         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 970         with an esize parameter.
 971         (operand_general_constraint_met_p): Update accordingly.
 972         Fix misindented code.
 973         * aarch64-asm.c (aarch64_ins_limm): Update call to
 974         aarch64_logical_immediate_p.
 975
 976 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 977
 978         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 979
 980 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 981
 982         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 983
 984 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 985
 986         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 987
 988 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 989
 990         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 991         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 992         xor3>: Delete mnemonics.
 993         <cp_abort>: Rename mnemonic from ...
 994         <cpabort>: ...to this.
 995         <setb>: Change to a X form instruction.
 996         <sync>: Change to 1 operand form.
 997         <copy>: Delete mnemonic.
 998         <copy_first>: Rename mnemonic from ...
 999         <copy>: ...to this.
1000         <paste, paste.>: Delete mnemonics.
1001         <paste_last>: Rename mnemonic from ...
1002         <paste.>: ...to this.
1003
1004 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1005
1006         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1007
1008 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1009
1010         * s390-mkopc.c (main): Support alternate arch strings.
1011
1012 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
1013
1014         * s390-opc.txt: Fix kmctr instruction type.
1015
1016 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
1017
1018         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1019         * i386-init.h: Regenerated.
1020
1021 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
1022
1023         * opcodes/arc-dis.c (print_insn_arc): Changed.
1024
1025 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
1026
1027         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1028         camellia_fl.
1029
1030 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1031
1032         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
1033         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1034         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1035
1036 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
1037
1038         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1039         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1040         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1041         PREFIX_MOD_3_0FAE_REG_4.
1042         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1043         PREFIX_MOD_3_0FAE_REG_4.
1044         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1045         (cpu_flags): Add CpuPTWRITE.
1046         * i386-opc.h (CpuPTWRITE): New.
1047         (i386_cpu_flags): Add cpuptwrite.
1048         * i386-opc.tbl: Add ptwrite instruction.
1049         * i386-init.h: Regenerated.
1050         * i386-tbl.h: Likewise.
1051
1052 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1053
1054         * arc-dis.h: Wrap around in extern "C".
1055
1056 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1057
1058         * aarch64-tbl.h (V8_2_INSN): New macro.
1059         (aarch64_opcode_table): Use it.
1060
1061 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1062
1063         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1064         CORE_INSN, __FP_INSN and SIMD_INSN.
1065
1066 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1067
1068         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1069         (aarch64_opcode_table): Update uses accordingly.
1070
1071 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1072         Kwok Cheung Yeung  <kcy@codesourcery.com>
1073
1074         opcodes/
1075         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1076         'e_cmplwi' to 'e_cmpli' instead.
1077         (OPVUPRT, OPVUPRT_MASK): Define.
1078         (powerpc_opcodes): Add E200Z4 insns.
1079         (vle_opcodes): Add context save/restore insns.
1080
1081 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1082
1083         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1084         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1085         "j".
1086
1087 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1088
1089         * arc-nps400-tbl.h: Change block comments to GNU format.
1090         * arc-dis.c: Add new globals addrtypenames,
1091         addrtypenames_max, and addtypeunknown.
1092         (get_addrtype): New function.
1093         (print_insn_arc): Print colons and address types when
1094         required.
1095         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1096         define insert and extract functions for all address types.
1097         (arc_operands): Add operands for colon and all address
1098         types.
1099         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1100         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1101         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1102         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1103         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1104         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1105
1106 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1107
1108         * configure: Regenerated.
1109
1110 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1111
1112         * arc-dis.c (skipclass): New structure.
1113         (decodelist): New variable.
1114         (is_compatible_p): New function.
1115         (new_element): Likewise.
1116         (skip_class_p): Likewise.
1117         (find_format_from_table): Use skip_class_p function.
1118         (find_format): Decode first the extension instructions.
1119         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1120         e_flags.
1121         (parse_option): New function.
1122         (parse_disassembler_options): Likewise.
1123         (print_arc_disassembler_options): Likewise.
1124         (print_insn_arc): Use parse_disassembler_options function.  Proper
1125         select ARCv2 cpu variant.
1126         * disassemble.c (disassembler_usage): Add ARC disassembler
1127         options.
1128
1129 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1130
1131         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1132         annotation from the "nal" entry and reorder it beyond "bltzal".
1133
1134 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1135
1136         * sparc-opc.c (ldtxa): New macro.
1137         (sparc_opcodes): Use the macro defined above to add entries for
1138         the LDTXA instructions.
1139         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1140         instruction.
1141
1142 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1143
1144         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1145         and "jmpc".
1146
1147 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1148
1149         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1150         (movzb): Adjust to cover all permitted suffixes.
1151         (movzw): New.
1152         * i386-tbl.h: Re-generate.
1153
1154 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1155
1156         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1157         (lgdt): Remove Tbyte from non-64-bit variant.
1158         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1159         xsaves64, xsavec64): Remove Disp16.
1160         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1161         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1162         64-bit variants.
1163         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1164         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1165         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1166         64-bit variants.
1167         * i386-tbl.h: Re-generate.
1168
1169 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1170
1171         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1172         * i386-tbl.h: Re-generate.
1173
1174 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1175
1176         * arm-dis.c (print_insn): Fix typo in comment.
1177
1178 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1179
1180         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1181         range of ldst_elemlist operands.
1182         (print_register_list): Use PRIi64 to print the index.
1183         (aarch64_print_operand): Likewise.
1184
1185 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1186
1187         * mcore-opc.h: Remove sentinal.
1188         * mcore-dis.c (print_insn_mcore): Adjust.
1189
1190 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1191
1192         * arc-opc.c: Correct description of availability of NPS400
1193         features.
1194
1195 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1196
1197         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1198         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1199         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1200         xor3>: New mnemonics.
1201         <setb>: Change to a VX form instruction.
1202         (insert_sh6): Add support for rldixor.
1203         (extract_sh6): Likewise.
1204
1205 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1206
1207         * arc-ext.h: Wrap in extern C.
1208
1209 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1210
1211         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1212         Use same method for determining instruction length on ARC700 and
1213         NPS-400.
1214         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1215         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1216         with the NPS400 subclass.
1217         * arc-opc.c: Likewise.
1218
1219 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1220
1221         * sparc-opc.c (rdasr): New macro.
1222         (wrasr): Likewise.
1223         (rdpr): Likewise.
1224         (wrpr): Likewise.
1225         (rdhpr): Likewise.
1226         (wrhpr): Likewise.
1227         (sparc_opcodes): Use the macros above to fix and expand the
1228         definition of read/write instructions from/to
1229         asr/privileged/hyperprivileged instructions.
1230         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1231         %hva_mask_nz.  Prefer softint_set and softint_clear over
1232         set_softint and clear_softint.
1233         (print_insn_sparc): Support %ver in Rd.
1234
1235 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1236
1237         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1238         architecture according to the hardware capabilities they require.
1239
1240 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1241
1242         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1243         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1244         bfd_mach_sparc_v9{c,d,e,v,m}.
1245         * sparc-opc.c (MASK_V9C): Define.
1246         (MASK_V9D): Likewise.
1247         (MASK_V9E): Likewise.
1248         (MASK_V9V): Likewise.
1249         (MASK_V9M): Likewise.
1250         (v6): Add MASK_V9{C,D,E,V,M}.
1251         (v6notlet): Likewise.
1252         (v7): Likewise.
1253         (v8): Likewise.
1254         (v9): Likewise.
1255         (v9andleon): Likewise.
1256         (v9a): Likewise.
1257         (v9b): Likewise.
1258         (v9c): Define.
1259         (v9d): Likewise.
1260         (v9e): Likewise.
1261         (v9v): Likewise.
1262         (v9m): Likewise.
1263         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1264
1265 2016-06-15  Nick Clifton  <nickc@redhat.com>
1266
1267         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1268         constants to match expected behaviour.
1269         (nds32_parse_opcode): Likewise.  Also for whitespace.
1270
1271 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1272
1273         * arc-opc.c (extract_rhv1): Extract value from insn.
1274
1275 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1276
1277         * arc-nps400-tbl.h: Add ldbit instruction.
1278         * arc-opc.c: Add flag classes required for ldbit.
1279
1280 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1281
1282         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1283         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1284         support the above instructions.
1285
1286 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1287
1288         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1289         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1290         csma, cbba, zncv, and hofs.
1291         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1292         support the above instructions.
1293
1294 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1295
1296         * arc-nps400-tbl.h: Add andab and orab instructions.
1297
1298 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1299
1300         * arc-nps400-tbl.h: Add addl-like instructions.
1301
1302 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1303
1304         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1305
1306 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1307
1308         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1309         instructions.
1310
1311 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1312
1313         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1314         variable.
1315         (init_disasm): Handle new command line option "insnlength".
1316         (print_s390_disassembler_options): Mention new option in help
1317         output.
1318         (print_insn_s390): Use the encoded insn length when dumping
1319         unknown instructions.
1320
1321 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1322
1323         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1324          to the address and set as symbol address for LDS/ STS immediate operands.
1325
1326 2016-06-07  Alan Modra  <amodra@gmail.com>
1327
1328         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1329         cpu for "vle" to e500.
1330         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1331         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1332         (PPCNONE): Delete, substitute throughout.
1333         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1334         except for major opcode 4 and 31.
1335         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1336
1337 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1338
1339         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1340         ARM_EXT_RAS in relevant entries.
1341
1342 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1343
1344         PR binutils/20196
1345         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1346         opcodes for E6500.
1347
1348 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1349
1350         PR binutis/18386
1351         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1352         (indir_v_mode): New.
1353         Add comments for '&'.
1354         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1355         (putop): Handle '&'.
1356         (intel_operand_size): Handle indir_v_mode.
1357         (OP_E_register): Likewise.
1358         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1359         64-bit indirect call/jmp for AMD64.
1360         * i386-tbl.h: Regenerated
1361
1362 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1363
1364         * arc-dis.c (struct arc_operand_iterator): New structure.
1365         (find_format_from_table): All the old content from find_format,
1366         with some minor adjustments, and parameter renaming.
1367         (find_format_long_instructions): New function.
1368         (find_format): Rewritten.
1369         (arc_insn_length): Add LSB parameter.
1370         (extract_operand_value): New function.
1371         (operand_iterator_next): New function.
1372         (print_insn_arc): Use new functions to find opcode, and iterator
1373         over operands.
1374         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1375         (extract_nps_3bit_dst_short): New function.
1376         (insert_nps_3bit_src2_short): New function.
1377         (extract_nps_3bit_src2_short): New function.
1378         (insert_nps_bitop1_size): New function.
1379         (extract_nps_bitop1_size): New function.
1380         (insert_nps_bitop2_size): New function.
1381         (extract_nps_bitop2_size): New function.
1382         (insert_nps_bitop_mod4_msb): New function.
1383         (extract_nps_bitop_mod4_msb): New function.
1384         (insert_nps_bitop_mod4_lsb): New function.
1385         (extract_nps_bitop_mod4_lsb): New function.
1386         (insert_nps_bitop_dst_pos3_pos4): New function.
1387         (extract_nps_bitop_dst_pos3_pos4): New function.
1388         (insert_nps_bitop_ins_ext): New function.
1389         (extract_nps_bitop_ins_ext): New function.
1390         (arc_operands): Add new operands.
1391         (arc_long_opcodes): New global array.
1392         (arc_num_long_opcodes): New global.
1393         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1394
1395 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1396
1397         * nds32-asm.h: Add extern "C".
1398         * sh-opc.h: Likewise.
1399
1400 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1401
1402         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1403         0,b,limm to the rflt instruction.
1404
1405 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1406
1407         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1408         constant.
1409
1410 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1411
1412         PR gas/20145
1413         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1414         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1415         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1416         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1417         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1418         * i386-init.h: Regenerated.
1419
1420 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1421
1422         PR gas/20145
1423         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1424         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1425         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1426         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1427         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1428         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1429         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1430         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1431         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1432         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1433         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1434         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1435         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1436         CpuRegMask for AVX512.
1437         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1438         and CpuRegMask.
1439         (set_bitfield_from_cpu_flag_init): New function.
1440         (set_bitfield): Remove const on f.  Call
1441         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1442         * i386-opc.h (CpuRegMMX): New.
1443         (CpuRegXMM): Likewise.
1444         (CpuRegYMM): Likewise.
1445         (CpuRegZMM): Likewise.
1446         (CpuRegMask): Likewise.
1447         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1448         and cpuregmask.
1449         * i386-init.h: Regenerated.
1450         * i386-tbl.h: Likewise.
1451
1452 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1453
1454         PR gas/20154
1455         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1456         (opcode_modifiers): Add AMD64 and Intel64.
1457         (main): Properly verify CpuMax.
1458         * i386-opc.h (CpuAMD64): Removed.
1459         (CpuIntel64): Likewise.
1460         (CpuMax): Set to CpuNo64.
1461         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1462         (AMD64): New.
1463         (Intel64): Likewise.
1464         (i386_opcode_modifier): Add amd64 and intel64.
1465         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1466         on call and jmp.
1467         * i386-init.h: Regenerated.
1468         * i386-tbl.h: Likewise.
1469
1470 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1471
1472         PR gas/20154
1473         * i386-gen.c (main): Fail if CpuMax is incorrect.
1474         * i386-opc.h (CpuMax): Set to CpuIntel64.
1475         * i386-tbl.h: Regenerated.
1476
1477 2016-05-27  Nick Clifton  <nickc@redhat.com>
1478
1479         PR target/20150
1480         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1481         (msp430dis_opcode_unsigned): New function.
1482         (msp430dis_opcode_signed): New function.
1483         (msp430_singleoperand): Use the new opcode reading functions.
1484         Only disassenmble bytes if they were successfully read.
1485         (msp430_doubleoperand): Likewise.
1486         (msp430_branchinstr): Likewise.
1487         (msp430x_callx_instr): Likewise.
1488         (print_insn_msp430): Check that it is safe to read bytes before
1489         attempting disassembly.  Use the new opcode reading functions.
1490
1491 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1492
1493         * ppc-opc.c (CY): New define.  Document it.
1494         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1495
1496 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1497
1498         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1499         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1500         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1501         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1502         CPU_ANY_AVX_FLAGS.
1503         * i386-init.h: Regenerated.
1504
1505 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1506
1507         PR gas/20141
1508         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1509         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1510         * i386-init.h: Regenerated.
1511
1512 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1513
1514         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1515         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1516         * i386-init.h: Regenerated.
1517
1518 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1519
1520         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1521         information.
1522         (print_insn_arc): Set insn_type information.
1523         * arc-opc.c (C_CC): Add F_CLASS_COND.
1524         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1525         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1526         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1527         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1528         (brne, brne_s, jeq_s, jne_s): Likewise.
1529
1530 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1531
1532         * arc-tbl.h (neg): New instruction variant.
1533
1534 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1535
1536         * arc-dis.c (find_format, find_format, get_auxreg)
1537         (print_insn_arc): Changed.
1538         * arc-ext.h (INSERT_XOP): Likewise.
1539
1540 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1541
1542         * tic54x-dis.c (sprint_mmr): Adjust.
1543         * tic54x-opc.c: Likewise.
1544
1545 2016-05-19  Alan Modra  <amodra@gmail.com>
1546
1547         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1548
1549 2016-05-19  Alan Modra  <amodra@gmail.com>
1550
1551         * ppc-opc.c: Formatting.
1552         (NSISIGNOPT): Define.
1553         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1554
1555 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1556
1557         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1558         replacing references to `micromips_ase' throughout.
1559         (_print_insn_mips): Don't use file-level microMIPS annotation to
1560         determine the disassembly mode with the symbol table.
1561
1562 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1563
1564         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1565
1566 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1567
1568         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1569         mips64r6.
1570         * mips-opc.c (D34): New macro.
1571         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1572
1573 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1574
1575         * i386-dis.c (prefix_table): Add RDPID instruction.
1576         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1577         (cpu_flags): Add RDPID bitfield.
1578         * i386-opc.h (enum): Add RDPID element.
1579         (i386_cpu_flags): Add RDPID field.
1580         * i386-opc.tbl: Add RDPID instruction.
1581         * i386-init.h: Regenerate.
1582         * i386-tbl.h: Regenerate.
1583
1584 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1585
1586         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1587         branch type of a symbol.
1588         (print_insn): Likewise.
1589
1590 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1591
1592         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1593         Mainline Security Extensions instructions.
1594         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1595         Extensions instructions.
1596         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1597         instructions.
1598         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1599         special registers.
1600
1601 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1602
1603         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1604
1605 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1606
1607         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1608         (arcExtMap_genOpcode): Likewise.
1609         * arc-opc.c (arg_32bit_rc): Define new variable.
1610         (arg_32bit_u6): Likewise.
1611         (arg_32bit_limm): Likewise.
1612
1613 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1614
1615         * aarch64-gen.c (VERIFIER): Define.
1616         * aarch64-opc.c (VERIFIER): Define.
1617         (verify_ldpsw): Use static linkage.
1618         * aarch64-opc.h (verify_ldpsw): Remove.
1619         * aarch64-tbl.h: Use VERIFIER for verifiers.
1620
1621 2016-04-28  Nick Clifton  <nickc@redhat.com>
1622
1623         PR target/19722
1624         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1625         * aarch64-opc.c (verify_ldpsw): New function.
1626         * aarch64-opc.h (verify_ldpsw): New prototype.
1627         * aarch64-tbl.h: Add initialiser for verifier field.
1628         (LDPSW): Set verifier to verify_ldpsw.
1629
1630 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1631
1632         PR binutils/19983
1633         PR binutils/19984
1634         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1635         smaller than address size.
1636
1637 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1638
1639         * alpha-dis.c: Regenerate.
1640         * crx-dis.c: Likewise.
1641         * disassemble.c: Likewise.
1642         * epiphany-opc.c: Likewise.
1643         * fr30-opc.c: Likewise.
1644         * frv-opc.c: Likewise.
1645         * ip2k-opc.c: Likewise.
1646         * iq2000-opc.c: Likewise.
1647         * lm32-opc.c: Likewise.
1648         * lm32-opinst.c: Likewise.
1649         * m32c-opc.c: Likewise.
1650         * m32r-opc.c: Likewise.
1651         * m32r-opinst.c: Likewise.
1652         * mep-opc.c: Likewise.
1653         * mt-opc.c: Likewise.
1654         * or1k-opc.c: Likewise.
1655         * or1k-opinst.c: Likewise.
1656         * tic80-opc.c: Likewise.
1657         * xc16x-opc.c: Likewise.
1658         * xstormy16-opc.c: Likewise.
1659
1660 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1661
1662         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1663         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1664         calcsd, and calcxd instructions.
1665         * arc-opc.c (insert_nps_bitop_size): Delete.
1666         (extract_nps_bitop_size): Delete.
1667         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1668         (extract_nps_qcmp_m3): Define.
1669         (extract_nps_qcmp_m2): Define.
1670         (extract_nps_qcmp_m1): Define.
1671         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1672         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1673         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1674         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1675         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1676         NPS_QCMP_M3.
1677
1678 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1679
1680         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1681
1682 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1683
1684         * Makefile.in: Regenerated with automake 1.11.6.
1685         * aclocal.m4: Likewise.
1686
1687 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1688
1689         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1690         instructions.
1691         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1692         (extract_nps_cmem_uimm16): New function.
1693         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1694
1695 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1696
1697         * arc-dis.c (arc_insn_length): New function.
1698         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1699         (find_format): Change insnLen parameter to unsigned.
1700
1701 2016-04-13  Nick Clifton  <nickc@redhat.com>
1702
1703         PR target/19937
1704         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1705         the LD.B and LD.BU instructions.
1706
1707 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1708
1709         * arc-dis.c (find_format): Check for extension flags.
1710         (print_flags): New function.
1711         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1712         .extAuxRegister.
1713         * arc-ext.c (arcExtMap_coreRegName): Use
1714         LAST_EXTENSION_CORE_REGISTER.
1715         (arcExtMap_coreReadWrite): Likewise.
1716         (dump_ARC_extmap): Update printing.
1717         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1718         (arc_aux_regs): Add cpu field.
1719         * arc-regs.h: Add cpu field, lower case name aux registers.
1720
1721 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1722
1723         * arc-tbl.h: Add rtsc, sleep with no arguments.
1724
1725 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1726
1727         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1728         Initialize.
1729         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1730         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1731         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1732         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1733         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1734         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1735         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1736         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1737         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1738         (arc_opcode arc_opcodes): Null terminate the array.
1739         (arc_num_opcodes): Remove.
1740         * arc-ext.h (INSERT_XOP): Define.
1741         (extInstruction_t): Likewise.
1742         (arcExtMap_instName): Delete.
1743         (arcExtMap_insn): New function.
1744         (arcExtMap_genOpcode): Likewise.
1745         * arc-ext.c (ExtInstruction): Remove.
1746         (create_map): Zero initialize instruction fields.
1747         (arcExtMap_instName): Remove.
1748         (arcExtMap_insn): New function.
1749         (dump_ARC_extmap): More info while debuging.
1750         (arcExtMap_genOpcode): New function.
1751         * arc-dis.c (find_format): New function.
1752         (print_insn_arc): Use find_format.
1753         (arc_get_disassembler): Enable dump_ARC_extmap only when
1754         debugging.
1755
1756 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1757
1758         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1759         instruction bits out.
1760
1761 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1762
1763         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1764         * arc-opc.c (arc_flag_operands): Add new flags.
1765         (arc_flag_classes): Add new classes.
1766
1767 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1768
1769         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1770
1771 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1772
1773         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1774         encode1, rflt, crc16, and crc32 instructions.
1775         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1776         (arc_flag_classes): Add C_NPS_R.
1777         (insert_nps_bitop_size_2b): New function.
1778         (extract_nps_bitop_size_2b): Likewise.
1779         (insert_nps_bitop_uimm8): Likewise.
1780         (extract_nps_bitop_uimm8): Likewise.
1781         (arc_operands): Add new operand entries.
1782
1783 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1784
1785         * arc-regs.h: Add a new subclass field.  Add double assist
1786         accumulator register values.
1787         * arc-tbl.h: Use DPA subclass to mark the double assist
1788         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1789         * arc-opc.c (RSP): Define instead of SP.
1790         (arc_aux_regs): Add the subclass field.
1791
1792 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1793
1794         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1795
1796 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1797
1798         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1799         NPS_R_SRC1.
1800
1801 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1802
1803         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1804         issues.  No functional changes.
1805
1806 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1807
1808         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1809         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1810         (RTT): Remove duplicate.
1811         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1812         (PCT_CONFIG*): Remove.
1813         (D1L, D1H, D2H, D2L): Define.
1814
1815 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1816
1817         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1818
1819 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1820
1821         * arc-tbl.h (invld07): Remove.
1822         * arc-ext-tbl.h: New file.
1823         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1824         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1825
1826 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1827
1828         Fix -Wstack-usage warnings.
1829         * aarch64-dis.c (print_operands): Substitute size.
1830         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1831
1832 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1833
1834         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1835         to get a proper diagnostic when an invalid ASR register is used.
1836
1837 2016-03-22  Nick Clifton  <nickc@redhat.com>
1838
1839         * configure: Regenerate.
1840
1841 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1842
1843         * arc-nps400-tbl.h: New file.
1844         * arc-opc.c: Add top level comment.
1845         (insert_nps_3bit_dst): New function.
1846         (extract_nps_3bit_dst): New function.
1847         (insert_nps_3bit_src2): New function.
1848         (extract_nps_3bit_src2): New function.
1849         (insert_nps_bitop_size): New function.
1850         (extract_nps_bitop_size): New function.
1851         (arc_flag_operands): Add nps400 entries.
1852         (arc_flag_classes): Add nps400 entries.
1853         (arc_operands): Add nps400 entries.
1854         (arc_opcodes): Add nps400 include.
1855
1856 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1857
1858         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1859         the new class enum values.
1860
1861 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1862
1863         * arc-dis.c (print_insn_arc): Handle nps400.
1864
1865 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1866
1867         * arc-opc.c (BASE): Delete.
1868
1869 2016-03-18  Nick Clifton  <nickc@redhat.com>
1870
1871         PR target/19721
1872         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1873         of MOV insn that aliases an ORR insn.
1874
1875 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1876
1877         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1878
1879 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1880
1881         * mcore-opc.h: Add const qualifiers.
1882         * microblaze-opc.h (struct op_code_struct): Likewise.
1883         * sh-opc.h: Likewise.
1884         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1885         (tic4x_print_op): Likewise.
1886
1887 2016-03-02  Alan Modra  <amodra@gmail.com>
1888
1889         * or1k-desc.h: Regenerate.
1890         * fr30-ibld.c: Regenerate.
1891         * rl78-decode.c: Regenerate.
1892
1893 2016-03-01  Nick Clifton  <nickc@redhat.com>
1894
1895         PR target/19747
1896         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1897
1898 2016-02-24  Renlin Li  <renlin.li@arm.com>
1899
1900         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1901         (print_insn_coprocessor): Support fp16 instructions.
1902
1903 2016-02-24  Renlin Li  <renlin.li@arm.com>
1904
1905         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1906         vminnm, vrint(mpna).
1907
1908 2016-02-24  Renlin Li  <renlin.li@arm.com>
1909
1910         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1911         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1912
1913 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1914
1915         * i386-dis.c (print_insn): Parenthesize expression to prevent
1916         truncated addresses.
1917         (OP_J): Likewise.
1918
1919 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1920             Janek van Oirschot  <jvanoirs@synopsys.com>
1921
1922         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1923         variable.
1924
1925 2016-02-04  Nick Clifton  <nickc@redhat.com>
1926
1927         PR target/19561
1928         * msp430-dis.c (print_insn_msp430): Add a special case for
1929         decoding an RRC instruction with the ZC bit set in the extension
1930         word.
1931
1932 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1933
1934         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1935         * epiphany-ibld.c: Regenerate.
1936         * fr30-ibld.c: Regenerate.
1937         * frv-ibld.c: Regenerate.
1938         * ip2k-ibld.c: Regenerate.
1939         * iq2000-ibld.c: Regenerate.
1940         * lm32-ibld.c: Regenerate.
1941         * m32c-ibld.c: Regenerate.
1942         * m32r-ibld.c: Regenerate.
1943         * mep-ibld.c: Regenerate.
1944         * mt-ibld.c: Regenerate.
1945         * or1k-ibld.c: Regenerate.
1946         * xc16x-ibld.c: Regenerate.
1947         * xstormy16-ibld.c: Regenerate.
1948
1949 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1950
1951         * epiphany-dis.c: Regenerated from latest cpu files.
1952
1953 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1954
1955         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1956         test bit.
1957
1958 2016-01-25  Renlin Li  <renlin.li@arm.com>
1959
1960         * arm-dis.c (mapping_symbol_for_insn): New function.
1961         (find_ifthen_state): Call mapping_symbol_for_insn().
1962
1963 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1964
1965         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1966         of MSR UAO immediate operand.
1967
1968 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1969
1970         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1971         instruction support.
1972
1973 2016-01-17  Alan Modra  <amodra@gmail.com>
1974
1975         * configure: Regenerate.
1976
1977 2016-01-14  Nick Clifton  <nickc@redhat.com>
1978
1979         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1980         instructions that can support stack pointer operations.
1981         * rl78-decode.c: Regenerate.
1982         * rl78-dis.c: Fix display of stack pointer in MOVW based
1983         instructions.
1984
1985 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1986
1987         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1988         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1989         erxtatus_el1 and erxaddr_el1.
1990
1991 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1992
1993         * arm-dis.c (arm_opcodes): Add "esb".
1994         (thumb_opcodes): Likewise.
1995
1996 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1997
1998         * ppc-opc.c <xscmpnedp>: Delete.
1999         <xvcmpnedp>: Likewise.
2000         <xvcmpnedp.>: Likewise.
2001         <xvcmpnesp>: Likewise.
2002         <xvcmpnesp.>: Likewise.
2003
2004 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
2005
2006         PR gas/13050
2007         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2008         addition to ISA_A.
2009
2010 2016-01-01  Alan Modra  <amodra@gmail.com>
2011
2012         Update year range in copyright notice of all files.
2013
2014 For older changes see ChangeLog-2015
2015 \f
2016 Copyright (C) 2016 Free Software Foundation, Inc.
2017
2018 Copying and distribution of this file, with or without modification,
2019 are permitted in any medium without royalty provided the copyright
2020 notice and this notice are preserved.
2021
2022 Local Variables:
2023 mode: change-log
2024 left-margin: 8
2025 fill-column: 74
2026 version-control: never
2027 End: