opcodes/ChangeLog

   1 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutis/20699
   4         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
   5         sizeflag.
   6
   7 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
   8
   9         PR binutis/20704
  10         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
  11
  12 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
  13
  14         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
  15         local variable to `index_regno'.
  16
  17 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
  18
  19         * arc-tbl.h: Removed any "inv.+" instructions from the table.
  20
  21 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
  22
  23         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
  24         usage on ISA basis.
  25
  26 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
  27
  28         PR target/20666
  29         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
  30
  31 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
  32
  33         PR target/20667
  34         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
  35         available.
  36
  37 2016-10-07  Alan Modra  <amodra@gmail.com>
  38
  39         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
  40
  41 2016-10-06  Alan Modra  <amodra@gmail.com>
  42
  43         * aarch64-opc.c: Spell fall through comments consistently.
  44         * i386-dis.c: Likewise.
  45         * aarch64-dis.c: Add missing fall through comments.
  46         * aarch64-opc.c: Likewise.
  47         * arc-dis.c: Likewise.
  48         * arm-dis.c: Likewise.
  49         * i386-dis.c: Likewise.
  50         * m68k-dis.c: Likewise.
  51         * mep-asm.c: Likewise.
  52         * ns32k-dis.c: Likewise.
  53         * sh-dis.c: Likewise.
  54         * tic4x-dis.c: Likewise.
  55         * tic6x-dis.c: Likewise.
  56         * vax-dis.c: Likewise.
  57
  58 2016-10-06  Alan Modra  <amodra@gmail.com>
  59
  60         * arc-ext.c (create_map): Add missing break.
  61         * msp430-decode.opc (encode_as): Likewise.
  62         * msp430-decode.c: Regenerate.
  63
  64 2016-10-06  Alan Modra  <amodra@gmail.com>
  65
  66         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
  67         * crx-dis.c (print_insn_crx): Likewise.
  68
  69 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  70
  71         PR binutils/20657
  72         * i386-dis.c (putop): Don't assign alt twice.
  73
  74 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
  75
  76         PR target/20553
  77         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
  78
  79 2016-09-29  Alan Modra  <amodra@gmail.com>
  80
  81         * ppc-opc.c (L): Make compulsory.
  82         (LOPT): New, optional form of L.
  83         (HTM_R): Define as LOPT.
  84         (L0, L1): Delete.
  85         (L32OPT): New, optional for 32-bit L.
  86         (L2OPT): New, 2-bit L for dcbf.
  87         (SVC_LEC): Update.
  88         (L2): Define.
  89         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
  90         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
  91         <dcbf>: Use L2OPT.
  92         <tlbiel, tlbie>: Use LOPT.
  93         <wclr, wclrall>: Use L2.
  94
  95 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
  96
  97         * Makefile.in: Regenerate.
  98         * configure: Likewise.
  99
 100 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 101
 102         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 103         (EXTINSN2OP): Use EXTINSN2OPF.
 104         (bspeekm, bspop, modapp): New extension instructions.
 105         * arc-opc.c (F_DNZ_ND): Define.
 106         (F_DNZ_D): Likewise.
 107         (F_SIZEB1): Changed.
 108         (C_DNZ_D): Define.
 109         (C_HARD): Changed.
 110         * arc-tbl.h (dbnz): New instruction.
 111         (prealloc): Allow it for ARC EM.
 112         (xbfu): Likewise.
 113
 114 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 115
 116         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 117         after commas in addresses.
 118         (aarch64_print_operand): Likewise.
 119
 120 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 121
 122         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 123         rather than "should be" or "expected to be" in error messages.
 124
 125 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 126
 127         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 128         (print_mnemonic_name): ...here.
 129         (print_comment): New function.
 130         (print_aarch64_insn): Call it.
 131         * aarch64-opc.c (aarch64_conds): Add SVE names.
 132         (aarch64_print_operand): Print alternative condition names in
 133         a comment.
 134
 135 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 136
 137         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 138         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 139         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 140         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 141         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 142         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 143         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 144         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 145         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 146         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 147         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 148         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 149         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 150         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 151         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 152         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 153         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 154         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 155         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 156         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 157         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 158         (aarch64_feature_sve): New variable.
 159         (SVE): New macro.
 160         (_SVE_INSN): Likewise.
 161         (aarch64_opcode_table): Add SVE instructions.
 162         * aarch64-opc.h (extract_fields): Declare.
 163         * aarch64-opc-2.c: Regenerate.
 164         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 165         * aarch64-asm-2.c: Regenerate.
 166         * aarch64-dis.c (extract_fields): Make global.
 167         (do_misc_decoding): Handle the new SVE aarch64_ops.
 168         * aarch64-dis-2.c: Regenerate.
 169
 170 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 171
 172         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 173         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 174         aarch64_field_kinds.
 175         * aarch64-opc.c (fields): Add corresponding entries.
 176         * aarch64-asm.c (aarch64_get_variant): New function.
 177         (aarch64_encode_variant_using_iclass): Likewise.
 178         (aarch64_opcode_encode): Call it.
 179         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 180         (aarch64_opcode_decode): Call it.
 181
 182 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 183
 184         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 185         and FP register operands.
 186         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 187         (FLD_SVE_Vn): New aarch64_field_kinds.
 188         * aarch64-opc.c (fields): Add corresponding entries.
 189         (aarch64_print_operand): Handle the new SVE core and FP register
 190         operands.
 191         * aarch64-opc-2.c: Regenerate.
 192         * aarch64-asm-2.c: Likewise.
 193         * aarch64-dis-2.c: Likewise.
 194
 195 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 196
 197         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 198         immediate operands.
 199         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 200         * aarch64-opc.c (fields): Add corresponding entry.
 201         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 202         operands.
 203         (aarch64_print_operand): Likewise.
 204         * aarch64-opc-2.c: Regenerate.
 205         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 206         (ins_sve_float_zero_one): New inserters.
 207         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 208         (aarch64_ins_sve_float_half_two): Likewise.
 209         (aarch64_ins_sve_float_zero_one): Likewise.
 210         * aarch64-asm-2.c: Regenerate.
 211         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 212         (ext_sve_float_zero_one): New extractors.
 213         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 214         (aarch64_ext_sve_float_half_two): Likewise.
 215         (aarch64_ext_sve_float_zero_one): Likewise.
 216         * aarch64-dis-2.c: Regenerate.
 217
 218 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 219
 220         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 221         integer immediate operands.
 222         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 223         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 224         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 225         * aarch64-opc.c (fields): Add corresponding entries.
 226         (operand_general_constraint_met_p): Handle the new SVE integer
 227         immediate operands.
 228         (aarch64_print_operand): Likewise.
 229         (aarch64_sve_dupm_mov_immediate_p): New function.
 230         * aarch64-opc-2.c: Regenerate.
 231         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 232         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 233         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 234         (aarch64_ins_limm): ...here.
 235         (aarch64_ins_inv_limm): New function.
 236         (aarch64_ins_sve_aimm): Likewise.
 237         (aarch64_ins_sve_asimm): Likewise.
 238         (aarch64_ins_sve_limm_mov): Likewise.
 239         (aarch64_ins_sve_shlimm): Likewise.
 240         (aarch64_ins_sve_shrimm): Likewise.
 241         * aarch64-asm-2.c: Regenerate.
 242         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 243         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 244         * aarch64-dis.c (decode_limm): New function, split out from...
 245         (aarch64_ext_limm): ...here.
 246         (aarch64_ext_inv_limm): New function.
 247         (decode_sve_aimm): Likewise.
 248         (aarch64_ext_sve_aimm): Likewise.
 249         (aarch64_ext_sve_asimm): Likewise.
 250         (aarch64_ext_sve_limm_mov): Likewise.
 251         (aarch64_top_bit): Likewise.
 252         (aarch64_ext_sve_shlimm): Likewise.
 253         (aarch64_ext_sve_shrimm): Likewise.
 254         * aarch64-dis-2.c: Regenerate.
 255
 256 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 257
 258         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 259         operands.
 260         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 261         the AARCH64_MOD_MUL_VL entry.
 262         (value_aligned_p): Cope with non-power-of-two alignments.
 263         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 264         (print_immediate_offset_address): Likewise.
 265         (aarch64_print_operand): Likewise.
 266         * aarch64-opc-2.c: Regenerate.
 267         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 268         (ins_sve_addr_ri_s9xvl): New inserters.
 269         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 270         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 271         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 272         * aarch64-asm-2.c: Regenerate.
 273         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 274         (ext_sve_addr_ri_s9xvl): New extractors.
 275         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 276         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 277         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 278         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 279         * aarch64-dis-2.c: Regenerate.
 280
 281 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 282
 283         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 284         address operands.
 285         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 286         (FLD_SVE_xs_22): New aarch64_field_kinds.
 287         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 288         (get_operand_specific_data): New function.
 289         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 290         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 291         (operand_general_constraint_met_p): Handle the new SVE address
 292         operands.
 293         (sve_reg): New array.
 294         (get_addr_sve_reg_name): New function.
 295         (aarch64_print_operand): Handle the new SVE address operands.
 296         * aarch64-opc-2.c: Regenerate.
 297         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 298         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 299         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 300         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 301         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 302         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 303         (aarch64_ins_sve_addr_zi_u5): Likewise.
 304         (aarch64_ins_sve_addr_zz): Likewise.
 305         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 306         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 307         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 308         * aarch64-asm-2.c: Regenerate.
 309         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 310         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 311         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 312         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 313         (aarch64_ext_sve_addr_ri_u6): Likewise.
 314         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 315         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 316         (aarch64_ext_sve_addr_zi_u5): Likewise.
 317         (aarch64_ext_sve_addr_zz): Likewise.
 318         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 319         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 320         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 321         * aarch64-dis-2.c: Regenerate.
 322
 323 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 324
 325         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 326         AARCH64_OPND_SVE_PATTERN_SCALED.
 327         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 328         * aarch64-opc.c (fields): Add a corresponding entry.
 329         (set_multiplier_out_of_range_error): New function.
 330         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 331         (operand_general_constraint_met_p): Handle
 332         AARCH64_OPND_SVE_PATTERN_SCALED.
 333         (print_register_offset_address): Use PRIi64 to print the
 334         shift amount.
 335         (aarch64_print_operand): Likewise.  Handle
 336         AARCH64_OPND_SVE_PATTERN_SCALED.
 337         * aarch64-opc-2.c: Regenerate.
 338         * aarch64-asm.h (ins_sve_scale): New inserter.
 339         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 340         * aarch64-asm-2.c: Regenerate.
 341         * aarch64-dis.h (ext_sve_scale): New inserter.
 342         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 343         * aarch64-dis-2.c: Regenerate.
 344
 345 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 346
 347         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 348         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 349         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 350         (FLD_SVE_prfop): Likewise.
 351         * aarch64-opc.c: Include libiberty.h.
 352         (aarch64_sve_pattern_array): New variable.
 353         (aarch64_sve_prfop_array): Likewise.
 354         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 355         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 356         AARCH64_OPND_SVE_PRFOP.
 357         * aarch64-asm-2.c: Regenerate.
 358         * aarch64-dis-2.c: Likewise.
 359         * aarch64-opc-2.c: Likewise.
 360
 361 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 362
 363         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 364         AARCH64_OPND_QLF_P_[ZM].
 365         (aarch64_print_operand): Print /z and /m where appropriate.
 366
 367 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 368
 369         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 370         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 371         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 372         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 373         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 374         * aarch64-opc.c (fields): Add corresponding entries here.
 375         (operand_general_constraint_met_p): Check that SVE register lists
 376         have the correct length.  Check the ranges of SVE index registers.
 377         Check for cases where p8-p15 are used in 3-bit predicate fields.
 378         (aarch64_print_operand): Handle the new SVE operands.
 379         * aarch64-opc-2.c: Regenerate.
 380         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 381         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 382         (aarch64_ins_sve_reglist): Likewise.
 383         * aarch64-asm-2.c: Regenerate.
 384         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 385         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 386         (aarch64_ext_sve_reglist): Likewise.
 387         * aarch64-dis-2.c: Regenerate.
 388
 389 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 390
 391         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 392         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 393         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 394         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 395         tied operands.
 396
 397 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 398
 399         * aarch64-opc.c (get_offset_int_reg_name): New function.
 400         (print_immediate_offset_address): Likewise.
 401         (print_register_offset_address): Take the base and offset
 402         registers as parameters.
 403         (aarch64_print_operand): Update caller accordingly.  Use
 404         print_immediate_offset_address.
 405
 406 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 407
 408         * aarch64-opc.c (BANK): New macro.
 409         (R32, R64): Take a register number as argument
 410         (int_reg): Use BANK.
 411
 412 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 413
 414         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 415         (aarch64_print_operand): Update accordingly.
 416
 417 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 418
 419         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 420         for FPIMM.
 421         * aarch64-asm.h (ins_fpimm): New inserter.
 422         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 423         * aarch64-asm-2.c: Regenerate.
 424         * aarch64-dis.h (ext_fpimm): New extractor.
 425         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 426         (aarch64_ext_fpimm): New function.
 427         * aarch64-dis-2.c: Regenerate.
 428
 429 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 430
 431         * aarch64-asm.c: Include libiberty.h.
 432         (insert_fields): New function.
 433         (aarch64_ins_imm): Use it.
 434         * aarch64-dis.c (extract_fields): New function.
 435         (aarch64_ext_imm): Use it.
 436
 437 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 438
 439         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 440         with an esize parameter.
 441         (operand_general_constraint_met_p): Update accordingly.
 442         Fix misindented code.
 443         * aarch64-asm.c (aarch64_ins_limm): Update call to
 444         aarch64_logical_immediate_p.
 445
 446 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 447
 448         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 449
 450 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 451
 452         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 453
 454 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 455
 456         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 457
 458 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 459
 460         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 461         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 462         xor3>: Delete mnemonics.
 463         <cp_abort>: Rename mnemonic from ...
 464         <cpabort>: ...to this.
 465         <setb>: Change to a X form instruction.
 466         <sync>: Change to 1 operand form.
 467         <copy>: Delete mnemonic.
 468         <copy_first>: Rename mnemonic from ...
 469         <copy>: ...to this.
 470         <paste, paste.>: Delete mnemonics.
 471         <paste_last>: Rename mnemonic from ...
 472         <paste.>: ...to this.
 473
 474 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 475
 476         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 477
 478 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 479
 480         * s390-mkopc.c (main): Support alternate arch strings.
 481
 482 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 483
 484         * s390-opc.txt: Fix kmctr instruction type.
 485
 486 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 487
 488         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 489         * i386-init.h: Regenerated.
 490
 491 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 492
 493         * opcodes/arc-dis.c (print_insn_arc): Changed.
 494
 495 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 496
 497         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 498         camellia_fl.
 499
 500 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 501
 502         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 503         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 504         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 505
 506 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 507
 508         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 509         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 510         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 511         PREFIX_MOD_3_0FAE_REG_4.
 512         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 513         PREFIX_MOD_3_0FAE_REG_4.
 514         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 515         (cpu_flags): Add CpuPTWRITE.
 516         * i386-opc.h (CpuPTWRITE): New.
 517         (i386_cpu_flags): Add cpuptwrite.
 518         * i386-opc.tbl: Add ptwrite instruction.
 519         * i386-init.h: Regenerated.
 520         * i386-tbl.h: Likewise.
 521
 522 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 523
 524         * arc-dis.h: Wrap around in extern "C".
 525
 526 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 527
 528         * aarch64-tbl.h (V8_2_INSN): New macro.
 529         (aarch64_opcode_table): Use it.
 530
 531 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 532
 533         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 534         CORE_INSN, __FP_INSN and SIMD_INSN.
 535
 536 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 537
 538         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 539         (aarch64_opcode_table): Update uses accordingly.
 540
 541 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 542         Kwok Cheung Yeung  <kcy@codesourcery.com>
 543
 544         opcodes/
 545         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 546         'e_cmplwi' to 'e_cmpli' instead.
 547         (OPVUPRT, OPVUPRT_MASK): Define.
 548         (powerpc_opcodes): Add E200Z4 insns.
 549         (vle_opcodes): Add context save/restore insns.
 550
 551 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 552
 553         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 554         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 555         "j".
 556
 557 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 558
 559         * arc-nps400-tbl.h: Change block comments to GNU format.
 560         * arc-dis.c: Add new globals addrtypenames,
 561         addrtypenames_max, and addtypeunknown.
 562         (get_addrtype): New function.
 563         (print_insn_arc): Print colons and address types when
 564         required.
 565         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 566         define insert and extract functions for all address types.
 567         (arc_operands): Add operands for colon and all address
 568         types.
 569         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 570         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 571         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 572         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 573         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 574         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 575
 576 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 577
 578         * configure: Regenerated.
 579
 580 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 581
 582         * arc-dis.c (skipclass): New structure.
 583         (decodelist): New variable.
 584         (is_compatible_p): New function.
 585         (new_element): Likewise.
 586         (skip_class_p): Likewise.
 587         (find_format_from_table): Use skip_class_p function.
 588         (find_format): Decode first the extension instructions.
 589         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 590         e_flags.
 591         (parse_option): New function.
 592         (parse_disassembler_options): Likewise.
 593         (print_arc_disassembler_options): Likewise.
 594         (print_insn_arc): Use parse_disassembler_options function.  Proper
 595         select ARCv2 cpu variant.
 596         * disassemble.c (disassembler_usage): Add ARC disassembler
 597         options.
 598
 599 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 600
 601         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 602         annotation from the "nal" entry and reorder it beyond "bltzal".
 603
 604 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 605
 606         * sparc-opc.c (ldtxa): New macro.
 607         (sparc_opcodes): Use the macro defined above to add entries for
 608         the LDTXA instructions.
 609         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 610         instruction.
 611
 612 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 613
 614         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 615         and "jmpc".
 616
 617 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 618
 619         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 620         (movzb): Adjust to cover all permitted suffixes.
 621         (movzw): New.
 622         * i386-tbl.h: Re-generate.
 623
 624 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 625
 626         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 627         (lgdt): Remove Tbyte from non-64-bit variant.
 628         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 629         xsaves64, xsavec64): Remove Disp16.
 630         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 631         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 632         64-bit variants.
 633         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 634         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 635         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 636         64-bit variants.
 637         * i386-tbl.h: Re-generate.
 638
 639 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 640
 641         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 642         * i386-tbl.h: Re-generate.
 643
 644 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 645
 646         * arm-dis.c (print_insn): Fix typo in comment.
 647
 648 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 649
 650         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 651         range of ldst_elemlist operands.
 652         (print_register_list): Use PRIi64 to print the index.
 653         (aarch64_print_operand): Likewise.
 654
 655 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 656
 657         * mcore-opc.h: Remove sentinal.
 658         * mcore-dis.c (print_insn_mcore): Adjust.
 659
 660 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 661
 662         * arc-opc.c: Correct description of availability of NPS400
 663         features.
 664
 665 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 666
 667         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 668         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 669         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 670         xor3>: New mnemonics.
 671         <setb>: Change to a VX form instruction.
 672         (insert_sh6): Add support for rldixor.
 673         (extract_sh6): Likewise.
 674
 675 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 676
 677         * arc-ext.h: Wrap in extern C.
 678
 679 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 680
 681         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 682         Use same method for determining instruction length on ARC700 and
 683         NPS-400.
 684         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 685         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 686         with the NPS400 subclass.
 687         * arc-opc.c: Likewise.
 688
 689 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 690
 691         * sparc-opc.c (rdasr): New macro.
 692         (wrasr): Likewise.
 693         (rdpr): Likewise.
 694         (wrpr): Likewise.
 695         (rdhpr): Likewise.
 696         (wrhpr): Likewise.
 697         (sparc_opcodes): Use the macros above to fix and expand the
 698         definition of read/write instructions from/to
 699         asr/privileged/hyperprivileged instructions.
 700         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 701         %hva_mask_nz.  Prefer softint_set and softint_clear over
 702         set_softint and clear_softint.
 703         (print_insn_sparc): Support %ver in Rd.
 704
 705 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 706
 707         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 708         architecture according to the hardware capabilities they require.
 709
 710 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 711
 712         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 713         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 714         bfd_mach_sparc_v9{c,d,e,v,m}.
 715         * sparc-opc.c (MASK_V9C): Define.
 716         (MASK_V9D): Likewise.
 717         (MASK_V9E): Likewise.
 718         (MASK_V9V): Likewise.
 719         (MASK_V9M): Likewise.
 720         (v6): Add MASK_V9{C,D,E,V,M}.
 721         (v6notlet): Likewise.
 722         (v7): Likewise.
 723         (v8): Likewise.
 724         (v9): Likewise.
 725         (v9andleon): Likewise.
 726         (v9a): Likewise.
 727         (v9b): Likewise.
 728         (v9c): Define.
 729         (v9d): Likewise.
 730         (v9e): Likewise.
 731         (v9v): Likewise.
 732         (v9m): Likewise.
 733         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 734
 735 2016-06-15  Nick Clifton  <nickc@redhat.com>
 736
 737         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 738         constants to match expected behaviour.
 739         (nds32_parse_opcode): Likewise.  Also for whitespace.
 740
 741 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 742
 743         * arc-opc.c (extract_rhv1): Extract value from insn.
 744
 745 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 746
 747         * arc-nps400-tbl.h: Add ldbit instruction.
 748         * arc-opc.c: Add flag classes required for ldbit.
 749
 750 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 751
 752         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 753         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 754         support the above instructions.
 755
 756 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 757
 758         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 759         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 760         csma, cbba, zncv, and hofs.
 761         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 762         support the above instructions.
 763
 764 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 765
 766         * arc-nps400-tbl.h: Add andab and orab instructions.
 767
 768 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 769
 770         * arc-nps400-tbl.h: Add addl-like instructions.
 771
 772 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 773
 774         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 775
 776 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 777
 778         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 779         instructions.
 780
 781 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 782
 783         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 784         variable.
 785         (init_disasm): Handle new command line option "insnlength".
 786         (print_s390_disassembler_options): Mention new option in help
 787         output.
 788         (print_insn_s390): Use the encoded insn length when dumping
 789         unknown instructions.
 790
 791 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 792
 793         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 794          to the address and set as symbol address for LDS/ STS immediate operands.
 795
 796 2016-06-07  Alan Modra  <amodra@gmail.com>
 797
 798         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 799         cpu for "vle" to e500.
 800         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 801         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 802         (PPCNONE): Delete, substitute throughout.
 803         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 804         except for major opcode 4 and 31.
 805         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 806
 807 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 808
 809         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 810         ARM_EXT_RAS in relevant entries.
 811
 812 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 813
 814         PR binutils/20196
 815         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 816         opcodes for E6500.
 817
 818 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 819
 820         PR binutis/18386
 821         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 822         (indir_v_mode): New.
 823         Add comments for '&'.
 824         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 825         (putop): Handle '&'.
 826         (intel_operand_size): Handle indir_v_mode.
 827         (OP_E_register): Likewise.
 828         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 829         64-bit indirect call/jmp for AMD64.
 830         * i386-tbl.h: Regenerated
 831
 832 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 833
 834         * arc-dis.c (struct arc_operand_iterator): New structure.
 835         (find_format_from_table): All the old content from find_format,
 836         with some minor adjustments, and parameter renaming.
 837         (find_format_long_instructions): New function.
 838         (find_format): Rewritten.
 839         (arc_insn_length): Add LSB parameter.
 840         (extract_operand_value): New function.
 841         (operand_iterator_next): New function.
 842         (print_insn_arc): Use new functions to find opcode, and iterator
 843         over operands.
 844         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 845         (extract_nps_3bit_dst_short): New function.
 846         (insert_nps_3bit_src2_short): New function.
 847         (extract_nps_3bit_src2_short): New function.
 848         (insert_nps_bitop1_size): New function.
 849         (extract_nps_bitop1_size): New function.
 850         (insert_nps_bitop2_size): New function.
 851         (extract_nps_bitop2_size): New function.
 852         (insert_nps_bitop_mod4_msb): New function.
 853         (extract_nps_bitop_mod4_msb): New function.
 854         (insert_nps_bitop_mod4_lsb): New function.
 855         (extract_nps_bitop_mod4_lsb): New function.
 856         (insert_nps_bitop_dst_pos3_pos4): New function.
 857         (extract_nps_bitop_dst_pos3_pos4): New function.
 858         (insert_nps_bitop_ins_ext): New function.
 859         (extract_nps_bitop_ins_ext): New function.
 860         (arc_operands): Add new operands.
 861         (arc_long_opcodes): New global array.
 862         (arc_num_long_opcodes): New global.
 863         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 864
 865 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 866
 867         * nds32-asm.h: Add extern "C".
 868         * sh-opc.h: Likewise.
 869
 870 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 871
 872         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 873         0,b,limm to the rflt instruction.
 874
 875 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 876
 877         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 878         constant.
 879
 880 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 881
 882         PR gas/20145
 883         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 884         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 885         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 886         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 887         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 888         * i386-init.h: Regenerated.
 889
 890 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 891
 892         PR gas/20145
 893         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 894         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 895         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 896         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 897         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 898         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 899         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 900         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 901         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 902         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 903         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 904         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 905         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 906         CpuRegMask for AVX512.
 907         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 908         and CpuRegMask.
 909         (set_bitfield_from_cpu_flag_init): New function.
 910         (set_bitfield): Remove const on f.  Call
 911         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 912         * i386-opc.h (CpuRegMMX): New.
 913         (CpuRegXMM): Likewise.
 914         (CpuRegYMM): Likewise.
 915         (CpuRegZMM): Likewise.
 916         (CpuRegMask): Likewise.
 917         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 918         and cpuregmask.
 919         * i386-init.h: Regenerated.
 920         * i386-tbl.h: Likewise.
 921
 922 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 923
 924         PR gas/20154
 925         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 926         (opcode_modifiers): Add AMD64 and Intel64.
 927         (main): Properly verify CpuMax.
 928         * i386-opc.h (CpuAMD64): Removed.
 929         (CpuIntel64): Likewise.
 930         (CpuMax): Set to CpuNo64.
 931         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 932         (AMD64): New.
 933         (Intel64): Likewise.
 934         (i386_opcode_modifier): Add amd64 and intel64.
 935         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 936         on call and jmp.
 937         * i386-init.h: Regenerated.
 938         * i386-tbl.h: Likewise.
 939
 940 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 941
 942         PR gas/20154
 943         * i386-gen.c (main): Fail if CpuMax is incorrect.
 944         * i386-opc.h (CpuMax): Set to CpuIntel64.
 945         * i386-tbl.h: Regenerated.
 946
 947 2016-05-27  Nick Clifton  <nickc@redhat.com>
 948
 949         PR target/20150
 950         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 951         (msp430dis_opcode_unsigned): New function.
 952         (msp430dis_opcode_signed): New function.
 953         (msp430_singleoperand): Use the new opcode reading functions.
 954         Only disassenmble bytes if they were successfully read.
 955         (msp430_doubleoperand): Likewise.
 956         (msp430_branchinstr): Likewise.
 957         (msp430x_callx_instr): Likewise.
 958         (print_insn_msp430): Check that it is safe to read bytes before
 959         attempting disassembly.  Use the new opcode reading functions.
 960
 961 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 962
 963         * ppc-opc.c (CY): New define.  Document it.
 964         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 965
 966 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 967
 968         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 969         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 970         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 971         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 972         CPU_ANY_AVX_FLAGS.
 973         * i386-init.h: Regenerated.
 974
 975 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 976
 977         PR gas/20141
 978         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 979         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 980         * i386-init.h: Regenerated.
 981
 982 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 983
 984         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 985         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 986         * i386-init.h: Regenerated.
 987
 988 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 989
 990         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 991         information.
 992         (print_insn_arc): Set insn_type information.
 993         * arc-opc.c (C_CC): Add F_CLASS_COND.
 994         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 995         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 996         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 997         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 998         (brne, brne_s, jeq_s, jne_s): Likewise.
 999
1000 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1001
1002         * arc-tbl.h (neg): New instruction variant.
1003
1004 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1005
1006         * arc-dis.c (find_format, find_format, get_auxreg)
1007         (print_insn_arc): Changed.
1008         * arc-ext.h (INSERT_XOP): Likewise.
1009
1010 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1011
1012         * tic54x-dis.c (sprint_mmr): Adjust.
1013         * tic54x-opc.c: Likewise.
1014
1015 2016-05-19  Alan Modra  <amodra@gmail.com>
1016
1017         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1018
1019 2016-05-19  Alan Modra  <amodra@gmail.com>
1020
1021         * ppc-opc.c: Formatting.
1022         (NSISIGNOPT): Define.
1023         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1024
1025 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1026
1027         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1028         replacing references to `micromips_ase' throughout.
1029         (_print_insn_mips): Don't use file-level microMIPS annotation to
1030         determine the disassembly mode with the symbol table.
1031
1032 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1033
1034         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1035
1036 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1037
1038         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1039         mips64r6.
1040         * mips-opc.c (D34): New macro.
1041         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1042
1043 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1044
1045         * i386-dis.c (prefix_table): Add RDPID instruction.
1046         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1047         (cpu_flags): Add RDPID bitfield.
1048         * i386-opc.h (enum): Add RDPID element.
1049         (i386_cpu_flags): Add RDPID field.
1050         * i386-opc.tbl: Add RDPID instruction.
1051         * i386-init.h: Regenerate.
1052         * i386-tbl.h: Regenerate.
1053
1054 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1055
1056         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1057         branch type of a symbol.
1058         (print_insn): Likewise.
1059
1060 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1061
1062         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1063         Mainline Security Extensions instructions.
1064         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1065         Extensions instructions.
1066         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1067         instructions.
1068         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1069         special registers.
1070
1071 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1072
1073         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1074
1075 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1076
1077         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1078         (arcExtMap_genOpcode): Likewise.
1079         * arc-opc.c (arg_32bit_rc): Define new variable.
1080         (arg_32bit_u6): Likewise.
1081         (arg_32bit_limm): Likewise.
1082
1083 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1084
1085         * aarch64-gen.c (VERIFIER): Define.
1086         * aarch64-opc.c (VERIFIER): Define.
1087         (verify_ldpsw): Use static linkage.
1088         * aarch64-opc.h (verify_ldpsw): Remove.
1089         * aarch64-tbl.h: Use VERIFIER for verifiers.
1090
1091 2016-04-28  Nick Clifton  <nickc@redhat.com>
1092
1093         PR target/19722
1094         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1095         * aarch64-opc.c (verify_ldpsw): New function.
1096         * aarch64-opc.h (verify_ldpsw): New prototype.
1097         * aarch64-tbl.h: Add initialiser for verifier field.
1098         (LDPSW): Set verifier to verify_ldpsw.
1099
1100 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1101
1102         PR binutils/19983
1103         PR binutils/19984
1104         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1105         smaller than address size.
1106
1107 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1108
1109         * alpha-dis.c: Regenerate.
1110         * crx-dis.c: Likewise.
1111         * disassemble.c: Likewise.
1112         * epiphany-opc.c: Likewise.
1113         * fr30-opc.c: Likewise.
1114         * frv-opc.c: Likewise.
1115         * ip2k-opc.c: Likewise.
1116         * iq2000-opc.c: Likewise.
1117         * lm32-opc.c: Likewise.
1118         * lm32-opinst.c: Likewise.
1119         * m32c-opc.c: Likewise.
1120         * m32r-opc.c: Likewise.
1121         * m32r-opinst.c: Likewise.
1122         * mep-opc.c: Likewise.
1123         * mt-opc.c: Likewise.
1124         * or1k-opc.c: Likewise.
1125         * or1k-opinst.c: Likewise.
1126         * tic80-opc.c: Likewise.
1127         * xc16x-opc.c: Likewise.
1128         * xstormy16-opc.c: Likewise.
1129
1130 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1131
1132         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1133         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1134         calcsd, and calcxd instructions.
1135         * arc-opc.c (insert_nps_bitop_size): Delete.
1136         (extract_nps_bitop_size): Delete.
1137         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1138         (extract_nps_qcmp_m3): Define.
1139         (extract_nps_qcmp_m2): Define.
1140         (extract_nps_qcmp_m1): Define.
1141         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1142         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1143         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1144         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1145         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1146         NPS_QCMP_M3.
1147
1148 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1149
1150         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1151
1152 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1153
1154         * Makefile.in: Regenerated with automake 1.11.6.
1155         * aclocal.m4: Likewise.
1156
1157 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1158
1159         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1160         instructions.
1161         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1162         (extract_nps_cmem_uimm16): New function.
1163         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1164
1165 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1166
1167         * arc-dis.c (arc_insn_length): New function.
1168         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1169         (find_format): Change insnLen parameter to unsigned.
1170
1171 2016-04-13  Nick Clifton  <nickc@redhat.com>
1172
1173         PR target/19937
1174         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1175         the LD.B and LD.BU instructions.
1176
1177 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1178
1179         * arc-dis.c (find_format): Check for extension flags.
1180         (print_flags): New function.
1181         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1182         .extAuxRegister.
1183         * arc-ext.c (arcExtMap_coreRegName): Use
1184         LAST_EXTENSION_CORE_REGISTER.
1185         (arcExtMap_coreReadWrite): Likewise.
1186         (dump_ARC_extmap): Update printing.
1187         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1188         (arc_aux_regs): Add cpu field.
1189         * arc-regs.h: Add cpu field, lower case name aux registers.
1190
1191 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1192
1193         * arc-tbl.h: Add rtsc, sleep with no arguments.
1194
1195 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1196
1197         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1198         Initialize.
1199         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1200         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1201         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1202         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1203         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1204         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1205         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1206         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1207         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1208         (arc_opcode arc_opcodes): Null terminate the array.
1209         (arc_num_opcodes): Remove.
1210         * arc-ext.h (INSERT_XOP): Define.
1211         (extInstruction_t): Likewise.
1212         (arcExtMap_instName): Delete.
1213         (arcExtMap_insn): New function.
1214         (arcExtMap_genOpcode): Likewise.
1215         * arc-ext.c (ExtInstruction): Remove.
1216         (create_map): Zero initialize instruction fields.
1217         (arcExtMap_instName): Remove.
1218         (arcExtMap_insn): New function.
1219         (dump_ARC_extmap): More info while debuging.
1220         (arcExtMap_genOpcode): New function.
1221         * arc-dis.c (find_format): New function.
1222         (print_insn_arc): Use find_format.
1223         (arc_get_disassembler): Enable dump_ARC_extmap only when
1224         debugging.
1225
1226 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1227
1228         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1229         instruction bits out.
1230
1231 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1232
1233         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1234         * arc-opc.c (arc_flag_operands): Add new flags.
1235         (arc_flag_classes): Add new classes.
1236
1237 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1238
1239         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1240
1241 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1242
1243         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1244         encode1, rflt, crc16, and crc32 instructions.
1245         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1246         (arc_flag_classes): Add C_NPS_R.
1247         (insert_nps_bitop_size_2b): New function.
1248         (extract_nps_bitop_size_2b): Likewise.
1249         (insert_nps_bitop_uimm8): Likewise.
1250         (extract_nps_bitop_uimm8): Likewise.
1251         (arc_operands): Add new operand entries.
1252
1253 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1254
1255         * arc-regs.h: Add a new subclass field.  Add double assist
1256         accumulator register values.
1257         * arc-tbl.h: Use DPA subclass to mark the double assist
1258         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1259         * arc-opc.c (RSP): Define instead of SP.
1260         (arc_aux_regs): Add the subclass field.
1261
1262 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1263
1264         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1265
1266 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1267
1268         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1269         NPS_R_SRC1.
1270
1271 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1272
1273         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1274         issues.  No functional changes.
1275
1276 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1277
1278         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1279         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1280         (RTT): Remove duplicate.
1281         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1282         (PCT_CONFIG*): Remove.
1283         (D1L, D1H, D2H, D2L): Define.
1284
1285 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1286
1287         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1288
1289 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1290
1291         * arc-tbl.h (invld07): Remove.
1292         * arc-ext-tbl.h: New file.
1293         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1294         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1295
1296 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1297
1298         Fix -Wstack-usage warnings.
1299         * aarch64-dis.c (print_operands): Substitute size.
1300         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1301
1302 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1303
1304         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1305         to get a proper diagnostic when an invalid ASR register is used.
1306
1307 2016-03-22  Nick Clifton  <nickc@redhat.com>
1308
1309         * configure: Regenerate.
1310
1311 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1312
1313         * arc-nps400-tbl.h: New file.
1314         * arc-opc.c: Add top level comment.
1315         (insert_nps_3bit_dst): New function.
1316         (extract_nps_3bit_dst): New function.
1317         (insert_nps_3bit_src2): New function.
1318         (extract_nps_3bit_src2): New function.
1319         (insert_nps_bitop_size): New function.
1320         (extract_nps_bitop_size): New function.
1321         (arc_flag_operands): Add nps400 entries.
1322         (arc_flag_classes): Add nps400 entries.
1323         (arc_operands): Add nps400 entries.
1324         (arc_opcodes): Add nps400 include.
1325
1326 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1327
1328         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1329         the new class enum values.
1330
1331 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1332
1333         * arc-dis.c (print_insn_arc): Handle nps400.
1334
1335 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1336
1337         * arc-opc.c (BASE): Delete.
1338
1339 2016-03-18  Nick Clifton  <nickc@redhat.com>
1340
1341         PR target/19721
1342         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1343         of MOV insn that aliases an ORR insn.
1344
1345 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1346
1347         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1348
1349 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1350
1351         * mcore-opc.h: Add const qualifiers.
1352         * microblaze-opc.h (struct op_code_struct): Likewise.
1353         * sh-opc.h: Likewise.
1354         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1355         (tic4x_print_op): Likewise.
1356
1357 2016-03-02  Alan Modra  <amodra@gmail.com>
1358
1359         * or1k-desc.h: Regenerate.
1360         * fr30-ibld.c: Regenerate.
1361         * rl78-decode.c: Regenerate.
1362
1363 2016-03-01  Nick Clifton  <nickc@redhat.com>
1364
1365         PR target/19747
1366         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1367
1368 2016-02-24  Renlin Li  <renlin.li@arm.com>
1369
1370         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1371         (print_insn_coprocessor): Support fp16 instructions.
1372
1373 2016-02-24  Renlin Li  <renlin.li@arm.com>
1374
1375         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1376         vminnm, vrint(mpna).
1377
1378 2016-02-24  Renlin Li  <renlin.li@arm.com>
1379
1380         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1381         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1382
1383 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1384
1385         * i386-dis.c (print_insn): Parenthesize expression to prevent
1386         truncated addresses.
1387         (OP_J): Likewise.
1388
1389 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1390             Janek van Oirschot  <jvanoirs@synopsys.com>
1391
1392         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1393         variable.
1394
1395 2016-02-04  Nick Clifton  <nickc@redhat.com>
1396
1397         PR target/19561
1398         * msp430-dis.c (print_insn_msp430): Add a special case for
1399         decoding an RRC instruction with the ZC bit set in the extension
1400         word.
1401
1402 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1403
1404         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1405         * epiphany-ibld.c: Regenerate.
1406         * fr30-ibld.c: Regenerate.
1407         * frv-ibld.c: Regenerate.
1408         * ip2k-ibld.c: Regenerate.
1409         * iq2000-ibld.c: Regenerate.
1410         * lm32-ibld.c: Regenerate.
1411         * m32c-ibld.c: Regenerate.
1412         * m32r-ibld.c: Regenerate.
1413         * mep-ibld.c: Regenerate.
1414         * mt-ibld.c: Regenerate.
1415         * or1k-ibld.c: Regenerate.
1416         * xc16x-ibld.c: Regenerate.
1417         * xstormy16-ibld.c: Regenerate.
1418
1419 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1420
1421         * epiphany-dis.c: Regenerated from latest cpu files.
1422
1423 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1424
1425         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1426         test bit.
1427
1428 2016-01-25  Renlin Li  <renlin.li@arm.com>
1429
1430         * arm-dis.c (mapping_symbol_for_insn): New function.
1431         (find_ifthen_state): Call mapping_symbol_for_insn().
1432
1433 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1434
1435         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1436         of MSR UAO immediate operand.
1437
1438 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1439
1440         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1441         instruction support.
1442
1443 2016-01-17  Alan Modra  <amodra@gmail.com>
1444
1445         * configure: Regenerate.
1446
1447 2016-01-14  Nick Clifton  <nickc@redhat.com>
1448
1449         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1450         instructions that can support stack pointer operations.
1451         * rl78-decode.c: Regenerate.
1452         * rl78-dis.c: Fix display of stack pointer in MOVW based
1453         instructions.
1454
1455 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1456
1457         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1458         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1459         erxtatus_el1 and erxaddr_el1.
1460
1461 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1462
1463         * arm-dis.c (arm_opcodes): Add "esb".
1464         (thumb_opcodes): Likewise.
1465
1466 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1467
1468         * ppc-opc.c <xscmpnedp>: Delete.
1469         <xvcmpnedp>: Likewise.
1470         <xvcmpnedp.>: Likewise.
1471         <xvcmpnesp>: Likewise.
1472         <xvcmpnesp.>: Likewise.
1473
1474 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1475
1476         PR gas/13050
1477         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1478         addition to ISA_A.
1479
1480 2016-01-01  Alan Modra  <amodra@gmail.com>
1481
1482         Update year range in copyright notice of all files.
1483
1484 For older changes see ChangeLog-2015
1485 \f
1486 Copyright (C) 2016 Free Software Foundation, Inc.
1487
1488 Copying and distribution of this file, with or without modification,
1489 are permitted in any medium without royalty provided the copyright
1490 notice and this notice are preserved.
1491
1492 Local Variables:
1493 mode: change-log
1494 left-margin: 8
1495 fill-column: 74
1496 version-control: never
1497 End: