opcodes/ChangeLog

   1 2016-10-06  Alan Modra  <amodra@gmail.com>
   2
   3         * arc-ext.c (create_map): Add missing break.
   4         * msp430-decode.opc (encode_as): Likewise.
   5         * msp430-decode.c: Regenerate.
   6
   7 2016-10-06  Alan Modra  <amodra@gmail.com>
   8
   9         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
  10         * crx-dis.c (print_insn_crx): Likewise.
  11
  12 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  13
  14         PR binutils/20657
  15         * i386-dis.c (putop): Don't assign alt twice.
  16
  17 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
  18
  19         PR target/20553
  20         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
  21
  22 2016-09-29  Alan Modra  <amodra@gmail.com>
  23
  24         * ppc-opc.c (L): Make compulsory.
  25         (LOPT): New, optional form of L.
  26         (HTM_R): Define as LOPT.
  27         (L0, L1): Delete.
  28         (L32OPT): New, optional for 32-bit L.
  29         (L2OPT): New, 2-bit L for dcbf.
  30         (SVC_LEC): Update.
  31         (L2): Define.
  32         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
  33         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
  34         <dcbf>: Use L2OPT.
  35         <tlbiel, tlbie>: Use LOPT.
  36         <wclr, wclrall>: Use L2.
  37
  38 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
  39
  40         * Makefile.in: Regenerate.
  41         * configure: Likewise.
  42
  43 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
  44
  45         * arc-ext-tbl.h (EXTINSN2OPF): Define.
  46         (EXTINSN2OP): Use EXTINSN2OPF.
  47         (bspeekm, bspop, modapp): New extension instructions.
  48         * arc-opc.c (F_DNZ_ND): Define.
  49         (F_DNZ_D): Likewise.
  50         (F_SIZEB1): Changed.
  51         (C_DNZ_D): Define.
  52         (C_HARD): Changed.
  53         * arc-tbl.h (dbnz): New instruction.
  54         (prealloc): Allow it for ARC EM.
  55         (xbfu): Likewise.
  56
  57 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  58
  59         * aarch64-opc.c (print_immediate_offset_address): Print spaces
  60         after commas in addresses.
  61         (aarch64_print_operand): Likewise.
  62
  63 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  64
  65         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
  66         rather than "should be" or "expected to be" in error messages.
  67
  68 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  69
  70         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
  71         (print_mnemonic_name): ...here.
  72         (print_comment): New function.
  73         (print_aarch64_insn): Call it.
  74         * aarch64-opc.c (aarch64_conds): Add SVE names.
  75         (aarch64_print_operand): Print alternative condition names in
  76         a comment.
  77
  78 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  79
  80         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
  81         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
  82         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
  83         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
  84         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
  85         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
  86         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
  87         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
  88         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
  89         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
  90         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
  91         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
  92         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
  93         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
  94         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
  95         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
  96         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
  97         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
  98         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
  99         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 100         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 101         (aarch64_feature_sve): New variable.
 102         (SVE): New macro.
 103         (_SVE_INSN): Likewise.
 104         (aarch64_opcode_table): Add SVE instructions.
 105         * aarch64-opc.h (extract_fields): Declare.
 106         * aarch64-opc-2.c: Regenerate.
 107         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 108         * aarch64-asm-2.c: Regenerate.
 109         * aarch64-dis.c (extract_fields): Make global.
 110         (do_misc_decoding): Handle the new SVE aarch64_ops.
 111         * aarch64-dis-2.c: Regenerate.
 112
 113 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 114
 115         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 116         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 117         aarch64_field_kinds.
 118         * aarch64-opc.c (fields): Add corresponding entries.
 119         * aarch64-asm.c (aarch64_get_variant): New function.
 120         (aarch64_encode_variant_using_iclass): Likewise.
 121         (aarch64_opcode_encode): Call it.
 122         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 123         (aarch64_opcode_decode): Call it.
 124
 125 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 126
 127         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 128         and FP register operands.
 129         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 130         (FLD_SVE_Vn): New aarch64_field_kinds.
 131         * aarch64-opc.c (fields): Add corresponding entries.
 132         (aarch64_print_operand): Handle the new SVE core and FP register
 133         operands.
 134         * aarch64-opc-2.c: Regenerate.
 135         * aarch64-asm-2.c: Likewise.
 136         * aarch64-dis-2.c: Likewise.
 137
 138 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 139
 140         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 141         immediate operands.
 142         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 143         * aarch64-opc.c (fields): Add corresponding entry.
 144         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 145         operands.
 146         (aarch64_print_operand): Likewise.
 147         * aarch64-opc-2.c: Regenerate.
 148         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 149         (ins_sve_float_zero_one): New inserters.
 150         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 151         (aarch64_ins_sve_float_half_two): Likewise.
 152         (aarch64_ins_sve_float_zero_one): Likewise.
 153         * aarch64-asm-2.c: Regenerate.
 154         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 155         (ext_sve_float_zero_one): New extractors.
 156         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 157         (aarch64_ext_sve_float_half_two): Likewise.
 158         (aarch64_ext_sve_float_zero_one): Likewise.
 159         * aarch64-dis-2.c: Regenerate.
 160
 161 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 162
 163         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 164         integer immediate operands.
 165         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 166         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 167         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 168         * aarch64-opc.c (fields): Add corresponding entries.
 169         (operand_general_constraint_met_p): Handle the new SVE integer
 170         immediate operands.
 171         (aarch64_print_operand): Likewise.
 172         (aarch64_sve_dupm_mov_immediate_p): New function.
 173         * aarch64-opc-2.c: Regenerate.
 174         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 175         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 176         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 177         (aarch64_ins_limm): ...here.
 178         (aarch64_ins_inv_limm): New function.
 179         (aarch64_ins_sve_aimm): Likewise.
 180         (aarch64_ins_sve_asimm): Likewise.
 181         (aarch64_ins_sve_limm_mov): Likewise.
 182         (aarch64_ins_sve_shlimm): Likewise.
 183         (aarch64_ins_sve_shrimm): Likewise.
 184         * aarch64-asm-2.c: Regenerate.
 185         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 186         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 187         * aarch64-dis.c (decode_limm): New function, split out from...
 188         (aarch64_ext_limm): ...here.
 189         (aarch64_ext_inv_limm): New function.
 190         (decode_sve_aimm): Likewise.
 191         (aarch64_ext_sve_aimm): Likewise.
 192         (aarch64_ext_sve_asimm): Likewise.
 193         (aarch64_ext_sve_limm_mov): Likewise.
 194         (aarch64_top_bit): Likewise.
 195         (aarch64_ext_sve_shlimm): Likewise.
 196         (aarch64_ext_sve_shrimm): Likewise.
 197         * aarch64-dis-2.c: Regenerate.
 198
 199 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 200
 201         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 202         operands.
 203         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 204         the AARCH64_MOD_MUL_VL entry.
 205         (value_aligned_p): Cope with non-power-of-two alignments.
 206         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 207         (print_immediate_offset_address): Likewise.
 208         (aarch64_print_operand): Likewise.
 209         * aarch64-opc-2.c: Regenerate.
 210         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 211         (ins_sve_addr_ri_s9xvl): New inserters.
 212         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 213         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 214         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 215         * aarch64-asm-2.c: Regenerate.
 216         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 217         (ext_sve_addr_ri_s9xvl): New extractors.
 218         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 219         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 220         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 221         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 222         * aarch64-dis-2.c: Regenerate.
 223
 224 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 225
 226         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 227         address operands.
 228         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 229         (FLD_SVE_xs_22): New aarch64_field_kinds.
 230         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 231         (get_operand_specific_data): New function.
 232         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 233         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 234         (operand_general_constraint_met_p): Handle the new SVE address
 235         operands.
 236         (sve_reg): New array.
 237         (get_addr_sve_reg_name): New function.
 238         (aarch64_print_operand): Handle the new SVE address operands.
 239         * aarch64-opc-2.c: Regenerate.
 240         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 241         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 242         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 243         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 244         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 245         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 246         (aarch64_ins_sve_addr_zi_u5): Likewise.
 247         (aarch64_ins_sve_addr_zz): Likewise.
 248         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 249         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 250         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 251         * aarch64-asm-2.c: Regenerate.
 252         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 253         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 254         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 255         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 256         (aarch64_ext_sve_addr_ri_u6): Likewise.
 257         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 258         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 259         (aarch64_ext_sve_addr_zi_u5): Likewise.
 260         (aarch64_ext_sve_addr_zz): Likewise.
 261         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 262         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 263         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 264         * aarch64-dis-2.c: Regenerate.
 265
 266 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 267
 268         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 269         AARCH64_OPND_SVE_PATTERN_SCALED.
 270         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 271         * aarch64-opc.c (fields): Add a corresponding entry.
 272         (set_multiplier_out_of_range_error): New function.
 273         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 274         (operand_general_constraint_met_p): Handle
 275         AARCH64_OPND_SVE_PATTERN_SCALED.
 276         (print_register_offset_address): Use PRIi64 to print the
 277         shift amount.
 278         (aarch64_print_operand): Likewise.  Handle
 279         AARCH64_OPND_SVE_PATTERN_SCALED.
 280         * aarch64-opc-2.c: Regenerate.
 281         * aarch64-asm.h (ins_sve_scale): New inserter.
 282         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 283         * aarch64-asm-2.c: Regenerate.
 284         * aarch64-dis.h (ext_sve_scale): New inserter.
 285         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 286         * aarch64-dis-2.c: Regenerate.
 287
 288 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 289
 290         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 291         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 292         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 293         (FLD_SVE_prfop): Likewise.
 294         * aarch64-opc.c: Include libiberty.h.
 295         (aarch64_sve_pattern_array): New variable.
 296         (aarch64_sve_prfop_array): Likewise.
 297         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 298         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 299         AARCH64_OPND_SVE_PRFOP.
 300         * aarch64-asm-2.c: Regenerate.
 301         * aarch64-dis-2.c: Likewise.
 302         * aarch64-opc-2.c: Likewise.
 303
 304 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 305
 306         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 307         AARCH64_OPND_QLF_P_[ZM].
 308         (aarch64_print_operand): Print /z and /m where appropriate.
 309
 310 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 311
 312         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 313         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 314         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 315         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 316         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 317         * aarch64-opc.c (fields): Add corresponding entries here.
 318         (operand_general_constraint_met_p): Check that SVE register lists
 319         have the correct length.  Check the ranges of SVE index registers.
 320         Check for cases where p8-p15 are used in 3-bit predicate fields.
 321         (aarch64_print_operand): Handle the new SVE operands.
 322         * aarch64-opc-2.c: Regenerate.
 323         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 324         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 325         (aarch64_ins_sve_reglist): Likewise.
 326         * aarch64-asm-2.c: Regenerate.
 327         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 328         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 329         (aarch64_ext_sve_reglist): Likewise.
 330         * aarch64-dis-2.c: Regenerate.
 331
 332 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 333
 334         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 335         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 336         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 337         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 338         tied operands.
 339
 340 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 341
 342         * aarch64-opc.c (get_offset_int_reg_name): New function.
 343         (print_immediate_offset_address): Likewise.
 344         (print_register_offset_address): Take the base and offset
 345         registers as parameters.
 346         (aarch64_print_operand): Update caller accordingly.  Use
 347         print_immediate_offset_address.
 348
 349 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 350
 351         * aarch64-opc.c (BANK): New macro.
 352         (R32, R64): Take a register number as argument
 353         (int_reg): Use BANK.
 354
 355 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 356
 357         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 358         (aarch64_print_operand): Update accordingly.
 359
 360 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 361
 362         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 363         for FPIMM.
 364         * aarch64-asm.h (ins_fpimm): New inserter.
 365         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 366         * aarch64-asm-2.c: Regenerate.
 367         * aarch64-dis.h (ext_fpimm): New extractor.
 368         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 369         (aarch64_ext_fpimm): New function.
 370         * aarch64-dis-2.c: Regenerate.
 371
 372 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 373
 374         * aarch64-asm.c: Include libiberty.h.
 375         (insert_fields): New function.
 376         (aarch64_ins_imm): Use it.
 377         * aarch64-dis.c (extract_fields): New function.
 378         (aarch64_ext_imm): Use it.
 379
 380 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 381
 382         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 383         with an esize parameter.
 384         (operand_general_constraint_met_p): Update accordingly.
 385         Fix misindented code.
 386         * aarch64-asm.c (aarch64_ins_limm): Update call to
 387         aarch64_logical_immediate_p.
 388
 389 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 390
 391         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 392
 393 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 394
 395         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 396
 397 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 398
 399         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 400
 401 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 402
 403         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 404         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 405         xor3>: Delete mnemonics.
 406         <cp_abort>: Rename mnemonic from ...
 407         <cpabort>: ...to this.
 408         <setb>: Change to a X form instruction.
 409         <sync>: Change to 1 operand form.
 410         <copy>: Delete mnemonic.
 411         <copy_first>: Rename mnemonic from ...
 412         <copy>: ...to this.
 413         <paste, paste.>: Delete mnemonics.
 414         <paste_last>: Rename mnemonic from ...
 415         <paste.>: ...to this.
 416
 417 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 418
 419         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 420
 421 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 422
 423         * s390-mkopc.c (main): Support alternate arch strings.
 424
 425 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 426
 427         * s390-opc.txt: Fix kmctr instruction type.
 428
 429 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 430
 431         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 432         * i386-init.h: Regenerated.
 433
 434 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 435
 436         * opcodes/arc-dis.c (print_insn_arc): Changed.
 437
 438 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 439
 440         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 441         camellia_fl.
 442
 443 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 444
 445         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 446         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 447         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 448
 449 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 450
 451         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 452         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 453         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 454         PREFIX_MOD_3_0FAE_REG_4.
 455         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 456         PREFIX_MOD_3_0FAE_REG_4.
 457         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 458         (cpu_flags): Add CpuPTWRITE.
 459         * i386-opc.h (CpuPTWRITE): New.
 460         (i386_cpu_flags): Add cpuptwrite.
 461         * i386-opc.tbl: Add ptwrite instruction.
 462         * i386-init.h: Regenerated.
 463         * i386-tbl.h: Likewise.
 464
 465 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 466
 467         * arc-dis.h: Wrap around in extern "C".
 468
 469 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 470
 471         * aarch64-tbl.h (V8_2_INSN): New macro.
 472         (aarch64_opcode_table): Use it.
 473
 474 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 475
 476         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 477         CORE_INSN, __FP_INSN and SIMD_INSN.
 478
 479 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 480
 481         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 482         (aarch64_opcode_table): Update uses accordingly.
 483
 484 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 485         Kwok Cheung Yeung  <kcy@codesourcery.com>
 486
 487         opcodes/
 488         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 489         'e_cmplwi' to 'e_cmpli' instead.
 490         (OPVUPRT, OPVUPRT_MASK): Define.
 491         (powerpc_opcodes): Add E200Z4 insns.
 492         (vle_opcodes): Add context save/restore insns.
 493
 494 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 495
 496         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 497         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 498         "j".
 499
 500 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 501
 502         * arc-nps400-tbl.h: Change block comments to GNU format.
 503         * arc-dis.c: Add new globals addrtypenames,
 504         addrtypenames_max, and addtypeunknown.
 505         (get_addrtype): New function.
 506         (print_insn_arc): Print colons and address types when
 507         required.
 508         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 509         define insert and extract functions for all address types.
 510         (arc_operands): Add operands for colon and all address
 511         types.
 512         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 513         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 514         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 515         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 516         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 517         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 518
 519 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 520
 521         * configure: Regenerated.
 522
 523 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 524
 525         * arc-dis.c (skipclass): New structure.
 526         (decodelist): New variable.
 527         (is_compatible_p): New function.
 528         (new_element): Likewise.
 529         (skip_class_p): Likewise.
 530         (find_format_from_table): Use skip_class_p function.
 531         (find_format): Decode first the extension instructions.
 532         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 533         e_flags.
 534         (parse_option): New function.
 535         (parse_disassembler_options): Likewise.
 536         (print_arc_disassembler_options): Likewise.
 537         (print_insn_arc): Use parse_disassembler_options function.  Proper
 538         select ARCv2 cpu variant.
 539         * disassemble.c (disassembler_usage): Add ARC disassembler
 540         options.
 541
 542 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 543
 544         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 545         annotation from the "nal" entry and reorder it beyond "bltzal".
 546
 547 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 548
 549         * sparc-opc.c (ldtxa): New macro.
 550         (sparc_opcodes): Use the macro defined above to add entries for
 551         the LDTXA instructions.
 552         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 553         instruction.
 554
 555 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 556
 557         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 558         and "jmpc".
 559
 560 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 561
 562         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 563         (movzb): Adjust to cover all permitted suffixes.
 564         (movzw): New.
 565         * i386-tbl.h: Re-generate.
 566
 567 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 568
 569         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 570         (lgdt): Remove Tbyte from non-64-bit variant.
 571         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 572         xsaves64, xsavec64): Remove Disp16.
 573         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 574         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 575         64-bit variants.
 576         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 577         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 578         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 579         64-bit variants.
 580         * i386-tbl.h: Re-generate.
 581
 582 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 583
 584         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 585         * i386-tbl.h: Re-generate.
 586
 587 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 588
 589         * arm-dis.c (print_insn): Fix typo in comment.
 590
 591 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 592
 593         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 594         range of ldst_elemlist operands.
 595         (print_register_list): Use PRIi64 to print the index.
 596         (aarch64_print_operand): Likewise.
 597
 598 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 599
 600         * mcore-opc.h: Remove sentinal.
 601         * mcore-dis.c (print_insn_mcore): Adjust.
 602
 603 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 604
 605         * arc-opc.c: Correct description of availability of NPS400
 606         features.
 607
 608 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 609
 610         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 611         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 612         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 613         xor3>: New mnemonics.
 614         <setb>: Change to a VX form instruction.
 615         (insert_sh6): Add support for rldixor.
 616         (extract_sh6): Likewise.
 617
 618 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 619
 620         * arc-ext.h: Wrap in extern C.
 621
 622 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 623
 624         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 625         Use same method for determining instruction length on ARC700 and
 626         NPS-400.
 627         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 628         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 629         with the NPS400 subclass.
 630         * arc-opc.c: Likewise.
 631
 632 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 633
 634         * sparc-opc.c (rdasr): New macro.
 635         (wrasr): Likewise.
 636         (rdpr): Likewise.
 637         (wrpr): Likewise.
 638         (rdhpr): Likewise.
 639         (wrhpr): Likewise.
 640         (sparc_opcodes): Use the macros above to fix and expand the
 641         definition of read/write instructions from/to
 642         asr/privileged/hyperprivileged instructions.
 643         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 644         %hva_mask_nz.  Prefer softint_set and softint_clear over
 645         set_softint and clear_softint.
 646         (print_insn_sparc): Support %ver in Rd.
 647
 648 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 649
 650         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 651         architecture according to the hardware capabilities they require.
 652
 653 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 654
 655         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 656         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 657         bfd_mach_sparc_v9{c,d,e,v,m}.
 658         * sparc-opc.c (MASK_V9C): Define.
 659         (MASK_V9D): Likewise.
 660         (MASK_V9E): Likewise.
 661         (MASK_V9V): Likewise.
 662         (MASK_V9M): Likewise.
 663         (v6): Add MASK_V9{C,D,E,V,M}.
 664         (v6notlet): Likewise.
 665         (v7): Likewise.
 666         (v8): Likewise.
 667         (v9): Likewise.
 668         (v9andleon): Likewise.
 669         (v9a): Likewise.
 670         (v9b): Likewise.
 671         (v9c): Define.
 672         (v9d): Likewise.
 673         (v9e): Likewise.
 674         (v9v): Likewise.
 675         (v9m): Likewise.
 676         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 677
 678 2016-06-15  Nick Clifton  <nickc@redhat.com>
 679
 680         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 681         constants to match expected behaviour.
 682         (nds32_parse_opcode): Likewise.  Also for whitespace.
 683
 684 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 685
 686         * arc-opc.c (extract_rhv1): Extract value from insn.
 687
 688 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 689
 690         * arc-nps400-tbl.h: Add ldbit instruction.
 691         * arc-opc.c: Add flag classes required for ldbit.
 692
 693 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 694
 695         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 696         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 697         support the above instructions.
 698
 699 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 700
 701         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 702         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 703         csma, cbba, zncv, and hofs.
 704         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 705         support the above instructions.
 706
 707 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 708
 709         * arc-nps400-tbl.h: Add andab and orab instructions.
 710
 711 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 712
 713         * arc-nps400-tbl.h: Add addl-like instructions.
 714
 715 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 716
 717         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 718
 719 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 720
 721         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 722         instructions.
 723
 724 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 725
 726         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 727         variable.
 728         (init_disasm): Handle new command line option "insnlength".
 729         (print_s390_disassembler_options): Mention new option in help
 730         output.
 731         (print_insn_s390): Use the encoded insn length when dumping
 732         unknown instructions.
 733
 734 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 735
 736         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 737          to the address and set as symbol address for LDS/ STS immediate operands.
 738
 739 2016-06-07  Alan Modra  <amodra@gmail.com>
 740
 741         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 742         cpu for "vle" to e500.
 743         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 744         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 745         (PPCNONE): Delete, substitute throughout.
 746         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 747         except for major opcode 4 and 31.
 748         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 749
 750 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 751
 752         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 753         ARM_EXT_RAS in relevant entries.
 754
 755 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 756
 757         PR binutils/20196
 758         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 759         opcodes for E6500.
 760
 761 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 762
 763         PR binutis/18386
 764         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 765         (indir_v_mode): New.
 766         Add comments for '&'.
 767         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 768         (putop): Handle '&'.
 769         (intel_operand_size): Handle indir_v_mode.
 770         (OP_E_register): Likewise.
 771         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 772         64-bit indirect call/jmp for AMD64.
 773         * i386-tbl.h: Regenerated
 774
 775 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 776
 777         * arc-dis.c (struct arc_operand_iterator): New structure.
 778         (find_format_from_table): All the old content from find_format,
 779         with some minor adjustments, and parameter renaming.
 780         (find_format_long_instructions): New function.
 781         (find_format): Rewritten.
 782         (arc_insn_length): Add LSB parameter.
 783         (extract_operand_value): New function.
 784         (operand_iterator_next): New function.
 785         (print_insn_arc): Use new functions to find opcode, and iterator
 786         over operands.
 787         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 788         (extract_nps_3bit_dst_short): New function.
 789         (insert_nps_3bit_src2_short): New function.
 790         (extract_nps_3bit_src2_short): New function.
 791         (insert_nps_bitop1_size): New function.
 792         (extract_nps_bitop1_size): New function.
 793         (insert_nps_bitop2_size): New function.
 794         (extract_nps_bitop2_size): New function.
 795         (insert_nps_bitop_mod4_msb): New function.
 796         (extract_nps_bitop_mod4_msb): New function.
 797         (insert_nps_bitop_mod4_lsb): New function.
 798         (extract_nps_bitop_mod4_lsb): New function.
 799         (insert_nps_bitop_dst_pos3_pos4): New function.
 800         (extract_nps_bitop_dst_pos3_pos4): New function.
 801         (insert_nps_bitop_ins_ext): New function.
 802         (extract_nps_bitop_ins_ext): New function.
 803         (arc_operands): Add new operands.
 804         (arc_long_opcodes): New global array.
 805         (arc_num_long_opcodes): New global.
 806         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 807
 808 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 809
 810         * nds32-asm.h: Add extern "C".
 811         * sh-opc.h: Likewise.
 812
 813 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 814
 815         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 816         0,b,limm to the rflt instruction.
 817
 818 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 819
 820         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 821         constant.
 822
 823 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 824
 825         PR gas/20145
 826         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 827         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 828         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 829         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 830         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 831         * i386-init.h: Regenerated.
 832
 833 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 834
 835         PR gas/20145
 836         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 837         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 838         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 839         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 840         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 841         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 842         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 843         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 844         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 845         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 846         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 847         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 848         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 849         CpuRegMask for AVX512.
 850         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 851         and CpuRegMask.
 852         (set_bitfield_from_cpu_flag_init): New function.
 853         (set_bitfield): Remove const on f.  Call
 854         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 855         * i386-opc.h (CpuRegMMX): New.
 856         (CpuRegXMM): Likewise.
 857         (CpuRegYMM): Likewise.
 858         (CpuRegZMM): Likewise.
 859         (CpuRegMask): Likewise.
 860         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 861         and cpuregmask.
 862         * i386-init.h: Regenerated.
 863         * i386-tbl.h: Likewise.
 864
 865 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 866
 867         PR gas/20154
 868         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 869         (opcode_modifiers): Add AMD64 and Intel64.
 870         (main): Properly verify CpuMax.
 871         * i386-opc.h (CpuAMD64): Removed.
 872         (CpuIntel64): Likewise.
 873         (CpuMax): Set to CpuNo64.
 874         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 875         (AMD64): New.
 876         (Intel64): Likewise.
 877         (i386_opcode_modifier): Add amd64 and intel64.
 878         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 879         on call and jmp.
 880         * i386-init.h: Regenerated.
 881         * i386-tbl.h: Likewise.
 882
 883 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 884
 885         PR gas/20154
 886         * i386-gen.c (main): Fail if CpuMax is incorrect.
 887         * i386-opc.h (CpuMax): Set to CpuIntel64.
 888         * i386-tbl.h: Regenerated.
 889
 890 2016-05-27  Nick Clifton  <nickc@redhat.com>
 891
 892         PR target/20150
 893         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 894         (msp430dis_opcode_unsigned): New function.
 895         (msp430dis_opcode_signed): New function.
 896         (msp430_singleoperand): Use the new opcode reading functions.
 897         Only disassenmble bytes if they were successfully read.
 898         (msp430_doubleoperand): Likewise.
 899         (msp430_branchinstr): Likewise.
 900         (msp430x_callx_instr): Likewise.
 901         (print_insn_msp430): Check that it is safe to read bytes before
 902         attempting disassembly.  Use the new opcode reading functions.
 903
 904 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 905
 906         * ppc-opc.c (CY): New define.  Document it.
 907         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 908
 909 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 910
 911         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 912         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 913         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 914         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 915         CPU_ANY_AVX_FLAGS.
 916         * i386-init.h: Regenerated.
 917
 918 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 919
 920         PR gas/20141
 921         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 922         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 923         * i386-init.h: Regenerated.
 924
 925 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 926
 927         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 928         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 929         * i386-init.h: Regenerated.
 930
 931 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 932
 933         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 934         information.
 935         (print_insn_arc): Set insn_type information.
 936         * arc-opc.c (C_CC): Add F_CLASS_COND.
 937         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 938         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 939         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 940         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 941         (brne, brne_s, jeq_s, jne_s): Likewise.
 942
 943 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 944
 945         * arc-tbl.h (neg): New instruction variant.
 946
 947 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 948
 949         * arc-dis.c (find_format, find_format, get_auxreg)
 950         (print_insn_arc): Changed.
 951         * arc-ext.h (INSERT_XOP): Likewise.
 952
 953 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 954
 955         * tic54x-dis.c (sprint_mmr): Adjust.
 956         * tic54x-opc.c: Likewise.
 957
 958 2016-05-19  Alan Modra  <amodra@gmail.com>
 959
 960         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 961
 962 2016-05-19  Alan Modra  <amodra@gmail.com>
 963
 964         * ppc-opc.c: Formatting.
 965         (NSISIGNOPT): Define.
 966         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 967
 968 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 969
 970         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 971         replacing references to `micromips_ase' throughout.
 972         (_print_insn_mips): Don't use file-level microMIPS annotation to
 973         determine the disassembly mode with the symbol table.
 974
 975 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 976
 977         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 978
 979 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 980
 981         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 982         mips64r6.
 983         * mips-opc.c (D34): New macro.
 984         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 985
 986 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 987
 988         * i386-dis.c (prefix_table): Add RDPID instruction.
 989         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 990         (cpu_flags): Add RDPID bitfield.
 991         * i386-opc.h (enum): Add RDPID element.
 992         (i386_cpu_flags): Add RDPID field.
 993         * i386-opc.tbl: Add RDPID instruction.
 994         * i386-init.h: Regenerate.
 995         * i386-tbl.h: Regenerate.
 996
 997 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 998
 999         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1000         branch type of a symbol.
1001         (print_insn): Likewise.
1002
1003 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1004
1005         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1006         Mainline Security Extensions instructions.
1007         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1008         Extensions instructions.
1009         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1010         instructions.
1011         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1012         special registers.
1013
1014 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1015
1016         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1017
1018 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1019
1020         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1021         (arcExtMap_genOpcode): Likewise.
1022         * arc-opc.c (arg_32bit_rc): Define new variable.
1023         (arg_32bit_u6): Likewise.
1024         (arg_32bit_limm): Likewise.
1025
1026 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1027
1028         * aarch64-gen.c (VERIFIER): Define.
1029         * aarch64-opc.c (VERIFIER): Define.
1030         (verify_ldpsw): Use static linkage.
1031         * aarch64-opc.h (verify_ldpsw): Remove.
1032         * aarch64-tbl.h: Use VERIFIER for verifiers.
1033
1034 2016-04-28  Nick Clifton  <nickc@redhat.com>
1035
1036         PR target/19722
1037         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1038         * aarch64-opc.c (verify_ldpsw): New function.
1039         * aarch64-opc.h (verify_ldpsw): New prototype.
1040         * aarch64-tbl.h: Add initialiser for verifier field.
1041         (LDPSW): Set verifier to verify_ldpsw.
1042
1043 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1044
1045         PR binutils/19983
1046         PR binutils/19984
1047         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1048         smaller than address size.
1049
1050 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1051
1052         * alpha-dis.c: Regenerate.
1053         * crx-dis.c: Likewise.
1054         * disassemble.c: Likewise.
1055         * epiphany-opc.c: Likewise.
1056         * fr30-opc.c: Likewise.
1057         * frv-opc.c: Likewise.
1058         * ip2k-opc.c: Likewise.
1059         * iq2000-opc.c: Likewise.
1060         * lm32-opc.c: Likewise.
1061         * lm32-opinst.c: Likewise.
1062         * m32c-opc.c: Likewise.
1063         * m32r-opc.c: Likewise.
1064         * m32r-opinst.c: Likewise.
1065         * mep-opc.c: Likewise.
1066         * mt-opc.c: Likewise.
1067         * or1k-opc.c: Likewise.
1068         * or1k-opinst.c: Likewise.
1069         * tic80-opc.c: Likewise.
1070         * xc16x-opc.c: Likewise.
1071         * xstormy16-opc.c: Likewise.
1072
1073 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1074
1075         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1076         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1077         calcsd, and calcxd instructions.
1078         * arc-opc.c (insert_nps_bitop_size): Delete.
1079         (extract_nps_bitop_size): Delete.
1080         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1081         (extract_nps_qcmp_m3): Define.
1082         (extract_nps_qcmp_m2): Define.
1083         (extract_nps_qcmp_m1): Define.
1084         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1085         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1086         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1087         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1088         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1089         NPS_QCMP_M3.
1090
1091 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1092
1093         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1094
1095 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1096
1097         * Makefile.in: Regenerated with automake 1.11.6.
1098         * aclocal.m4: Likewise.
1099
1100 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1101
1102         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1103         instructions.
1104         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1105         (extract_nps_cmem_uimm16): New function.
1106         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1107
1108 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1109
1110         * arc-dis.c (arc_insn_length): New function.
1111         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1112         (find_format): Change insnLen parameter to unsigned.
1113
1114 2016-04-13  Nick Clifton  <nickc@redhat.com>
1115
1116         PR target/19937
1117         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1118         the LD.B and LD.BU instructions.
1119
1120 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1121
1122         * arc-dis.c (find_format): Check for extension flags.
1123         (print_flags): New function.
1124         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1125         .extAuxRegister.
1126         * arc-ext.c (arcExtMap_coreRegName): Use
1127         LAST_EXTENSION_CORE_REGISTER.
1128         (arcExtMap_coreReadWrite): Likewise.
1129         (dump_ARC_extmap): Update printing.
1130         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1131         (arc_aux_regs): Add cpu field.
1132         * arc-regs.h: Add cpu field, lower case name aux registers.
1133
1134 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1135
1136         * arc-tbl.h: Add rtsc, sleep with no arguments.
1137
1138 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1139
1140         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1141         Initialize.
1142         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1143         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1144         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1145         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1146         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1147         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1148         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1149         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1150         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1151         (arc_opcode arc_opcodes): Null terminate the array.
1152         (arc_num_opcodes): Remove.
1153         * arc-ext.h (INSERT_XOP): Define.
1154         (extInstruction_t): Likewise.
1155         (arcExtMap_instName): Delete.
1156         (arcExtMap_insn): New function.
1157         (arcExtMap_genOpcode): Likewise.
1158         * arc-ext.c (ExtInstruction): Remove.
1159         (create_map): Zero initialize instruction fields.
1160         (arcExtMap_instName): Remove.
1161         (arcExtMap_insn): New function.
1162         (dump_ARC_extmap): More info while debuging.
1163         (arcExtMap_genOpcode): New function.
1164         * arc-dis.c (find_format): New function.
1165         (print_insn_arc): Use find_format.
1166         (arc_get_disassembler): Enable dump_ARC_extmap only when
1167         debugging.
1168
1169 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1170
1171         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1172         instruction bits out.
1173
1174 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1175
1176         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1177         * arc-opc.c (arc_flag_operands): Add new flags.
1178         (arc_flag_classes): Add new classes.
1179
1180 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1181
1182         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1183
1184 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1185
1186         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1187         encode1, rflt, crc16, and crc32 instructions.
1188         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1189         (arc_flag_classes): Add C_NPS_R.
1190         (insert_nps_bitop_size_2b): New function.
1191         (extract_nps_bitop_size_2b): Likewise.
1192         (insert_nps_bitop_uimm8): Likewise.
1193         (extract_nps_bitop_uimm8): Likewise.
1194         (arc_operands): Add new operand entries.
1195
1196 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1197
1198         * arc-regs.h: Add a new subclass field.  Add double assist
1199         accumulator register values.
1200         * arc-tbl.h: Use DPA subclass to mark the double assist
1201         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1202         * arc-opc.c (RSP): Define instead of SP.
1203         (arc_aux_regs): Add the subclass field.
1204
1205 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1206
1207         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1208
1209 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1210
1211         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1212         NPS_R_SRC1.
1213
1214 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1215
1216         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1217         issues.  No functional changes.
1218
1219 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1220
1221         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1222         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1223         (RTT): Remove duplicate.
1224         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1225         (PCT_CONFIG*): Remove.
1226         (D1L, D1H, D2H, D2L): Define.
1227
1228 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1229
1230         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1231
1232 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1233
1234         * arc-tbl.h (invld07): Remove.
1235         * arc-ext-tbl.h: New file.
1236         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1237         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1238
1239 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1240
1241         Fix -Wstack-usage warnings.
1242         * aarch64-dis.c (print_operands): Substitute size.
1243         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1244
1245 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1246
1247         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1248         to get a proper diagnostic when an invalid ASR register is used.
1249
1250 2016-03-22  Nick Clifton  <nickc@redhat.com>
1251
1252         * configure: Regenerate.
1253
1254 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1255
1256         * arc-nps400-tbl.h: New file.
1257         * arc-opc.c: Add top level comment.
1258         (insert_nps_3bit_dst): New function.
1259         (extract_nps_3bit_dst): New function.
1260         (insert_nps_3bit_src2): New function.
1261         (extract_nps_3bit_src2): New function.
1262         (insert_nps_bitop_size): New function.
1263         (extract_nps_bitop_size): New function.
1264         (arc_flag_operands): Add nps400 entries.
1265         (arc_flag_classes): Add nps400 entries.
1266         (arc_operands): Add nps400 entries.
1267         (arc_opcodes): Add nps400 include.
1268
1269 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1270
1271         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1272         the new class enum values.
1273
1274 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1275
1276         * arc-dis.c (print_insn_arc): Handle nps400.
1277
1278 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1279
1280         * arc-opc.c (BASE): Delete.
1281
1282 2016-03-18  Nick Clifton  <nickc@redhat.com>
1283
1284         PR target/19721
1285         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1286         of MOV insn that aliases an ORR insn.
1287
1288 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1289
1290         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1291
1292 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1293
1294         * mcore-opc.h: Add const qualifiers.
1295         * microblaze-opc.h (struct op_code_struct): Likewise.
1296         * sh-opc.h: Likewise.
1297         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1298         (tic4x_print_op): Likewise.
1299
1300 2016-03-02  Alan Modra  <amodra@gmail.com>
1301
1302         * or1k-desc.h: Regenerate.
1303         * fr30-ibld.c: Regenerate.
1304         * rl78-decode.c: Regenerate.
1305
1306 2016-03-01  Nick Clifton  <nickc@redhat.com>
1307
1308         PR target/19747
1309         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1310
1311 2016-02-24  Renlin Li  <renlin.li@arm.com>
1312
1313         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1314         (print_insn_coprocessor): Support fp16 instructions.
1315
1316 2016-02-24  Renlin Li  <renlin.li@arm.com>
1317
1318         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1319         vminnm, vrint(mpna).
1320
1321 2016-02-24  Renlin Li  <renlin.li@arm.com>
1322
1323         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1324         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1325
1326 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1327
1328         * i386-dis.c (print_insn): Parenthesize expression to prevent
1329         truncated addresses.
1330         (OP_J): Likewise.
1331
1332 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1333             Janek van Oirschot  <jvanoirs@synopsys.com>
1334
1335         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1336         variable.
1337
1338 2016-02-04  Nick Clifton  <nickc@redhat.com>
1339
1340         PR target/19561
1341         * msp430-dis.c (print_insn_msp430): Add a special case for
1342         decoding an RRC instruction with the ZC bit set in the extension
1343         word.
1344
1345 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1346
1347         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1348         * epiphany-ibld.c: Regenerate.
1349         * fr30-ibld.c: Regenerate.
1350         * frv-ibld.c: Regenerate.
1351         * ip2k-ibld.c: Regenerate.
1352         * iq2000-ibld.c: Regenerate.
1353         * lm32-ibld.c: Regenerate.
1354         * m32c-ibld.c: Regenerate.
1355         * m32r-ibld.c: Regenerate.
1356         * mep-ibld.c: Regenerate.
1357         * mt-ibld.c: Regenerate.
1358         * or1k-ibld.c: Regenerate.
1359         * xc16x-ibld.c: Regenerate.
1360         * xstormy16-ibld.c: Regenerate.
1361
1362 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1363
1364         * epiphany-dis.c: Regenerated from latest cpu files.
1365
1366 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1367
1368         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1369         test bit.
1370
1371 2016-01-25  Renlin Li  <renlin.li@arm.com>
1372
1373         * arm-dis.c (mapping_symbol_for_insn): New function.
1374         (find_ifthen_state): Call mapping_symbol_for_insn().
1375
1376 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1377
1378         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1379         of MSR UAO immediate operand.
1380
1381 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1382
1383         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1384         instruction support.
1385
1386 2016-01-17  Alan Modra  <amodra@gmail.com>
1387
1388         * configure: Regenerate.
1389
1390 2016-01-14  Nick Clifton  <nickc@redhat.com>
1391
1392         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1393         instructions that can support stack pointer operations.
1394         * rl78-decode.c: Regenerate.
1395         * rl78-dis.c: Fix display of stack pointer in MOVW based
1396         instructions.
1397
1398 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1399
1400         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1401         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1402         erxtatus_el1 and erxaddr_el1.
1403
1404 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1405
1406         * arm-dis.c (arm_opcodes): Add "esb".
1407         (thumb_opcodes): Likewise.
1408
1409 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1410
1411         * ppc-opc.c <xscmpnedp>: Delete.
1412         <xvcmpnedp>: Likewise.
1413         <xvcmpnedp.>: Likewise.
1414         <xvcmpnesp>: Likewise.
1415         <xvcmpnesp.>: Likewise.
1416
1417 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1418
1419         PR gas/13050
1420         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1421         addition to ISA_A.
1422
1423 2016-01-01  Alan Modra  <amodra@gmail.com>
1424
1425         Update year range in copyright notice of all files.
1426
1427 For older changes see ChangeLog-2015
1428 \f
1429 Copyright (C) 2016 Free Software Foundation, Inc.
1430
1431 Copying and distribution of this file, with or without modification,
1432 are permitted in any medium without royalty provided the copyright
1433 notice and this notice are preserved.
1434
1435 Local Variables:
1436 mode: change-log
1437 left-margin: 8
1438 fill-column: 74
1439 version-control: never
1440 End: