opcodes/ChangeLog

   1 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
   4         variable to `reglane_index'.
   5
   6 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
   7
   8         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
   9
  10 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  11
  12         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
  13
  14 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  15
  16         * mips16-opc.c (mips16_opcodes): Update comment naming structure
  17         members.
  18
  19 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  20
  21         * mips-dis.c (print_mips_disassembler_options): Reformat output.
  22
  23 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  24
  25         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
  26         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
  27
  28 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  29
  30         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
  31
  32 2016-12-01  Nick Clifton  <nickc@redhat.com>
  33
  34         PR binutils/20893
  35         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
  36         opcode designator.
  37
  38 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  39
  40         * arc-opc.c (insert_ra_chk): New function.
  41         (insert_rb_chk): Likewise.
  42         (insert_rad): Update text error message.
  43         (insert_rcd): Likewise.
  44         (insert_rhv2): Likewise.
  45         (insert_r0): Likewise.
  46         (insert_r1): Likewise.
  47         (insert_r2): Likewise.
  48         (insert_r3): Likewise.
  49         (insert_sp): Likewise.
  50         (insert_gp): Likewise.
  51         (insert_pcl): Likewise.
  52         (insert_blink): Likewise.
  53         (insert_ilink1): Likewise.
  54         (insert_ilink2): Likewise.
  55         (insert_ras): Likewise.
  56         (insert_rbs): Likewise.
  57         (insert_rcs): Likewise.
  58         (insert_simm3s): Likewise.
  59         (insert_rrange): Likewise.
  60         (insert_fpel): Likewise.
  61         (insert_blinkel): Likewise.
  62         (insert_pcel): Likewise.
  63         (insert_nps_3bit_dst): Likewise.
  64         (insert_nps_3bit_dst_short): Likewise.
  65         (insert_nps_3bit_src2_short): Likewise.
  66         (insert_nps_bitop_size_2b): Likewise.
  67         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
  68         (RA_CHK): Define.
  69         (RB): Adjust.
  70         (RB_CHK): Define.
  71         (RC): Adjust.
  72         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
  73         * arc-tbl.h (div, divu): All instructions are DIVREM class.
  74         Change first insn argument to check for LP_COUNT usage.
  75         (rem): Likewise.
  76         (ld, ldd): All instructions are LOAD class.  Change first insn
  77         argument to check for LP_COUNT usage.
  78         (st, std): All instructions are STORE class.
  79         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
  80         Change first insn argument to check for LP_COUNT usage.
  81         (mov): All instructions are MOVE class.  Change first insn
  82         argument to check for LP_COUNT usage.
  83
  84 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  85
  86         * arc-dis.c (is_compatible_p): Remove function.
  87         (skip_this_opcode): Don't add any decoding class to decode list.
  88         Remove warning.
  89         (find_format_from_table): Go through all opcodes, and warn if we
  90         use a guessed mnemonic.
  91
  92 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
  93             Amit Pawar  <amit.pawar@amd.com>
  94
  95         PR binutils/20637
  96         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
  97         instructions.
  98
  99 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 100
 101         * configure: Regenerate.
 102
 103 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 104
 105         * sparc-opc.c (HWS_V8): Definition moved from
 106         gas/config/tc-sparc.c.
 107         (HWS_V9): Likewise.
 108         (HWS_VA): Likewise.
 109         (HWS_VB): Likewise.
 110         (HWS_VC): Likewise.
 111         (HWS_VD): Likewise.
 112         (HWS_VE): Likewise.
 113         (HWS_VV): Likewise.
 114         (HWS_VM): Likewise.
 115         (HWS2_VM): Likewise.
 116         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 117         existing entries.
 118
 119 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 120
 121         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 122         instructions.
 123
 124 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 125
 126         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 127         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 128         (aarch64_opcode_table): Add fcmla and fcadd.
 129         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 130         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 131         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 132         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 133         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 134         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 135         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 136         (operand_general_constraint_met_p): Rotate and index range check.
 137         (aarch64_print_operand): Handle rotate operand.
 138         * aarch64-asm-2.c: Regenerate.
 139         * aarch64-dis-2.c: Likewise.
 140         * aarch64-opc-2.c: Likewise.
 141
 142 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 143
 144         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 145         * aarch64-asm-2.c: Regenerate.
 146         * aarch64-dis-2.c: Regenerate.
 147         * aarch64-opc-2.c: Regenerate.
 148
 149 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 150
 151         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 152         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 153         * aarch64-asm-2.c: Regenerate.
 154         * aarch64-dis-2.c: Regenerate.
 155         * aarch64-opc-2.c: Regenerate.
 156
 157 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 158
 159         * aarch64-tbl.h (QL_X1NIL): New.
 160         (arch64_opcode_table): Add ldraa, ldrab.
 161         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 162         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 163         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 164         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 165         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 166         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 167         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 168         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 169         (aarch64_print_operand): Likewise.
 170         * aarch64-asm-2.c: Regenerate.
 171         * aarch64-dis-2.c: Regenerate.
 172         * aarch64-opc-2.c: Regenerate.
 173
 174 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 175
 176         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 177         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 178         * aarch64-asm-2.c: Regenerate.
 179         * aarch64-dis-2.c: Regenerate.
 180         * aarch64-opc-2.c: Regenerate.
 181
 182 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 183
 184         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 185         (AARCH64_OPERANDS): Add Rm_SP.
 186         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 187         * aarch64-asm-2.c: Regenerate.
 188         * aarch64-dis-2.c: Regenerate.
 189         * aarch64-opc-2.c: Regenerate.
 190
 191 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 192
 193         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 194         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 195         autdzb, xpaci, xpacd.
 196         * aarch64-asm-2.c: Regenerate.
 197         * aarch64-dis-2.c: Regenerate.
 198         * aarch64-opc-2.c: Regenerate.
 199
 200 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 201
 202         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 203         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 204         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 205         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 206
 207 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 208
 209         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 210         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 211         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 212         autibsp.
 213         * aarch64-asm-2.c: Regenerate.
 214         * aarch64-dis-2.c: Regenerate.
 215
 216 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 217
 218         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 219
 220 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 221
 222         PR binutils/20799
 223         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 224         * i386-dis.c (EdqwS): Removed.
 225         (dqw_swap_mode): Likewise.
 226         (intel_operand_size): Don't check dqw_swap_mode.
 227         (OP_E_register): Likewise.
 228         (OP_E_memory): Likewise.
 229         (OP_G): Likewise.
 230         (OP_EX): Likewise.
 231         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 232         * i386-tbl.h: Regerated.
 233
 234 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         * i386-opc.tbl: Merge AVX512F vmovq.
 237         * i386-tbl.h: Regerated.
 238
 239 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 240
 241         PR binutils/20701
 242         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 243         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 244         (three_byte_table): Remove THREE_BYTE_0F7A.
 245
 246 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 247
 248         PR binutils/20775
 249         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 250         (FGRPd9_4): Replace 1 with 2.
 251         (FGRPd9_5): Replace 2 with 3.
 252         (FGRPd9_6): Replace 3 with 4.
 253         (FGRPd9_7): Replace 4 with 5.
 254         (FGRPda_5): Replace 5 with 6.
 255         (FGRPdb_4): Replace 6 with 7.
 256         (FGRPde_3): Replace 7 with 8.
 257         (FGRPdf_4): Replace 8 with 9.
 258         (fgrps): Add an entry for Bad_Opcode.
 259
 260 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 261
 262         * arc-opc.c (arc_flag_operands): Add F_DI14.
 263         (arc_flag_classes): Add C_DI14.
 264         * arc-nps400-tbl.h: Add new exc instructions.
 265
 266 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 267
 268         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 269         major opcode 0xa.
 270         * arc-nps-400-tbl.h: Add dcmac instruction.
 271         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 272         (insert_nps_rbdouble_64): Added.
 273         (extract_nps_rbdouble_64): Added.
 274         (insert_nps_proto_size): Added.
 275         (extract_nps_proto_size): Added.
 276
 277 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 278
 279         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 280         relating to long instruction processing, add new limm field.
 281         (OPCODE): Rename to...
 282         (OPCODE_32BIT_INSN): ...this.
 283         (OPCODE_AC): Delete.
 284         (skip_this_opcode): Handle different instruction lengths, update
 285         macro name.
 286         (special_flag_p): Update parameter type.
 287         (find_format_from_table): Update for more instruction lengths.
 288         (find_format_long_instructions): Delete.
 289         (find_format): Update for more instruction lengths.
 290         (arc_insn_length): Likewise.
 291         (extract_operand_value): Update for more instruction lengths.
 292         (operand_iterator_next): Remove code relating to long
 293         instructions.
 294         (arc_opcode_to_insn_type): New function.
 295         (print_insn_arc):Update for more instructions lengths.
 296         * arc-ext.c (extInstruction_t): Change argument type.
 297         * arc-ext.h (extInstruction_t): Change argument type.
 298         * arc-fxi.h: Change type unsigned to unsigned long long
 299         extensively throughout.
 300         * arc-nps400-tbl.h: Add long instructions taken from
 301         arc_long_opcodes table in arc-opc.c.
 302         * arc-opc.c: Update parameter types on insert/extract handlers.
 303         (arc_long_opcodes): Delete.
 304         (arc_num_long_opcodes): Delete.
 305         (arc_opcode_len): Update for more instruction lengths.
 306
 307 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 308
 309         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 310
 311 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 312
 313         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 314         with arc_opcode_len.
 315         (find_format_long_instructions): Likewise.
 316         * arc-opc.c (arc_opcode_len): New function.
 317
 318 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 319
 320         * arc-nps400-tbl.h: Fix some instruction masks.
 321
 322 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 323
 324         * i386-dis.c (REG_82): Removed.
 325         (X86_64_82_REG_0): Likewise.
 326         (X86_64_82_REG_1): Likewise.
 327         (X86_64_82_REG_2): Likewise.
 328         (X86_64_82_REG_3): Likewise.
 329         (X86_64_82_REG_4): Likewise.
 330         (X86_64_82_REG_5): Likewise.
 331         (X86_64_82_REG_6): Likewise.
 332         (X86_64_82_REG_7): Likewise.
 333         (X86_64_82): New.
 334         (dis386): Use X86_64_82 instead of REG_82.
 335         (reg_table): Remove REG_82.
 336         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 337         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 338         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 339         X86_64_82_REG_7.
 340
 341 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 342
 343         PR binutils/20754
 344         * i386-dis.c (REG_82): New.
 345         (X86_64_82_REG_0): Likewise.
 346         (X86_64_82_REG_1): Likewise.
 347         (X86_64_82_REG_2): Likewise.
 348         (X86_64_82_REG_3): Likewise.
 349         (X86_64_82_REG_4): Likewise.
 350         (X86_64_82_REG_5): Likewise.
 351         (X86_64_82_REG_6): Likewise.
 352         (X86_64_82_REG_7): Likewise.
 353         (dis386): Use REG_82.
 354         (reg_table): Add REG_82.
 355         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 356         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 357         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 358
 359 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 360
 361         * i386-dis.c (REG_82): Renamed to ...
 362         (REG_83): This.
 363         (dis386): Updated.
 364         (reg_table): Likewise.
 365
 366 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 367
 368         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 369         * i386-dis-evex.h (evex_table): Updated.
 370         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 371         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 372         (cpu_flags): Add CpuAVX512_4VNNIW.
 373         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 374         (i386_cpu_flags): Add cpuavx512_4vnniw.
 375         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 376         * i386-init.h: Regenerate.
 377         * i386-tbl.h: Ditto.
 378
 379 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 380
 381         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 382         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 383         * i386-dis-evex.h (evex_table): Updated.
 384         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 385         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 386         (cpu_flags): Add CpuAVX512_4FMAPS.
 387         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 388         * i386-opc.h (AVX512_4FMAP): New.
 389         (i386_cpu_flags): Add cpuavx512_4fmaps.
 390         (ImplicitQuadGroup): New.
 391         (i386_opcode_modifier): Add implicitquadgroup.
 392         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 393         * i386-init.h: Regenerate.
 394         * i386-tbl.h: Ditto.
 395
 396 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 397             Andrew Waterman <andrew@sifive.com>
 398
 399         Add support for RISC-V architecture.
 400         * configure.ac: Add entry for bfd_riscv_arch.
 401         * configure: Regenerate.
 402         * disassemble.c (disassembler): Add support for riscv.
 403         (disassembler_usage): Likewise.
 404         * riscv-dis.c: New file.
 405         * riscv-opc.c: New file.
 406
 407 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 408
 409         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 410         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 411         (rm_table): Update the RM_0FAE_REG_7 entry.
 412         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 413         (cpu_flags): Remove CpuPCOMMIT.
 414         * i386-opc.h (CpuPCOMMIT): Removed.
 415         (i386_cpu_flags): Remove cpupcommit.
 416         * i386-opc.tbl: Remove pcommit.
 417         * i386-init.h: Regenerated.
 418         * i386-tbl.h: Likewise.
 419
 420 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 421
 422         PR binutis/20705
 423         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 424         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 425         32-bit mode.  Don't check vex.register_specifier in 32-bit
 426         mode.
 427         (OP_VEX): Check for invalid mask registers.
 428
 429 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 430
 431         PR binutis/20699
 432         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 433         sizeflag.
 434
 435 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 436
 437         PR binutis/20704
 438         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 439
 440 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 441
 442         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 443         local variable to `index_regno'.
 444
 445 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 446
 447         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 448
 449 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 450
 451         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 452         usage on ISA basis.
 453
 454 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 455
 456         PR target/20666
 457         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 458
 459 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 460
 461         PR target/20667
 462         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 463         available.
 464
 465 2016-10-07  Alan Modra  <amodra@gmail.com>
 466
 467         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 468
 469 2016-10-06  Alan Modra  <amodra@gmail.com>
 470
 471         * aarch64-opc.c: Spell fall through comments consistently.
 472         * i386-dis.c: Likewise.
 473         * aarch64-dis.c: Add missing fall through comments.
 474         * aarch64-opc.c: Likewise.
 475         * arc-dis.c: Likewise.
 476         * arm-dis.c: Likewise.
 477         * i386-dis.c: Likewise.
 478         * m68k-dis.c: Likewise.
 479         * mep-asm.c: Likewise.
 480         * ns32k-dis.c: Likewise.
 481         * sh-dis.c: Likewise.
 482         * tic4x-dis.c: Likewise.
 483         * tic6x-dis.c: Likewise.
 484         * vax-dis.c: Likewise.
 485
 486 2016-10-06  Alan Modra  <amodra@gmail.com>
 487
 488         * arc-ext.c (create_map): Add missing break.
 489         * msp430-decode.opc (encode_as): Likewise.
 490         * msp430-decode.c: Regenerate.
 491
 492 2016-10-06  Alan Modra  <amodra@gmail.com>
 493
 494         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 495         * crx-dis.c (print_insn_crx): Likewise.
 496
 497 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 498
 499         PR binutils/20657
 500         * i386-dis.c (putop): Don't assign alt twice.
 501
 502 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 503
 504         PR target/20553
 505         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 506
 507 2016-09-29  Alan Modra  <amodra@gmail.com>
 508
 509         * ppc-opc.c (L): Make compulsory.
 510         (LOPT): New, optional form of L.
 511         (HTM_R): Define as LOPT.
 512         (L0, L1): Delete.
 513         (L32OPT): New, optional for 32-bit L.
 514         (L2OPT): New, 2-bit L for dcbf.
 515         (SVC_LEC): Update.
 516         (L2): Define.
 517         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 518         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 519         <dcbf>: Use L2OPT.
 520         <tlbiel, tlbie>: Use LOPT.
 521         <wclr, wclrall>: Use L2.
 522
 523 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 524
 525         * Makefile.in: Regenerate.
 526         * configure: Likewise.
 527
 528 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 529
 530         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 531         (EXTINSN2OP): Use EXTINSN2OPF.
 532         (bspeekm, bspop, modapp): New extension instructions.
 533         * arc-opc.c (F_DNZ_ND): Define.
 534         (F_DNZ_D): Likewise.
 535         (F_SIZEB1): Changed.
 536         (C_DNZ_D): Define.
 537         (C_HARD): Changed.
 538         * arc-tbl.h (dbnz): New instruction.
 539         (prealloc): Allow it for ARC EM.
 540         (xbfu): Likewise.
 541
 542 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 543
 544         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 545         after commas in addresses.
 546         (aarch64_print_operand): Likewise.
 547
 548 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 549
 550         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 551         rather than "should be" or "expected to be" in error messages.
 552
 553 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 554
 555         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 556         (print_mnemonic_name): ...here.
 557         (print_comment): New function.
 558         (print_aarch64_insn): Call it.
 559         * aarch64-opc.c (aarch64_conds): Add SVE names.
 560         (aarch64_print_operand): Print alternative condition names in
 561         a comment.
 562
 563 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 564
 565         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 566         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 567         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 568         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 569         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 570         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 571         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 572         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 573         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 574         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 575         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 576         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 577         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 578         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 579         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 580         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 581         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 582         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 583         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 584         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 585         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 586         (aarch64_feature_sve): New variable.
 587         (SVE): New macro.
 588         (_SVE_INSN): Likewise.
 589         (aarch64_opcode_table): Add SVE instructions.
 590         * aarch64-opc.h (extract_fields): Declare.
 591         * aarch64-opc-2.c: Regenerate.
 592         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 593         * aarch64-asm-2.c: Regenerate.
 594         * aarch64-dis.c (extract_fields): Make global.
 595         (do_misc_decoding): Handle the new SVE aarch64_ops.
 596         * aarch64-dis-2.c: Regenerate.
 597
 598 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 599
 600         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 601         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 602         aarch64_field_kinds.
 603         * aarch64-opc.c (fields): Add corresponding entries.
 604         * aarch64-asm.c (aarch64_get_variant): New function.
 605         (aarch64_encode_variant_using_iclass): Likewise.
 606         (aarch64_opcode_encode): Call it.
 607         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 608         (aarch64_opcode_decode): Call it.
 609
 610 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 611
 612         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 613         and FP register operands.
 614         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 615         (FLD_SVE_Vn): New aarch64_field_kinds.
 616         * aarch64-opc.c (fields): Add corresponding entries.
 617         (aarch64_print_operand): Handle the new SVE core and FP register
 618         operands.
 619         * aarch64-opc-2.c: Regenerate.
 620         * aarch64-asm-2.c: Likewise.
 621         * aarch64-dis-2.c: Likewise.
 622
 623 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 624
 625         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 626         immediate operands.
 627         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 628         * aarch64-opc.c (fields): Add corresponding entry.
 629         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 630         operands.
 631         (aarch64_print_operand): Likewise.
 632         * aarch64-opc-2.c: Regenerate.
 633         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 634         (ins_sve_float_zero_one): New inserters.
 635         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 636         (aarch64_ins_sve_float_half_two): Likewise.
 637         (aarch64_ins_sve_float_zero_one): Likewise.
 638         * aarch64-asm-2.c: Regenerate.
 639         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 640         (ext_sve_float_zero_one): New extractors.
 641         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 642         (aarch64_ext_sve_float_half_two): Likewise.
 643         (aarch64_ext_sve_float_zero_one): Likewise.
 644         * aarch64-dis-2.c: Regenerate.
 645
 646 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 647
 648         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 649         integer immediate operands.
 650         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 651         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 652         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 653         * aarch64-opc.c (fields): Add corresponding entries.
 654         (operand_general_constraint_met_p): Handle the new SVE integer
 655         immediate operands.
 656         (aarch64_print_operand): Likewise.
 657         (aarch64_sve_dupm_mov_immediate_p): New function.
 658         * aarch64-opc-2.c: Regenerate.
 659         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 660         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 661         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 662         (aarch64_ins_limm): ...here.
 663         (aarch64_ins_inv_limm): New function.
 664         (aarch64_ins_sve_aimm): Likewise.
 665         (aarch64_ins_sve_asimm): Likewise.
 666         (aarch64_ins_sve_limm_mov): Likewise.
 667         (aarch64_ins_sve_shlimm): Likewise.
 668         (aarch64_ins_sve_shrimm): Likewise.
 669         * aarch64-asm-2.c: Regenerate.
 670         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 671         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 672         * aarch64-dis.c (decode_limm): New function, split out from...
 673         (aarch64_ext_limm): ...here.
 674         (aarch64_ext_inv_limm): New function.
 675         (decode_sve_aimm): Likewise.
 676         (aarch64_ext_sve_aimm): Likewise.
 677         (aarch64_ext_sve_asimm): Likewise.
 678         (aarch64_ext_sve_limm_mov): Likewise.
 679         (aarch64_top_bit): Likewise.
 680         (aarch64_ext_sve_shlimm): Likewise.
 681         (aarch64_ext_sve_shrimm): Likewise.
 682         * aarch64-dis-2.c: Regenerate.
 683
 684 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 685
 686         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 687         operands.
 688         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 689         the AARCH64_MOD_MUL_VL entry.
 690         (value_aligned_p): Cope with non-power-of-two alignments.
 691         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 692         (print_immediate_offset_address): Likewise.
 693         (aarch64_print_operand): Likewise.
 694         * aarch64-opc-2.c: Regenerate.
 695         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 696         (ins_sve_addr_ri_s9xvl): New inserters.
 697         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 698         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 699         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 700         * aarch64-asm-2.c: Regenerate.
 701         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 702         (ext_sve_addr_ri_s9xvl): New extractors.
 703         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 704         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 705         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 706         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 707         * aarch64-dis-2.c: Regenerate.
 708
 709 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 710
 711         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 712         address operands.
 713         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 714         (FLD_SVE_xs_22): New aarch64_field_kinds.
 715         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 716         (get_operand_specific_data): New function.
 717         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 718         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 719         (operand_general_constraint_met_p): Handle the new SVE address
 720         operands.
 721         (sve_reg): New array.
 722         (get_addr_sve_reg_name): New function.
 723         (aarch64_print_operand): Handle the new SVE address operands.
 724         * aarch64-opc-2.c: Regenerate.
 725         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 726         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 727         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 728         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 729         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 730         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 731         (aarch64_ins_sve_addr_zi_u5): Likewise.
 732         (aarch64_ins_sve_addr_zz): Likewise.
 733         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 734         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 735         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 736         * aarch64-asm-2.c: Regenerate.
 737         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 738         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 739         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 740         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 741         (aarch64_ext_sve_addr_ri_u6): Likewise.
 742         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 743         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 744         (aarch64_ext_sve_addr_zi_u5): Likewise.
 745         (aarch64_ext_sve_addr_zz): Likewise.
 746         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 747         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 748         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 749         * aarch64-dis-2.c: Regenerate.
 750
 751 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 752
 753         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 754         AARCH64_OPND_SVE_PATTERN_SCALED.
 755         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 756         * aarch64-opc.c (fields): Add a corresponding entry.
 757         (set_multiplier_out_of_range_error): New function.
 758         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 759         (operand_general_constraint_met_p): Handle
 760         AARCH64_OPND_SVE_PATTERN_SCALED.
 761         (print_register_offset_address): Use PRIi64 to print the
 762         shift amount.
 763         (aarch64_print_operand): Likewise.  Handle
 764         AARCH64_OPND_SVE_PATTERN_SCALED.
 765         * aarch64-opc-2.c: Regenerate.
 766         * aarch64-asm.h (ins_sve_scale): New inserter.
 767         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 768         * aarch64-asm-2.c: Regenerate.
 769         * aarch64-dis.h (ext_sve_scale): New inserter.
 770         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 771         * aarch64-dis-2.c: Regenerate.
 772
 773 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 774
 775         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 776         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 777         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 778         (FLD_SVE_prfop): Likewise.
 779         * aarch64-opc.c: Include libiberty.h.
 780         (aarch64_sve_pattern_array): New variable.
 781         (aarch64_sve_prfop_array): Likewise.
 782         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 783         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 784         AARCH64_OPND_SVE_PRFOP.
 785         * aarch64-asm-2.c: Regenerate.
 786         * aarch64-dis-2.c: Likewise.
 787         * aarch64-opc-2.c: Likewise.
 788
 789 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 790
 791         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 792         AARCH64_OPND_QLF_P_[ZM].
 793         (aarch64_print_operand): Print /z and /m where appropriate.
 794
 795 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 796
 797         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 798         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 799         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 800         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 801         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 802         * aarch64-opc.c (fields): Add corresponding entries here.
 803         (operand_general_constraint_met_p): Check that SVE register lists
 804         have the correct length.  Check the ranges of SVE index registers.
 805         Check for cases where p8-p15 are used in 3-bit predicate fields.
 806         (aarch64_print_operand): Handle the new SVE operands.
 807         * aarch64-opc-2.c: Regenerate.
 808         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 809         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 810         (aarch64_ins_sve_reglist): Likewise.
 811         * aarch64-asm-2.c: Regenerate.
 812         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 813         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 814         (aarch64_ext_sve_reglist): Likewise.
 815         * aarch64-dis-2.c: Regenerate.
 816
 817 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 818
 819         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 820         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 821         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 822         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 823         tied operands.
 824
 825 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 826
 827         * aarch64-opc.c (get_offset_int_reg_name): New function.
 828         (print_immediate_offset_address): Likewise.
 829         (print_register_offset_address): Take the base and offset
 830         registers as parameters.
 831         (aarch64_print_operand): Update caller accordingly.  Use
 832         print_immediate_offset_address.
 833
 834 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 835
 836         * aarch64-opc.c (BANK): New macro.
 837         (R32, R64): Take a register number as argument
 838         (int_reg): Use BANK.
 839
 840 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 841
 842         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 843         (aarch64_print_operand): Update accordingly.
 844
 845 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 846
 847         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 848         for FPIMM.
 849         * aarch64-asm.h (ins_fpimm): New inserter.
 850         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 851         * aarch64-asm-2.c: Regenerate.
 852         * aarch64-dis.h (ext_fpimm): New extractor.
 853         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 854         (aarch64_ext_fpimm): New function.
 855         * aarch64-dis-2.c: Regenerate.
 856
 857 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 858
 859         * aarch64-asm.c: Include libiberty.h.
 860         (insert_fields): New function.
 861         (aarch64_ins_imm): Use it.
 862         * aarch64-dis.c (extract_fields): New function.
 863         (aarch64_ext_imm): Use it.
 864
 865 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 866
 867         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 868         with an esize parameter.
 869         (operand_general_constraint_met_p): Update accordingly.
 870         Fix misindented code.
 871         * aarch64-asm.c (aarch64_ins_limm): Update call to
 872         aarch64_logical_immediate_p.
 873
 874 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 875
 876         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 877
 878 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 879
 880         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 881
 882 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 883
 884         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 885
 886 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 887
 888         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 889         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 890         xor3>: Delete mnemonics.
 891         <cp_abort>: Rename mnemonic from ...
 892         <cpabort>: ...to this.
 893         <setb>: Change to a X form instruction.
 894         <sync>: Change to 1 operand form.
 895         <copy>: Delete mnemonic.
 896         <copy_first>: Rename mnemonic from ...
 897         <copy>: ...to this.
 898         <paste, paste.>: Delete mnemonics.
 899         <paste_last>: Rename mnemonic from ...
 900         <paste.>: ...to this.
 901
 902 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 903
 904         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 905
 906 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 907
 908         * s390-mkopc.c (main): Support alternate arch strings.
 909
 910 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 911
 912         * s390-opc.txt: Fix kmctr instruction type.
 913
 914 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 915
 916         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 917         * i386-init.h: Regenerated.
 918
 919 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 920
 921         * opcodes/arc-dis.c (print_insn_arc): Changed.
 922
 923 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 924
 925         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 926         camellia_fl.
 927
 928 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 929
 930         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 931         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 932         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 933
 934 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 935
 936         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 937         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 938         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 939         PREFIX_MOD_3_0FAE_REG_4.
 940         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 941         PREFIX_MOD_3_0FAE_REG_4.
 942         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 943         (cpu_flags): Add CpuPTWRITE.
 944         * i386-opc.h (CpuPTWRITE): New.
 945         (i386_cpu_flags): Add cpuptwrite.
 946         * i386-opc.tbl: Add ptwrite instruction.
 947         * i386-init.h: Regenerated.
 948         * i386-tbl.h: Likewise.
 949
 950 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 951
 952         * arc-dis.h: Wrap around in extern "C".
 953
 954 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 955
 956         * aarch64-tbl.h (V8_2_INSN): New macro.
 957         (aarch64_opcode_table): Use it.
 958
 959 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 960
 961         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 962         CORE_INSN, __FP_INSN and SIMD_INSN.
 963
 964 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 965
 966         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 967         (aarch64_opcode_table): Update uses accordingly.
 968
 969 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 970         Kwok Cheung Yeung  <kcy@codesourcery.com>
 971
 972         opcodes/
 973         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 974         'e_cmplwi' to 'e_cmpli' instead.
 975         (OPVUPRT, OPVUPRT_MASK): Define.
 976         (powerpc_opcodes): Add E200Z4 insns.
 977         (vle_opcodes): Add context save/restore insns.
 978
 979 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 980
 981         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 982         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 983         "j".
 984
 985 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 986
 987         * arc-nps400-tbl.h: Change block comments to GNU format.
 988         * arc-dis.c: Add new globals addrtypenames,
 989         addrtypenames_max, and addtypeunknown.
 990         (get_addrtype): New function.
 991         (print_insn_arc): Print colons and address types when
 992         required.
 993         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 994         define insert and extract functions for all address types.
 995         (arc_operands): Add operands for colon and all address
 996         types.
 997         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 998         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 999         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1000         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1001         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1002         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1003
1004 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1005
1006         * configure: Regenerated.
1007
1008 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1009
1010         * arc-dis.c (skipclass): New structure.
1011         (decodelist): New variable.
1012         (is_compatible_p): New function.
1013         (new_element): Likewise.
1014         (skip_class_p): Likewise.
1015         (find_format_from_table): Use skip_class_p function.
1016         (find_format): Decode first the extension instructions.
1017         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1018         e_flags.
1019         (parse_option): New function.
1020         (parse_disassembler_options): Likewise.
1021         (print_arc_disassembler_options): Likewise.
1022         (print_insn_arc): Use parse_disassembler_options function.  Proper
1023         select ARCv2 cpu variant.
1024         * disassemble.c (disassembler_usage): Add ARC disassembler
1025         options.
1026
1027 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1028
1029         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1030         annotation from the "nal" entry and reorder it beyond "bltzal".
1031
1032 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1033
1034         * sparc-opc.c (ldtxa): New macro.
1035         (sparc_opcodes): Use the macro defined above to add entries for
1036         the LDTXA instructions.
1037         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1038         instruction.
1039
1040 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1041
1042         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1043         and "jmpc".
1044
1045 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1046
1047         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1048         (movzb): Adjust to cover all permitted suffixes.
1049         (movzw): New.
1050         * i386-tbl.h: Re-generate.
1051
1052 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1053
1054         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1055         (lgdt): Remove Tbyte from non-64-bit variant.
1056         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1057         xsaves64, xsavec64): Remove Disp16.
1058         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1059         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1060         64-bit variants.
1061         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1062         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1063         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1064         64-bit variants.
1065         * i386-tbl.h: Re-generate.
1066
1067 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1068
1069         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1070         * i386-tbl.h: Re-generate.
1071
1072 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1073
1074         * arm-dis.c (print_insn): Fix typo in comment.
1075
1076 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1077
1078         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1079         range of ldst_elemlist operands.
1080         (print_register_list): Use PRIi64 to print the index.
1081         (aarch64_print_operand): Likewise.
1082
1083 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1084
1085         * mcore-opc.h: Remove sentinal.
1086         * mcore-dis.c (print_insn_mcore): Adjust.
1087
1088 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1089
1090         * arc-opc.c: Correct description of availability of NPS400
1091         features.
1092
1093 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1094
1095         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1096         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1097         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1098         xor3>: New mnemonics.
1099         <setb>: Change to a VX form instruction.
1100         (insert_sh6): Add support for rldixor.
1101         (extract_sh6): Likewise.
1102
1103 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1104
1105         * arc-ext.h: Wrap in extern C.
1106
1107 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1108
1109         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1110         Use same method for determining instruction length on ARC700 and
1111         NPS-400.
1112         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1113         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1114         with the NPS400 subclass.
1115         * arc-opc.c: Likewise.
1116
1117 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1118
1119         * sparc-opc.c (rdasr): New macro.
1120         (wrasr): Likewise.
1121         (rdpr): Likewise.
1122         (wrpr): Likewise.
1123         (rdhpr): Likewise.
1124         (wrhpr): Likewise.
1125         (sparc_opcodes): Use the macros above to fix and expand the
1126         definition of read/write instructions from/to
1127         asr/privileged/hyperprivileged instructions.
1128         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1129         %hva_mask_nz.  Prefer softint_set and softint_clear over
1130         set_softint and clear_softint.
1131         (print_insn_sparc): Support %ver in Rd.
1132
1133 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1134
1135         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1136         architecture according to the hardware capabilities they require.
1137
1138 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1139
1140         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1141         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1142         bfd_mach_sparc_v9{c,d,e,v,m}.
1143         * sparc-opc.c (MASK_V9C): Define.
1144         (MASK_V9D): Likewise.
1145         (MASK_V9E): Likewise.
1146         (MASK_V9V): Likewise.
1147         (MASK_V9M): Likewise.
1148         (v6): Add MASK_V9{C,D,E,V,M}.
1149         (v6notlet): Likewise.
1150         (v7): Likewise.
1151         (v8): Likewise.
1152         (v9): Likewise.
1153         (v9andleon): Likewise.
1154         (v9a): Likewise.
1155         (v9b): Likewise.
1156         (v9c): Define.
1157         (v9d): Likewise.
1158         (v9e): Likewise.
1159         (v9v): Likewise.
1160         (v9m): Likewise.
1161         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1162
1163 2016-06-15  Nick Clifton  <nickc@redhat.com>
1164
1165         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1166         constants to match expected behaviour.
1167         (nds32_parse_opcode): Likewise.  Also for whitespace.
1168
1169 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1170
1171         * arc-opc.c (extract_rhv1): Extract value from insn.
1172
1173 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1174
1175         * arc-nps400-tbl.h: Add ldbit instruction.
1176         * arc-opc.c: Add flag classes required for ldbit.
1177
1178 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1179
1180         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1181         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1182         support the above instructions.
1183
1184 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1185
1186         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1187         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1188         csma, cbba, zncv, and hofs.
1189         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1190         support the above instructions.
1191
1192 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1193
1194         * arc-nps400-tbl.h: Add andab and orab instructions.
1195
1196 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1197
1198         * arc-nps400-tbl.h: Add addl-like instructions.
1199
1200 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1201
1202         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1203
1204 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1205
1206         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1207         instructions.
1208
1209 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1210
1211         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1212         variable.
1213         (init_disasm): Handle new command line option "insnlength".
1214         (print_s390_disassembler_options): Mention new option in help
1215         output.
1216         (print_insn_s390): Use the encoded insn length when dumping
1217         unknown instructions.
1218
1219 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1220
1221         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1222          to the address and set as symbol address for LDS/ STS immediate operands.
1223
1224 2016-06-07  Alan Modra  <amodra@gmail.com>
1225
1226         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1227         cpu for "vle" to e500.
1228         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1229         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1230         (PPCNONE): Delete, substitute throughout.
1231         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1232         except for major opcode 4 and 31.
1233         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1234
1235 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1236
1237         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1238         ARM_EXT_RAS in relevant entries.
1239
1240 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1241
1242         PR binutils/20196
1243         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1244         opcodes for E6500.
1245
1246 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1247
1248         PR binutis/18386
1249         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1250         (indir_v_mode): New.
1251         Add comments for '&'.
1252         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1253         (putop): Handle '&'.
1254         (intel_operand_size): Handle indir_v_mode.
1255         (OP_E_register): Likewise.
1256         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1257         64-bit indirect call/jmp for AMD64.
1258         * i386-tbl.h: Regenerated
1259
1260 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1261
1262         * arc-dis.c (struct arc_operand_iterator): New structure.
1263         (find_format_from_table): All the old content from find_format,
1264         with some minor adjustments, and parameter renaming.
1265         (find_format_long_instructions): New function.
1266         (find_format): Rewritten.
1267         (arc_insn_length): Add LSB parameter.
1268         (extract_operand_value): New function.
1269         (operand_iterator_next): New function.
1270         (print_insn_arc): Use new functions to find opcode, and iterator
1271         over operands.
1272         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1273         (extract_nps_3bit_dst_short): New function.
1274         (insert_nps_3bit_src2_short): New function.
1275         (extract_nps_3bit_src2_short): New function.
1276         (insert_nps_bitop1_size): New function.
1277         (extract_nps_bitop1_size): New function.
1278         (insert_nps_bitop2_size): New function.
1279         (extract_nps_bitop2_size): New function.
1280         (insert_nps_bitop_mod4_msb): New function.
1281         (extract_nps_bitop_mod4_msb): New function.
1282         (insert_nps_bitop_mod4_lsb): New function.
1283         (extract_nps_bitop_mod4_lsb): New function.
1284         (insert_nps_bitop_dst_pos3_pos4): New function.
1285         (extract_nps_bitop_dst_pos3_pos4): New function.
1286         (insert_nps_bitop_ins_ext): New function.
1287         (extract_nps_bitop_ins_ext): New function.
1288         (arc_operands): Add new operands.
1289         (arc_long_opcodes): New global array.
1290         (arc_num_long_opcodes): New global.
1291         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1292
1293 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1294
1295         * nds32-asm.h: Add extern "C".
1296         * sh-opc.h: Likewise.
1297
1298 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1299
1300         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1301         0,b,limm to the rflt instruction.
1302
1303 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1304
1305         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1306         constant.
1307
1308 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1309
1310         PR gas/20145
1311         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1312         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1313         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1314         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1315         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1316         * i386-init.h: Regenerated.
1317
1318 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1319
1320         PR gas/20145
1321         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1322         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1323         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1324         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1325         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1326         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1327         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1328         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1329         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1330         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1331         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1332         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1333         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1334         CpuRegMask for AVX512.
1335         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1336         and CpuRegMask.
1337         (set_bitfield_from_cpu_flag_init): New function.
1338         (set_bitfield): Remove const on f.  Call
1339         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1340         * i386-opc.h (CpuRegMMX): New.
1341         (CpuRegXMM): Likewise.
1342         (CpuRegYMM): Likewise.
1343         (CpuRegZMM): Likewise.
1344         (CpuRegMask): Likewise.
1345         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1346         and cpuregmask.
1347         * i386-init.h: Regenerated.
1348         * i386-tbl.h: Likewise.
1349
1350 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1351
1352         PR gas/20154
1353         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1354         (opcode_modifiers): Add AMD64 and Intel64.
1355         (main): Properly verify CpuMax.
1356         * i386-opc.h (CpuAMD64): Removed.
1357         (CpuIntel64): Likewise.
1358         (CpuMax): Set to CpuNo64.
1359         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1360         (AMD64): New.
1361         (Intel64): Likewise.
1362         (i386_opcode_modifier): Add amd64 and intel64.
1363         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1364         on call and jmp.
1365         * i386-init.h: Regenerated.
1366         * i386-tbl.h: Likewise.
1367
1368 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1369
1370         PR gas/20154
1371         * i386-gen.c (main): Fail if CpuMax is incorrect.
1372         * i386-opc.h (CpuMax): Set to CpuIntel64.
1373         * i386-tbl.h: Regenerated.
1374
1375 2016-05-27  Nick Clifton  <nickc@redhat.com>
1376
1377         PR target/20150
1378         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1379         (msp430dis_opcode_unsigned): New function.
1380         (msp430dis_opcode_signed): New function.
1381         (msp430_singleoperand): Use the new opcode reading functions.
1382         Only disassenmble bytes if they were successfully read.
1383         (msp430_doubleoperand): Likewise.
1384         (msp430_branchinstr): Likewise.
1385         (msp430x_callx_instr): Likewise.
1386         (print_insn_msp430): Check that it is safe to read bytes before
1387         attempting disassembly.  Use the new opcode reading functions.
1388
1389 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1390
1391         * ppc-opc.c (CY): New define.  Document it.
1392         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1393
1394 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1395
1396         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1397         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1398         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1399         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1400         CPU_ANY_AVX_FLAGS.
1401         * i386-init.h: Regenerated.
1402
1403 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1404
1405         PR gas/20141
1406         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1407         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1408         * i386-init.h: Regenerated.
1409
1410 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1411
1412         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1413         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1414         * i386-init.h: Regenerated.
1415
1416 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1417
1418         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1419         information.
1420         (print_insn_arc): Set insn_type information.
1421         * arc-opc.c (C_CC): Add F_CLASS_COND.
1422         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1423         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1424         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1425         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1426         (brne, brne_s, jeq_s, jne_s): Likewise.
1427
1428 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1429
1430         * arc-tbl.h (neg): New instruction variant.
1431
1432 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1433
1434         * arc-dis.c (find_format, find_format, get_auxreg)
1435         (print_insn_arc): Changed.
1436         * arc-ext.h (INSERT_XOP): Likewise.
1437
1438 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1439
1440         * tic54x-dis.c (sprint_mmr): Adjust.
1441         * tic54x-opc.c: Likewise.
1442
1443 2016-05-19  Alan Modra  <amodra@gmail.com>
1444
1445         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1446
1447 2016-05-19  Alan Modra  <amodra@gmail.com>
1448
1449         * ppc-opc.c: Formatting.
1450         (NSISIGNOPT): Define.
1451         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1452
1453 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1454
1455         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1456         replacing references to `micromips_ase' throughout.
1457         (_print_insn_mips): Don't use file-level microMIPS annotation to
1458         determine the disassembly mode with the symbol table.
1459
1460 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1461
1462         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1463
1464 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1465
1466         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1467         mips64r6.
1468         * mips-opc.c (D34): New macro.
1469         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1470
1471 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1472
1473         * i386-dis.c (prefix_table): Add RDPID instruction.
1474         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1475         (cpu_flags): Add RDPID bitfield.
1476         * i386-opc.h (enum): Add RDPID element.
1477         (i386_cpu_flags): Add RDPID field.
1478         * i386-opc.tbl: Add RDPID instruction.
1479         * i386-init.h: Regenerate.
1480         * i386-tbl.h: Regenerate.
1481
1482 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1483
1484         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1485         branch type of a symbol.
1486         (print_insn): Likewise.
1487
1488 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1489
1490         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1491         Mainline Security Extensions instructions.
1492         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1493         Extensions instructions.
1494         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1495         instructions.
1496         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1497         special registers.
1498
1499 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1500
1501         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1502
1503 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1504
1505         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1506         (arcExtMap_genOpcode): Likewise.
1507         * arc-opc.c (arg_32bit_rc): Define new variable.
1508         (arg_32bit_u6): Likewise.
1509         (arg_32bit_limm): Likewise.
1510
1511 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1512
1513         * aarch64-gen.c (VERIFIER): Define.
1514         * aarch64-opc.c (VERIFIER): Define.
1515         (verify_ldpsw): Use static linkage.
1516         * aarch64-opc.h (verify_ldpsw): Remove.
1517         * aarch64-tbl.h: Use VERIFIER for verifiers.
1518
1519 2016-04-28  Nick Clifton  <nickc@redhat.com>
1520
1521         PR target/19722
1522         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1523         * aarch64-opc.c (verify_ldpsw): New function.
1524         * aarch64-opc.h (verify_ldpsw): New prototype.
1525         * aarch64-tbl.h: Add initialiser for verifier field.
1526         (LDPSW): Set verifier to verify_ldpsw.
1527
1528 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1529
1530         PR binutils/19983
1531         PR binutils/19984
1532         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1533         smaller than address size.
1534
1535 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1536
1537         * alpha-dis.c: Regenerate.
1538         * crx-dis.c: Likewise.
1539         * disassemble.c: Likewise.
1540         * epiphany-opc.c: Likewise.
1541         * fr30-opc.c: Likewise.
1542         * frv-opc.c: Likewise.
1543         * ip2k-opc.c: Likewise.
1544         * iq2000-opc.c: Likewise.
1545         * lm32-opc.c: Likewise.
1546         * lm32-opinst.c: Likewise.
1547         * m32c-opc.c: Likewise.
1548         * m32r-opc.c: Likewise.
1549         * m32r-opinst.c: Likewise.
1550         * mep-opc.c: Likewise.
1551         * mt-opc.c: Likewise.
1552         * or1k-opc.c: Likewise.
1553         * or1k-opinst.c: Likewise.
1554         * tic80-opc.c: Likewise.
1555         * xc16x-opc.c: Likewise.
1556         * xstormy16-opc.c: Likewise.
1557
1558 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1559
1560         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1561         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1562         calcsd, and calcxd instructions.
1563         * arc-opc.c (insert_nps_bitop_size): Delete.
1564         (extract_nps_bitop_size): Delete.
1565         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1566         (extract_nps_qcmp_m3): Define.
1567         (extract_nps_qcmp_m2): Define.
1568         (extract_nps_qcmp_m1): Define.
1569         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1570         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1571         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1572         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1573         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1574         NPS_QCMP_M3.
1575
1576 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1577
1578         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1579
1580 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1581
1582         * Makefile.in: Regenerated with automake 1.11.6.
1583         * aclocal.m4: Likewise.
1584
1585 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1586
1587         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1588         instructions.
1589         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1590         (extract_nps_cmem_uimm16): New function.
1591         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1592
1593 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1594
1595         * arc-dis.c (arc_insn_length): New function.
1596         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1597         (find_format): Change insnLen parameter to unsigned.
1598
1599 2016-04-13  Nick Clifton  <nickc@redhat.com>
1600
1601         PR target/19937
1602         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1603         the LD.B and LD.BU instructions.
1604
1605 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1606
1607         * arc-dis.c (find_format): Check for extension flags.
1608         (print_flags): New function.
1609         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1610         .extAuxRegister.
1611         * arc-ext.c (arcExtMap_coreRegName): Use
1612         LAST_EXTENSION_CORE_REGISTER.
1613         (arcExtMap_coreReadWrite): Likewise.
1614         (dump_ARC_extmap): Update printing.
1615         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1616         (arc_aux_regs): Add cpu field.
1617         * arc-regs.h: Add cpu field, lower case name aux registers.
1618
1619 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1620
1621         * arc-tbl.h: Add rtsc, sleep with no arguments.
1622
1623 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1624
1625         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1626         Initialize.
1627         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1628         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1629         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1630         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1631         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1632         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1633         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1634         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1635         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1636         (arc_opcode arc_opcodes): Null terminate the array.
1637         (arc_num_opcodes): Remove.
1638         * arc-ext.h (INSERT_XOP): Define.
1639         (extInstruction_t): Likewise.
1640         (arcExtMap_instName): Delete.
1641         (arcExtMap_insn): New function.
1642         (arcExtMap_genOpcode): Likewise.
1643         * arc-ext.c (ExtInstruction): Remove.
1644         (create_map): Zero initialize instruction fields.
1645         (arcExtMap_instName): Remove.
1646         (arcExtMap_insn): New function.
1647         (dump_ARC_extmap): More info while debuging.
1648         (arcExtMap_genOpcode): New function.
1649         * arc-dis.c (find_format): New function.
1650         (print_insn_arc): Use find_format.
1651         (arc_get_disassembler): Enable dump_ARC_extmap only when
1652         debugging.
1653
1654 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1655
1656         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1657         instruction bits out.
1658
1659 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1660
1661         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1662         * arc-opc.c (arc_flag_operands): Add new flags.
1663         (arc_flag_classes): Add new classes.
1664
1665 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1666
1667         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1668
1669 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1670
1671         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1672         encode1, rflt, crc16, and crc32 instructions.
1673         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1674         (arc_flag_classes): Add C_NPS_R.
1675         (insert_nps_bitop_size_2b): New function.
1676         (extract_nps_bitop_size_2b): Likewise.
1677         (insert_nps_bitop_uimm8): Likewise.
1678         (extract_nps_bitop_uimm8): Likewise.
1679         (arc_operands): Add new operand entries.
1680
1681 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1682
1683         * arc-regs.h: Add a new subclass field.  Add double assist
1684         accumulator register values.
1685         * arc-tbl.h: Use DPA subclass to mark the double assist
1686         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1687         * arc-opc.c (RSP): Define instead of SP.
1688         (arc_aux_regs): Add the subclass field.
1689
1690 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1691
1692         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1693
1694 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1695
1696         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1697         NPS_R_SRC1.
1698
1699 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1700
1701         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1702         issues.  No functional changes.
1703
1704 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1705
1706         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1707         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1708         (RTT): Remove duplicate.
1709         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1710         (PCT_CONFIG*): Remove.
1711         (D1L, D1H, D2H, D2L): Define.
1712
1713 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1714
1715         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1716
1717 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1718
1719         * arc-tbl.h (invld07): Remove.
1720         * arc-ext-tbl.h: New file.
1721         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1722         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1723
1724 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1725
1726         Fix -Wstack-usage warnings.
1727         * aarch64-dis.c (print_operands): Substitute size.
1728         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1729
1730 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1731
1732         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1733         to get a proper diagnostic when an invalid ASR register is used.
1734
1735 2016-03-22  Nick Clifton  <nickc@redhat.com>
1736
1737         * configure: Regenerate.
1738
1739 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1740
1741         * arc-nps400-tbl.h: New file.
1742         * arc-opc.c: Add top level comment.
1743         (insert_nps_3bit_dst): New function.
1744         (extract_nps_3bit_dst): New function.
1745         (insert_nps_3bit_src2): New function.
1746         (extract_nps_3bit_src2): New function.
1747         (insert_nps_bitop_size): New function.
1748         (extract_nps_bitop_size): New function.
1749         (arc_flag_operands): Add nps400 entries.
1750         (arc_flag_classes): Add nps400 entries.
1751         (arc_operands): Add nps400 entries.
1752         (arc_opcodes): Add nps400 include.
1753
1754 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1755
1756         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1757         the new class enum values.
1758
1759 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1760
1761         * arc-dis.c (print_insn_arc): Handle nps400.
1762
1763 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1764
1765         * arc-opc.c (BASE): Delete.
1766
1767 2016-03-18  Nick Clifton  <nickc@redhat.com>
1768
1769         PR target/19721
1770         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1771         of MOV insn that aliases an ORR insn.
1772
1773 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1774
1775         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1776
1777 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1778
1779         * mcore-opc.h: Add const qualifiers.
1780         * microblaze-opc.h (struct op_code_struct): Likewise.
1781         * sh-opc.h: Likewise.
1782         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1783         (tic4x_print_op): Likewise.
1784
1785 2016-03-02  Alan Modra  <amodra@gmail.com>
1786
1787         * or1k-desc.h: Regenerate.
1788         * fr30-ibld.c: Regenerate.
1789         * rl78-decode.c: Regenerate.
1790
1791 2016-03-01  Nick Clifton  <nickc@redhat.com>
1792
1793         PR target/19747
1794         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1795
1796 2016-02-24  Renlin Li  <renlin.li@arm.com>
1797
1798         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1799         (print_insn_coprocessor): Support fp16 instructions.
1800
1801 2016-02-24  Renlin Li  <renlin.li@arm.com>
1802
1803         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1804         vminnm, vrint(mpna).
1805
1806 2016-02-24  Renlin Li  <renlin.li@arm.com>
1807
1808         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1809         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1810
1811 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1812
1813         * i386-dis.c (print_insn): Parenthesize expression to prevent
1814         truncated addresses.
1815         (OP_J): Likewise.
1816
1817 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1818             Janek van Oirschot  <jvanoirs@synopsys.com>
1819
1820         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1821         variable.
1822
1823 2016-02-04  Nick Clifton  <nickc@redhat.com>
1824
1825         PR target/19561
1826         * msp430-dis.c (print_insn_msp430): Add a special case for
1827         decoding an RRC instruction with the ZC bit set in the extension
1828         word.
1829
1830 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1831
1832         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1833         * epiphany-ibld.c: Regenerate.
1834         * fr30-ibld.c: Regenerate.
1835         * frv-ibld.c: Regenerate.
1836         * ip2k-ibld.c: Regenerate.
1837         * iq2000-ibld.c: Regenerate.
1838         * lm32-ibld.c: Regenerate.
1839         * m32c-ibld.c: Regenerate.
1840         * m32r-ibld.c: Regenerate.
1841         * mep-ibld.c: Regenerate.
1842         * mt-ibld.c: Regenerate.
1843         * or1k-ibld.c: Regenerate.
1844         * xc16x-ibld.c: Regenerate.
1845         * xstormy16-ibld.c: Regenerate.
1846
1847 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1848
1849         * epiphany-dis.c: Regenerated from latest cpu files.
1850
1851 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1852
1853         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1854         test bit.
1855
1856 2016-01-25  Renlin Li  <renlin.li@arm.com>
1857
1858         * arm-dis.c (mapping_symbol_for_insn): New function.
1859         (find_ifthen_state): Call mapping_symbol_for_insn().
1860
1861 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1862
1863         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1864         of MSR UAO immediate operand.
1865
1866 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1867
1868         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1869         instruction support.
1870
1871 2016-01-17  Alan Modra  <amodra@gmail.com>
1872
1873         * configure: Regenerate.
1874
1875 2016-01-14  Nick Clifton  <nickc@redhat.com>
1876
1877         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1878         instructions that can support stack pointer operations.
1879         * rl78-decode.c: Regenerate.
1880         * rl78-dis.c: Fix display of stack pointer in MOVW based
1881         instructions.
1882
1883 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1884
1885         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1886         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1887         erxtatus_el1 and erxaddr_el1.
1888
1889 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1890
1891         * arm-dis.c (arm_opcodes): Add "esb".
1892         (thumb_opcodes): Likewise.
1893
1894 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1895
1896         * ppc-opc.c <xscmpnedp>: Delete.
1897         <xvcmpnedp>: Likewise.
1898         <xvcmpnedp.>: Likewise.
1899         <xvcmpnesp>: Likewise.
1900         <xvcmpnesp.>: Likewise.
1901
1902 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1903
1904         PR gas/13050
1905         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1906         addition to ISA_A.
1907
1908 2016-01-01  Alan Modra  <amodra@gmail.com>
1909
1910         Update year range in copyright notice of all files.
1911
1912 For older changes see ChangeLog-2015
1913 \f
1914 Copyright (C) 2016 Free Software Foundation, Inc.
1915
1916 Copying and distribution of this file, with or without modification,
1917 are permitted in any medium without royalty provided the copyright
1918 notice and this notice are preserved.
1919
1920 Local Variables:
1921 mode: change-log
1922 left-margin: 8
1923 fill-column: 74
1924 version-control: never
1925 End: