opcodes/ChangeLog

   1 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * mips16-opc.c (mips16_opcodes): Update comment naming structure
   4         members.
   5
   6 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
   7
   8         * mips-dis.c (print_mips_disassembler_options): Reformat output.
   9
  10 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  11
  12         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
  13         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
  14
  15 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  16
  17         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
  18
  19 2016-12-01  Nick Clifton  <nickc@redhat.com>
  20
  21         PR binutils/20893
  22         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
  23         opcode designator.
  24
  25 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  26
  27         * arc-opc.c (insert_ra_chk): New function.
  28         (insert_rb_chk): Likewise.
  29         (insert_rad): Update text error message.
  30         (insert_rcd): Likewise.
  31         (insert_rhv2): Likewise.
  32         (insert_r0): Likewise.
  33         (insert_r1): Likewise.
  34         (insert_r2): Likewise.
  35         (insert_r3): Likewise.
  36         (insert_sp): Likewise.
  37         (insert_gp): Likewise.
  38         (insert_pcl): Likewise.
  39         (insert_blink): Likewise.
  40         (insert_ilink1): Likewise.
  41         (insert_ilink2): Likewise.
  42         (insert_ras): Likewise.
  43         (insert_rbs): Likewise.
  44         (insert_rcs): Likewise.
  45         (insert_simm3s): Likewise.
  46         (insert_rrange): Likewise.
  47         (insert_fpel): Likewise.
  48         (insert_blinkel): Likewise.
  49         (insert_pcel): Likewise.
  50         (insert_nps_3bit_dst): Likewise.
  51         (insert_nps_3bit_dst_short): Likewise.
  52         (insert_nps_3bit_src2_short): Likewise.
  53         (insert_nps_bitop_size_2b): Likewise.
  54         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
  55         (RA_CHK): Define.
  56         (RB): Adjust.
  57         (RB_CHK): Define.
  58         (RC): Adjust.
  59         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
  60         * arc-tbl.h (div, divu): All instructions are DIVREM class.
  61         Change first insn argument to check for LP_COUNT usage.
  62         (rem): Likewise.
  63         (ld, ldd): All instructions are LOAD class.  Change first insn
  64         argument to check for LP_COUNT usage.
  65         (st, std): All instructions are STORE class.
  66         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
  67         Change first insn argument to check for LP_COUNT usage.
  68         (mov): All instructions are MOVE class.  Change first insn
  69         argument to check for LP_COUNT usage.
  70
  71 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  72
  73         * arc-dis.c (is_compatible_p): Remove function.
  74         (skip_this_opcode): Don't add any decoding class to decode list.
  75         Remove warning.
  76         (find_format_from_table): Go through all opcodes, and warn if we
  77         use a guessed mnemonic.
  78
  79 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
  80             Amit Pawar  <amit.pawar@amd.com>
  81
  82         PR binutils/20637
  83         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
  84         instructions.
  85
  86 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
  87
  88         * configure: Regenerate.
  89
  90 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
  91
  92         * sparc-opc.c (HWS_V8): Definition moved from
  93         gas/config/tc-sparc.c.
  94         (HWS_V9): Likewise.
  95         (HWS_VA): Likewise.
  96         (HWS_VB): Likewise.
  97         (HWS_VC): Likewise.
  98         (HWS_VD): Likewise.
  99         (HWS_VE): Likewise.
 100         (HWS_VV): Likewise.
 101         (HWS_VM): Likewise.
 102         (HWS2_VM): Likewise.
 103         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 104         existing entries.
 105
 106 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 107
 108         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 109         instructions.
 110
 111 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 112
 113         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 114         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 115         (aarch64_opcode_table): Add fcmla and fcadd.
 116         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 117         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 118         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 119         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 120         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 121         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 122         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 123         (operand_general_constraint_met_p): Rotate and index range check.
 124         (aarch64_print_operand): Handle rotate operand.
 125         * aarch64-asm-2.c: Regenerate.
 126         * aarch64-dis-2.c: Likewise.
 127         * aarch64-opc-2.c: Likewise.
 128
 129 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 130
 131         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 132         * aarch64-asm-2.c: Regenerate.
 133         * aarch64-dis-2.c: Regenerate.
 134         * aarch64-opc-2.c: Regenerate.
 135
 136 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 137
 138         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 139         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 140         * aarch64-asm-2.c: Regenerate.
 141         * aarch64-dis-2.c: Regenerate.
 142         * aarch64-opc-2.c: Regenerate.
 143
 144 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 145
 146         * aarch64-tbl.h (QL_X1NIL): New.
 147         (arch64_opcode_table): Add ldraa, ldrab.
 148         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 149         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 150         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 151         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 152         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 153         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 154         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 155         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 156         (aarch64_print_operand): Likewise.
 157         * aarch64-asm-2.c: Regenerate.
 158         * aarch64-dis-2.c: Regenerate.
 159         * aarch64-opc-2.c: Regenerate.
 160
 161 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 162
 163         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 164         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 165         * aarch64-asm-2.c: Regenerate.
 166         * aarch64-dis-2.c: Regenerate.
 167         * aarch64-opc-2.c: Regenerate.
 168
 169 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 170
 171         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 172         (AARCH64_OPERANDS): Add Rm_SP.
 173         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 174         * aarch64-asm-2.c: Regenerate.
 175         * aarch64-dis-2.c: Regenerate.
 176         * aarch64-opc-2.c: Regenerate.
 177
 178 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 179
 180         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 181         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 182         autdzb, xpaci, xpacd.
 183         * aarch64-asm-2.c: Regenerate.
 184         * aarch64-dis-2.c: Regenerate.
 185         * aarch64-opc-2.c: Regenerate.
 186
 187 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 188
 189         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 190         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 191         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 192         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 193
 194 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 195
 196         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 197         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 198         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 199         autibsp.
 200         * aarch64-asm-2.c: Regenerate.
 201         * aarch64-dis-2.c: Regenerate.
 202
 203 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 204
 205         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 206
 207 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 208
 209         PR binutils/20799
 210         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 211         * i386-dis.c (EdqwS): Removed.
 212         (dqw_swap_mode): Likewise.
 213         (intel_operand_size): Don't check dqw_swap_mode.
 214         (OP_E_register): Likewise.
 215         (OP_E_memory): Likewise.
 216         (OP_G): Likewise.
 217         (OP_EX): Likewise.
 218         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 219         * i386-tbl.h: Regerated.
 220
 221 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 222
 223         * i386-opc.tbl: Merge AVX512F vmovq.
 224         * i386-tbl.h: Regerated.
 225
 226 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 227
 228         PR binutils/20701
 229         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 230         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 231         (three_byte_table): Remove THREE_BYTE_0F7A.
 232
 233 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 234
 235         PR binutils/20775
 236         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 237         (FGRPd9_4): Replace 1 with 2.
 238         (FGRPd9_5): Replace 2 with 3.
 239         (FGRPd9_6): Replace 3 with 4.
 240         (FGRPd9_7): Replace 4 with 5.
 241         (FGRPda_5): Replace 5 with 6.
 242         (FGRPdb_4): Replace 6 with 7.
 243         (FGRPde_3): Replace 7 with 8.
 244         (FGRPdf_4): Replace 8 with 9.
 245         (fgrps): Add an entry for Bad_Opcode.
 246
 247 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 248
 249         * arc-opc.c (arc_flag_operands): Add F_DI14.
 250         (arc_flag_classes): Add C_DI14.
 251         * arc-nps400-tbl.h: Add new exc instructions.
 252
 253 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 254
 255         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 256         major opcode 0xa.
 257         * arc-nps-400-tbl.h: Add dcmac instruction.
 258         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 259         (insert_nps_rbdouble_64): Added.
 260         (extract_nps_rbdouble_64): Added.
 261         (insert_nps_proto_size): Added.
 262         (extract_nps_proto_size): Added.
 263
 264 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 265
 266         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 267         relating to long instruction processing, add new limm field.
 268         (OPCODE): Rename to...
 269         (OPCODE_32BIT_INSN): ...this.
 270         (OPCODE_AC): Delete.
 271         (skip_this_opcode): Handle different instruction lengths, update
 272         macro name.
 273         (special_flag_p): Update parameter type.
 274         (find_format_from_table): Update for more instruction lengths.
 275         (find_format_long_instructions): Delete.
 276         (find_format): Update for more instruction lengths.
 277         (arc_insn_length): Likewise.
 278         (extract_operand_value): Update for more instruction lengths.
 279         (operand_iterator_next): Remove code relating to long
 280         instructions.
 281         (arc_opcode_to_insn_type): New function.
 282         (print_insn_arc):Update for more instructions lengths.
 283         * arc-ext.c (extInstruction_t): Change argument type.
 284         * arc-ext.h (extInstruction_t): Change argument type.
 285         * arc-fxi.h: Change type unsigned to unsigned long long
 286         extensively throughout.
 287         * arc-nps400-tbl.h: Add long instructions taken from
 288         arc_long_opcodes table in arc-opc.c.
 289         * arc-opc.c: Update parameter types on insert/extract handlers.
 290         (arc_long_opcodes): Delete.
 291         (arc_num_long_opcodes): Delete.
 292         (arc_opcode_len): Update for more instruction lengths.
 293
 294 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 295
 296         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 297
 298 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 299
 300         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 301         with arc_opcode_len.
 302         (find_format_long_instructions): Likewise.
 303         * arc-opc.c (arc_opcode_len): New function.
 304
 305 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 306
 307         * arc-nps400-tbl.h: Fix some instruction masks.
 308
 309 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 310
 311         * i386-dis.c (REG_82): Removed.
 312         (X86_64_82_REG_0): Likewise.
 313         (X86_64_82_REG_1): Likewise.
 314         (X86_64_82_REG_2): Likewise.
 315         (X86_64_82_REG_3): Likewise.
 316         (X86_64_82_REG_4): Likewise.
 317         (X86_64_82_REG_5): Likewise.
 318         (X86_64_82_REG_6): Likewise.
 319         (X86_64_82_REG_7): Likewise.
 320         (X86_64_82): New.
 321         (dis386): Use X86_64_82 instead of REG_82.
 322         (reg_table): Remove REG_82.
 323         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 324         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 325         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 326         X86_64_82_REG_7.
 327
 328 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 329
 330         PR binutils/20754
 331         * i386-dis.c (REG_82): New.
 332         (X86_64_82_REG_0): Likewise.
 333         (X86_64_82_REG_1): Likewise.
 334         (X86_64_82_REG_2): Likewise.
 335         (X86_64_82_REG_3): Likewise.
 336         (X86_64_82_REG_4): Likewise.
 337         (X86_64_82_REG_5): Likewise.
 338         (X86_64_82_REG_6): Likewise.
 339         (X86_64_82_REG_7): Likewise.
 340         (dis386): Use REG_82.
 341         (reg_table): Add REG_82.
 342         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 343         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 344         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 345
 346 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 347
 348         * i386-dis.c (REG_82): Renamed to ...
 349         (REG_83): This.
 350         (dis386): Updated.
 351         (reg_table): Likewise.
 352
 353 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 354
 355         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 356         * i386-dis-evex.h (evex_table): Updated.
 357         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 358         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 359         (cpu_flags): Add CpuAVX512_4VNNIW.
 360         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 361         (i386_cpu_flags): Add cpuavx512_4vnniw.
 362         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 363         * i386-init.h: Regenerate.
 364         * i386-tbl.h: Ditto.
 365
 366 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 367
 368         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 369         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 370         * i386-dis-evex.h (evex_table): Updated.
 371         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 372         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 373         (cpu_flags): Add CpuAVX512_4FMAPS.
 374         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 375         * i386-opc.h (AVX512_4FMAP): New.
 376         (i386_cpu_flags): Add cpuavx512_4fmaps.
 377         (ImplicitQuadGroup): New.
 378         (i386_opcode_modifier): Add implicitquadgroup.
 379         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 380         * i386-init.h: Regenerate.
 381         * i386-tbl.h: Ditto.
 382
 383 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 384             Andrew Waterman <andrew@sifive.com>
 385
 386         Add support for RISC-V architecture.
 387         * configure.ac: Add entry for bfd_riscv_arch.
 388         * configure: Regenerate.
 389         * disassemble.c (disassembler): Add support for riscv.
 390         (disassembler_usage): Likewise.
 391         * riscv-dis.c: New file.
 392         * riscv-opc.c: New file.
 393
 394 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 395
 396         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 397         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 398         (rm_table): Update the RM_0FAE_REG_7 entry.
 399         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 400         (cpu_flags): Remove CpuPCOMMIT.
 401         * i386-opc.h (CpuPCOMMIT): Removed.
 402         (i386_cpu_flags): Remove cpupcommit.
 403         * i386-opc.tbl: Remove pcommit.
 404         * i386-init.h: Regenerated.
 405         * i386-tbl.h: Likewise.
 406
 407 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 408
 409         PR binutis/20705
 410         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 411         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 412         32-bit mode.  Don't check vex.register_specifier in 32-bit
 413         mode.
 414         (OP_VEX): Check for invalid mask registers.
 415
 416 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 417
 418         PR binutis/20699
 419         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 420         sizeflag.
 421
 422 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 423
 424         PR binutis/20704
 425         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 426
 427 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 428
 429         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 430         local variable to `index_regno'.
 431
 432 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 433
 434         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 435
 436 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 437
 438         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 439         usage on ISA basis.
 440
 441 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 442
 443         PR target/20666
 444         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 445
 446 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 447
 448         PR target/20667
 449         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 450         available.
 451
 452 2016-10-07  Alan Modra  <amodra@gmail.com>
 453
 454         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 455
 456 2016-10-06  Alan Modra  <amodra@gmail.com>
 457
 458         * aarch64-opc.c: Spell fall through comments consistently.
 459         * i386-dis.c: Likewise.
 460         * aarch64-dis.c: Add missing fall through comments.
 461         * aarch64-opc.c: Likewise.
 462         * arc-dis.c: Likewise.
 463         * arm-dis.c: Likewise.
 464         * i386-dis.c: Likewise.
 465         * m68k-dis.c: Likewise.
 466         * mep-asm.c: Likewise.
 467         * ns32k-dis.c: Likewise.
 468         * sh-dis.c: Likewise.
 469         * tic4x-dis.c: Likewise.
 470         * tic6x-dis.c: Likewise.
 471         * vax-dis.c: Likewise.
 472
 473 2016-10-06  Alan Modra  <amodra@gmail.com>
 474
 475         * arc-ext.c (create_map): Add missing break.
 476         * msp430-decode.opc (encode_as): Likewise.
 477         * msp430-decode.c: Regenerate.
 478
 479 2016-10-06  Alan Modra  <amodra@gmail.com>
 480
 481         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 482         * crx-dis.c (print_insn_crx): Likewise.
 483
 484 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 485
 486         PR binutils/20657
 487         * i386-dis.c (putop): Don't assign alt twice.
 488
 489 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 490
 491         PR target/20553
 492         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 493
 494 2016-09-29  Alan Modra  <amodra@gmail.com>
 495
 496         * ppc-opc.c (L): Make compulsory.
 497         (LOPT): New, optional form of L.
 498         (HTM_R): Define as LOPT.
 499         (L0, L1): Delete.
 500         (L32OPT): New, optional for 32-bit L.
 501         (L2OPT): New, 2-bit L for dcbf.
 502         (SVC_LEC): Update.
 503         (L2): Define.
 504         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 505         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 506         <dcbf>: Use L2OPT.
 507         <tlbiel, tlbie>: Use LOPT.
 508         <wclr, wclrall>: Use L2.
 509
 510 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 511
 512         * Makefile.in: Regenerate.
 513         * configure: Likewise.
 514
 515 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 516
 517         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 518         (EXTINSN2OP): Use EXTINSN2OPF.
 519         (bspeekm, bspop, modapp): New extension instructions.
 520         * arc-opc.c (F_DNZ_ND): Define.
 521         (F_DNZ_D): Likewise.
 522         (F_SIZEB1): Changed.
 523         (C_DNZ_D): Define.
 524         (C_HARD): Changed.
 525         * arc-tbl.h (dbnz): New instruction.
 526         (prealloc): Allow it for ARC EM.
 527         (xbfu): Likewise.
 528
 529 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 530
 531         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 532         after commas in addresses.
 533         (aarch64_print_operand): Likewise.
 534
 535 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 536
 537         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 538         rather than "should be" or "expected to be" in error messages.
 539
 540 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 541
 542         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 543         (print_mnemonic_name): ...here.
 544         (print_comment): New function.
 545         (print_aarch64_insn): Call it.
 546         * aarch64-opc.c (aarch64_conds): Add SVE names.
 547         (aarch64_print_operand): Print alternative condition names in
 548         a comment.
 549
 550 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 551
 552         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 553         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 554         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 555         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 556         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 557         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 558         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 559         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 560         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 561         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 562         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 563         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 564         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 565         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 566         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 567         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 568         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 569         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 570         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 571         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 572         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 573         (aarch64_feature_sve): New variable.
 574         (SVE): New macro.
 575         (_SVE_INSN): Likewise.
 576         (aarch64_opcode_table): Add SVE instructions.
 577         * aarch64-opc.h (extract_fields): Declare.
 578         * aarch64-opc-2.c: Regenerate.
 579         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 580         * aarch64-asm-2.c: Regenerate.
 581         * aarch64-dis.c (extract_fields): Make global.
 582         (do_misc_decoding): Handle the new SVE aarch64_ops.
 583         * aarch64-dis-2.c: Regenerate.
 584
 585 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 586
 587         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 588         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 589         aarch64_field_kinds.
 590         * aarch64-opc.c (fields): Add corresponding entries.
 591         * aarch64-asm.c (aarch64_get_variant): New function.
 592         (aarch64_encode_variant_using_iclass): Likewise.
 593         (aarch64_opcode_encode): Call it.
 594         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 595         (aarch64_opcode_decode): Call it.
 596
 597 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 598
 599         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 600         and FP register operands.
 601         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 602         (FLD_SVE_Vn): New aarch64_field_kinds.
 603         * aarch64-opc.c (fields): Add corresponding entries.
 604         (aarch64_print_operand): Handle the new SVE core and FP register
 605         operands.
 606         * aarch64-opc-2.c: Regenerate.
 607         * aarch64-asm-2.c: Likewise.
 608         * aarch64-dis-2.c: Likewise.
 609
 610 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 611
 612         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 613         immediate operands.
 614         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 615         * aarch64-opc.c (fields): Add corresponding entry.
 616         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 617         operands.
 618         (aarch64_print_operand): Likewise.
 619         * aarch64-opc-2.c: Regenerate.
 620         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 621         (ins_sve_float_zero_one): New inserters.
 622         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 623         (aarch64_ins_sve_float_half_two): Likewise.
 624         (aarch64_ins_sve_float_zero_one): Likewise.
 625         * aarch64-asm-2.c: Regenerate.
 626         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 627         (ext_sve_float_zero_one): New extractors.
 628         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 629         (aarch64_ext_sve_float_half_two): Likewise.
 630         (aarch64_ext_sve_float_zero_one): Likewise.
 631         * aarch64-dis-2.c: Regenerate.
 632
 633 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 634
 635         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 636         integer immediate operands.
 637         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 638         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 639         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 640         * aarch64-opc.c (fields): Add corresponding entries.
 641         (operand_general_constraint_met_p): Handle the new SVE integer
 642         immediate operands.
 643         (aarch64_print_operand): Likewise.
 644         (aarch64_sve_dupm_mov_immediate_p): New function.
 645         * aarch64-opc-2.c: Regenerate.
 646         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 647         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 648         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 649         (aarch64_ins_limm): ...here.
 650         (aarch64_ins_inv_limm): New function.
 651         (aarch64_ins_sve_aimm): Likewise.
 652         (aarch64_ins_sve_asimm): Likewise.
 653         (aarch64_ins_sve_limm_mov): Likewise.
 654         (aarch64_ins_sve_shlimm): Likewise.
 655         (aarch64_ins_sve_shrimm): Likewise.
 656         * aarch64-asm-2.c: Regenerate.
 657         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 658         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 659         * aarch64-dis.c (decode_limm): New function, split out from...
 660         (aarch64_ext_limm): ...here.
 661         (aarch64_ext_inv_limm): New function.
 662         (decode_sve_aimm): Likewise.
 663         (aarch64_ext_sve_aimm): Likewise.
 664         (aarch64_ext_sve_asimm): Likewise.
 665         (aarch64_ext_sve_limm_mov): Likewise.
 666         (aarch64_top_bit): Likewise.
 667         (aarch64_ext_sve_shlimm): Likewise.
 668         (aarch64_ext_sve_shrimm): Likewise.
 669         * aarch64-dis-2.c: Regenerate.
 670
 671 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 672
 673         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 674         operands.
 675         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 676         the AARCH64_MOD_MUL_VL entry.
 677         (value_aligned_p): Cope with non-power-of-two alignments.
 678         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 679         (print_immediate_offset_address): Likewise.
 680         (aarch64_print_operand): Likewise.
 681         * aarch64-opc-2.c: Regenerate.
 682         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 683         (ins_sve_addr_ri_s9xvl): New inserters.
 684         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 685         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 686         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 687         * aarch64-asm-2.c: Regenerate.
 688         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 689         (ext_sve_addr_ri_s9xvl): New extractors.
 690         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 691         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 692         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 693         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 694         * aarch64-dis-2.c: Regenerate.
 695
 696 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 697
 698         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 699         address operands.
 700         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 701         (FLD_SVE_xs_22): New aarch64_field_kinds.
 702         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 703         (get_operand_specific_data): New function.
 704         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 705         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 706         (operand_general_constraint_met_p): Handle the new SVE address
 707         operands.
 708         (sve_reg): New array.
 709         (get_addr_sve_reg_name): New function.
 710         (aarch64_print_operand): Handle the new SVE address operands.
 711         * aarch64-opc-2.c: Regenerate.
 712         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 713         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 714         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 715         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 716         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 717         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 718         (aarch64_ins_sve_addr_zi_u5): Likewise.
 719         (aarch64_ins_sve_addr_zz): Likewise.
 720         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 721         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 722         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 723         * aarch64-asm-2.c: Regenerate.
 724         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 725         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 726         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 727         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 728         (aarch64_ext_sve_addr_ri_u6): Likewise.
 729         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 730         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 731         (aarch64_ext_sve_addr_zi_u5): Likewise.
 732         (aarch64_ext_sve_addr_zz): Likewise.
 733         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 734         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 735         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 736         * aarch64-dis-2.c: Regenerate.
 737
 738 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 739
 740         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 741         AARCH64_OPND_SVE_PATTERN_SCALED.
 742         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 743         * aarch64-opc.c (fields): Add a corresponding entry.
 744         (set_multiplier_out_of_range_error): New function.
 745         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 746         (operand_general_constraint_met_p): Handle
 747         AARCH64_OPND_SVE_PATTERN_SCALED.
 748         (print_register_offset_address): Use PRIi64 to print the
 749         shift amount.
 750         (aarch64_print_operand): Likewise.  Handle
 751         AARCH64_OPND_SVE_PATTERN_SCALED.
 752         * aarch64-opc-2.c: Regenerate.
 753         * aarch64-asm.h (ins_sve_scale): New inserter.
 754         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 755         * aarch64-asm-2.c: Regenerate.
 756         * aarch64-dis.h (ext_sve_scale): New inserter.
 757         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 758         * aarch64-dis-2.c: Regenerate.
 759
 760 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 761
 762         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 763         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 764         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 765         (FLD_SVE_prfop): Likewise.
 766         * aarch64-opc.c: Include libiberty.h.
 767         (aarch64_sve_pattern_array): New variable.
 768         (aarch64_sve_prfop_array): Likewise.
 769         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 770         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 771         AARCH64_OPND_SVE_PRFOP.
 772         * aarch64-asm-2.c: Regenerate.
 773         * aarch64-dis-2.c: Likewise.
 774         * aarch64-opc-2.c: Likewise.
 775
 776 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 777
 778         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 779         AARCH64_OPND_QLF_P_[ZM].
 780         (aarch64_print_operand): Print /z and /m where appropriate.
 781
 782 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 783
 784         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 785         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 786         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 787         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 788         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 789         * aarch64-opc.c (fields): Add corresponding entries here.
 790         (operand_general_constraint_met_p): Check that SVE register lists
 791         have the correct length.  Check the ranges of SVE index registers.
 792         Check for cases where p8-p15 are used in 3-bit predicate fields.
 793         (aarch64_print_operand): Handle the new SVE operands.
 794         * aarch64-opc-2.c: Regenerate.
 795         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 796         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 797         (aarch64_ins_sve_reglist): Likewise.
 798         * aarch64-asm-2.c: Regenerate.
 799         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 800         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 801         (aarch64_ext_sve_reglist): Likewise.
 802         * aarch64-dis-2.c: Regenerate.
 803
 804 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 805
 806         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 807         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 808         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 809         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 810         tied operands.
 811
 812 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 813
 814         * aarch64-opc.c (get_offset_int_reg_name): New function.
 815         (print_immediate_offset_address): Likewise.
 816         (print_register_offset_address): Take the base and offset
 817         registers as parameters.
 818         (aarch64_print_operand): Update caller accordingly.  Use
 819         print_immediate_offset_address.
 820
 821 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 822
 823         * aarch64-opc.c (BANK): New macro.
 824         (R32, R64): Take a register number as argument
 825         (int_reg): Use BANK.
 826
 827 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 828
 829         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 830         (aarch64_print_operand): Update accordingly.
 831
 832 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 833
 834         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 835         for FPIMM.
 836         * aarch64-asm.h (ins_fpimm): New inserter.
 837         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 838         * aarch64-asm-2.c: Regenerate.
 839         * aarch64-dis.h (ext_fpimm): New extractor.
 840         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 841         (aarch64_ext_fpimm): New function.
 842         * aarch64-dis-2.c: Regenerate.
 843
 844 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 845
 846         * aarch64-asm.c: Include libiberty.h.
 847         (insert_fields): New function.
 848         (aarch64_ins_imm): Use it.
 849         * aarch64-dis.c (extract_fields): New function.
 850         (aarch64_ext_imm): Use it.
 851
 852 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 853
 854         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 855         with an esize parameter.
 856         (operand_general_constraint_met_p): Update accordingly.
 857         Fix misindented code.
 858         * aarch64-asm.c (aarch64_ins_limm): Update call to
 859         aarch64_logical_immediate_p.
 860
 861 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 862
 863         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 864
 865 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 866
 867         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 868
 869 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 870
 871         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 872
 873 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 874
 875         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 876         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 877         xor3>: Delete mnemonics.
 878         <cp_abort>: Rename mnemonic from ...
 879         <cpabort>: ...to this.
 880         <setb>: Change to a X form instruction.
 881         <sync>: Change to 1 operand form.
 882         <copy>: Delete mnemonic.
 883         <copy_first>: Rename mnemonic from ...
 884         <copy>: ...to this.
 885         <paste, paste.>: Delete mnemonics.
 886         <paste_last>: Rename mnemonic from ...
 887         <paste.>: ...to this.
 888
 889 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 890
 891         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 892
 893 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 894
 895         * s390-mkopc.c (main): Support alternate arch strings.
 896
 897 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 898
 899         * s390-opc.txt: Fix kmctr instruction type.
 900
 901 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 902
 903         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 904         * i386-init.h: Regenerated.
 905
 906 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 907
 908         * opcodes/arc-dis.c (print_insn_arc): Changed.
 909
 910 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 911
 912         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 913         camellia_fl.
 914
 915 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 916
 917         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 918         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 919         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 920
 921 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 922
 923         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 924         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 925         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 926         PREFIX_MOD_3_0FAE_REG_4.
 927         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 928         PREFIX_MOD_3_0FAE_REG_4.
 929         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 930         (cpu_flags): Add CpuPTWRITE.
 931         * i386-opc.h (CpuPTWRITE): New.
 932         (i386_cpu_flags): Add cpuptwrite.
 933         * i386-opc.tbl: Add ptwrite instruction.
 934         * i386-init.h: Regenerated.
 935         * i386-tbl.h: Likewise.
 936
 937 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 938
 939         * arc-dis.h: Wrap around in extern "C".
 940
 941 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 942
 943         * aarch64-tbl.h (V8_2_INSN): New macro.
 944         (aarch64_opcode_table): Use it.
 945
 946 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 947
 948         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 949         CORE_INSN, __FP_INSN and SIMD_INSN.
 950
 951 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 952
 953         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 954         (aarch64_opcode_table): Update uses accordingly.
 955
 956 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 957         Kwok Cheung Yeung  <kcy@codesourcery.com>
 958
 959         opcodes/
 960         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 961         'e_cmplwi' to 'e_cmpli' instead.
 962         (OPVUPRT, OPVUPRT_MASK): Define.
 963         (powerpc_opcodes): Add E200Z4 insns.
 964         (vle_opcodes): Add context save/restore insns.
 965
 966 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 967
 968         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 969         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 970         "j".
 971
 972 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 973
 974         * arc-nps400-tbl.h: Change block comments to GNU format.
 975         * arc-dis.c: Add new globals addrtypenames,
 976         addrtypenames_max, and addtypeunknown.
 977         (get_addrtype): New function.
 978         (print_insn_arc): Print colons and address types when
 979         required.
 980         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 981         define insert and extract functions for all address types.
 982         (arc_operands): Add operands for colon and all address
 983         types.
 984         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 985         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 986         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 987         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 988         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 989         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 990
 991 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 992
 993         * configure: Regenerated.
 994
 995 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 996
 997         * arc-dis.c (skipclass): New structure.
 998         (decodelist): New variable.
 999         (is_compatible_p): New function.
1000         (new_element): Likewise.
1001         (skip_class_p): Likewise.
1002         (find_format_from_table): Use skip_class_p function.
1003         (find_format): Decode first the extension instructions.
1004         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1005         e_flags.
1006         (parse_option): New function.
1007         (parse_disassembler_options): Likewise.
1008         (print_arc_disassembler_options): Likewise.
1009         (print_insn_arc): Use parse_disassembler_options function.  Proper
1010         select ARCv2 cpu variant.
1011         * disassemble.c (disassembler_usage): Add ARC disassembler
1012         options.
1013
1014 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1015
1016         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1017         annotation from the "nal" entry and reorder it beyond "bltzal".
1018
1019 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1020
1021         * sparc-opc.c (ldtxa): New macro.
1022         (sparc_opcodes): Use the macro defined above to add entries for
1023         the LDTXA instructions.
1024         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1025         instruction.
1026
1027 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1028
1029         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1030         and "jmpc".
1031
1032 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1033
1034         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1035         (movzb): Adjust to cover all permitted suffixes.
1036         (movzw): New.
1037         * i386-tbl.h: Re-generate.
1038
1039 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1040
1041         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1042         (lgdt): Remove Tbyte from non-64-bit variant.
1043         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1044         xsaves64, xsavec64): Remove Disp16.
1045         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1046         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1047         64-bit variants.
1048         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1049         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1050         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1051         64-bit variants.
1052         * i386-tbl.h: Re-generate.
1053
1054 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1057         * i386-tbl.h: Re-generate.
1058
1059 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1060
1061         * arm-dis.c (print_insn): Fix typo in comment.
1062
1063 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1064
1065         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1066         range of ldst_elemlist operands.
1067         (print_register_list): Use PRIi64 to print the index.
1068         (aarch64_print_operand): Likewise.
1069
1070 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1071
1072         * mcore-opc.h: Remove sentinal.
1073         * mcore-dis.c (print_insn_mcore): Adjust.
1074
1075 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1076
1077         * arc-opc.c: Correct description of availability of NPS400
1078         features.
1079
1080 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1081
1082         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1083         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1084         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1085         xor3>: New mnemonics.
1086         <setb>: Change to a VX form instruction.
1087         (insert_sh6): Add support for rldixor.
1088         (extract_sh6): Likewise.
1089
1090 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1091
1092         * arc-ext.h: Wrap in extern C.
1093
1094 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1095
1096         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1097         Use same method for determining instruction length on ARC700 and
1098         NPS-400.
1099         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1100         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1101         with the NPS400 subclass.
1102         * arc-opc.c: Likewise.
1103
1104 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1105
1106         * sparc-opc.c (rdasr): New macro.
1107         (wrasr): Likewise.
1108         (rdpr): Likewise.
1109         (wrpr): Likewise.
1110         (rdhpr): Likewise.
1111         (wrhpr): Likewise.
1112         (sparc_opcodes): Use the macros above to fix and expand the
1113         definition of read/write instructions from/to
1114         asr/privileged/hyperprivileged instructions.
1115         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1116         %hva_mask_nz.  Prefer softint_set and softint_clear over
1117         set_softint and clear_softint.
1118         (print_insn_sparc): Support %ver in Rd.
1119
1120 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1121
1122         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1123         architecture according to the hardware capabilities they require.
1124
1125 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1126
1127         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1128         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1129         bfd_mach_sparc_v9{c,d,e,v,m}.
1130         * sparc-opc.c (MASK_V9C): Define.
1131         (MASK_V9D): Likewise.
1132         (MASK_V9E): Likewise.
1133         (MASK_V9V): Likewise.
1134         (MASK_V9M): Likewise.
1135         (v6): Add MASK_V9{C,D,E,V,M}.
1136         (v6notlet): Likewise.
1137         (v7): Likewise.
1138         (v8): Likewise.
1139         (v9): Likewise.
1140         (v9andleon): Likewise.
1141         (v9a): Likewise.
1142         (v9b): Likewise.
1143         (v9c): Define.
1144         (v9d): Likewise.
1145         (v9e): Likewise.
1146         (v9v): Likewise.
1147         (v9m): Likewise.
1148         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1149
1150 2016-06-15  Nick Clifton  <nickc@redhat.com>
1151
1152         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1153         constants to match expected behaviour.
1154         (nds32_parse_opcode): Likewise.  Also for whitespace.
1155
1156 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1157
1158         * arc-opc.c (extract_rhv1): Extract value from insn.
1159
1160 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1161
1162         * arc-nps400-tbl.h: Add ldbit instruction.
1163         * arc-opc.c: Add flag classes required for ldbit.
1164
1165 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1166
1167         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1168         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1169         support the above instructions.
1170
1171 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1172
1173         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1174         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1175         csma, cbba, zncv, and hofs.
1176         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1177         support the above instructions.
1178
1179 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1180
1181         * arc-nps400-tbl.h: Add andab and orab instructions.
1182
1183 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1184
1185         * arc-nps400-tbl.h: Add addl-like instructions.
1186
1187 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1188
1189         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1190
1191 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1192
1193         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1194         instructions.
1195
1196 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1197
1198         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1199         variable.
1200         (init_disasm): Handle new command line option "insnlength".
1201         (print_s390_disassembler_options): Mention new option in help
1202         output.
1203         (print_insn_s390): Use the encoded insn length when dumping
1204         unknown instructions.
1205
1206 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1207
1208         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1209          to the address and set as symbol address for LDS/ STS immediate operands.
1210
1211 2016-06-07  Alan Modra  <amodra@gmail.com>
1212
1213         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1214         cpu for "vle" to e500.
1215         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1216         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1217         (PPCNONE): Delete, substitute throughout.
1218         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1219         except for major opcode 4 and 31.
1220         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1221
1222 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1223
1224         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1225         ARM_EXT_RAS in relevant entries.
1226
1227 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1228
1229         PR binutils/20196
1230         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1231         opcodes for E6500.
1232
1233 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1234
1235         PR binutis/18386
1236         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1237         (indir_v_mode): New.
1238         Add comments for '&'.
1239         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1240         (putop): Handle '&'.
1241         (intel_operand_size): Handle indir_v_mode.
1242         (OP_E_register): Likewise.
1243         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1244         64-bit indirect call/jmp for AMD64.
1245         * i386-tbl.h: Regenerated
1246
1247 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1248
1249         * arc-dis.c (struct arc_operand_iterator): New structure.
1250         (find_format_from_table): All the old content from find_format,
1251         with some minor adjustments, and parameter renaming.
1252         (find_format_long_instructions): New function.
1253         (find_format): Rewritten.
1254         (arc_insn_length): Add LSB parameter.
1255         (extract_operand_value): New function.
1256         (operand_iterator_next): New function.
1257         (print_insn_arc): Use new functions to find opcode, and iterator
1258         over operands.
1259         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1260         (extract_nps_3bit_dst_short): New function.
1261         (insert_nps_3bit_src2_short): New function.
1262         (extract_nps_3bit_src2_short): New function.
1263         (insert_nps_bitop1_size): New function.
1264         (extract_nps_bitop1_size): New function.
1265         (insert_nps_bitop2_size): New function.
1266         (extract_nps_bitop2_size): New function.
1267         (insert_nps_bitop_mod4_msb): New function.
1268         (extract_nps_bitop_mod4_msb): New function.
1269         (insert_nps_bitop_mod4_lsb): New function.
1270         (extract_nps_bitop_mod4_lsb): New function.
1271         (insert_nps_bitop_dst_pos3_pos4): New function.
1272         (extract_nps_bitop_dst_pos3_pos4): New function.
1273         (insert_nps_bitop_ins_ext): New function.
1274         (extract_nps_bitop_ins_ext): New function.
1275         (arc_operands): Add new operands.
1276         (arc_long_opcodes): New global array.
1277         (arc_num_long_opcodes): New global.
1278         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1279
1280 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1281
1282         * nds32-asm.h: Add extern "C".
1283         * sh-opc.h: Likewise.
1284
1285 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1286
1287         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1288         0,b,limm to the rflt instruction.
1289
1290 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1291
1292         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1293         constant.
1294
1295 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1296
1297         PR gas/20145
1298         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1299         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1300         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1301         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1302         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1303         * i386-init.h: Regenerated.
1304
1305 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1306
1307         PR gas/20145
1308         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1309         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1310         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1311         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1312         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1313         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1314         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1315         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1316         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1317         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1318         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1319         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1320         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1321         CpuRegMask for AVX512.
1322         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1323         and CpuRegMask.
1324         (set_bitfield_from_cpu_flag_init): New function.
1325         (set_bitfield): Remove const on f.  Call
1326         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1327         * i386-opc.h (CpuRegMMX): New.
1328         (CpuRegXMM): Likewise.
1329         (CpuRegYMM): Likewise.
1330         (CpuRegZMM): Likewise.
1331         (CpuRegMask): Likewise.
1332         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1333         and cpuregmask.
1334         * i386-init.h: Regenerated.
1335         * i386-tbl.h: Likewise.
1336
1337 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1338
1339         PR gas/20154
1340         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1341         (opcode_modifiers): Add AMD64 and Intel64.
1342         (main): Properly verify CpuMax.
1343         * i386-opc.h (CpuAMD64): Removed.
1344         (CpuIntel64): Likewise.
1345         (CpuMax): Set to CpuNo64.
1346         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1347         (AMD64): New.
1348         (Intel64): Likewise.
1349         (i386_opcode_modifier): Add amd64 and intel64.
1350         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1351         on call and jmp.
1352         * i386-init.h: Regenerated.
1353         * i386-tbl.h: Likewise.
1354
1355 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1356
1357         PR gas/20154
1358         * i386-gen.c (main): Fail if CpuMax is incorrect.
1359         * i386-opc.h (CpuMax): Set to CpuIntel64.
1360         * i386-tbl.h: Regenerated.
1361
1362 2016-05-27  Nick Clifton  <nickc@redhat.com>
1363
1364         PR target/20150
1365         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1366         (msp430dis_opcode_unsigned): New function.
1367         (msp430dis_opcode_signed): New function.
1368         (msp430_singleoperand): Use the new opcode reading functions.
1369         Only disassenmble bytes if they were successfully read.
1370         (msp430_doubleoperand): Likewise.
1371         (msp430_branchinstr): Likewise.
1372         (msp430x_callx_instr): Likewise.
1373         (print_insn_msp430): Check that it is safe to read bytes before
1374         attempting disassembly.  Use the new opcode reading functions.
1375
1376 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1377
1378         * ppc-opc.c (CY): New define.  Document it.
1379         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1380
1381 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1382
1383         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1384         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1385         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1386         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1387         CPU_ANY_AVX_FLAGS.
1388         * i386-init.h: Regenerated.
1389
1390 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1391
1392         PR gas/20141
1393         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1394         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1395         * i386-init.h: Regenerated.
1396
1397 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1398
1399         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1400         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1401         * i386-init.h: Regenerated.
1402
1403 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1404
1405         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1406         information.
1407         (print_insn_arc): Set insn_type information.
1408         * arc-opc.c (C_CC): Add F_CLASS_COND.
1409         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1410         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1411         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1412         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1413         (brne, brne_s, jeq_s, jne_s): Likewise.
1414
1415 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1416
1417         * arc-tbl.h (neg): New instruction variant.
1418
1419 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1420
1421         * arc-dis.c (find_format, find_format, get_auxreg)
1422         (print_insn_arc): Changed.
1423         * arc-ext.h (INSERT_XOP): Likewise.
1424
1425 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1426
1427         * tic54x-dis.c (sprint_mmr): Adjust.
1428         * tic54x-opc.c: Likewise.
1429
1430 2016-05-19  Alan Modra  <amodra@gmail.com>
1431
1432         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1433
1434 2016-05-19  Alan Modra  <amodra@gmail.com>
1435
1436         * ppc-opc.c: Formatting.
1437         (NSISIGNOPT): Define.
1438         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1439
1440 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1441
1442         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1443         replacing references to `micromips_ase' throughout.
1444         (_print_insn_mips): Don't use file-level microMIPS annotation to
1445         determine the disassembly mode with the symbol table.
1446
1447 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1448
1449         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1450
1451 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1452
1453         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1454         mips64r6.
1455         * mips-opc.c (D34): New macro.
1456         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1457
1458 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1459
1460         * i386-dis.c (prefix_table): Add RDPID instruction.
1461         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1462         (cpu_flags): Add RDPID bitfield.
1463         * i386-opc.h (enum): Add RDPID element.
1464         (i386_cpu_flags): Add RDPID field.
1465         * i386-opc.tbl: Add RDPID instruction.
1466         * i386-init.h: Regenerate.
1467         * i386-tbl.h: Regenerate.
1468
1469 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1470
1471         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1472         branch type of a symbol.
1473         (print_insn): Likewise.
1474
1475 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1476
1477         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1478         Mainline Security Extensions instructions.
1479         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1480         Extensions instructions.
1481         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1482         instructions.
1483         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1484         special registers.
1485
1486 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1487
1488         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1489
1490 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1491
1492         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1493         (arcExtMap_genOpcode): Likewise.
1494         * arc-opc.c (arg_32bit_rc): Define new variable.
1495         (arg_32bit_u6): Likewise.
1496         (arg_32bit_limm): Likewise.
1497
1498 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1499
1500         * aarch64-gen.c (VERIFIER): Define.
1501         * aarch64-opc.c (VERIFIER): Define.
1502         (verify_ldpsw): Use static linkage.
1503         * aarch64-opc.h (verify_ldpsw): Remove.
1504         * aarch64-tbl.h: Use VERIFIER for verifiers.
1505
1506 2016-04-28  Nick Clifton  <nickc@redhat.com>
1507
1508         PR target/19722
1509         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1510         * aarch64-opc.c (verify_ldpsw): New function.
1511         * aarch64-opc.h (verify_ldpsw): New prototype.
1512         * aarch64-tbl.h: Add initialiser for verifier field.
1513         (LDPSW): Set verifier to verify_ldpsw.
1514
1515 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1516
1517         PR binutils/19983
1518         PR binutils/19984
1519         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1520         smaller than address size.
1521
1522 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1523
1524         * alpha-dis.c: Regenerate.
1525         * crx-dis.c: Likewise.
1526         * disassemble.c: Likewise.
1527         * epiphany-opc.c: Likewise.
1528         * fr30-opc.c: Likewise.
1529         * frv-opc.c: Likewise.
1530         * ip2k-opc.c: Likewise.
1531         * iq2000-opc.c: Likewise.
1532         * lm32-opc.c: Likewise.
1533         * lm32-opinst.c: Likewise.
1534         * m32c-opc.c: Likewise.
1535         * m32r-opc.c: Likewise.
1536         * m32r-opinst.c: Likewise.
1537         * mep-opc.c: Likewise.
1538         * mt-opc.c: Likewise.
1539         * or1k-opc.c: Likewise.
1540         * or1k-opinst.c: Likewise.
1541         * tic80-opc.c: Likewise.
1542         * xc16x-opc.c: Likewise.
1543         * xstormy16-opc.c: Likewise.
1544
1545 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1546
1547         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1548         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1549         calcsd, and calcxd instructions.
1550         * arc-opc.c (insert_nps_bitop_size): Delete.
1551         (extract_nps_bitop_size): Delete.
1552         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1553         (extract_nps_qcmp_m3): Define.
1554         (extract_nps_qcmp_m2): Define.
1555         (extract_nps_qcmp_m1): Define.
1556         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1557         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1558         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1559         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1560         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1561         NPS_QCMP_M3.
1562
1563 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1564
1565         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1566
1567 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1568
1569         * Makefile.in: Regenerated with automake 1.11.6.
1570         * aclocal.m4: Likewise.
1571
1572 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1573
1574         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1575         instructions.
1576         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1577         (extract_nps_cmem_uimm16): New function.
1578         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1579
1580 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1581
1582         * arc-dis.c (arc_insn_length): New function.
1583         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1584         (find_format): Change insnLen parameter to unsigned.
1585
1586 2016-04-13  Nick Clifton  <nickc@redhat.com>
1587
1588         PR target/19937
1589         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1590         the LD.B and LD.BU instructions.
1591
1592 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1593
1594         * arc-dis.c (find_format): Check for extension flags.
1595         (print_flags): New function.
1596         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1597         .extAuxRegister.
1598         * arc-ext.c (arcExtMap_coreRegName): Use
1599         LAST_EXTENSION_CORE_REGISTER.
1600         (arcExtMap_coreReadWrite): Likewise.
1601         (dump_ARC_extmap): Update printing.
1602         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1603         (arc_aux_regs): Add cpu field.
1604         * arc-regs.h: Add cpu field, lower case name aux registers.
1605
1606 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1607
1608         * arc-tbl.h: Add rtsc, sleep with no arguments.
1609
1610 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1611
1612         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1613         Initialize.
1614         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1615         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1616         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1617         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1618         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1619         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1620         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1621         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1622         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1623         (arc_opcode arc_opcodes): Null terminate the array.
1624         (arc_num_opcodes): Remove.
1625         * arc-ext.h (INSERT_XOP): Define.
1626         (extInstruction_t): Likewise.
1627         (arcExtMap_instName): Delete.
1628         (arcExtMap_insn): New function.
1629         (arcExtMap_genOpcode): Likewise.
1630         * arc-ext.c (ExtInstruction): Remove.
1631         (create_map): Zero initialize instruction fields.
1632         (arcExtMap_instName): Remove.
1633         (arcExtMap_insn): New function.
1634         (dump_ARC_extmap): More info while debuging.
1635         (arcExtMap_genOpcode): New function.
1636         * arc-dis.c (find_format): New function.
1637         (print_insn_arc): Use find_format.
1638         (arc_get_disassembler): Enable dump_ARC_extmap only when
1639         debugging.
1640
1641 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1642
1643         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1644         instruction bits out.
1645
1646 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1647
1648         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1649         * arc-opc.c (arc_flag_operands): Add new flags.
1650         (arc_flag_classes): Add new classes.
1651
1652 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1653
1654         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1655
1656 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1657
1658         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1659         encode1, rflt, crc16, and crc32 instructions.
1660         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1661         (arc_flag_classes): Add C_NPS_R.
1662         (insert_nps_bitop_size_2b): New function.
1663         (extract_nps_bitop_size_2b): Likewise.
1664         (insert_nps_bitop_uimm8): Likewise.
1665         (extract_nps_bitop_uimm8): Likewise.
1666         (arc_operands): Add new operand entries.
1667
1668 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1669
1670         * arc-regs.h: Add a new subclass field.  Add double assist
1671         accumulator register values.
1672         * arc-tbl.h: Use DPA subclass to mark the double assist
1673         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1674         * arc-opc.c (RSP): Define instead of SP.
1675         (arc_aux_regs): Add the subclass field.
1676
1677 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1678
1679         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1680
1681 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1682
1683         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1684         NPS_R_SRC1.
1685
1686 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1687
1688         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1689         issues.  No functional changes.
1690
1691 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1692
1693         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1694         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1695         (RTT): Remove duplicate.
1696         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1697         (PCT_CONFIG*): Remove.
1698         (D1L, D1H, D2H, D2L): Define.
1699
1700 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1701
1702         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1703
1704 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1705
1706         * arc-tbl.h (invld07): Remove.
1707         * arc-ext-tbl.h: New file.
1708         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1709         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1710
1711 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1712
1713         Fix -Wstack-usage warnings.
1714         * aarch64-dis.c (print_operands): Substitute size.
1715         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1716
1717 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1718
1719         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1720         to get a proper diagnostic when an invalid ASR register is used.
1721
1722 2016-03-22  Nick Clifton  <nickc@redhat.com>
1723
1724         * configure: Regenerate.
1725
1726 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1727
1728         * arc-nps400-tbl.h: New file.
1729         * arc-opc.c: Add top level comment.
1730         (insert_nps_3bit_dst): New function.
1731         (extract_nps_3bit_dst): New function.
1732         (insert_nps_3bit_src2): New function.
1733         (extract_nps_3bit_src2): New function.
1734         (insert_nps_bitop_size): New function.
1735         (extract_nps_bitop_size): New function.
1736         (arc_flag_operands): Add nps400 entries.
1737         (arc_flag_classes): Add nps400 entries.
1738         (arc_operands): Add nps400 entries.
1739         (arc_opcodes): Add nps400 include.
1740
1741 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1742
1743         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1744         the new class enum values.
1745
1746 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1747
1748         * arc-dis.c (print_insn_arc): Handle nps400.
1749
1750 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1751
1752         * arc-opc.c (BASE): Delete.
1753
1754 2016-03-18  Nick Clifton  <nickc@redhat.com>
1755
1756         PR target/19721
1757         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1758         of MOV insn that aliases an ORR insn.
1759
1760 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1761
1762         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1763
1764 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1765
1766         * mcore-opc.h: Add const qualifiers.
1767         * microblaze-opc.h (struct op_code_struct): Likewise.
1768         * sh-opc.h: Likewise.
1769         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1770         (tic4x_print_op): Likewise.
1771
1772 2016-03-02  Alan Modra  <amodra@gmail.com>
1773
1774         * or1k-desc.h: Regenerate.
1775         * fr30-ibld.c: Regenerate.
1776         * rl78-decode.c: Regenerate.
1777
1778 2016-03-01  Nick Clifton  <nickc@redhat.com>
1779
1780         PR target/19747
1781         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1782
1783 2016-02-24  Renlin Li  <renlin.li@arm.com>
1784
1785         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1786         (print_insn_coprocessor): Support fp16 instructions.
1787
1788 2016-02-24  Renlin Li  <renlin.li@arm.com>
1789
1790         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1791         vminnm, vrint(mpna).
1792
1793 2016-02-24  Renlin Li  <renlin.li@arm.com>
1794
1795         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1796         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1797
1798 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1799
1800         * i386-dis.c (print_insn): Parenthesize expression to prevent
1801         truncated addresses.
1802         (OP_J): Likewise.
1803
1804 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1805             Janek van Oirschot  <jvanoirs@synopsys.com>
1806
1807         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1808         variable.
1809
1810 2016-02-04  Nick Clifton  <nickc@redhat.com>
1811
1812         PR target/19561
1813         * msp430-dis.c (print_insn_msp430): Add a special case for
1814         decoding an RRC instruction with the ZC bit set in the extension
1815         word.
1816
1817 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1818
1819         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1820         * epiphany-ibld.c: Regenerate.
1821         * fr30-ibld.c: Regenerate.
1822         * frv-ibld.c: Regenerate.
1823         * ip2k-ibld.c: Regenerate.
1824         * iq2000-ibld.c: Regenerate.
1825         * lm32-ibld.c: Regenerate.
1826         * m32c-ibld.c: Regenerate.
1827         * m32r-ibld.c: Regenerate.
1828         * mep-ibld.c: Regenerate.
1829         * mt-ibld.c: Regenerate.
1830         * or1k-ibld.c: Regenerate.
1831         * xc16x-ibld.c: Regenerate.
1832         * xstormy16-ibld.c: Regenerate.
1833
1834 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1835
1836         * epiphany-dis.c: Regenerated from latest cpu files.
1837
1838 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1839
1840         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1841         test bit.
1842
1843 2016-01-25  Renlin Li  <renlin.li@arm.com>
1844
1845         * arm-dis.c (mapping_symbol_for_insn): New function.
1846         (find_ifthen_state): Call mapping_symbol_for_insn().
1847
1848 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1849
1850         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1851         of MSR UAO immediate operand.
1852
1853 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1854
1855         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1856         instruction support.
1857
1858 2016-01-17  Alan Modra  <amodra@gmail.com>
1859
1860         * configure: Regenerate.
1861
1862 2016-01-14  Nick Clifton  <nickc@redhat.com>
1863
1864         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1865         instructions that can support stack pointer operations.
1866         * rl78-decode.c: Regenerate.
1867         * rl78-dis.c: Fix display of stack pointer in MOVW based
1868         instructions.
1869
1870 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1871
1872         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1873         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1874         erxtatus_el1 and erxaddr_el1.
1875
1876 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1877
1878         * arm-dis.c (arm_opcodes): Add "esb".
1879         (thumb_opcodes): Likewise.
1880
1881 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1882
1883         * ppc-opc.c <xscmpnedp>: Delete.
1884         <xvcmpnedp>: Likewise.
1885         <xvcmpnedp.>: Likewise.
1886         <xvcmpnesp>: Likewise.
1887         <xvcmpnesp.>: Likewise.
1888
1889 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1890
1891         PR gas/13050
1892         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1893         addition to ISA_A.
1894
1895 2016-01-01  Alan Modra  <amodra@gmail.com>
1896
1897         Update year range in copyright notice of all files.
1898
1899 For older changes see ChangeLog-2015
1900 \f
1901 Copyright (C) 2016 Free Software Foundation, Inc.
1902
1903 Copying and distribution of this file, with or without modification,
1904 are permitted in any medium without royalty provided the copyright
1905 notice and this notice are preserved.
1906
1907 Local Variables:
1908 mode: change-log
1909 left-margin: 8
1910 fill-column: 74
1911 version-control: never
1912 End: