opcodes/ChangeLog

   1 2016-12-20  Andrew Waterman  <andrew@sifive.com>
   2
   3         * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
   4         "*.aqrl".
   5
   6 2016-12-20  Andrew Waterman  <andrew@sifive.com>
   7
   8         * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
   9         INSN_ALIAS.
  10
  11 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  12
  13         * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
  14         format.
  15
  16 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  17
  18         * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
  19         XLEN when none is provided.
  20
  21 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  22
  23         * riscv-opc.c: Formatting fixes.
  24
  25 2016-12-20  Alan Modra  <amodra@gmail.com>
  26
  27         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
  28         * Makefile.in: Regenerate.
  29         * po/POTFILES.in: Regenerate.
  30
  31 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
  32
  33         * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
  34         Only examine ELF file structures here.
  35
  36 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
  37
  38         * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
  39         `bfd_mips_elf_get_abiflags' here.
  40
  41 2016-12-16  Nick Clifton  <nickc@redhat.com>
  42
  43         * arm-dis.c (print_insn_thumb32): Fix compile time warning
  44         computing value_in_comment.
  45
  46 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  47
  48         * mips-dis.c (mips_convert_abiflags_ases): New function.
  49         (set_default_mips_dis_options): Also infer ASE flags from ELF
  50         file structures.
  51
  52 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  53
  54         * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
  55         header flag interpretation code.
  56
  57 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  58
  59         * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
  60         `pinfo2' with SP-relative "sd" entries.
  61
  62 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  63
  64         * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
  65         compact jumps.
  66
  67 2016-12-13 Renlin Li <renlin.li@arm.com>
  68
  69         * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
  70         qualifier.
  71         (operand_general_constraint_met_p): Remove case for CP_REG.
  72         (aarch64_print_operand): Print CRn, CRm operand using imm field.
  73         * aarch64-tbl.h (QL_SYS): Use CR qualifier.
  74         (QL_SYSL): Likewise.
  75         (aarch64_opcode_table): Change CRn, CRm operand class and type.
  76         * aarch64-opc-2.c : Regenerate.
  77         * aarch64-asm-2.c : Likewise.
  78         * aarch64-dis-2.c : Likewise.
  79
  80 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  81
  82         * rx-dis.c: Include <setjmp.h>
  83         (struct private): New.
  84         (rx_get_byte): Check return value of read_memory_func, and
  85         call memory_error_func and OPCODES_SIGLONGJMP on error.
  86         (print_insn_rx): Call OPCODES_SIGSETJMP.
  87
  88 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  89
  90         * rl78-dis.c: Include <setjmp.h>.
  91         (struct private): New.
  92         (rl78_get_byte): Check return value of read_memory_func, and
  93         call memory_error_func and OPCODES_SIGLONGJMP on error.
  94         (print_insn_rl78_common): Call OPCODES_SIGJMP.
  95
  96 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  97
  98         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
  99
 100 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 101
 102         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
 103         than UINT.
 104
 105 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 106
 107         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
 108         to separate `extend' and its uninterpreted argument output.
 109         Separate hexadecimal halves of undecoded extended instructions
 110         output.
 111
 112 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 113
 114         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
 115         indentation space across.
 116
 117 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 118
 119         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
 120         adjustment for PC-relative operations following MIPS16e compact
 121         jumps or undefined RR/J(AL)R(C) encodings.
 122
 123 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 124
 125         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
 126         variable to `reglane_index'.
 127
 128 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
 129
 130         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
 131
 132 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 133
 134         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
 135
 136 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 137
 138         * mips16-opc.c (mips16_opcodes): Update comment naming structure
 139         members.
 140
 141 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 142
 143         * mips-dis.c (print_mips_disassembler_options): Reformat output.
 144
 145 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 146
 147         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
 148         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
 149
 150 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 151
 152         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
 153
 154 2016-12-01  Nick Clifton  <nickc@redhat.com>
 155
 156         PR binutils/20893
 157         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
 158         opcode designator.
 159
 160 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 161
 162         * arc-opc.c (insert_ra_chk): New function.
 163         (insert_rb_chk): Likewise.
 164         (insert_rad): Update text error message.
 165         (insert_rcd): Likewise.
 166         (insert_rhv2): Likewise.
 167         (insert_r0): Likewise.
 168         (insert_r1): Likewise.
 169         (insert_r2): Likewise.
 170         (insert_r3): Likewise.
 171         (insert_sp): Likewise.
 172         (insert_gp): Likewise.
 173         (insert_pcl): Likewise.
 174         (insert_blink): Likewise.
 175         (insert_ilink1): Likewise.
 176         (insert_ilink2): Likewise.
 177         (insert_ras): Likewise.
 178         (insert_rbs): Likewise.
 179         (insert_rcs): Likewise.
 180         (insert_simm3s): Likewise.
 181         (insert_rrange): Likewise.
 182         (insert_fpel): Likewise.
 183         (insert_blinkel): Likewise.
 184         (insert_pcel): Likewise.
 185         (insert_nps_3bit_dst): Likewise.
 186         (insert_nps_3bit_dst_short): Likewise.
 187         (insert_nps_3bit_src2_short): Likewise.
 188         (insert_nps_bitop_size_2b): Likewise.
 189         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 190         (RA_CHK): Define.
 191         (RB): Adjust.
 192         (RB_CHK): Define.
 193         (RC): Adjust.
 194         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 195         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 196         Change first insn argument to check for LP_COUNT usage.
 197         (rem): Likewise.
 198         (ld, ldd): All instructions are LOAD class.  Change first insn
 199         argument to check for LP_COUNT usage.
 200         (st, std): All instructions are STORE class.
 201         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 202         Change first insn argument to check for LP_COUNT usage.
 203         (mov): All instructions are MOVE class.  Change first insn
 204         argument to check for LP_COUNT usage.
 205
 206 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 207
 208         * arc-dis.c (is_compatible_p): Remove function.
 209         (skip_this_opcode): Don't add any decoding class to decode list.
 210         Remove warning.
 211         (find_format_from_table): Go through all opcodes, and warn if we
 212         use a guessed mnemonic.
 213
 214 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 215             Amit Pawar  <amit.pawar@amd.com>
 216
 217         PR binutils/20637
 218         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 219         instructions.
 220
 221 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 222
 223         * configure: Regenerate.
 224
 225 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 226
 227         * sparc-opc.c (HWS_V8): Definition moved from
 228         gas/config/tc-sparc.c.
 229         (HWS_V9): Likewise.
 230         (HWS_VA): Likewise.
 231         (HWS_VB): Likewise.
 232         (HWS_VC): Likewise.
 233         (HWS_VD): Likewise.
 234         (HWS_VE): Likewise.
 235         (HWS_VV): Likewise.
 236         (HWS_VM): Likewise.
 237         (HWS2_VM): Likewise.
 238         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 239         existing entries.
 240
 241 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 242
 243         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 244         instructions.
 245
 246 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 247
 248         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 249         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 250         (aarch64_opcode_table): Add fcmla and fcadd.
 251         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 252         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 253         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 254         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 255         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 256         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 257         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 258         (operand_general_constraint_met_p): Rotate and index range check.
 259         (aarch64_print_operand): Handle rotate operand.
 260         * aarch64-asm-2.c: Regenerate.
 261         * aarch64-dis-2.c: Likewise.
 262         * aarch64-opc-2.c: Likewise.
 263
 264 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 265
 266         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 267         * aarch64-asm-2.c: Regenerate.
 268         * aarch64-dis-2.c: Regenerate.
 269         * aarch64-opc-2.c: Regenerate.
 270
 271 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 272
 273         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 274         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 275         * aarch64-asm-2.c: Regenerate.
 276         * aarch64-dis-2.c: Regenerate.
 277         * aarch64-opc-2.c: Regenerate.
 278
 279 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 280
 281         * aarch64-tbl.h (QL_X1NIL): New.
 282         (arch64_opcode_table): Add ldraa, ldrab.
 283         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 284         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 285         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 286         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 287         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 288         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 289         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 290         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 291         (aarch64_print_operand): Likewise.
 292         * aarch64-asm-2.c: Regenerate.
 293         * aarch64-dis-2.c: Regenerate.
 294         * aarch64-opc-2.c: Regenerate.
 295
 296 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 297
 298         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 299         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 300         * aarch64-asm-2.c: Regenerate.
 301         * aarch64-dis-2.c: Regenerate.
 302         * aarch64-opc-2.c: Regenerate.
 303
 304 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 305
 306         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 307         (AARCH64_OPERANDS): Add Rm_SP.
 308         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 309         * aarch64-asm-2.c: Regenerate.
 310         * aarch64-dis-2.c: Regenerate.
 311         * aarch64-opc-2.c: Regenerate.
 312
 313 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 314
 315         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 316         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 317         autdzb, xpaci, xpacd.
 318         * aarch64-asm-2.c: Regenerate.
 319         * aarch64-dis-2.c: Regenerate.
 320         * aarch64-opc-2.c: Regenerate.
 321
 322 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 323
 324         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 325         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 326         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 327         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 328
 329 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 330
 331         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 332         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 333         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 334         autibsp.
 335         * aarch64-asm-2.c: Regenerate.
 336         * aarch64-dis-2.c: Regenerate.
 337
 338 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 339
 340         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 341
 342 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 343
 344         PR binutils/20799
 345         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 346         * i386-dis.c (EdqwS): Removed.
 347         (dqw_swap_mode): Likewise.
 348         (intel_operand_size): Don't check dqw_swap_mode.
 349         (OP_E_register): Likewise.
 350         (OP_E_memory): Likewise.
 351         (OP_G): Likewise.
 352         (OP_EX): Likewise.
 353         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 354         * i386-tbl.h: Regerated.
 355
 356 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 357
 358         * i386-opc.tbl: Merge AVX512F vmovq.
 359         * i386-tbl.h: Regerated.
 360
 361 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 362
 363         PR binutils/20701
 364         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 365         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 366         (three_byte_table): Remove THREE_BYTE_0F7A.
 367
 368 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 369
 370         PR binutils/20775
 371         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 372         (FGRPd9_4): Replace 1 with 2.
 373         (FGRPd9_5): Replace 2 with 3.
 374         (FGRPd9_6): Replace 3 with 4.
 375         (FGRPd9_7): Replace 4 with 5.
 376         (FGRPda_5): Replace 5 with 6.
 377         (FGRPdb_4): Replace 6 with 7.
 378         (FGRPde_3): Replace 7 with 8.
 379         (FGRPdf_4): Replace 8 with 9.
 380         (fgrps): Add an entry for Bad_Opcode.
 381
 382 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 383
 384         * arc-opc.c (arc_flag_operands): Add F_DI14.
 385         (arc_flag_classes): Add C_DI14.
 386         * arc-nps400-tbl.h: Add new exc instructions.
 387
 388 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 389
 390         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 391         major opcode 0xa.
 392         * arc-nps-400-tbl.h: Add dcmac instruction.
 393         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 394         (insert_nps_rbdouble_64): Added.
 395         (extract_nps_rbdouble_64): Added.
 396         (insert_nps_proto_size): Added.
 397         (extract_nps_proto_size): Added.
 398
 399 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 400
 401         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 402         relating to long instruction processing, add new limm field.
 403         (OPCODE): Rename to...
 404         (OPCODE_32BIT_INSN): ...this.
 405         (OPCODE_AC): Delete.
 406         (skip_this_opcode): Handle different instruction lengths, update
 407         macro name.
 408         (special_flag_p): Update parameter type.
 409         (find_format_from_table): Update for more instruction lengths.
 410         (find_format_long_instructions): Delete.
 411         (find_format): Update for more instruction lengths.
 412         (arc_insn_length): Likewise.
 413         (extract_operand_value): Update for more instruction lengths.
 414         (operand_iterator_next): Remove code relating to long
 415         instructions.
 416         (arc_opcode_to_insn_type): New function.
 417         (print_insn_arc):Update for more instructions lengths.
 418         * arc-ext.c (extInstruction_t): Change argument type.
 419         * arc-ext.h (extInstruction_t): Change argument type.
 420         * arc-fxi.h: Change type unsigned to unsigned long long
 421         extensively throughout.
 422         * arc-nps400-tbl.h: Add long instructions taken from
 423         arc_long_opcodes table in arc-opc.c.
 424         * arc-opc.c: Update parameter types on insert/extract handlers.
 425         (arc_long_opcodes): Delete.
 426         (arc_num_long_opcodes): Delete.
 427         (arc_opcode_len): Update for more instruction lengths.
 428
 429 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 430
 431         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 432
 433 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 434
 435         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 436         with arc_opcode_len.
 437         (find_format_long_instructions): Likewise.
 438         * arc-opc.c (arc_opcode_len): New function.
 439
 440 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 441
 442         * arc-nps400-tbl.h: Fix some instruction masks.
 443
 444 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 445
 446         * i386-dis.c (REG_82): Removed.
 447         (X86_64_82_REG_0): Likewise.
 448         (X86_64_82_REG_1): Likewise.
 449         (X86_64_82_REG_2): Likewise.
 450         (X86_64_82_REG_3): Likewise.
 451         (X86_64_82_REG_4): Likewise.
 452         (X86_64_82_REG_5): Likewise.
 453         (X86_64_82_REG_6): Likewise.
 454         (X86_64_82_REG_7): Likewise.
 455         (X86_64_82): New.
 456         (dis386): Use X86_64_82 instead of REG_82.
 457         (reg_table): Remove REG_82.
 458         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 459         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 460         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 461         X86_64_82_REG_7.
 462
 463 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 464
 465         PR binutils/20754
 466         * i386-dis.c (REG_82): New.
 467         (X86_64_82_REG_0): Likewise.
 468         (X86_64_82_REG_1): Likewise.
 469         (X86_64_82_REG_2): Likewise.
 470         (X86_64_82_REG_3): Likewise.
 471         (X86_64_82_REG_4): Likewise.
 472         (X86_64_82_REG_5): Likewise.
 473         (X86_64_82_REG_6): Likewise.
 474         (X86_64_82_REG_7): Likewise.
 475         (dis386): Use REG_82.
 476         (reg_table): Add REG_82.
 477         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 478         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 479         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 480
 481 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 482
 483         * i386-dis.c (REG_82): Renamed to ...
 484         (REG_83): This.
 485         (dis386): Updated.
 486         (reg_table): Likewise.
 487
 488 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 489
 490         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 491         * i386-dis-evex.h (evex_table): Updated.
 492         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 493         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 494         (cpu_flags): Add CpuAVX512_4VNNIW.
 495         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 496         (i386_cpu_flags): Add cpuavx512_4vnniw.
 497         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 498         * i386-init.h: Regenerate.
 499         * i386-tbl.h: Ditto.
 500
 501 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 502
 503         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 504         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 505         * i386-dis-evex.h (evex_table): Updated.
 506         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 507         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 508         (cpu_flags): Add CpuAVX512_4FMAPS.
 509         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 510         * i386-opc.h (AVX512_4FMAP): New.
 511         (i386_cpu_flags): Add cpuavx512_4fmaps.
 512         (ImplicitQuadGroup): New.
 513         (i386_opcode_modifier): Add implicitquadgroup.
 514         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 515         * i386-init.h: Regenerate.
 516         * i386-tbl.h: Ditto.
 517
 518 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 519             Andrew Waterman <andrew@sifive.com>
 520
 521         Add support for RISC-V architecture.
 522         * configure.ac: Add entry for bfd_riscv_arch.
 523         * configure: Regenerate.
 524         * disassemble.c (disassembler): Add support for riscv.
 525         (disassembler_usage): Likewise.
 526         * riscv-dis.c: New file.
 527         * riscv-opc.c: New file.
 528
 529 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 530
 531         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 532         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 533         (rm_table): Update the RM_0FAE_REG_7 entry.
 534         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 535         (cpu_flags): Remove CpuPCOMMIT.
 536         * i386-opc.h (CpuPCOMMIT): Removed.
 537         (i386_cpu_flags): Remove cpupcommit.
 538         * i386-opc.tbl: Remove pcommit.
 539         * i386-init.h: Regenerated.
 540         * i386-tbl.h: Likewise.
 541
 542 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 543
 544         PR binutis/20705
 545         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 546         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 547         32-bit mode.  Don't check vex.register_specifier in 32-bit
 548         mode.
 549         (OP_VEX): Check for invalid mask registers.
 550
 551 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 552
 553         PR binutis/20699
 554         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 555         sizeflag.
 556
 557 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 558
 559         PR binutis/20704
 560         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 561
 562 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 563
 564         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 565         local variable to `index_regno'.
 566
 567 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 568
 569         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 570
 571 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 572
 573         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 574         usage on ISA basis.
 575
 576 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 577
 578         PR target/20666
 579         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 580
 581 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 582
 583         PR target/20667
 584         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 585         available.
 586
 587 2016-10-07  Alan Modra  <amodra@gmail.com>
 588
 589         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 590
 591 2016-10-06  Alan Modra  <amodra@gmail.com>
 592
 593         * aarch64-opc.c: Spell fall through comments consistently.
 594         * i386-dis.c: Likewise.
 595         * aarch64-dis.c: Add missing fall through comments.
 596         * aarch64-opc.c: Likewise.
 597         * arc-dis.c: Likewise.
 598         * arm-dis.c: Likewise.
 599         * i386-dis.c: Likewise.
 600         * m68k-dis.c: Likewise.
 601         * mep-asm.c: Likewise.
 602         * ns32k-dis.c: Likewise.
 603         * sh-dis.c: Likewise.
 604         * tic4x-dis.c: Likewise.
 605         * tic6x-dis.c: Likewise.
 606         * vax-dis.c: Likewise.
 607
 608 2016-10-06  Alan Modra  <amodra@gmail.com>
 609
 610         * arc-ext.c (create_map): Add missing break.
 611         * msp430-decode.opc (encode_as): Likewise.
 612         * msp430-decode.c: Regenerate.
 613
 614 2016-10-06  Alan Modra  <amodra@gmail.com>
 615
 616         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 617         * crx-dis.c (print_insn_crx): Likewise.
 618
 619 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 620
 621         PR binutils/20657
 622         * i386-dis.c (putop): Don't assign alt twice.
 623
 624 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 625
 626         PR target/20553
 627         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 628
 629 2016-09-29  Alan Modra  <amodra@gmail.com>
 630
 631         * ppc-opc.c (L): Make compulsory.
 632         (LOPT): New, optional form of L.
 633         (HTM_R): Define as LOPT.
 634         (L0, L1): Delete.
 635         (L32OPT): New, optional for 32-bit L.
 636         (L2OPT): New, 2-bit L for dcbf.
 637         (SVC_LEC): Update.
 638         (L2): Define.
 639         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 640         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 641         <dcbf>: Use L2OPT.
 642         <tlbiel, tlbie>: Use LOPT.
 643         <wclr, wclrall>: Use L2.
 644
 645 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 646
 647         * Makefile.in: Regenerate.
 648         * configure: Likewise.
 649
 650 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 651
 652         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 653         (EXTINSN2OP): Use EXTINSN2OPF.
 654         (bspeekm, bspop, modapp): New extension instructions.
 655         * arc-opc.c (F_DNZ_ND): Define.
 656         (F_DNZ_D): Likewise.
 657         (F_SIZEB1): Changed.
 658         (C_DNZ_D): Define.
 659         (C_HARD): Changed.
 660         * arc-tbl.h (dbnz): New instruction.
 661         (prealloc): Allow it for ARC EM.
 662         (xbfu): Likewise.
 663
 664 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 665
 666         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 667         after commas in addresses.
 668         (aarch64_print_operand): Likewise.
 669
 670 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 671
 672         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 673         rather than "should be" or "expected to be" in error messages.
 674
 675 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 676
 677         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 678         (print_mnemonic_name): ...here.
 679         (print_comment): New function.
 680         (print_aarch64_insn): Call it.
 681         * aarch64-opc.c (aarch64_conds): Add SVE names.
 682         (aarch64_print_operand): Print alternative condition names in
 683         a comment.
 684
 685 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 686
 687         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 688         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 689         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 690         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 691         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 692         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 693         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 694         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 695         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 696         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 697         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 698         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 699         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 700         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 701         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 702         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 703         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 704         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 705         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 706         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 707         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 708         (aarch64_feature_sve): New variable.
 709         (SVE): New macro.
 710         (_SVE_INSN): Likewise.
 711         (aarch64_opcode_table): Add SVE instructions.
 712         * aarch64-opc.h (extract_fields): Declare.
 713         * aarch64-opc-2.c: Regenerate.
 714         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 715         * aarch64-asm-2.c: Regenerate.
 716         * aarch64-dis.c (extract_fields): Make global.
 717         (do_misc_decoding): Handle the new SVE aarch64_ops.
 718         * aarch64-dis-2.c: Regenerate.
 719
 720 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 721
 722         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 723         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 724         aarch64_field_kinds.
 725         * aarch64-opc.c (fields): Add corresponding entries.
 726         * aarch64-asm.c (aarch64_get_variant): New function.
 727         (aarch64_encode_variant_using_iclass): Likewise.
 728         (aarch64_opcode_encode): Call it.
 729         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 730         (aarch64_opcode_decode): Call it.
 731
 732 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 733
 734         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 735         and FP register operands.
 736         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 737         (FLD_SVE_Vn): New aarch64_field_kinds.
 738         * aarch64-opc.c (fields): Add corresponding entries.
 739         (aarch64_print_operand): Handle the new SVE core and FP register
 740         operands.
 741         * aarch64-opc-2.c: Regenerate.
 742         * aarch64-asm-2.c: Likewise.
 743         * aarch64-dis-2.c: Likewise.
 744
 745 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 746
 747         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 748         immediate operands.
 749         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 750         * aarch64-opc.c (fields): Add corresponding entry.
 751         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 752         operands.
 753         (aarch64_print_operand): Likewise.
 754         * aarch64-opc-2.c: Regenerate.
 755         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 756         (ins_sve_float_zero_one): New inserters.
 757         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 758         (aarch64_ins_sve_float_half_two): Likewise.
 759         (aarch64_ins_sve_float_zero_one): Likewise.
 760         * aarch64-asm-2.c: Regenerate.
 761         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 762         (ext_sve_float_zero_one): New extractors.
 763         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 764         (aarch64_ext_sve_float_half_two): Likewise.
 765         (aarch64_ext_sve_float_zero_one): Likewise.
 766         * aarch64-dis-2.c: Regenerate.
 767
 768 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 769
 770         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 771         integer immediate operands.
 772         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 773         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 774         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 775         * aarch64-opc.c (fields): Add corresponding entries.
 776         (operand_general_constraint_met_p): Handle the new SVE integer
 777         immediate operands.
 778         (aarch64_print_operand): Likewise.
 779         (aarch64_sve_dupm_mov_immediate_p): New function.
 780         * aarch64-opc-2.c: Regenerate.
 781         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 782         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 783         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 784         (aarch64_ins_limm): ...here.
 785         (aarch64_ins_inv_limm): New function.
 786         (aarch64_ins_sve_aimm): Likewise.
 787         (aarch64_ins_sve_asimm): Likewise.
 788         (aarch64_ins_sve_limm_mov): Likewise.
 789         (aarch64_ins_sve_shlimm): Likewise.
 790         (aarch64_ins_sve_shrimm): Likewise.
 791         * aarch64-asm-2.c: Regenerate.
 792         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 793         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 794         * aarch64-dis.c (decode_limm): New function, split out from...
 795         (aarch64_ext_limm): ...here.
 796         (aarch64_ext_inv_limm): New function.
 797         (decode_sve_aimm): Likewise.
 798         (aarch64_ext_sve_aimm): Likewise.
 799         (aarch64_ext_sve_asimm): Likewise.
 800         (aarch64_ext_sve_limm_mov): Likewise.
 801         (aarch64_top_bit): Likewise.
 802         (aarch64_ext_sve_shlimm): Likewise.
 803         (aarch64_ext_sve_shrimm): Likewise.
 804         * aarch64-dis-2.c: Regenerate.
 805
 806 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 807
 808         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 809         operands.
 810         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 811         the AARCH64_MOD_MUL_VL entry.
 812         (value_aligned_p): Cope with non-power-of-two alignments.
 813         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 814         (print_immediate_offset_address): Likewise.
 815         (aarch64_print_operand): Likewise.
 816         * aarch64-opc-2.c: Regenerate.
 817         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 818         (ins_sve_addr_ri_s9xvl): New inserters.
 819         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 820         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 821         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 822         * aarch64-asm-2.c: Regenerate.
 823         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 824         (ext_sve_addr_ri_s9xvl): New extractors.
 825         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 826         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 827         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 828         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 829         * aarch64-dis-2.c: Regenerate.
 830
 831 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 832
 833         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 834         address operands.
 835         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 836         (FLD_SVE_xs_22): New aarch64_field_kinds.
 837         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 838         (get_operand_specific_data): New function.
 839         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 840         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 841         (operand_general_constraint_met_p): Handle the new SVE address
 842         operands.
 843         (sve_reg): New array.
 844         (get_addr_sve_reg_name): New function.
 845         (aarch64_print_operand): Handle the new SVE address operands.
 846         * aarch64-opc-2.c: Regenerate.
 847         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 848         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 849         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 850         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 851         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 852         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 853         (aarch64_ins_sve_addr_zi_u5): Likewise.
 854         (aarch64_ins_sve_addr_zz): Likewise.
 855         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 856         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 857         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 858         * aarch64-asm-2.c: Regenerate.
 859         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 860         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 861         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 862         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 863         (aarch64_ext_sve_addr_ri_u6): Likewise.
 864         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 865         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 866         (aarch64_ext_sve_addr_zi_u5): Likewise.
 867         (aarch64_ext_sve_addr_zz): Likewise.
 868         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 869         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 870         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 871         * aarch64-dis-2.c: Regenerate.
 872
 873 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 874
 875         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 876         AARCH64_OPND_SVE_PATTERN_SCALED.
 877         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 878         * aarch64-opc.c (fields): Add a corresponding entry.
 879         (set_multiplier_out_of_range_error): New function.
 880         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 881         (operand_general_constraint_met_p): Handle
 882         AARCH64_OPND_SVE_PATTERN_SCALED.
 883         (print_register_offset_address): Use PRIi64 to print the
 884         shift amount.
 885         (aarch64_print_operand): Likewise.  Handle
 886         AARCH64_OPND_SVE_PATTERN_SCALED.
 887         * aarch64-opc-2.c: Regenerate.
 888         * aarch64-asm.h (ins_sve_scale): New inserter.
 889         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 890         * aarch64-asm-2.c: Regenerate.
 891         * aarch64-dis.h (ext_sve_scale): New inserter.
 892         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 893         * aarch64-dis-2.c: Regenerate.
 894
 895 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 896
 897         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 898         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 899         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 900         (FLD_SVE_prfop): Likewise.
 901         * aarch64-opc.c: Include libiberty.h.
 902         (aarch64_sve_pattern_array): New variable.
 903         (aarch64_sve_prfop_array): Likewise.
 904         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 905         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 906         AARCH64_OPND_SVE_PRFOP.
 907         * aarch64-asm-2.c: Regenerate.
 908         * aarch64-dis-2.c: Likewise.
 909         * aarch64-opc-2.c: Likewise.
 910
 911 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 912
 913         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 914         AARCH64_OPND_QLF_P_[ZM].
 915         (aarch64_print_operand): Print /z and /m where appropriate.
 916
 917 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 918
 919         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 920         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 921         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 922         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 923         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 924         * aarch64-opc.c (fields): Add corresponding entries here.
 925         (operand_general_constraint_met_p): Check that SVE register lists
 926         have the correct length.  Check the ranges of SVE index registers.
 927         Check for cases where p8-p15 are used in 3-bit predicate fields.
 928         (aarch64_print_operand): Handle the new SVE operands.
 929         * aarch64-opc-2.c: Regenerate.
 930         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 931         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 932         (aarch64_ins_sve_reglist): Likewise.
 933         * aarch64-asm-2.c: Regenerate.
 934         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 935         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 936         (aarch64_ext_sve_reglist): Likewise.
 937         * aarch64-dis-2.c: Regenerate.
 938
 939 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 940
 941         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 942         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 943         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 944         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 945         tied operands.
 946
 947 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 948
 949         * aarch64-opc.c (get_offset_int_reg_name): New function.
 950         (print_immediate_offset_address): Likewise.
 951         (print_register_offset_address): Take the base and offset
 952         registers as parameters.
 953         (aarch64_print_operand): Update caller accordingly.  Use
 954         print_immediate_offset_address.
 955
 956 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 957
 958         * aarch64-opc.c (BANK): New macro.
 959         (R32, R64): Take a register number as argument
 960         (int_reg): Use BANK.
 961
 962 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 963
 964         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 965         (aarch64_print_operand): Update accordingly.
 966
 967 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 968
 969         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 970         for FPIMM.
 971         * aarch64-asm.h (ins_fpimm): New inserter.
 972         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 973         * aarch64-asm-2.c: Regenerate.
 974         * aarch64-dis.h (ext_fpimm): New extractor.
 975         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 976         (aarch64_ext_fpimm): New function.
 977         * aarch64-dis-2.c: Regenerate.
 978
 979 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 980
 981         * aarch64-asm.c: Include libiberty.h.
 982         (insert_fields): New function.
 983         (aarch64_ins_imm): Use it.
 984         * aarch64-dis.c (extract_fields): New function.
 985         (aarch64_ext_imm): Use it.
 986
 987 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 988
 989         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 990         with an esize parameter.
 991         (operand_general_constraint_met_p): Update accordingly.
 992         Fix misindented code.
 993         * aarch64-asm.c (aarch64_ins_limm): Update call to
 994         aarch64_logical_immediate_p.
 995
 996 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 997
 998         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 999
1000 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1001
1002         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1003
1004 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
1005
1006         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1007
1008 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
1009
1010         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1011         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1012         xor3>: Delete mnemonics.
1013         <cp_abort>: Rename mnemonic from ...
1014         <cpabort>: ...to this.
1015         <setb>: Change to a X form instruction.
1016         <sync>: Change to 1 operand form.
1017         <copy>: Delete mnemonic.
1018         <copy_first>: Rename mnemonic from ...
1019         <copy>: ...to this.
1020         <paste, paste.>: Delete mnemonics.
1021         <paste_last>: Rename mnemonic from ...
1022         <paste.>: ...to this.
1023
1024 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1025
1026         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1027
1028 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1029
1030         * s390-mkopc.c (main): Support alternate arch strings.
1031
1032 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
1033
1034         * s390-opc.txt: Fix kmctr instruction type.
1035
1036 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
1037
1038         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1039         * i386-init.h: Regenerated.
1040
1041 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
1042
1043         * opcodes/arc-dis.c (print_insn_arc): Changed.
1044
1045 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
1046
1047         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1048         camellia_fl.
1049
1050 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1051
1052         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
1053         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1054         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1055
1056 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
1057
1058         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1059         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1060         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1061         PREFIX_MOD_3_0FAE_REG_4.
1062         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1063         PREFIX_MOD_3_0FAE_REG_4.
1064         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1065         (cpu_flags): Add CpuPTWRITE.
1066         * i386-opc.h (CpuPTWRITE): New.
1067         (i386_cpu_flags): Add cpuptwrite.
1068         * i386-opc.tbl: Add ptwrite instruction.
1069         * i386-init.h: Regenerated.
1070         * i386-tbl.h: Likewise.
1071
1072 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1073
1074         * arc-dis.h: Wrap around in extern "C".
1075
1076 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1077
1078         * aarch64-tbl.h (V8_2_INSN): New macro.
1079         (aarch64_opcode_table): Use it.
1080
1081 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1082
1083         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1084         CORE_INSN, __FP_INSN and SIMD_INSN.
1085
1086 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1087
1088         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1089         (aarch64_opcode_table): Update uses accordingly.
1090
1091 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1092         Kwok Cheung Yeung  <kcy@codesourcery.com>
1093
1094         opcodes/
1095         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1096         'e_cmplwi' to 'e_cmpli' instead.
1097         (OPVUPRT, OPVUPRT_MASK): Define.
1098         (powerpc_opcodes): Add E200Z4 insns.
1099         (vle_opcodes): Add context save/restore insns.
1100
1101 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1102
1103         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1104         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1105         "j".
1106
1107 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1108
1109         * arc-nps400-tbl.h: Change block comments to GNU format.
1110         * arc-dis.c: Add new globals addrtypenames,
1111         addrtypenames_max, and addtypeunknown.
1112         (get_addrtype): New function.
1113         (print_insn_arc): Print colons and address types when
1114         required.
1115         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1116         define insert and extract functions for all address types.
1117         (arc_operands): Add operands for colon and all address
1118         types.
1119         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1120         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1121         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1122         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1123         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1124         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1125
1126 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1127
1128         * configure: Regenerated.
1129
1130 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1131
1132         * arc-dis.c (skipclass): New structure.
1133         (decodelist): New variable.
1134         (is_compatible_p): New function.
1135         (new_element): Likewise.
1136         (skip_class_p): Likewise.
1137         (find_format_from_table): Use skip_class_p function.
1138         (find_format): Decode first the extension instructions.
1139         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1140         e_flags.
1141         (parse_option): New function.
1142         (parse_disassembler_options): Likewise.
1143         (print_arc_disassembler_options): Likewise.
1144         (print_insn_arc): Use parse_disassembler_options function.  Proper
1145         select ARCv2 cpu variant.
1146         * disassemble.c (disassembler_usage): Add ARC disassembler
1147         options.
1148
1149 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1150
1151         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1152         annotation from the "nal" entry and reorder it beyond "bltzal".
1153
1154 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1155
1156         * sparc-opc.c (ldtxa): New macro.
1157         (sparc_opcodes): Use the macro defined above to add entries for
1158         the LDTXA instructions.
1159         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1160         instruction.
1161
1162 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1163
1164         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1165         and "jmpc".
1166
1167 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1168
1169         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1170         (movzb): Adjust to cover all permitted suffixes.
1171         (movzw): New.
1172         * i386-tbl.h: Re-generate.
1173
1174 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1175
1176         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1177         (lgdt): Remove Tbyte from non-64-bit variant.
1178         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1179         xsaves64, xsavec64): Remove Disp16.
1180         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1181         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1182         64-bit variants.
1183         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1184         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1185         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1186         64-bit variants.
1187         * i386-tbl.h: Re-generate.
1188
1189 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1190
1191         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1192         * i386-tbl.h: Re-generate.
1193
1194 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1195
1196         * arm-dis.c (print_insn): Fix typo in comment.
1197
1198 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1199
1200         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1201         range of ldst_elemlist operands.
1202         (print_register_list): Use PRIi64 to print the index.
1203         (aarch64_print_operand): Likewise.
1204
1205 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1206
1207         * mcore-opc.h: Remove sentinal.
1208         * mcore-dis.c (print_insn_mcore): Adjust.
1209
1210 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1211
1212         * arc-opc.c: Correct description of availability of NPS400
1213         features.
1214
1215 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1216
1217         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1218         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1219         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1220         xor3>: New mnemonics.
1221         <setb>: Change to a VX form instruction.
1222         (insert_sh6): Add support for rldixor.
1223         (extract_sh6): Likewise.
1224
1225 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1226
1227         * arc-ext.h: Wrap in extern C.
1228
1229 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1230
1231         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1232         Use same method for determining instruction length on ARC700 and
1233         NPS-400.
1234         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1235         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1236         with the NPS400 subclass.
1237         * arc-opc.c: Likewise.
1238
1239 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1240
1241         * sparc-opc.c (rdasr): New macro.
1242         (wrasr): Likewise.
1243         (rdpr): Likewise.
1244         (wrpr): Likewise.
1245         (rdhpr): Likewise.
1246         (wrhpr): Likewise.
1247         (sparc_opcodes): Use the macros above to fix and expand the
1248         definition of read/write instructions from/to
1249         asr/privileged/hyperprivileged instructions.
1250         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1251         %hva_mask_nz.  Prefer softint_set and softint_clear over
1252         set_softint and clear_softint.
1253         (print_insn_sparc): Support %ver in Rd.
1254
1255 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1256
1257         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1258         architecture according to the hardware capabilities they require.
1259
1260 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1261
1262         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1263         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1264         bfd_mach_sparc_v9{c,d,e,v,m}.
1265         * sparc-opc.c (MASK_V9C): Define.
1266         (MASK_V9D): Likewise.
1267         (MASK_V9E): Likewise.
1268         (MASK_V9V): Likewise.
1269         (MASK_V9M): Likewise.
1270         (v6): Add MASK_V9{C,D,E,V,M}.
1271         (v6notlet): Likewise.
1272         (v7): Likewise.
1273         (v8): Likewise.
1274         (v9): Likewise.
1275         (v9andleon): Likewise.
1276         (v9a): Likewise.
1277         (v9b): Likewise.
1278         (v9c): Define.
1279         (v9d): Likewise.
1280         (v9e): Likewise.
1281         (v9v): Likewise.
1282         (v9m): Likewise.
1283         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1284
1285 2016-06-15  Nick Clifton  <nickc@redhat.com>
1286
1287         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1288         constants to match expected behaviour.
1289         (nds32_parse_opcode): Likewise.  Also for whitespace.
1290
1291 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1292
1293         * arc-opc.c (extract_rhv1): Extract value from insn.
1294
1295 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1296
1297         * arc-nps400-tbl.h: Add ldbit instruction.
1298         * arc-opc.c: Add flag classes required for ldbit.
1299
1300 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1301
1302         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1303         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1304         support the above instructions.
1305
1306 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1307
1308         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1309         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1310         csma, cbba, zncv, and hofs.
1311         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1312         support the above instructions.
1313
1314 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1315
1316         * arc-nps400-tbl.h: Add andab and orab instructions.
1317
1318 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1319
1320         * arc-nps400-tbl.h: Add addl-like instructions.
1321
1322 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1323
1324         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1325
1326 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1327
1328         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1329         instructions.
1330
1331 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1332
1333         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1334         variable.
1335         (init_disasm): Handle new command line option "insnlength".
1336         (print_s390_disassembler_options): Mention new option in help
1337         output.
1338         (print_insn_s390): Use the encoded insn length when dumping
1339         unknown instructions.
1340
1341 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1342
1343         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1344          to the address and set as symbol address for LDS/ STS immediate operands.
1345
1346 2016-06-07  Alan Modra  <amodra@gmail.com>
1347
1348         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1349         cpu for "vle" to e500.
1350         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1351         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1352         (PPCNONE): Delete, substitute throughout.
1353         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1354         except for major opcode 4 and 31.
1355         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1356
1357 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1358
1359         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1360         ARM_EXT_RAS in relevant entries.
1361
1362 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1363
1364         PR binutils/20196
1365         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1366         opcodes for E6500.
1367
1368 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1369
1370         PR binutis/18386
1371         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1372         (indir_v_mode): New.
1373         Add comments for '&'.
1374         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1375         (putop): Handle '&'.
1376         (intel_operand_size): Handle indir_v_mode.
1377         (OP_E_register): Likewise.
1378         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1379         64-bit indirect call/jmp for AMD64.
1380         * i386-tbl.h: Regenerated
1381
1382 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1383
1384         * arc-dis.c (struct arc_operand_iterator): New structure.
1385         (find_format_from_table): All the old content from find_format,
1386         with some minor adjustments, and parameter renaming.
1387         (find_format_long_instructions): New function.
1388         (find_format): Rewritten.
1389         (arc_insn_length): Add LSB parameter.
1390         (extract_operand_value): New function.
1391         (operand_iterator_next): New function.
1392         (print_insn_arc): Use new functions to find opcode, and iterator
1393         over operands.
1394         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1395         (extract_nps_3bit_dst_short): New function.
1396         (insert_nps_3bit_src2_short): New function.
1397         (extract_nps_3bit_src2_short): New function.
1398         (insert_nps_bitop1_size): New function.
1399         (extract_nps_bitop1_size): New function.
1400         (insert_nps_bitop2_size): New function.
1401         (extract_nps_bitop2_size): New function.
1402         (insert_nps_bitop_mod4_msb): New function.
1403         (extract_nps_bitop_mod4_msb): New function.
1404         (insert_nps_bitop_mod4_lsb): New function.
1405         (extract_nps_bitop_mod4_lsb): New function.
1406         (insert_nps_bitop_dst_pos3_pos4): New function.
1407         (extract_nps_bitop_dst_pos3_pos4): New function.
1408         (insert_nps_bitop_ins_ext): New function.
1409         (extract_nps_bitop_ins_ext): New function.
1410         (arc_operands): Add new operands.
1411         (arc_long_opcodes): New global array.
1412         (arc_num_long_opcodes): New global.
1413         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1414
1415 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1416
1417         * nds32-asm.h: Add extern "C".
1418         * sh-opc.h: Likewise.
1419
1420 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1421
1422         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1423         0,b,limm to the rflt instruction.
1424
1425 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1426
1427         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1428         constant.
1429
1430 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1431
1432         PR gas/20145
1433         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1434         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1435         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1436         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1437         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1438         * i386-init.h: Regenerated.
1439
1440 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1441
1442         PR gas/20145
1443         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1444         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1445         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1446         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1447         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1448         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1449         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1450         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1451         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1452         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1453         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1454         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1455         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1456         CpuRegMask for AVX512.
1457         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1458         and CpuRegMask.
1459         (set_bitfield_from_cpu_flag_init): New function.
1460         (set_bitfield): Remove const on f.  Call
1461         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1462         * i386-opc.h (CpuRegMMX): New.
1463         (CpuRegXMM): Likewise.
1464         (CpuRegYMM): Likewise.
1465         (CpuRegZMM): Likewise.
1466         (CpuRegMask): Likewise.
1467         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1468         and cpuregmask.
1469         * i386-init.h: Regenerated.
1470         * i386-tbl.h: Likewise.
1471
1472 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1473
1474         PR gas/20154
1475         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1476         (opcode_modifiers): Add AMD64 and Intel64.
1477         (main): Properly verify CpuMax.
1478         * i386-opc.h (CpuAMD64): Removed.
1479         (CpuIntel64): Likewise.
1480         (CpuMax): Set to CpuNo64.
1481         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1482         (AMD64): New.
1483         (Intel64): Likewise.
1484         (i386_opcode_modifier): Add amd64 and intel64.
1485         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1486         on call and jmp.
1487         * i386-init.h: Regenerated.
1488         * i386-tbl.h: Likewise.
1489
1490 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1491
1492         PR gas/20154
1493         * i386-gen.c (main): Fail if CpuMax is incorrect.
1494         * i386-opc.h (CpuMax): Set to CpuIntel64.
1495         * i386-tbl.h: Regenerated.
1496
1497 2016-05-27  Nick Clifton  <nickc@redhat.com>
1498
1499         PR target/20150
1500         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1501         (msp430dis_opcode_unsigned): New function.
1502         (msp430dis_opcode_signed): New function.
1503         (msp430_singleoperand): Use the new opcode reading functions.
1504         Only disassenmble bytes if they were successfully read.
1505         (msp430_doubleoperand): Likewise.
1506         (msp430_branchinstr): Likewise.
1507         (msp430x_callx_instr): Likewise.
1508         (print_insn_msp430): Check that it is safe to read bytes before
1509         attempting disassembly.  Use the new opcode reading functions.
1510
1511 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1512
1513         * ppc-opc.c (CY): New define.  Document it.
1514         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1515
1516 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1517
1518         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1519         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1520         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1521         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1522         CPU_ANY_AVX_FLAGS.
1523         * i386-init.h: Regenerated.
1524
1525 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1526
1527         PR gas/20141
1528         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1529         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1530         * i386-init.h: Regenerated.
1531
1532 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1533
1534         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1535         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1536         * i386-init.h: Regenerated.
1537
1538 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1539
1540         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1541         information.
1542         (print_insn_arc): Set insn_type information.
1543         * arc-opc.c (C_CC): Add F_CLASS_COND.
1544         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1545         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1546         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1547         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1548         (brne, brne_s, jeq_s, jne_s): Likewise.
1549
1550 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1551
1552         * arc-tbl.h (neg): New instruction variant.
1553
1554 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1555
1556         * arc-dis.c (find_format, find_format, get_auxreg)
1557         (print_insn_arc): Changed.
1558         * arc-ext.h (INSERT_XOP): Likewise.
1559
1560 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1561
1562         * tic54x-dis.c (sprint_mmr): Adjust.
1563         * tic54x-opc.c: Likewise.
1564
1565 2016-05-19  Alan Modra  <amodra@gmail.com>
1566
1567         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1568
1569 2016-05-19  Alan Modra  <amodra@gmail.com>
1570
1571         * ppc-opc.c: Formatting.
1572         (NSISIGNOPT): Define.
1573         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1574
1575 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1576
1577         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1578         replacing references to `micromips_ase' throughout.
1579         (_print_insn_mips): Don't use file-level microMIPS annotation to
1580         determine the disassembly mode with the symbol table.
1581
1582 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1583
1584         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1585
1586 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1587
1588         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1589         mips64r6.
1590         * mips-opc.c (D34): New macro.
1591         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1592
1593 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1594
1595         * i386-dis.c (prefix_table): Add RDPID instruction.
1596         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1597         (cpu_flags): Add RDPID bitfield.
1598         * i386-opc.h (enum): Add RDPID element.
1599         (i386_cpu_flags): Add RDPID field.
1600         * i386-opc.tbl: Add RDPID instruction.
1601         * i386-init.h: Regenerate.
1602         * i386-tbl.h: Regenerate.
1603
1604 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1605
1606         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1607         branch type of a symbol.
1608         (print_insn): Likewise.
1609
1610 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1611
1612         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1613         Mainline Security Extensions instructions.
1614         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1615         Extensions instructions.
1616         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1617         instructions.
1618         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1619         special registers.
1620
1621 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1622
1623         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1624
1625 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1626
1627         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1628         (arcExtMap_genOpcode): Likewise.
1629         * arc-opc.c (arg_32bit_rc): Define new variable.
1630         (arg_32bit_u6): Likewise.
1631         (arg_32bit_limm): Likewise.
1632
1633 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1634
1635         * aarch64-gen.c (VERIFIER): Define.
1636         * aarch64-opc.c (VERIFIER): Define.
1637         (verify_ldpsw): Use static linkage.
1638         * aarch64-opc.h (verify_ldpsw): Remove.
1639         * aarch64-tbl.h: Use VERIFIER for verifiers.
1640
1641 2016-04-28  Nick Clifton  <nickc@redhat.com>
1642
1643         PR target/19722
1644         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1645         * aarch64-opc.c (verify_ldpsw): New function.
1646         * aarch64-opc.h (verify_ldpsw): New prototype.
1647         * aarch64-tbl.h: Add initialiser for verifier field.
1648         (LDPSW): Set verifier to verify_ldpsw.
1649
1650 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1651
1652         PR binutils/19983
1653         PR binutils/19984
1654         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1655         smaller than address size.
1656
1657 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1658
1659         * alpha-dis.c: Regenerate.
1660         * crx-dis.c: Likewise.
1661         * disassemble.c: Likewise.
1662         * epiphany-opc.c: Likewise.
1663         * fr30-opc.c: Likewise.
1664         * frv-opc.c: Likewise.
1665         * ip2k-opc.c: Likewise.
1666         * iq2000-opc.c: Likewise.
1667         * lm32-opc.c: Likewise.
1668         * lm32-opinst.c: Likewise.
1669         * m32c-opc.c: Likewise.
1670         * m32r-opc.c: Likewise.
1671         * m32r-opinst.c: Likewise.
1672         * mep-opc.c: Likewise.
1673         * mt-opc.c: Likewise.
1674         * or1k-opc.c: Likewise.
1675         * or1k-opinst.c: Likewise.
1676         * tic80-opc.c: Likewise.
1677         * xc16x-opc.c: Likewise.
1678         * xstormy16-opc.c: Likewise.
1679
1680 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1681
1682         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1683         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1684         calcsd, and calcxd instructions.
1685         * arc-opc.c (insert_nps_bitop_size): Delete.
1686         (extract_nps_bitop_size): Delete.
1687         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1688         (extract_nps_qcmp_m3): Define.
1689         (extract_nps_qcmp_m2): Define.
1690         (extract_nps_qcmp_m1): Define.
1691         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1692         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1693         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1694         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1695         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1696         NPS_QCMP_M3.
1697
1698 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1699
1700         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1701
1702 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1703
1704         * Makefile.in: Regenerated with automake 1.11.6.
1705         * aclocal.m4: Likewise.
1706
1707 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1708
1709         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1710         instructions.
1711         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1712         (extract_nps_cmem_uimm16): New function.
1713         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1714
1715 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1716
1717         * arc-dis.c (arc_insn_length): New function.
1718         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1719         (find_format): Change insnLen parameter to unsigned.
1720
1721 2016-04-13  Nick Clifton  <nickc@redhat.com>
1722
1723         PR target/19937
1724         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1725         the LD.B and LD.BU instructions.
1726
1727 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1728
1729         * arc-dis.c (find_format): Check for extension flags.
1730         (print_flags): New function.
1731         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1732         .extAuxRegister.
1733         * arc-ext.c (arcExtMap_coreRegName): Use
1734         LAST_EXTENSION_CORE_REGISTER.
1735         (arcExtMap_coreReadWrite): Likewise.
1736         (dump_ARC_extmap): Update printing.
1737         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1738         (arc_aux_regs): Add cpu field.
1739         * arc-regs.h: Add cpu field, lower case name aux registers.
1740
1741 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1742
1743         * arc-tbl.h: Add rtsc, sleep with no arguments.
1744
1745 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1746
1747         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1748         Initialize.
1749         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1750         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1751         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1752         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1753         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1754         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1755         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1756         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1757         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1758         (arc_opcode arc_opcodes): Null terminate the array.
1759         (arc_num_opcodes): Remove.
1760         * arc-ext.h (INSERT_XOP): Define.
1761         (extInstruction_t): Likewise.
1762         (arcExtMap_instName): Delete.
1763         (arcExtMap_insn): New function.
1764         (arcExtMap_genOpcode): Likewise.
1765         * arc-ext.c (ExtInstruction): Remove.
1766         (create_map): Zero initialize instruction fields.
1767         (arcExtMap_instName): Remove.
1768         (arcExtMap_insn): New function.
1769         (dump_ARC_extmap): More info while debuging.
1770         (arcExtMap_genOpcode): New function.
1771         * arc-dis.c (find_format): New function.
1772         (print_insn_arc): Use find_format.
1773         (arc_get_disassembler): Enable dump_ARC_extmap only when
1774         debugging.
1775
1776 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1777
1778         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1779         instruction bits out.
1780
1781 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1782
1783         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1784         * arc-opc.c (arc_flag_operands): Add new flags.
1785         (arc_flag_classes): Add new classes.
1786
1787 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1788
1789         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1790
1791 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1792
1793         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1794         encode1, rflt, crc16, and crc32 instructions.
1795         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1796         (arc_flag_classes): Add C_NPS_R.
1797         (insert_nps_bitop_size_2b): New function.
1798         (extract_nps_bitop_size_2b): Likewise.
1799         (insert_nps_bitop_uimm8): Likewise.
1800         (extract_nps_bitop_uimm8): Likewise.
1801         (arc_operands): Add new operand entries.
1802
1803 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1804
1805         * arc-regs.h: Add a new subclass field.  Add double assist
1806         accumulator register values.
1807         * arc-tbl.h: Use DPA subclass to mark the double assist
1808         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1809         * arc-opc.c (RSP): Define instead of SP.
1810         (arc_aux_regs): Add the subclass field.
1811
1812 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1813
1814         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1815
1816 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1817
1818         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1819         NPS_R_SRC1.
1820
1821 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1822
1823         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1824         issues.  No functional changes.
1825
1826 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1827
1828         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1829         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1830         (RTT): Remove duplicate.
1831         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1832         (PCT_CONFIG*): Remove.
1833         (D1L, D1H, D2H, D2L): Define.
1834
1835 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1836
1837         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1838
1839 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1840
1841         * arc-tbl.h (invld07): Remove.
1842         * arc-ext-tbl.h: New file.
1843         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1844         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1845
1846 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1847
1848         Fix -Wstack-usage warnings.
1849         * aarch64-dis.c (print_operands): Substitute size.
1850         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1851
1852 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1853
1854         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1855         to get a proper diagnostic when an invalid ASR register is used.
1856
1857 2016-03-22  Nick Clifton  <nickc@redhat.com>
1858
1859         * configure: Regenerate.
1860
1861 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1862
1863         * arc-nps400-tbl.h: New file.
1864         * arc-opc.c: Add top level comment.
1865         (insert_nps_3bit_dst): New function.
1866         (extract_nps_3bit_dst): New function.
1867         (insert_nps_3bit_src2): New function.
1868         (extract_nps_3bit_src2): New function.
1869         (insert_nps_bitop_size): New function.
1870         (extract_nps_bitop_size): New function.
1871         (arc_flag_operands): Add nps400 entries.
1872         (arc_flag_classes): Add nps400 entries.
1873         (arc_operands): Add nps400 entries.
1874         (arc_opcodes): Add nps400 include.
1875
1876 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1877
1878         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1879         the new class enum values.
1880
1881 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1882
1883         * arc-dis.c (print_insn_arc): Handle nps400.
1884
1885 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1886
1887         * arc-opc.c (BASE): Delete.
1888
1889 2016-03-18  Nick Clifton  <nickc@redhat.com>
1890
1891         PR target/19721
1892         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1893         of MOV insn that aliases an ORR insn.
1894
1895 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1896
1897         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1898
1899 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1900
1901         * mcore-opc.h: Add const qualifiers.
1902         * microblaze-opc.h (struct op_code_struct): Likewise.
1903         * sh-opc.h: Likewise.
1904         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1905         (tic4x_print_op): Likewise.
1906
1907 2016-03-02  Alan Modra  <amodra@gmail.com>
1908
1909         * or1k-desc.h: Regenerate.
1910         * fr30-ibld.c: Regenerate.
1911         * rl78-decode.c: Regenerate.
1912
1913 2016-03-01  Nick Clifton  <nickc@redhat.com>
1914
1915         PR target/19747
1916         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1917
1918 2016-02-24  Renlin Li  <renlin.li@arm.com>
1919
1920         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1921         (print_insn_coprocessor): Support fp16 instructions.
1922
1923 2016-02-24  Renlin Li  <renlin.li@arm.com>
1924
1925         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1926         vminnm, vrint(mpna).
1927
1928 2016-02-24  Renlin Li  <renlin.li@arm.com>
1929
1930         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1931         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1932
1933 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1934
1935         * i386-dis.c (print_insn): Parenthesize expression to prevent
1936         truncated addresses.
1937         (OP_J): Likewise.
1938
1939 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1940             Janek van Oirschot  <jvanoirs@synopsys.com>
1941
1942         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1943         variable.
1944
1945 2016-02-04  Nick Clifton  <nickc@redhat.com>
1946
1947         PR target/19561
1948         * msp430-dis.c (print_insn_msp430): Add a special case for
1949         decoding an RRC instruction with the ZC bit set in the extension
1950         word.
1951
1952 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1953
1954         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1955         * epiphany-ibld.c: Regenerate.
1956         * fr30-ibld.c: Regenerate.
1957         * frv-ibld.c: Regenerate.
1958         * ip2k-ibld.c: Regenerate.
1959         * iq2000-ibld.c: Regenerate.
1960         * lm32-ibld.c: Regenerate.
1961         * m32c-ibld.c: Regenerate.
1962         * m32r-ibld.c: Regenerate.
1963         * mep-ibld.c: Regenerate.
1964         * mt-ibld.c: Regenerate.
1965         * or1k-ibld.c: Regenerate.
1966         * xc16x-ibld.c: Regenerate.
1967         * xstormy16-ibld.c: Regenerate.
1968
1969 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1970
1971         * epiphany-dis.c: Regenerated from latest cpu files.
1972
1973 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1974
1975         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1976         test bit.
1977
1978 2016-01-25  Renlin Li  <renlin.li@arm.com>
1979
1980         * arm-dis.c (mapping_symbol_for_insn): New function.
1981         (find_ifthen_state): Call mapping_symbol_for_insn().
1982
1983 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1984
1985         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1986         of MSR UAO immediate operand.
1987
1988 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1989
1990         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1991         instruction support.
1992
1993 2016-01-17  Alan Modra  <amodra@gmail.com>
1994
1995         * configure: Regenerate.
1996
1997 2016-01-14  Nick Clifton  <nickc@redhat.com>
1998
1999         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2000         instructions that can support stack pointer operations.
2001         * rl78-decode.c: Regenerate.
2002         * rl78-dis.c: Fix display of stack pointer in MOVW based
2003         instructions.
2004
2005 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
2006
2007         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2008         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
2009         erxtatus_el1 and erxaddr_el1.
2010
2011 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
2012
2013         * arm-dis.c (arm_opcodes): Add "esb".
2014         (thumb_opcodes): Likewise.
2015
2016 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
2017
2018         * ppc-opc.c <xscmpnedp>: Delete.
2019         <xvcmpnedp>: Likewise.
2020         <xvcmpnedp.>: Likewise.
2021         <xvcmpnesp>: Likewise.
2022         <xvcmpnesp.>: Likewise.
2023
2024 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
2025
2026         PR gas/13050
2027         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2028         addition to ISA_A.
2029
2030 2016-01-01  Alan Modra  <amodra@gmail.com>
2031
2032         Update year range in copyright notice of all files.
2033
2034 For older changes see ChangeLog-2015
2035 \f
2036 Copyright (C) 2016 Free Software Foundation, Inc.
2037
2038 Copying and distribution of this file, with or without modification,
2039 are permitted in any medium without royalty provided the copyright
2040 notice and this notice are preserved.
2041
2042 Local Variables:
2043 mode: change-log
2044 left-margin: 8
2045 fill-column: 74
2046 version-control: never
2047 End: