opcodes/ChangeLog

   1 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
   4         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
   5         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
   6         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
   7         * i386-tbl.h: Regenerated.
   8
   9 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
  12         meaningless.
  13         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
  14         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
  15         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
  16         * i386-tbl.h: Re-generate.
  17
  18 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  19
  20         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
  21         AVX512_4VNNIW insns.
  22         * i386-tbl.h: Re-generate.
  23
  24 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  25
  26         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
  27         meaningless.
  28         * i386-tbl.h: Re-generate.
  29
  30 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
  33         meaningless.
  34         * i386-tbl.h: Re-generate.
  35
  36 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
  39         meaningless.
  40         * i386-tbl.h: Re-generate.
  41
  42 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
  45         meaningless.
  46         * i386-tbl.h: Re-generate.
  47
  48 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
  51         meaningless.
  52         * i386-tbl.h: Re-generate.
  53
  54 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
  57         * i386-tbl.h: Re-generate.
  58
  59 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
  62         * i386-tbl.h: Re-generate.
  63
  64 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
  67         meaningless.
  68         * i386-tbl.h: Re-generate.
  69
  70 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  71
  72         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
  73         meaningless.
  74         * i386-tbl.h: Re-generate.
  75
  76 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  77
  78         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
  79         * i386-tbl.h: Re-generate.
  80
  81 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  82
  83         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
  84         * i386-tbl.h: Re-generate.
  85
  86 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  87
  88         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
  89         * i386-tbl.h: Re-generate.
  90
  91 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
  94         meaningless.
  95         * i386-tbl.h: Re-generate.
  96
  97 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 100         meaningless.
 101         * i386-tbl.h: Re-generate.
 102
 103 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 104
 105         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 106         meaningless.
 107         * i386-tbl.h: Re-generate.
 108
 109 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 110
 111         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 112         * i386-tbl.h: Re-generate.
 113
 114 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 115
 116         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 117         * i386-tbl.h: Re-generate.
 118
 119 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 120
 121         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 122         * i386-tbl.h: Re-generate.
 123
 124 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 125
 126         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 127         (vpbroadcastw, rdpid): Drop NoRex64.
 128         * i386-tbl.h: Re-generate.
 129
 130 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 133         store templates, adding D.
 134         * i386-tbl.h: Re-generate.
 135
 136 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 137
 138         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 139         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 140         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 141         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 142         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 143         Fold load and store templates where possible, adding D. Drop
 144         IgnoreSize where it was pointlessly present. Drop redundant
 145         *word.
 146         * i386-tbl.h: Re-generate.
 147
 148 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 151         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 152         (intel_operand_size): Handle v_bndmk_mode.
 153         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 154
 155 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 156
 157         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 158
 159 2018-08-31  Kito Cheng  <kito@andestech.com>
 160
 161         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 162         compressed floating point instructions.
 163
 164 2018-08-30  Kito Cheng  <kito@andestech.com>
 165
 166         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 167         riscv_opcode.xlen_requirement.
 168         * riscv-opc.c (riscv_opcodes): Update for struct change.
 169
 170 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 171
 172         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 173         psr (PWRPSR) instruction.
 174
 175 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 176
 177         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 178
 179 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 180
 181         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 182
 183 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 184
 185         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 186         loongson3a as an alias of gs464 for compatibility.
 187         * mips-opc.c (mips_opcodes): Change Comments.
 188
 189 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 190
 191         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 192         option.
 193         (print_mips_disassembler_options): Document -M loongson-ext.
 194         * mips-opc.c (LEXT2): New macro.
 195         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 196
 197 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 198
 199          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 200          descriptors.
 201          (parse_mips_ase_option): Handle -M loongson-ext option.
 202          (print_mips_disassembler_options): Document -M loongson-ext.
 203          * mips-opc.c (IL3A): Delete.
 204          * mips-opc.c (LEXT): New macro.
 205          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 206          instructions.
 207
 208 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 209
 210         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 211         descriptors.
 212         (parse_mips_ase_option): Handle -M loongson-cam option.
 213         (print_mips_disassembler_options): Document -M loongson-cam.
 214         * mips-opc.c (LCAM): New macro.
 215         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 216         instructions.
 217
 218 2018-08-21  Alan Modra  <amodra@gmail.com>
 219
 220         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 221         (skip_optional_operands): Count optional operands, and update
 222         ppc_optional_operand_value call.
 223         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 224         (extract_vlensi): Likewise.
 225         (extract_fxm): Return default value for missing optional operand.
 226         (extract_ls, extract_raq, extract_tbr): Likewise.
 227         (insert_sxl, extract_sxl): New functions.
 228         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 229         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 230         flag and extra entry.
 231         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 232         extract_sxl.
 233
 234 2018-08-20  Alan Modra  <amodra@gmail.com>
 235
 236         * sh-opc.h (MASK): Simplify.
 237
 238 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 239
 240         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 241         BM_RESERVED0 or BM_RESERVED1
 242         (bm_rel_decode, bm_n_bytes): Ditto.
 243
 244 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 245
 246         * s12z.h: Delete.
 247
 248 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 249
 250         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 251         address with the addr32 prefix and without base nor index
 252         registers.
 253
 254 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 255
 256         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 257         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 258         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 259         (cpu_flags): Add CpuCMOV and CpuFXSR.
 260         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 261         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 262         * i386-init.h: Regenerated.
 263         * i386-tbl.h: Likewise.
 264
 265 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 266
 267         * arc-regs.h: Update auxiliary registers.
 268
 269 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 272         (RegIP, RegIZ): Define.
 273         * i386-reg.tbl: Adjust comments.
 274         (rip): Use Qword instead of BaseIndex. Use RegIP.
 275         (eip): Use Dword instead of BaseIndex. Use RegIP.
 276         (riz): Add Qword. Use RegIZ.
 277         (eiz): Add Dword. Use RegIZ.
 278         * i386-tbl.h: Re-generate.
 279
 280 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 283         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 284         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 285         * i386-tbl.h: Re-generate.
 286
 287 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 288
 289         * i386-gen.c (operand_types): Remove Mem field.
 290         * i386-opc.h (union i386_operand_type): Remove mem field.
 291         * i386-init.h, i386-tbl.h: Re-generate.
 292
 293 2018-08-01  Alan Modra  <amodra@gmail.com>
 294
 295         * po/POTFILES.in: Regenerate.
 296
 297 2018-07-31  Nick Clifton  <nickc@redhat.com>
 298
 299         * po/sv.po: Updated Swedish translation.
 300
 301 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 302
 303         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 304         * i386-init.h, i386-tbl.h: Re-generate.
 305
 306 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-opc.h (ZEROING_MASKING) Rename to ...
 309         (DYNAMIC_MASKING): ... this. Adjust comment.
 310         * i386-opc.tbl (MaskingMorZ): Define.
 311         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 312         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 313         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 314         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 315         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 316         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 317         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 318         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 319         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 320
 321 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-opc.tbl: Use element rather than vector size for AVX512*
 324         scatter/gather insns.
 325         * i386-tbl.h: Re-generate.
 326
 327 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 328
 329         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 330         (cpu_flags): Drop CpuVREX.
 331         * i386-opc.h (CpuVREX): Delete.
 332         (union i386_cpu_flags): Remove cpuvrex.
 333         * i386-init.h, i386-tbl.h: Re-generate.
 334
 335 2018-07-30  Jim Wilson  <jimw@sifive.com>
 336
 337         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 338         fields.
 339         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 340
 341 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 342
 343         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 344         * Makefile.in: Regenerated.
 345         * configure.ac: Add C-SKY.
 346         * configure: Regenerated.
 347         * csky-dis.c: New file.
 348         * csky-opc.h: New file.
 349         * disassemble.c (ARCH_csky): Define.
 350         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 351         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 352
 353 2018-07-27  Alan Modra  <amodra@gmail.com>
 354
 355         * ppc-opc.c (insert_sprbat): Correct function parameter and
 356         return type.
 357         (extract_sprbat): Likewise, variable too.
 358
 359 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 360             Alan Modra  <amodra@gmail.com>
 361
 362         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 363         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 364         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 365         support disjointed BAT.
 366         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 367         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 368         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 369
 370 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 371             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 372
 373         * i386-gen.c (adjust_broadcast_modifier): New function.
 374         (process_i386_opcode_modifier): Add an argument for operands.
 375         Adjust the Broadcast value based on operands.
 376         (output_i386_opcode): Pass operand_types to
 377         process_i386_opcode_modifier.
 378         (process_i386_opcodes): Pass NULL as operands to
 379         process_i386_opcode_modifier.
 380         * i386-opc.h (BYTE_BROADCAST): New.
 381         (WORD_BROADCAST): Likewise.
 382         (DWORD_BROADCAST): Likewise.
 383         (QWORD_BROADCAST): Likewise.
 384         (i386_opcode_modifier): Expand broadcast to 3 bits.
 385         * i386-tbl.h: Regenerated.
 386
 387 2018-07-24  Alan Modra  <amodra@gmail.com>
 388
 389         PR 23430
 390         * or1k-desc.h: Regenerate.
 391
 392 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 395         vcvtusi2ss, and vcvtusi2sd.
 396         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 397         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 398         * i386-tbl.h: Re-generate.
 399
 400 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 401
 402         * arc-opc.c (extract_w6): Fix extending the sign.
 403
 404 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 405
 406         * arc-tbl.h (vewt): Allow it for ARC EM family.
 407
 408 2018-07-23  Alan Modra  <amodra@gmail.com>
 409
 410         PR 23419
 411         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 412         opcode variants for mtspr/mfspr encodings.
 413
 414 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 415             Maciej W. Rozycki  <macro@mips.com>
 416
 417         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 418         loongson3a descriptors.
 419         (parse_mips_ase_option): Handle -M loongson-mmi option.
 420         (print_mips_disassembler_options): Document -M loongson-mmi.
 421         * mips-opc.c (LMMI): New macro.
 422         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 423         instructions.
 424
 425 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 426
 427         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 428         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 429         IgnoreSize and [XYZ]MMword where applicable.
 430         * i386-tbl.h: Re-generate.
 431
 432 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 433
 434         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 435         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 436         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 437         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 438         * i386-tbl.h: Re-generate.
 439
 440 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 441
 442         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 443         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 444         VPCLMULQDQ templates into their respective AVX512VL counterparts
 445         where possible, using Disp8ShiftVL and CheckRegSize instead of
 446         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 447         * i386-tbl.h: Re-generate.
 448
 449 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 450
 451         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 452         AVX512VL counterparts where possible, using Disp8ShiftVL and
 453         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 454         IgnoreSize) as appropriate.
 455         * i386-tbl.h: Re-generate.
 456
 457 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 458
 459         * i386-opc.tbl: Fold AVX512BW templates into their respective
 460         AVX512VL counterparts where possible, using Disp8ShiftVL and
 461         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 462         IgnoreSize) as appropriate.
 463         * i386-tbl.h: Re-generate.
 464
 465 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 466
 467         * i386-opc.tbl: Fold AVX512CD templates into their respective
 468         AVX512VL counterparts where possible, using Disp8ShiftVL and
 469         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 470         IgnoreSize) as appropriate.
 471         * i386-tbl.h: Re-generate.
 472
 473 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 474
 475         * i386-opc.h (DISP8_SHIFT_VL): New.
 476         * i386-opc.tbl (Disp8ShiftVL):  Define.
 477         (various): Fold AVX512VL templates into their respective
 478         AVX512F counterparts where possible, using Disp8ShiftVL and
 479         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 480         IgnoreSize) as appropriate.
 481         * i386-tbl.h: Re-generate.
 482
 483 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 484
 485         * Makefile.am: Change dependencies and rule for
 486         $(srcdir)/i386-init.h.
 487         * Makefile.in: Re-generate.
 488         * i386-gen.c (process_i386_opcodes): New local variable
 489         "marker". Drop opening of input file. Recognize marker and line
 490         number directives.
 491         * i386-opc.tbl (OPCODE_I386_H): Define.
 492         (i386-opc.h): Include it.
 493         (None): Undefine.
 494
 495 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 496
 497         PR gas/23418
 498         * i386-opc.h (Byte): Update comments.
 499         (Word): Likewise.
 500         (Dword): Likewise.
 501         (Fword): Likewise.
 502         (Qword): Likewise.
 503         (Tbyte): Likewise.
 504         (Xmmword): Likewise.
 505         (Ymmword): Likewise.
 506         (Zmmword): Likewise.
 507         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 508         vcvttps2uqq.
 509         * i386-tbl.h: Regenerated.
 510
 511 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 512
 513         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 514         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 515         * aarch64-asm-2.c: Regenerate.
 516         * aarch64-dis-2.c: Regenerate.
 517         * aarch64-opc-2.c: Regenerate.
 518
 519 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 520
 521         PR binutils/23192
 522         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 523         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 524         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 525         sqdmulh, sqrdmulh): Use Em16.
 526
 527 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 528
 529         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 530         csdb together with them.
 531         (thumb32_opcodes): Likewise.
 532
 533 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 534
 535         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 536         requiring 32-bit registers as operands 2 and 3. Improve
 537         comments.
 538         (mwait, mwaitx): Fold templates. Improve comments.
 539         OPERAND_TYPE_INOUTPORTREG.
 540         * i386-tbl.h: Re-generate.
 541
 542 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 543
 544         * i386-gen.c (operand_type_init): Remove
 545         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 546         OPERAND_TYPE_INOUTPORTREG.
 547         * i386-init.h: Re-generate.
 548
 549 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 552         (wrssq, wrussq): Add Qword.
 553         * i386-tbl.h: Re-generate.
 554
 555 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 556
 557         * i386-opc.h: Rename OTMax to OTNum.
 558         (OTNumOfUints): Adjust calculation.
 559         (OTUnused): Directly alias to OTNum.
 560
 561 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 562
 563         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 564         `reg_xys'.
 565         (lea_reg_xys): Likewise.
 566         (print_insn_loop_primitive): Rename `reg' local variable to
 567         `reg_dxy'.
 568
 569 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 570
 571         PR binutils/23242
 572         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 573
 574 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 575
 576         PR binutils/23369
 577         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 578         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 579
 580 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 581
 582         PR tdep/8282
 583         * mips-dis.c (mips_option_arg_t): New enumeration.
 584         (mips_options): New variable.
 585         (disassembler_options_mips): New function.
 586         (print_mips_disassembler_options): Reimplement in terms of
 587         `disassembler_options_mips'.
 588         * arm-dis.c (disassembler_options_arm): Adapt to using the
 589         `disasm_options_and_args_t' structure.
 590         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 591         * s390-dis.c (disassembler_options_s390): Likewise.
 592
 593 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 594
 595         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 596         expected result.
 597         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 598         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 599         * testsuite/ld-arm/tls-longplt.d: Likewise.
 600
 601 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 602
 603         PR binutils/23192
 604         * aarch64-asm-2.c: Regenerate.
 605         * aarch64-dis-2.c: Likewise.
 606         * aarch64-opc-2.c: Likewise.
 607         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 608         * aarch64-opc.c (operand_general_constraint_met_p,
 609         aarch64_print_operand): Likewise.
 610         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 611         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 612         fmlal2, fmlsl2.
 613         (AARCH64_OPERANDS): Add Em2.
 614
 615 2018-06-26  Nick Clifton  <nickc@redhat.com>
 616
 617         * po/uk.po: Updated Ukranian translation.
 618         * po/de.po: Updated German translation.
 619         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 620
 621 2018-06-26  Nick Clifton  <nickc@redhat.com>
 622
 623         * nfp-dis.c: Fix spelling mistake.
 624
 625 2018-06-24  Nick Clifton  <nickc@redhat.com>
 626
 627         * configure: Regenerate.
 628         * po/opcodes.pot: Regenerate.
 629
 630 2018-06-24  Nick Clifton  <nickc@redhat.com>
 631
 632         2.31 branch created.
 633
 634 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 635
 636         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 637         * aarch64-asm-2.c: Regenerate.
 638         * aarch64-dis-2.c: Likewise.
 639
 640 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 641
 642         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 643         `-M ginv' option description.
 644
 645 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 646
 647         PR gas/23305
 648         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 649         la and lla.
 650
 651 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 652
 653         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 654         * configure.ac: Remove AC_PREREQ.
 655         * Makefile.in: Re-generate.
 656         * aclocal.m4: Re-generate.
 657         * configure: Re-generate.
 658
 659 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 660
 661         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 662         mips64r6 descriptors.
 663         (parse_mips_ase_option): Handle -Mginv option.
 664         (print_mips_disassembler_options): Document -Mginv.
 665         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 666         (GINV): New macro.
 667         (mips_opcodes): Define ginvi and ginvt.
 668
 669 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 670             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 671
 672         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 673         * mips-opc.c (CRC, CRC64): New macros.
 674         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 675         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 676         crc32cd for CRC64.
 677
 678 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 679
 680         PR 20319
 681         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 682         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 683
 684 2018-06-06  Alan Modra  <amodra@gmail.com>
 685
 686         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 687         setjmp.  Move init for some other vars later too.
 688
 689 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 690
 691         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 692         (dis_private): Add new fields for property section tracking.
 693         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 694         (xtensa_instruction_fits): New functions.
 695         (fetch_data): Bump minimal fetch size to 4.
 696         (print_insn_xtensa): Make struct dis_private static.
 697         Load and prepare property table on section change.
 698         Don't disassemble literals. Don't disassemble instructions that
 699         cross property table boundaries.
 700
 701 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 702
 703         * configure: Regenerated.
 704
 705 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 708         * i386-tbl.h: Re-generate.
 709
 710 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 711
 712         * i386-opc.tbl (sldt, str): Add NoRex64.
 713         * i386-tbl.h: Re-generate.
 714
 715 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 716
 717         * i386-opc.tbl (invpcid): Add Oword.
 718         * i386-tbl.h: Re-generate.
 719
 720 2018-06-01  Alan Modra  <amodra@gmail.com>
 721
 722         * sysdep.h (_bfd_error_handler): Don't declare.
 723         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 724         * rl78-decode.opc: Likewise.
 725         * msp430-decode.c: Regenerate.
 726         * rl78-decode.c: Regenerate.
 727
 728 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 729
 730         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 731         * i386-init.h : Regenerated.
 732
 733 2018-05-25  Alan Modra  <amodra@gmail.com>
 734
 735         * Makefile.in: Regenerate.
 736         * po/POTFILES.in: Regenerate.
 737
 738 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 739
 740         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 741         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 742         (insert_bab, extract_bab, insert_btab, extract_btab,
 743         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 744         (BAT, BBA VBA RBS XB6S): Delete macros.
 745         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 746         (BB, BD, RBX, XC6): Update for new macros.
 747         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 748         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 749         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 750         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 751
 752 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 753
 754         * Makefile.am: Add support for s12z architecture.
 755         * configure.ac: Likewise.
 756         * disassemble.c: Likewise.
 757         * disassemble.h: Likewise.
 758         * Makefile.in: Regenerate.
 759         * configure: Regenerate.
 760         * s12z-dis.c: New file.
 761         * s12z.h: New file.
 762
 763 2018-05-18  Alan Modra  <amodra@gmail.com>
 764
 765         * nfp-dis.c: Don't #include libbfd.h.
 766         (init_nfp3200_priv): Use bfd_get_section_contents.
 767         (nit_nfp6000_mecsr_sec): Likewise.
 768
 769 2018-05-17  Nick Clifton  <nickc@redhat.com>
 770
 771         * po/zh_CN.po: Updated simplified Chinese translation.
 772
 773 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 774
 775         PR binutils/23109
 776         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 777         * aarch64-dis-2.c: Regenerate.
 778
 779 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 780
 781         PR binutils/21446
 782         * aarch64-asm.c (opintl.h): Include.
 783         (aarch64_ins_sysreg): Enforce read/write constraints.
 784         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 785         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 786         (F_REG_READ, F_REG_WRITE): New.
 787         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 788         AARCH64_OPND_SYSREG.
 789         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 790         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 791         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 792         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 793         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 794         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 795         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 796         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 797         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 798         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 799         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 800         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 801         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 802         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 803         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 804         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 805         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 806
 807 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 808
 809         PR binutils/21446
 810         * aarch64-dis.c (no_notes: New.
 811         (parse_aarch64_dis_option): Support notes.
 812         (aarch64_decode_insn, print_operands): Likewise.
 813         (print_aarch64_disassembler_options): Document notes.
 814         * aarch64-opc.c (aarch64_print_operand): Support notes.
 815
 816 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 817
 818         PR binutils/21446
 819         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 820         and take error struct.
 821         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 822         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 823         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 824         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 825         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 826         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 827         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 828         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 829         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 830         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 831         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 832         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 833         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 834         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 835         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 836         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 837         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 838         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 839         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 840         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 841         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 842         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 843         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 844         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 845         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 846         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 847         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 848         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 849         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 850         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 851         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 852         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 853         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 854         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 855         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 856         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 857         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 858         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 859         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 860         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 861         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 862         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 863         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 864         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 865         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 866         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 867         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 868         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 869         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 870         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 871         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 872         (determine_disassembling_preference, aarch64_decode_insn,
 873         print_insn_aarch64_word, print_insn_data): Take errors struct.
 874         (print_insn_aarch64): Use errors.
 875         * aarch64-asm-2.c: Regenerate.
 876         * aarch64-dis-2.c: Regenerate.
 877         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 878         boolean in aarch64_insert_operan.
 879         (print_operand_extractor): Likewise.
 880         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 881
 882 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 883
 884         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 885
 886 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 887
 888         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 889
 890 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 891
 892         * cr16-opc.c (cr16_instruction): Comment typo fix.
 893         * hppa-dis.c (print_insn_hppa): Likewise.
 894
 895 2018-05-08  Jim Wilson  <jimw@sifive.com>
 896
 897         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 898         (match_c_slli64, match_srxi_as_c_srxi): New.
 899         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 900         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 901         <c.slli, c.srli, c.srai>: Use match_s_slli.
 902         <c.slli64, c.srli64, c.srai64>: New.
 903
 904 2018-05-08  Alan Modra  <amodra@gmail.com>
 905
 906         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 907         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 908         partition opcode space for index lookup.
 909
 910 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 911
 912         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 913         <insn_length>: ...with this.  Update usage.
 914         Remove duplicate call to *info->memory_error_func.
 915
 916 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 917             H.J. Lu  <hongjiu.lu@intel.com>
 918
 919         * i386-dis.c (Gva): New.
 920         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 921         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 922         (prefix_table): New instructions (see prefix above).
 923         (mod_table): New instructions (see prefix above).
 924         (OP_G): Handle va_mode.
 925         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 926         CPU_MOVDIR64B_FLAGS.
 927         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 928         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 929         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 930         * i386-opc.tbl: Add movidir{i,64b}.
 931         * i386-init.h: Regenerated.
 932         * i386-tbl.h: Likewise.
 933
 934 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 935
 936         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 937         AddrPrefixOpReg.
 938         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 939         (AddrPrefixOpReg): This.
 940         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 941         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 942
 943 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 944
 945         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 946         (vle_num_opcodes): Likewise.
 947         (spe2_num_opcodes): Likewise.
 948         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 949         initialization loop.
 950         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 951         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 952         only once.
 953
 954 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 955
 956         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 957
 958 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 959
 960         Makefile.am: Added nfp-dis.c.
 961         configure.ac: Added bfd_nfp_arch.
 962         disassemble.h: Added print_insn_nfp prototype.
 963         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 964         nfp-dis.c: New, for NFP support.
 965         po/POTFILES.in: Added nfp-dis.c to the list.
 966         Makefile.in: Regenerate.
 967         configure: Regenerate.
 968
 969 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 970
 971         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 972         templates into their base ones.
 973         * i386-tlb.h: Re-generate.
 974
 975 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 976
 977         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 978         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 979         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 980         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 981         * i386-init.h: Re-generate.
 982
 983 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 984
 985         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 986         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 987         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 988         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 989         comment.
 990         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 991         and CpuRegMask.
 992         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 993         CpuRegMask: Delete.
 994         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 995         cpuregzmm, and cpuregmask.
 996         * i386-init.h: Re-generate.
 997         * i386-tbl.h: Re-generate.
 998
 999 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1000
1001         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1002         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1003         * i386-init.h: Re-generate.
1004
1005 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1006
1007         * i386-gen.c (VexImmExt): Delete.
1008         * i386-opc.h (VexImmExt, veximmext): Delete.
1009         * i386-opc.tbl: Drop all VexImmExt uses.
1010         * i386-tlb.h: Re-generate.
1011
1012 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1013
1014         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1015         register-only forms.
1016         * i386-tlb.h: Re-generate.
1017
1018 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1019
1020         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1021
1022 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1023
1024         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1025         PREFIX_0F1C.
1026         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1027         (cpu_flags): Add CpuCLDEMOTE.
1028         * i386-init.h: Regenerate.
1029         * i386-opc.h (enum): Add CpuCLDEMOTE,
1030         (i386_cpu_flags): Add cpucldemote.
1031         * i386-opc.tbl: Add cldemote.
1032         * i386-tbl.h: Regenerate.
1033
1034 2018-04-16  Alan Modra  <amodra@gmail.com>
1035
1036         * Makefile.am: Remove sh5 and sh64 support.
1037         * configure.ac: Likewise.
1038         * disassemble.c: Likewise.
1039         * disassemble.h: Likewise.
1040         * sh-dis.c: Likewise.
1041         * sh64-dis.c: Delete.
1042         * sh64-opc.c: Delete.
1043         * sh64-opc.h: Delete.
1044         * Makefile.in: Regenerate.
1045         * configure: Regenerate.
1046         * po/POTFILES.in: Regenerate.
1047
1048 2018-04-16  Alan Modra  <amodra@gmail.com>
1049
1050         * Makefile.am: Remove w65 support.
1051         * configure.ac: Likewise.
1052         * disassemble.c: Likewise.
1053         * disassemble.h: Likewise.
1054         * w65-dis.c: Delete.
1055         * w65-opc.h: Delete.
1056         * Makefile.in: Regenerate.
1057         * configure: Regenerate.
1058         * po/POTFILES.in: Regenerate.
1059
1060 2018-04-16  Alan Modra  <amodra@gmail.com>
1061
1062         * configure.ac: Remove we32k support.
1063         * configure: Regenerate.
1064
1065 2018-04-16  Alan Modra  <amodra@gmail.com>
1066
1067         * Makefile.am: Remove m88k support.
1068         * configure.ac: Likewise.
1069         * disassemble.c: Likewise.
1070         * disassemble.h: Likewise.
1071         * m88k-dis.c: Delete.
1072         * Makefile.in: Regenerate.
1073         * configure: Regenerate.
1074         * po/POTFILES.in: Regenerate.
1075
1076 2018-04-16  Alan Modra  <amodra@gmail.com>
1077
1078         * Makefile.am: Remove i370 support.
1079         * configure.ac: Likewise.
1080         * disassemble.c: Likewise.
1081         * disassemble.h: Likewise.
1082         * i370-dis.c: Delete.
1083         * i370-opc.c: Delete.
1084         * Makefile.in: Regenerate.
1085         * configure: Regenerate.
1086         * po/POTFILES.in: Regenerate.
1087
1088 2018-04-16  Alan Modra  <amodra@gmail.com>
1089
1090         * Makefile.am: Remove h8500 support.
1091         * configure.ac: Likewise.
1092         * disassemble.c: Likewise.
1093         * disassemble.h: Likewise.
1094         * h8500-dis.c: Delete.
1095         * h8500-opc.h: Delete.
1096         * Makefile.in: Regenerate.
1097         * configure: Regenerate.
1098         * po/POTFILES.in: Regenerate.
1099
1100 2018-04-16  Alan Modra  <amodra@gmail.com>
1101
1102         * configure.ac: Remove tahoe support.
1103         * configure: Regenerate.
1104
1105 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1106
1107         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1108         umwait.
1109         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1110         64-bit mode.
1111         * i386-tbl.h: Regenerated.
1112
1113 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1114
1115         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1116         PREFIX_MOD_1_0FAE_REG_6.
1117         (va_mode): New.
1118         (OP_E_register): Use va_mode.
1119         * i386-dis-evex.h (prefix_table):
1120         New instructions (see prefixes above).
1121         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1122         (cpu_flags): Likewise.
1123         * i386-opc.h (enum): Likewise.
1124         (i386_cpu_flags): Likewise.
1125         * i386-opc.tbl: Add umonitor, umwait, tpause.
1126         * i386-init.h: Regenerate.
1127         * i386-tbl.h: Likewise.
1128
1129 2018-04-11  Alan Modra  <amodra@gmail.com>
1130
1131         * opcodes/i860-dis.c: Delete.
1132         * opcodes/i960-dis.c: Delete.
1133         * Makefile.am: Remove i860 and i960 support.
1134         * configure.ac: Likewise.
1135         * disassemble.c: Likewise.
1136         * disassemble.h: Likewise.
1137         * Makefile.in: Regenerate.
1138         * configure: Regenerate.
1139         * po/POTFILES.in: Regenerate.
1140
1141 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1142
1143         PR binutils/23025
1144         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1145         to 0.
1146         (print_insn): Clear vex instead of vex.evex.
1147
1148 2018-04-04  Nick Clifton  <nickc@redhat.com>
1149
1150         * po/es.po: Updated Spanish translation.
1151
1152 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1153
1154         * i386-gen.c (opcode_modifiers): Delete VecESize.
1155         * i386-opc.h (VecESize): Delete.
1156         (struct i386_opcode_modifier): Delete vecesize.
1157         * i386-opc.tbl: Drop VecESize.
1158         * i386-tlb.h: Re-generate.
1159
1160 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1161
1162         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1163         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1164         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1165         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1166         * i386-tlb.h: Re-generate.
1167
1168 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1169
1170         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1171         Fold AVX512 forms
1172         * i386-tlb.h: Re-generate.
1173
1174 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1175
1176         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1177         (vex_len_table): Drop Y for vcvt*2si.
1178         (putop): Replace plain 'Y' handling by abort().
1179
1180 2018-03-28  Nick Clifton  <nickc@redhat.com>
1181
1182         PR 22988
1183         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1184         instructions with only a base address register.
1185         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1186         handle AARHC64_OPND_SVE_ADDR_R.
1187         (aarch64_print_operand): Likewise.
1188         * aarch64-asm-2.c: Regenerate.
1189         * aarch64_dis-2.c: Regenerate.
1190         * aarch64-opc-2.c: Regenerate.
1191
1192 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1193
1194         * i386-opc.tbl: Drop VecESize from register only insn forms and
1195         memory forms not allowing broadcast.
1196         * i386-tlb.h: Re-generate.
1197
1198 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1199
1200         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1201         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1202         sha256*): Drop Disp<N>.
1203
1204 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1205
1206         * i386-dis.c (EbndS, bnd_swap_mode): New.
1207         (prefix_table): Use EbndS.
1208         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1209         * i386-opc.tbl (bndmov): Move misplaced Load.
1210         * i386-tlb.h: Re-generate.
1211
1212 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1213
1214         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1215         templates allowing memory operands and folded ones for register
1216         only flavors.
1217         * i386-tlb.h: Re-generate.
1218
1219 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1220
1221         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1222         256-bit templates. Drop redundant leftover Disp<N>.
1223         * i386-tlb.h: Re-generate.
1224
1225 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1226
1227         * riscv-opc.c (riscv_insn_types): New.
1228
1229 2018-03-13  Nick Clifton  <nickc@redhat.com>
1230
1231         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1232
1233 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1234
1235         * i386-opc.tbl: Add Optimize to clr.
1236         * i386-tbl.h: Regenerated.
1237
1238 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1239
1240         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1241         * i386-opc.h (OldGcc): Removed.
1242         (i386_opcode_modifier): Remove oldgcc.
1243         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1244         instructions for old (<= 2.8.1) versions of gcc.
1245         * i386-tbl.h: Regenerated.
1246
1247 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1248
1249         * i386-opc.h (EVEXDYN): New.
1250         * i386-opc.tbl: Fold various AVX512VL templates.
1251         * i386-tlb.h: Re-generate.
1252
1253 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1254
1255         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1256         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1257         vpexpandd, vpexpandq): Fold AFX512VF templates.
1258         * i386-tlb.h: Re-generate.
1259
1260 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1261
1262         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1263         Fold 128- and 256-bit VEX-encoded templates.
1264         * i386-tlb.h: Re-generate.
1265
1266 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1267
1268         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1269         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1270         vpexpandd, vpexpandq): Fold AVX512F templates.
1271         * i386-tlb.h: Re-generate.
1272
1273 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1274
1275         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1276         64-bit templates. Drop Disp<N>.
1277         * i386-tlb.h: Re-generate.
1278
1279 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1280
1281         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1282         and 256-bit templates.
1283         * i386-tlb.h: Re-generate.
1284
1285 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1286
1287         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1288         * i386-tlb.h: Re-generate.
1289
1290 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1291
1292         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1293         Drop NoAVX.
1294         * i386-tlb.h: Re-generate.
1295
1296 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1297
1298         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1299         * i386-tlb.h: Re-generate.
1300
1301 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1302
1303         * i386-gen.c (opcode_modifiers): Delete FloatD.
1304         * i386-opc.h (FloatD): Delete.
1305         (struct i386_opcode_modifier): Delete floatd.
1306         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1307         FloatD by D.
1308         * i386-tlb.h: Re-generate.
1309
1310 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1311
1312         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1313
1314 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1315
1316         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1317         * i386-tlb.h: Re-generate.
1318
1319 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1320
1321         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1322         forms.
1323         * i386-tlb.h: Re-generate.
1324
1325 2018-03-07  Alan Modra  <amodra@gmail.com>
1326
1327         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1328         bfd_arch_rs6000.
1329         * disassemble.h (print_insn_rs6000): Delete.
1330         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1331         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1332         (print_insn_rs6000): Delete.
1333
1334 2018-03-03  Alan Modra  <amodra@gmail.com>
1335
1336         * sysdep.h (opcodes_error_handler): Define.
1337         (_bfd_error_handler): Declare.
1338         * Makefile.am: Remove stray #.
1339         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1340         EDIT" comment.
1341         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1342         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1343         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1344         opcodes_error_handler to print errors.  Standardize error messages.
1345         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1346         and include opintl.h.
1347         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1348         * i386-gen.c: Standardize error messages.
1349         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1350         * Makefile.in: Regenerate.
1351         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1352         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1353         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1354         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1355         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1356         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1357         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1358         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1359         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1360         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1361         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1362         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1363         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1364
1365 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1366
1367         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1368         vpsub[bwdq] instructions.
1369         * i386-tbl.h: Regenerated.
1370
1371 2018-03-01  Alan Modra  <amodra@gmail.com>
1372
1373         * configure.ac (ALL_LINGUAS): Sort.
1374         * configure: Regenerate.
1375
1376 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1377
1378         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1379         macro by assignements.
1380
1381 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1382
1383         PR gas/22871
1384         * i386-gen.c (opcode_modifiers): Add Optimize.
1385         * i386-opc.h (Optimize): New enum.
1386         (i386_opcode_modifier): Add optimize.
1387         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1388         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1389         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1390         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1391         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1392         vpxord and vpxorq.
1393         * i386-tbl.h: Regenerated.
1394
1395 2018-02-26  Alan Modra  <amodra@gmail.com>
1396
1397         * crx-dis.c (getregliststring): Allocate a large enough buffer
1398         to silence false positive gcc8 warning.
1399
1400 2018-02-22  Shea Levy <shea@shealevy.com>
1401
1402         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1403
1404 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1405
1406         * i386-opc.tbl: Add {rex},
1407         * i386-tbl.h: Regenerated.
1408
1409 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1410
1411         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1412         (mips16_opcodes): Replace `M' with `m' for "restore".
1413
1414 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1415
1416         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1417
1418 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1419
1420         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1421         variable to `function_index'.
1422
1423 2018-02-13  Nick Clifton  <nickc@redhat.com>
1424
1425         PR 22823
1426         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1427         about truncation of printing.
1428
1429 2018-02-12  Henry Wong <henry@stuffedcow.net>
1430
1431         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1432
1433 2018-02-05  Nick Clifton  <nickc@redhat.com>
1434
1435         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1436
1437 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1438
1439         * i386-dis.c (enum): Add pconfig.
1440         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1441         (cpu_flags): Add CpuPCONFIG.
1442         * i386-opc.h (enum): Add CpuPCONFIG.
1443         (i386_cpu_flags): Add cpupconfig.
1444         * i386-opc.tbl: Add PCONFIG instruction.
1445         * i386-init.h: Regenerate.
1446         * i386-tbl.h: Likewise.
1447
1448 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1449
1450         * i386-dis.c (enum): Add PREFIX_0F09.
1451         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1452         (cpu_flags): Add CpuWBNOINVD.
1453         * i386-opc.h (enum): Add CpuWBNOINVD.
1454         (i386_cpu_flags): Add cpuwbnoinvd.
1455         * i386-opc.tbl: Add WBNOINVD instruction.
1456         * i386-init.h: Regenerate.
1457         * i386-tbl.h: Likewise.
1458
1459 2018-01-17  Jim Wilson  <jimw@sifive.com>
1460
1461         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1462
1463 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1464
1465         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1466         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1467         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1468         (cpu_flags): Add CpuIBT, CpuSHSTK.
1469         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1470         (i386_cpu_flags): Add cpuibt, cpushstk.
1471         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1472         * i386-init.h: Regenerate.
1473         * i386-tbl.h: Likewise.
1474
1475 2018-01-16  Nick Clifton  <nickc@redhat.com>
1476
1477         * po/pt_BR.po: Updated Brazilian Portugese translation.
1478         * po/de.po: Updated German translation.
1479
1480 2018-01-15  Jim Wilson  <jimw@sifive.com>
1481
1482         * riscv-opc.c (match_c_nop): New.
1483         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1484
1485 2018-01-15  Nick Clifton  <nickc@redhat.com>
1486
1487         * po/uk.po: Updated Ukranian translation.
1488
1489 2018-01-13  Nick Clifton  <nickc@redhat.com>
1490
1491         * po/opcodes.pot: Regenerated.
1492
1493 2018-01-13  Nick Clifton  <nickc@redhat.com>
1494
1495         * configure: Regenerate.
1496
1497 2018-01-13  Nick Clifton  <nickc@redhat.com>
1498
1499         2.30 branch created.
1500
1501 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1502
1503         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1504         * i386-tbl.h: Regenerate.
1505
1506 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1507
1508         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1509         * i386-tbl.h: Re-generate.
1510
1511 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1512
1513         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1514         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1515         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1516         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1517         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1518         Disp8MemShift of AVX512VL forms.
1519         * i386-tbl.h: Re-generate.
1520
1521 2018-01-09  Jim Wilson  <jimw@sifive.com>
1522
1523         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1524         then the hi_addr value is zero.
1525
1526 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1527
1528         * arm-dis.c (arm_opcodes): Add csdb.
1529         (thumb32_opcodes): Add csdb.
1530
1531 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1532
1533         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1534         * aarch64-asm-2.c: Regenerate.
1535         * aarch64-dis-2.c: Regenerate.
1536         * aarch64-opc-2.c: Regenerate.
1537
1538 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1539
1540         PR gas/22681
1541         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1542         Remove AVX512 vmovd with 64-bit operands.
1543         * i386-tbl.h: Regenerated.
1544
1545 2018-01-05  Jim Wilson  <jimw@sifive.com>
1546
1547         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1548         jalr.
1549
1550 2018-01-03  Alan Modra  <amodra@gmail.com>
1551
1552         Update year range in copyright notice of all files.
1553
1554 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1555
1556         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1557         and OPERAND_TYPE_REGZMM entries.
1558
1559 For older changes see ChangeLog-2017
1560 \f
1561 Copyright (C) 2018 Free Software Foundation, Inc.
1562
1563 Copying and distribution of this file, with or without modification,
1564 are permitted in any medium without royalty provided the copyright
1565 notice and this notice are preserved.
1566
1567 Local Variables:
1568 mode: change-log
1569 left-margin: 8
1570 fill-column: 74
1571 version-control: never
1572 End: