opcodes/ChangeLog

   1 2018-11-27  Jim Wilson  <jimw@sifive.com>
   2
   3         * riscv-opc.c (ciw): Fix whitespace to align columns.
   4         (ca): New.
   5
   6 2018-11-21  John Darrington  <john@darrington.wattle.id.au>
   7
   8         * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
   9         if the postbyte matches the appropriate pattern.
  10
  11 2018-11-13  Francois H. Theron <francois.theron@netronome.com>
  12
  13         * nfp-dis.c: Fix crc[] disassembly if operands are swapped.
  14
  15 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  16
  17         * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
  18         IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
  19         IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
  20         CIGDVAC and GZVA.
  21         (aarch64_sys_ins_reg_supported_p): New check for above.
  22
  23 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  24
  25         * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
  26         TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
  27         RGSR_EL1 and GCR_EL1.
  28         (aarch64_sys_reg_supported_p): New check for above.
  29         (aarch64_pstatefields): New entry for TCO.
  30         (aarch64_pstatefield_supported_p): New check for above.
  31
  32 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  33
  34         * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
  35         * aarch64-asm.h (ins_addr_simple_2): Declare the above.
  36         * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
  37         * aarch64-dis.h (ext_addr_simple_2): Declare the above.
  38         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
  39         AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
  40         (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
  41         * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
  42         (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
  43         * aarch64-asm-2.c: Regenerated.
  44         * aarch64-dis-2.c: Regenerated.
  45         * aarch64-opc-2.c: Regenerated.
  46
  47 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  48
  49         * aarch64-tbl.h (QL_LDG): New.
  50         (aarch64_opcode_table): Add ldg.
  51         * aarch64-asm-2.c: Regenerated.
  52         * aarch64-dis-2.c: Regenerated.
  53         * aarch64-opc-2.c: Regenerated.
  54
  55 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  56
  57         * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
  58         for AARCH64_OPND_QLF_imm_tag.
  59         (operand_general_constraint_met_p): Add case for
  60         AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
  61         (aarch64_print_operand): Likewise.
  62         * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
  63         (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
  64         for both offset and pre/post indexed versions.
  65         (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
  66         * aarch64-asm-2.c: Regenerated.
  67         * aarch64-dis-2.c: Regenerated.
  68         * aarch64-opc-2.c: Regenerated.
  69
  70 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  71
  72         * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
  73         * aarch64-asm-2.c: Regenerated.
  74         * aarch64-dis-2.c: Regenerated.
  75         * aarch64-opc-2.c: Regenerated.
  76
  77 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  78
  79         * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
  80         (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
  81         * aarch64-opc.c (fields): Add entry for imm4_3.
  82         (operand_general_constraint_met_p): Add cases for
  83         AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
  84         (aarch64_print_operand): Likewise.
  85         * aarch64-tbl.h (QL_ADDG): New.
  86         (aarch64_opcode_table): Add addg, subg, irg and gmi.
  87         (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
  88         * aarch64-asm.c (aarch64_ins_imm): Add case for
  89         operand_need_shift_by_four.
  90         * aarch64-asm-2.c: Regenerated.
  91         * aarch64-dis-2.c: Regenerated.
  92         * aarch64-opc-2.c: Regenerated.
  93
  94 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  95
  96         * aarch64-tbl.h (aarch64_feature_memtag): New.
  97         (MEMTAG, MEMTAG_INSN): New.
  98
  99 2018-11-06  Sudakshina Das  <sudi.das@arm.com>
 100
 101         * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
 102         with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
 103
 104 2018-11-06  Alan Modra  <amodra@gmail.com>
 105
 106         * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
 107         (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
 108         (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
 109         (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
 110         Don't return zero on error, insert mask bits instead.
 111         (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
 112         (insert_sh6, extract_sh6): Delete dead code.
 113         (insert_sprbat, insert_sprg): Use unsigned comparisions.
 114         (powerpc_operands <OIMM>): Set shift count rather than using
 115         PPC_OPSHIFT_INV.
 116         <SE_SDH, SE_SDW>: Likewise.  Don't use insert/extract functions.
 117
 118 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 119
 120         * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
 121         vpbroadcast{d,q} with GPR operand.
 122
 123 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
 126         * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
 127         cases up one level in the hierarchy.
 128
 129 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 130
 131         * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
 132         MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
 133         (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
 134         into MOD_VEX_0F93_P_3_LEN_0.
 135         (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
 136         operand cases up one level in the hierarchy.
 137
 138 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 139
 140         * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
 141         VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
 142         EVEX_W_0F3A22_P_2): Delete.
 143         (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
 144         entries up one level in the hierarchy.
 145         (OP_E_memory): Handle dq_mode when determining Disp8 shift
 146         value.
 147         * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
 148         entries up one level in the hierarchy.
 149         * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
 150         VexWIG for AVX flavors.
 151         * i386-tbl.h: Re-generate.
 152
 153 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 154
 155         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
 156         vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
 157         vcvtusi2ss, kmovd): Drop VexW=1.
 158         * i386-tbl.h: Re-generate.
 159
 160 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 161
 162         * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
 163         EVex512, EVexLIG, EVexDYN): New.
 164         (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
 165         insns): Use Vex128 instead of Vex=3 (aka VexLIG).
 166         (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
 167         of EVex=4 (aka EVexLIG).
 168         * i386-tbl.h: Re-generate.
 169
 170 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 171
 172         * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
 173         (vpmaxub): Re-order attributes on AVX512BW flavor.
 174         * i386-tbl.h: Re-generate.
 175
 176 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 177
 178         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
 179         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
 180         Vex=1 on AVX / AVX2 flavors.
 181         (vpmaxub): Re-order attributes on AVX512BW flavor.
 182         * i386-tbl.h: Re-generate.
 183
 184 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-opc.tbl (VexW0, VexW1): New.
 187         (vphadd*, vphsub*): Use VexW0 on XOP variants.
 188         * i386-tbl.h: Re-generate.
 189
 190 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
 191
 192         * s12z-dis.c (decode_possible_symbol): Add fallback case.
 193         (rel_15_7): Likewise.
 194
 195 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
 196
 197         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
 198         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
 199         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
 200
 201 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
 202
 203         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
 204         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
 205
 206 2018-10-10  Jan Beulich  <jbeulich@suse.com>
 207
 208         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
 209         Size64. Add Size.
 210         * i386-opc.h (Size16, Size32, Size64): Delete.
 211         (Size): New.
 212         (SIZE16, SIZE32, SIZE64): Define.
 213         (struct i386_opcode_modifier): Drop size16, size32, and size64.
 214         Add size.
 215         * i386-opc.tbl (Size16, Size32, Size64): Define.
 216         * i386-tbl.h: Re-generate.
 217
 218 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 219
 220         * aarch64-opc.c (operand_general_constraint_met_p): Add
 221         SSBS in the check for one-bit immediate.
 222         (aarch64_sys_regs): New entry for SSBS.
 223         (aarch64_sys_reg_supported_p): New check for above.
 224         (aarch64_pstatefields): New entry for SSBS.
 225         (aarch64_pstatefield_supported_p): New check for above.
 226
 227 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 228
 229         * aarch64-opc.c (aarch64_sys_regs): New entries for
 230         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
 231         (aarch64_sys_reg_supported_p): New checks for above.
 232
 233 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 234
 235         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
 236         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
 237         with the hint immediate.
 238         * aarch64-opc.c (aarch64_hint_options): New entries for
 239         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
 240         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
 241         while checking for HINT_OPD_F_NOPRINT flag.
 242         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
 243         extract value.
 244         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
 245         (aarch64_opcode_table): Add entry for BTI.
 246         (AARCH64_OPERANDS): Add new description for BTI targets.
 247         * aarch64-asm-2.c: Regenerate.
 248         * aarch64-dis-2.c: Regenerate.
 249         * aarch64-opc-2.c: Regenerate.
 250
 251 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 252
 253         * aarch64-opc.c (aarch64_sys_regs): New entries for
 254         rndr and rndrrs.
 255         (aarch64_sys_reg_supported_p): New check for above.
 256
 257 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 258
 259         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
 260         (aarch64_sys_ins_reg_supported_p): New check for above.
 261
 262 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 263
 264         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
 265         AARCH64_OPND_SYSREG_SR.
 266         * aarch64-opc.c (aarch64_print_operand): Likewise.
 267         (aarch64_sys_regs_sr): Define table.
 268         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
 269         AARCH64_FEATURE_PREDRES.
 270         * aarch64-tbl.h (aarch64_feature_predres): New.
 271         (PREDRES, PREDRES_INSN): New.
 272         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
 273         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
 274         * aarch64-asm-2.c: Regenerate.
 275         * aarch64-dis-2.c: Regenerate.
 276         * aarch64-opc-2.c: Regenerate.
 277
 278 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 279
 280         * aarch64-tbl.h (aarch64_feature_sb): New.
 281         (SB, SB_INSN): New.
 282         (aarch64_opcode_table): Add entry for sb.
 283         * aarch64-asm-2.c: Regenerate.
 284         * aarch64-dis-2.c: Regenerate.
 285         * aarch64-opc-2.c: Regenerate.
 286
 287 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 288
 289         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 290         (aarch64_feature_frintts): New.
 291         (FLAGMANIP, FRINTTS): New.
 292         (aarch64_opcode_table): Add entries for xaflag, axflag
 293         and frint[32,64][x,z] instructions.
 294         * aarch64-asm-2.c: Regenerate.
 295         * aarch64-dis-2.c: Regenerate.
 296         * aarch64-opc-2.c: Regenerate.
 297
 298 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 299
 300         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 301         (ARMV8_5, V8_5_INSN): New.
 302
 303 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 304
 305         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 306
 307 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 308
 309         * i386-dis.c (rm_table): Add enclv.
 310         * i386-opc.tbl: Add enclv.
 311         * i386-tbl.h: Regenerated.
 312
 313 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 314
 315         * arm-dis.c (arm_opcodes): Add sb.
 316         (thumb32_opcodes): Likewise.
 317
 318 2018-10-05  Richard Henderson  <rth@twiddle.net>
 319             Stafford Horne  <shorne@gmail.com>
 320
 321         * or1k-desc.c: Regenerate.
 322         * or1k-desc.h: Regenerate.
 323         * or1k-opc.c: Regenerate.
 324         * or1k-opc.h: Regenerate.
 325         * or1k-opinst.c: Regenerate.
 326
 327 2018-10-05  Richard Henderson  <rth@twiddle.net>
 328
 329         * or1k-asm.c: Regenerated.
 330         * or1k-desc.c: Regenerated.
 331         * or1k-desc.h: Regenerated.
 332         * or1k-dis.c: Regenerated.
 333         * or1k-ibld.c: Regenerated.
 334         * or1k-opc.c: Regenerated.
 335         * or1k-opc.h: Regenerated.
 336         * or1k-opinst.c: Regenerated.
 337
 338 2018-10-05  Richard Henderson  <rth@twiddle.net>
 339
 340         * or1k-asm.c: Regenerate.
 341
 342 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 343
 344         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 345         * aarch64-dis.c (print_operands): Refactor to take notes.
 346         (print_verifier_notes): New.
 347         (print_aarch64_insn): Apply constraint verifier.
 348         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 349         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 350
 351 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 352
 353         * aarch64-opc.c (init_insn_block): New.
 354         (verify_constraints, aarch64_is_destructive_by_operands): New.
 355         * aarch64-opc.h (verify_constraints): New.
 356
 357 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 358
 359         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 360         * aarch64-opc.c (verify_ldpsw): Update arguments.
 361
 362 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 363
 364         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 365         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 366
 367 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 368
 369         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 370         * aarch64-dis.c (insn_sequence): New.
 371
 372 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 373
 374         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 375         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 376         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 377         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 378         constraints.
 379         (_SVE_INSNC): New.
 380         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 381         constraints.
 382         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 383         F_SCAN flags.
 384         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 385         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 386         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 387         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 388         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 389         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 390         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 391
 392 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 393
 394         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 395
 396 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 397
 398         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 399         are used when extracting signed fields and converting them to
 400         potentially 64-bit types.
 401
 402 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 403
 404         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 405         * Makefile.in: Re-generate.
 406         * aclocal.m4: Re-generate.
 407         * configure: Re-generate.
 408         * configure.ac: Remove check for -Wno-missing-field-initializers.
 409         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 410         (csky_v2_opcodes): Likewise.
 411
 412 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 413
 414         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 415
 416 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 417
 418         * nds32-asm.c (operand_fields): Remove the unused fields.
 419         (nds32_opcodes): Remove the unused instructions.
 420         * nds32-dis.c (nds32_ex9_info): Removed.
 421         (nds32_parse_opcode): Updated.
 422         (print_insn_nds32): Likewise.
 423         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 424         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 425         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 426         build_opcode_hash_table): New functions.
 427         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 428         nds32_opcode_table): New.
 429         (hw_ktabs): Declare it to a pointer rather than an array.
 430         (build_hash_table): Removed.
 431         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 432         SYN_ROPT and upadte HW_GPR and HW_INT.
 433         * nds32-dis.c (keywords): Remove const.
 434         (match_field): New function.
 435         (nds32_parse_opcode): Updated.
 436         * disassemble.c (disassemble_init_for_target):
 437         Add disassemble_init_nds32.
 438         * nds32-dis.c (eum map_type): New.
 439         (nds32_private_data): Likewise.
 440         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 441         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 442         (print_insn_nds32): Updated.
 443         * nds32-asm.c (parse_aext_reg): Add new parameter.
 444         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 445         are allowed to use.
 446         All callers changed.
 447         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 448         (operand_fields): Add new fields.
 449         (nds32_opcodes): Add new instructions.
 450         (keyword_aridxi_mx): New keyword.
 451         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 452         and NASM_ATTR_ZOL.
 453         (ALU2_1, ALU2_2, ALU2_3): New macros.
 454         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 455
 456 2018-09-17  Kito Cheng  <kito@andestech.com>
 457
 458         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 459
 460 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 461
 462         PR gas/23670
 463         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 464         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 465         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 466         (EVEX_LEN_0F7E_P_1): Likewise.
 467         (EVEX_LEN_0F7E_P_2): Likewise.
 468         (EVEX_LEN_0FD6_P_2): Likewise.
 469         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 470         (EVEX_LEN_TABLE): Likewise.
 471         (EVEX_LEN_0F6E_P_2): New enum.
 472         (EVEX_LEN_0F7E_P_1): Likewise.
 473         (EVEX_LEN_0F7E_P_2): Likewise.
 474         (EVEX_LEN_0FD6_P_2): Likewise.
 475         (evex_len_table): New.
 476         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 477         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 478         * i386-tbl.h: Regenerated.
 479
 480 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 481
 482         PR gas/23665
 483         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 484         VEX_LEN_0F7E_P_2 entries.
 485         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 486         * i386-tbl.h: Regenerated.
 487
 488 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 489
 490         * i386-dis.c (VZERO_Fixup): Removed.
 491         (VZERO): Likewise.
 492         (VEX_LEN_0F10_P_1): Likewise.
 493         (VEX_LEN_0F10_P_3): Likewise.
 494         (VEX_LEN_0F11_P_1): Likewise.
 495         (VEX_LEN_0F11_P_3): Likewise.
 496         (VEX_LEN_0F2E_P_0): Likewise.
 497         (VEX_LEN_0F2E_P_2): Likewise.
 498         (VEX_LEN_0F2F_P_0): Likewise.
 499         (VEX_LEN_0F2F_P_2): Likewise.
 500         (VEX_LEN_0F51_P_1): Likewise.
 501         (VEX_LEN_0F51_P_3): Likewise.
 502         (VEX_LEN_0F52_P_1): Likewise.
 503         (VEX_LEN_0F53_P_1): Likewise.
 504         (VEX_LEN_0F58_P_1): Likewise.
 505         (VEX_LEN_0F58_P_3): Likewise.
 506         (VEX_LEN_0F59_P_1): Likewise.
 507         (VEX_LEN_0F59_P_3): Likewise.
 508         (VEX_LEN_0F5A_P_1): Likewise.
 509         (VEX_LEN_0F5A_P_3): Likewise.
 510         (VEX_LEN_0F5C_P_1): Likewise.
 511         (VEX_LEN_0F5C_P_3): Likewise.
 512         (VEX_LEN_0F5D_P_1): Likewise.
 513         (VEX_LEN_0F5D_P_3): Likewise.
 514         (VEX_LEN_0F5E_P_1): Likewise.
 515         (VEX_LEN_0F5E_P_3): Likewise.
 516         (VEX_LEN_0F5F_P_1): Likewise.
 517         (VEX_LEN_0F5F_P_3): Likewise.
 518         (VEX_LEN_0FC2_P_1): Likewise.
 519         (VEX_LEN_0FC2_P_3): Likewise.
 520         (VEX_LEN_0F3A0A_P_2): Likewise.
 521         (VEX_LEN_0F3A0B_P_2): Likewise.
 522         (VEX_W_0F10_P_0): Likewise.
 523         (VEX_W_0F10_P_1): Likewise.
 524         (VEX_W_0F10_P_2): Likewise.
 525         (VEX_W_0F10_P_3): Likewise.
 526         (VEX_W_0F11_P_0): Likewise.
 527         (VEX_W_0F11_P_1): Likewise.
 528         (VEX_W_0F11_P_2): Likewise.
 529         (VEX_W_0F11_P_3): Likewise.
 530         (VEX_W_0F12_P_0_M_0): Likewise.
 531         (VEX_W_0F12_P_0_M_1): Likewise.
 532         (VEX_W_0F12_P_1): Likewise.
 533         (VEX_W_0F12_P_2): Likewise.
 534         (VEX_W_0F12_P_3): Likewise.
 535         (VEX_W_0F13_M_0): Likewise.
 536         (VEX_W_0F14): Likewise.
 537         (VEX_W_0F15): Likewise.
 538         (VEX_W_0F16_P_0_M_0): Likewise.
 539         (VEX_W_0F16_P_0_M_1): Likewise.
 540         (VEX_W_0F16_P_1): Likewise.
 541         (VEX_W_0F16_P_2): Likewise.
 542         (VEX_W_0F17_M_0): Likewise.
 543         (VEX_W_0F28): Likewise.
 544         (VEX_W_0F29): Likewise.
 545         (VEX_W_0F2B_M_0): Likewise.
 546         (VEX_W_0F2E_P_0): Likewise.
 547         (VEX_W_0F2E_P_2): Likewise.
 548         (VEX_W_0F2F_P_0): Likewise.
 549         (VEX_W_0F2F_P_2): Likewise.
 550         (VEX_W_0F50_M_0): Likewise.
 551         (VEX_W_0F51_P_0): Likewise.
 552         (VEX_W_0F51_P_1): Likewise.
 553         (VEX_W_0F51_P_2): Likewise.
 554         (VEX_W_0F51_P_3): Likewise.
 555         (VEX_W_0F52_P_0): Likewise.
 556         (VEX_W_0F52_P_1): Likewise.
 557         (VEX_W_0F53_P_0): Likewise.
 558         (VEX_W_0F53_P_1): Likewise.
 559         (VEX_W_0F58_P_0): Likewise.
 560         (VEX_W_0F58_P_1): Likewise.
 561         (VEX_W_0F58_P_2): Likewise.
 562         (VEX_W_0F58_P_3): Likewise.
 563         (VEX_W_0F59_P_0): Likewise.
 564         (VEX_W_0F59_P_1): Likewise.
 565         (VEX_W_0F59_P_2): Likewise.
 566         (VEX_W_0F59_P_3): Likewise.
 567         (VEX_W_0F5A_P_0): Likewise.
 568         (VEX_W_0F5A_P_1): Likewise.
 569         (VEX_W_0F5A_P_3): Likewise.
 570         (VEX_W_0F5B_P_0): Likewise.
 571         (VEX_W_0F5B_P_1): Likewise.
 572         (VEX_W_0F5B_P_2): Likewise.
 573         (VEX_W_0F5C_P_0): Likewise.
 574         (VEX_W_0F5C_P_1): Likewise.
 575         (VEX_W_0F5C_P_2): Likewise.
 576         (VEX_W_0F5C_P_3): Likewise.
 577         (VEX_W_0F5D_P_0): Likewise.
 578         (VEX_W_0F5D_P_1): Likewise.
 579         (VEX_W_0F5D_P_2): Likewise.
 580         (VEX_W_0F5D_P_3): Likewise.
 581         (VEX_W_0F5E_P_0): Likewise.
 582         (VEX_W_0F5E_P_1): Likewise.
 583         (VEX_W_0F5E_P_2): Likewise.
 584         (VEX_W_0F5E_P_3): Likewise.
 585         (VEX_W_0F5F_P_0): Likewise.
 586         (VEX_W_0F5F_P_1): Likewise.
 587         (VEX_W_0F5F_P_2): Likewise.
 588         (VEX_W_0F5F_P_3): Likewise.
 589         (VEX_W_0F60_P_2): Likewise.
 590         (VEX_W_0F61_P_2): Likewise.
 591         (VEX_W_0F62_P_2): Likewise.
 592         (VEX_W_0F63_P_2): Likewise.
 593         (VEX_W_0F64_P_2): Likewise.
 594         (VEX_W_0F65_P_2): Likewise.
 595         (VEX_W_0F66_P_2): Likewise.
 596         (VEX_W_0F67_P_2): Likewise.
 597         (VEX_W_0F68_P_2): Likewise.
 598         (VEX_W_0F69_P_2): Likewise.
 599         (VEX_W_0F6A_P_2): Likewise.
 600         (VEX_W_0F6B_P_2): Likewise.
 601         (VEX_W_0F6C_P_2): Likewise.
 602         (VEX_W_0F6D_P_2): Likewise.
 603         (VEX_W_0F6F_P_1): Likewise.
 604         (VEX_W_0F6F_P_2): Likewise.
 605         (VEX_W_0F70_P_1): Likewise.
 606         (VEX_W_0F70_P_2): Likewise.
 607         (VEX_W_0F70_P_3): Likewise.
 608         (VEX_W_0F71_R_2_P_2): Likewise.
 609         (VEX_W_0F71_R_4_P_2): Likewise.
 610         (VEX_W_0F71_R_6_P_2): Likewise.
 611         (VEX_W_0F72_R_2_P_2): Likewise.
 612         (VEX_W_0F72_R_4_P_2): Likewise.
 613         (VEX_W_0F72_R_6_P_2): Likewise.
 614         (VEX_W_0F73_R_2_P_2): Likewise.
 615         (VEX_W_0F73_R_3_P_2): Likewise.
 616         (VEX_W_0F73_R_6_P_2): Likewise.
 617         (VEX_W_0F73_R_7_P_2): Likewise.
 618         (VEX_W_0F74_P_2): Likewise.
 619         (VEX_W_0F75_P_2): Likewise.
 620         (VEX_W_0F76_P_2): Likewise.
 621         (VEX_W_0F77_P_0): Likewise.
 622         (VEX_W_0F7C_P_2): Likewise.
 623         (VEX_W_0F7C_P_3): Likewise.
 624         (VEX_W_0F7D_P_2): Likewise.
 625         (VEX_W_0F7D_P_3): Likewise.
 626         (VEX_W_0F7E_P_1): Likewise.
 627         (VEX_W_0F7F_P_1): Likewise.
 628         (VEX_W_0F7F_P_2): Likewise.
 629         (VEX_W_0FAE_R_2_M_0): Likewise.
 630         (VEX_W_0FAE_R_3_M_0): Likewise.
 631         (VEX_W_0FC2_P_0): Likewise.
 632         (VEX_W_0FC2_P_1): Likewise.
 633         (VEX_W_0FC2_P_2): Likewise.
 634         (VEX_W_0FC2_P_3): Likewise.
 635         (VEX_W_0FD0_P_2): Likewise.
 636         (VEX_W_0FD0_P_3): Likewise.
 637         (VEX_W_0FD1_P_2): Likewise.
 638         (VEX_W_0FD2_P_2): Likewise.
 639         (VEX_W_0FD3_P_2): Likewise.
 640         (VEX_W_0FD4_P_2): Likewise.
 641         (VEX_W_0FD5_P_2): Likewise.
 642         (VEX_W_0FD6_P_2): Likewise.
 643         (VEX_W_0FD7_P_2_M_1): Likewise.
 644         (VEX_W_0FD8_P_2): Likewise.
 645         (VEX_W_0FD9_P_2): Likewise.
 646         (VEX_W_0FDA_P_2): Likewise.
 647         (VEX_W_0FDB_P_2): Likewise.
 648         (VEX_W_0FDC_P_2): Likewise.
 649         (VEX_W_0FDD_P_2): Likewise.
 650         (VEX_W_0FDE_P_2): Likewise.
 651         (VEX_W_0FDF_P_2): Likewise.
 652         (VEX_W_0FE0_P_2): Likewise.
 653         (VEX_W_0FE1_P_2): Likewise.
 654         (VEX_W_0FE2_P_2): Likewise.
 655         (VEX_W_0FE3_P_2): Likewise.
 656         (VEX_W_0FE4_P_2): Likewise.
 657         (VEX_W_0FE5_P_2): Likewise.
 658         (VEX_W_0FE6_P_1): Likewise.
 659         (VEX_W_0FE6_P_2): Likewise.
 660         (VEX_W_0FE6_P_3): Likewise.
 661         (VEX_W_0FE7_P_2_M_0): Likewise.
 662         (VEX_W_0FE8_P_2): Likewise.
 663         (VEX_W_0FE9_P_2): Likewise.
 664         (VEX_W_0FEA_P_2): Likewise.
 665         (VEX_W_0FEB_P_2): Likewise.
 666         (VEX_W_0FEC_P_2): Likewise.
 667         (VEX_W_0FED_P_2): Likewise.
 668         (VEX_W_0FEE_P_2): Likewise.
 669         (VEX_W_0FEF_P_2): Likewise.
 670         (VEX_W_0FF0_P_3_M_0): Likewise.
 671         (VEX_W_0FF1_P_2): Likewise.
 672         (VEX_W_0FF2_P_2): Likewise.
 673         (VEX_W_0FF3_P_2): Likewise.
 674         (VEX_W_0FF4_P_2): Likewise.
 675         (VEX_W_0FF5_P_2): Likewise.
 676         (VEX_W_0FF6_P_2): Likewise.
 677         (VEX_W_0FF7_P_2): Likewise.
 678         (VEX_W_0FF8_P_2): Likewise.
 679         (VEX_W_0FF9_P_2): Likewise.
 680         (VEX_W_0FFA_P_2): Likewise.
 681         (VEX_W_0FFB_P_2): Likewise.
 682         (VEX_W_0FFC_P_2): Likewise.
 683         (VEX_W_0FFD_P_2): Likewise.
 684         (VEX_W_0FFE_P_2): Likewise.
 685         (VEX_W_0F3800_P_2): Likewise.
 686         (VEX_W_0F3801_P_2): Likewise.
 687         (VEX_W_0F3802_P_2): Likewise.
 688         (VEX_W_0F3803_P_2): Likewise.
 689         (VEX_W_0F3804_P_2): Likewise.
 690         (VEX_W_0F3805_P_2): Likewise.
 691         (VEX_W_0F3806_P_2): Likewise.
 692         (VEX_W_0F3807_P_2): Likewise.
 693         (VEX_W_0F3808_P_2): Likewise.
 694         (VEX_W_0F3809_P_2): Likewise.
 695         (VEX_W_0F380A_P_2): Likewise.
 696         (VEX_W_0F380B_P_2): Likewise.
 697         (VEX_W_0F3817_P_2): Likewise.
 698         (VEX_W_0F381C_P_2): Likewise.
 699         (VEX_W_0F381D_P_2): Likewise.
 700         (VEX_W_0F381E_P_2): Likewise.
 701         (VEX_W_0F3820_P_2): Likewise.
 702         (VEX_W_0F3821_P_2): Likewise.
 703         (VEX_W_0F3822_P_2): Likewise.
 704         (VEX_W_0F3823_P_2): Likewise.
 705         (VEX_W_0F3824_P_2): Likewise.
 706         (VEX_W_0F3825_P_2): Likewise.
 707         (VEX_W_0F3828_P_2): Likewise.
 708         (VEX_W_0F3829_P_2): Likewise.
 709         (VEX_W_0F382A_P_2_M_0): Likewise.
 710         (VEX_W_0F382B_P_2): Likewise.
 711         (VEX_W_0F3830_P_2): Likewise.
 712         (VEX_W_0F3831_P_2): Likewise.
 713         (VEX_W_0F3832_P_2): Likewise.
 714         (VEX_W_0F3833_P_2): Likewise.
 715         (VEX_W_0F3834_P_2): Likewise.
 716         (VEX_W_0F3835_P_2): Likewise.
 717         (VEX_W_0F3837_P_2): Likewise.
 718         (VEX_W_0F3838_P_2): Likewise.
 719         (VEX_W_0F3839_P_2): Likewise.
 720         (VEX_W_0F383A_P_2): Likewise.
 721         (VEX_W_0F383B_P_2): Likewise.
 722         (VEX_W_0F383C_P_2): Likewise.
 723         (VEX_W_0F383D_P_2): Likewise.
 724         (VEX_W_0F383E_P_2): Likewise.
 725         (VEX_W_0F383F_P_2): Likewise.
 726         (VEX_W_0F3840_P_2): Likewise.
 727         (VEX_W_0F3841_P_2): Likewise.
 728         (VEX_W_0F38DB_P_2): Likewise.
 729         (VEX_W_0F3A08_P_2): Likewise.
 730         (VEX_W_0F3A09_P_2): Likewise.
 731         (VEX_W_0F3A0A_P_2): Likewise.
 732         (VEX_W_0F3A0B_P_2): Likewise.
 733         (VEX_W_0F3A0C_P_2): Likewise.
 734         (VEX_W_0F3A0D_P_2): Likewise.
 735         (VEX_W_0F3A0E_P_2): Likewise.
 736         (VEX_W_0F3A0F_P_2): Likewise.
 737         (VEX_W_0F3A21_P_2): Likewise.
 738         (VEX_W_0F3A40_P_2): Likewise.
 739         (VEX_W_0F3A41_P_2): Likewise.
 740         (VEX_W_0F3A42_P_2): Likewise.
 741         (VEX_W_0F3A62_P_2): Likewise.
 742         (VEX_W_0F3A63_P_2): Likewise.
 743         (VEX_W_0F3ADF_P_2): Likewise.
 744         (VEX_LEN_0F77_P_0): New.
 745         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 746         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 747         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 748         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 749         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 750         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 751         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 752         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 753         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 754         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 755         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 756         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 757         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 758         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 759         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 760         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 761         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 762         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 763         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 764         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 765         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 766         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 767         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 768         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 769         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 770         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 771         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 772         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 773         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 774         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 775         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 776         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 777         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 778         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 779         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 780         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 781         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 782         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 783         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 784         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 785         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 786         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 787         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 788         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 789         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 790         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 791         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 792         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 793         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 794         (vex_table): Update VEX 0F28 and 0F29 entries.
 795         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 796         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 797         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 798         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 799         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 800         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 801         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 802         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 803         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 804         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 805         VEX_LEN_0F3A0B_P_2 entries.
 806         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 807         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 808         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 809         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 810         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 811         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 812         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 813         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 814         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 815         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 816         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 817         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 818         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 819         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 820         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 821         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 822         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 823         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 824         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 825         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 826         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 827         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 828         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 829         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 830         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 831         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 832         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 833         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 834         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 835         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 836         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 837         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 838         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 839         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 840         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 841         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 842         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 843         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 844         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 845         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 846         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 847         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 848         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 849         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 850         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 851         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 852         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 853         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 854         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 855         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 856         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 857         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 858         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 859         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 860         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 861         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 862         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 863         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 864         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 865         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 866         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 867         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 868         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 869         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 870         VEX_W_0F3ADF_P_2 entries.
 871         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 872         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 873         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 874
 875 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 876
 877         * i386-opc.tbl (VexWIG): New.
 878         Replace VexW=3 with VexWIG.
 879
 880 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 881
 882         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 883         * i386-tbl.h: Regenerated.
 884
 885 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 886
 887         PR gas/23665
 888         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 889         VEX_LEN_0FD6_P_2 entries.
 890         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 891         * i386-tbl.h: Regenerated.
 892
 893 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 894
 895         PR gas/23642
 896         * i386-opc.h (VEXWIG): New.
 897         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 898         * i386-tbl.h: Regenerated.
 899
 900 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 901
 902         PR binutils/23655
 903         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 904         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 905         * i386-dis.c (EXxEVexR64): New.
 906         (evex_rounding_64_mode): Likewise.
 907         (OP_Rounding): Handle evex_rounding_64_mode.
 908
 909 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 910
 911         PR binutils/23655
 912         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 913         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 914         * i386-dis.c (Edqa): New.
 915         (dqa_mode): Likewise.
 916         (intel_operand_size): Handle dqa_mode as m_mode.
 917         (OP_E_register): Handle dqa_mode as dq_mode.
 918         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 919
 920 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 921
 922         * i386-dis.c (OP_E_memory): Reformat.
 923
 924 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 925
 926         * i386-opc.tbl (crc32): Fold byte and word forms.
 927         * i386-tbl.h: Re-generate.
 928
 929 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 930
 931         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 932         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 933         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 934         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 935         * i386-tbl.h: Regenerated.
 936
 937 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 938
 939         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 940         meaningless.
 941         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 942         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 943         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 944         * i386-tbl.h: Re-generate.
 945
 946 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 949         AVX512_4VNNIW insns.
 950         * i386-tbl.h: Re-generate.
 951
 952 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 955         meaningless.
 956         * i386-tbl.h: Re-generate.
 957
 958 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 959
 960         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 961         meaningless.
 962         * i386-tbl.h: Re-generate.
 963
 964 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 965
 966         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 967         meaningless.
 968         * i386-tbl.h: Re-generate.
 969
 970 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 971
 972         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 973         meaningless.
 974         * i386-tbl.h: Re-generate.
 975
 976 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 977
 978         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 979         meaningless.
 980         * i386-tbl.h: Re-generate.
 981
 982 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 985         * i386-tbl.h: Re-generate.
 986
 987 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 990         * i386-tbl.h: Re-generate.
 991
 992 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 993
 994         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 995         meaningless.
 996         * i386-tbl.h: Re-generate.
 997
 998 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 999
1000         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
1001         meaningless.
1002         * i386-tbl.h: Re-generate.
1003
1004 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1005
1006         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
1007         * i386-tbl.h: Re-generate.
1008
1009 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1010
1011         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
1012         * i386-tbl.h: Re-generate.
1013
1014 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1015
1016         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
1017         * i386-tbl.h: Re-generate.
1018
1019 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
1022         meaningless.
1023         * i386-tbl.h: Re-generate.
1024
1025 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1026
1027         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
1028         meaningless.
1029         * i386-tbl.h: Re-generate.
1030
1031 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1032
1033         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1034         meaningless.
1035         * i386-tbl.h: Re-generate.
1036
1037 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1038
1039         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1040         * i386-tbl.h: Re-generate.
1041
1042 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1043
1044         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1045         * i386-tbl.h: Re-generate.
1046
1047 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1048
1049         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1050         * i386-tbl.h: Re-generate.
1051
1052 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1053
1054         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1055         (vpbroadcastw, rdpid): Drop NoRex64.
1056         * i386-tbl.h: Re-generate.
1057
1058 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1059
1060         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1061         store templates, adding D.
1062         * i386-tbl.h: Re-generate.
1063
1064 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1065
1066         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1067         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1068         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1069         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1070         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1071         Fold load and store templates where possible, adding D. Drop
1072         IgnoreSize where it was pointlessly present. Drop redundant
1073         *word.
1074         * i386-tbl.h: Re-generate.
1075
1076 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1077
1078         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1079         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1080         (intel_operand_size): Handle v_bndmk_mode.
1081         (OP_E_memory): Likewise. Produce (bad) when also riprel.
1082
1083 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
1084
1085         * disassemble.c (ARCH_s12z): Define if ARCH_all.
1086
1087 2018-08-31  Kito Cheng  <kito@andestech.com>
1088
1089         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1090         compressed floating point instructions.
1091
1092 2018-08-30  Kito Cheng  <kito@andestech.com>
1093
1094         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1095         riscv_opcode.xlen_requirement.
1096         * riscv-opc.c (riscv_opcodes): Update for struct change.
1097
1098 2018-08-29  Martin Aberg  <maberg@gaisler.com>
1099
1100         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1101         psr (PWRPSR) instruction.
1102
1103 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1104
1105         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1106
1107 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1108
1109         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1110
1111 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1112
1113         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1114         loongson3a as an alias of gs464 for compatibility.
1115         * mips-opc.c (mips_opcodes): Change Comments.
1116
1117 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1118
1119         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1120         option.
1121         (print_mips_disassembler_options): Document -M loongson-ext.
1122         * mips-opc.c (LEXT2): New macro.
1123         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1124
1125 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1126
1127          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1128          descriptors.
1129          (parse_mips_ase_option): Handle -M loongson-ext option.
1130          (print_mips_disassembler_options): Document -M loongson-ext.
1131          * mips-opc.c (IL3A): Delete.
1132          * mips-opc.c (LEXT): New macro.
1133          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1134          instructions.
1135
1136 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1137
1138         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1139         descriptors.
1140         (parse_mips_ase_option): Handle -M loongson-cam option.
1141         (print_mips_disassembler_options): Document -M loongson-cam.
1142         * mips-opc.c (LCAM): New macro.
1143         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1144         instructions.
1145
1146 2018-08-21  Alan Modra  <amodra@gmail.com>
1147
1148         * ppc-dis.c (operand_value_powerpc): Init "invalid".
1149         (skip_optional_operands): Count optional operands, and update
1150         ppc_optional_operand_value call.
1151         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1152         (extract_vlensi): Likewise.
1153         (extract_fxm): Return default value for missing optional operand.
1154         (extract_ls, extract_raq, extract_tbr): Likewise.
1155         (insert_sxl, extract_sxl): New functions.
1156         (insert_esync, extract_esync): Remove Power9 handling and simplify.
1157         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1158         flag and extra entry.
1159         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1160         extract_sxl.
1161
1162 2018-08-20  Alan Modra  <amodra@gmail.com>
1163
1164         * sh-opc.h (MASK): Simplify.
1165
1166 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1167
1168         * s12z-dis.c (bm_decode): Deal with cases where the mode is
1169         BM_RESERVED0 or BM_RESERVED1
1170         (bm_rel_decode, bm_n_bytes): Ditto.
1171
1172 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1173
1174         * s12z.h: Delete.
1175
1176 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1177
1178         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1179         address with the addr32 prefix and without base nor index
1180         registers.
1181
1182 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1183
1184         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1185         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1186         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1187         (cpu_flags): Add CpuCMOV and CpuFXSR.
1188         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1189         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1190         * i386-init.h: Regenerated.
1191         * i386-tbl.h: Likewise.
1192
1193 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1194
1195         * arc-regs.h: Update auxiliary registers.
1196
1197 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1198
1199         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1200         (RegIP, RegIZ): Define.
1201         * i386-reg.tbl: Adjust comments.
1202         (rip): Use Qword instead of BaseIndex. Use RegIP.
1203         (eip): Use Dword instead of BaseIndex. Use RegIP.
1204         (riz): Add Qword. Use RegIZ.
1205         (eiz): Add Dword. Use RegIZ.
1206         * i386-tbl.h: Re-generate.
1207
1208 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1209
1210         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1211         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1212         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1213         * i386-tbl.h: Re-generate.
1214
1215 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1216
1217         * i386-gen.c (operand_types): Remove Mem field.
1218         * i386-opc.h (union i386_operand_type): Remove mem field.
1219         * i386-init.h, i386-tbl.h: Re-generate.
1220
1221 2018-08-01  Alan Modra  <amodra@gmail.com>
1222
1223         * po/POTFILES.in: Regenerate.
1224
1225 2018-07-31  Nick Clifton  <nickc@redhat.com>
1226
1227         * po/sv.po: Updated Swedish translation.
1228
1229 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1230
1231         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1232         * i386-init.h, i386-tbl.h: Re-generate.
1233
1234 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1235
1236         * i386-opc.h (ZEROING_MASKING) Rename to ...
1237         (DYNAMIC_MASKING): ... this. Adjust comment.
1238         * i386-opc.tbl (MaskingMorZ): Define.
1239         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1240         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1241         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1242         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1243         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1244         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1245         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1246         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1247         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1248
1249 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1250
1251         * i386-opc.tbl: Use element rather than vector size for AVX512*
1252         scatter/gather insns.
1253         * i386-tbl.h: Re-generate.
1254
1255 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1256
1257         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1258         (cpu_flags): Drop CpuVREX.
1259         * i386-opc.h (CpuVREX): Delete.
1260         (union i386_cpu_flags): Remove cpuvrex.
1261         * i386-init.h, i386-tbl.h: Re-generate.
1262
1263 2018-07-30  Jim Wilson  <jimw@sifive.com>
1264
1265         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1266         fields.
1267         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1268
1269 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1270
1271         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1272         * Makefile.in: Regenerated.
1273         * configure.ac: Add C-SKY.
1274         * configure: Regenerated.
1275         * csky-dis.c: New file.
1276         * csky-opc.h: New file.
1277         * disassemble.c (ARCH_csky): Define.
1278         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1279         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1280
1281 2018-07-27  Alan Modra  <amodra@gmail.com>
1282
1283         * ppc-opc.c (insert_sprbat): Correct function parameter and
1284         return type.
1285         (extract_sprbat): Likewise, variable too.
1286
1287 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1288             Alan Modra  <amodra@gmail.com>
1289
1290         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1291         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1292         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1293         support disjointed BAT.
1294         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1295         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1296         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1297
1298 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1299             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1300
1301         * i386-gen.c (adjust_broadcast_modifier): New function.
1302         (process_i386_opcode_modifier): Add an argument for operands.
1303         Adjust the Broadcast value based on operands.
1304         (output_i386_opcode): Pass operand_types to
1305         process_i386_opcode_modifier.
1306         (process_i386_opcodes): Pass NULL as operands to
1307         process_i386_opcode_modifier.
1308         * i386-opc.h (BYTE_BROADCAST): New.
1309         (WORD_BROADCAST): Likewise.
1310         (DWORD_BROADCAST): Likewise.
1311         (QWORD_BROADCAST): Likewise.
1312         (i386_opcode_modifier): Expand broadcast to 3 bits.
1313         * i386-tbl.h: Regenerated.
1314
1315 2018-07-24  Alan Modra  <amodra@gmail.com>
1316
1317         PR 23430
1318         * or1k-desc.h: Regenerate.
1319
1320 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1321
1322         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1323         vcvtusi2ss, and vcvtusi2sd.
1324         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1325         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1326         * i386-tbl.h: Re-generate.
1327
1328 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1329
1330         * arc-opc.c (extract_w6): Fix extending the sign.
1331
1332 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1333
1334         * arc-tbl.h (vewt): Allow it for ARC EM family.
1335
1336 2018-07-23  Alan Modra  <amodra@gmail.com>
1337
1338         PR 23419
1339         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1340         opcode variants for mtspr/mfspr encodings.
1341
1342 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1343             Maciej W. Rozycki  <macro@mips.com>
1344
1345         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1346         loongson3a descriptors.
1347         (parse_mips_ase_option): Handle -M loongson-mmi option.
1348         (print_mips_disassembler_options): Document -M loongson-mmi.
1349         * mips-opc.c (LMMI): New macro.
1350         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1351         instructions.
1352
1353 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1354
1355         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1356         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1357         IgnoreSize and [XYZ]MMword where applicable.
1358         * i386-tbl.h: Re-generate.
1359
1360 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1361
1362         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1363         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1364         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1365         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1366         * i386-tbl.h: Re-generate.
1367
1368 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1369
1370         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1371         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1372         VPCLMULQDQ templates into their respective AVX512VL counterparts
1373         where possible, using Disp8ShiftVL and CheckRegSize instead of
1374         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1375         * i386-tbl.h: Re-generate.
1376
1377 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1378
1379         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1380         AVX512VL counterparts where possible, using Disp8ShiftVL and
1381         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1382         IgnoreSize) as appropriate.
1383         * i386-tbl.h: Re-generate.
1384
1385 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1386
1387         * i386-opc.tbl: Fold AVX512BW templates into their respective
1388         AVX512VL counterparts where possible, using Disp8ShiftVL and
1389         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1390         IgnoreSize) as appropriate.
1391         * i386-tbl.h: Re-generate.
1392
1393 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1394
1395         * i386-opc.tbl: Fold AVX512CD templates into their respective
1396         AVX512VL counterparts where possible, using Disp8ShiftVL and
1397         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1398         IgnoreSize) as appropriate.
1399         * i386-tbl.h: Re-generate.
1400
1401 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1402
1403         * i386-opc.h (DISP8_SHIFT_VL): New.
1404         * i386-opc.tbl (Disp8ShiftVL):  Define.
1405         (various): Fold AVX512VL templates into their respective
1406         AVX512F counterparts where possible, using Disp8ShiftVL and
1407         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1408         IgnoreSize) as appropriate.
1409         * i386-tbl.h: Re-generate.
1410
1411 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1412
1413         * Makefile.am: Change dependencies and rule for
1414         $(srcdir)/i386-init.h.
1415         * Makefile.in: Re-generate.
1416         * i386-gen.c (process_i386_opcodes): New local variable
1417         "marker". Drop opening of input file. Recognize marker and line
1418         number directives.
1419         * i386-opc.tbl (OPCODE_I386_H): Define.
1420         (i386-opc.h): Include it.
1421         (None): Undefine.
1422
1423 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1424
1425         PR gas/23418
1426         * i386-opc.h (Byte): Update comments.
1427         (Word): Likewise.
1428         (Dword): Likewise.
1429         (Fword): Likewise.
1430         (Qword): Likewise.
1431         (Tbyte): Likewise.
1432         (Xmmword): Likewise.
1433         (Ymmword): Likewise.
1434         (Zmmword): Likewise.
1435         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1436         vcvttps2uqq.
1437         * i386-tbl.h: Regenerated.
1438
1439 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1440
1441         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1442         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1443         * aarch64-asm-2.c: Regenerate.
1444         * aarch64-dis-2.c: Regenerate.
1445         * aarch64-opc-2.c: Regenerate.
1446
1447 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1448
1449         PR binutils/23192
1450         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1451         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1452         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1453         sqdmulh, sqrdmulh): Use Em16.
1454
1455 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1456
1457         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1458         csdb together with them.
1459         (thumb32_opcodes): Likewise.
1460
1461 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1462
1463         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1464         requiring 32-bit registers as operands 2 and 3. Improve
1465         comments.
1466         (mwait, mwaitx): Fold templates. Improve comments.
1467         OPERAND_TYPE_INOUTPORTREG.
1468         * i386-tbl.h: Re-generate.
1469
1470 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1471
1472         * i386-gen.c (operand_type_init): Remove
1473         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1474         OPERAND_TYPE_INOUTPORTREG.
1475         * i386-init.h: Re-generate.
1476
1477 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1478
1479         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1480         (wrssq, wrussq): Add Qword.
1481         * i386-tbl.h: Re-generate.
1482
1483 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1484
1485         * i386-opc.h: Rename OTMax to OTNum.
1486         (OTNumOfUints): Adjust calculation.
1487         (OTUnused): Directly alias to OTNum.
1488
1489 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1490
1491         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1492         `reg_xys'.
1493         (lea_reg_xys): Likewise.
1494         (print_insn_loop_primitive): Rename `reg' local variable to
1495         `reg_dxy'.
1496
1497 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1498
1499         PR binutils/23242
1500         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1501
1502 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1503
1504         PR binutils/23369
1505         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1506         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1507
1508 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1509
1510         PR tdep/8282
1511         * mips-dis.c (mips_option_arg_t): New enumeration.
1512         (mips_options): New variable.
1513         (disassembler_options_mips): New function.
1514         (print_mips_disassembler_options): Reimplement in terms of
1515         `disassembler_options_mips'.
1516         * arm-dis.c (disassembler_options_arm): Adapt to using the
1517         `disasm_options_and_args_t' structure.
1518         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1519         * s390-dis.c (disassembler_options_s390): Likewise.
1520
1521 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1522
1523         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1524         expected result.
1525         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1526         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1527         * testsuite/ld-arm/tls-longplt.d: Likewise.
1528
1529 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1530
1531         PR binutils/23192
1532         * aarch64-asm-2.c: Regenerate.
1533         * aarch64-dis-2.c: Likewise.
1534         * aarch64-opc-2.c: Likewise.
1535         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1536         * aarch64-opc.c (operand_general_constraint_met_p,
1537         aarch64_print_operand): Likewise.
1538         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1539         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1540         fmlal2, fmlsl2.
1541         (AARCH64_OPERANDS): Add Em2.
1542
1543 2018-06-26  Nick Clifton  <nickc@redhat.com>
1544
1545         * po/uk.po: Updated Ukranian translation.
1546         * po/de.po: Updated German translation.
1547         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1548
1549 2018-06-26  Nick Clifton  <nickc@redhat.com>
1550
1551         * nfp-dis.c: Fix spelling mistake.
1552
1553 2018-06-24  Nick Clifton  <nickc@redhat.com>
1554
1555         * configure: Regenerate.
1556         * po/opcodes.pot: Regenerate.
1557
1558 2018-06-24  Nick Clifton  <nickc@redhat.com>
1559
1560         2.31 branch created.
1561
1562 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1563
1564         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1565         * aarch64-asm-2.c: Regenerate.
1566         * aarch64-dis-2.c: Likewise.
1567
1568 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1569
1570         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1571         `-M ginv' option description.
1572
1573 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1574
1575         PR gas/23305
1576         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1577         la and lla.
1578
1579 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1580
1581         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1582         * configure.ac: Remove AC_PREREQ.
1583         * Makefile.in: Re-generate.
1584         * aclocal.m4: Re-generate.
1585         * configure: Re-generate.
1586
1587 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1588
1589         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1590         mips64r6 descriptors.
1591         (parse_mips_ase_option): Handle -Mginv option.
1592         (print_mips_disassembler_options): Document -Mginv.
1593         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1594         (GINV): New macro.
1595         (mips_opcodes): Define ginvi and ginvt.
1596
1597 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1598             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1599
1600         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1601         * mips-opc.c (CRC, CRC64): New macros.
1602         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1603         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1604         crc32cd for CRC64.
1605
1606 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1607
1608         PR 20319
1609         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1610         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1611
1612 2018-06-06  Alan Modra  <amodra@gmail.com>
1613
1614         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1615         setjmp.  Move init for some other vars later too.
1616
1617 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1618
1619         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1620         (dis_private): Add new fields for property section tracking.
1621         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1622         (xtensa_instruction_fits): New functions.
1623         (fetch_data): Bump minimal fetch size to 4.
1624         (print_insn_xtensa): Make struct dis_private static.
1625         Load and prepare property table on section change.
1626         Don't disassemble literals. Don't disassemble instructions that
1627         cross property table boundaries.
1628
1629 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1630
1631         * configure: Regenerated.
1632
1633 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1634
1635         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1636         * i386-tbl.h: Re-generate.
1637
1638 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1639
1640         * i386-opc.tbl (sldt, str): Add NoRex64.
1641         * i386-tbl.h: Re-generate.
1642
1643 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1644
1645         * i386-opc.tbl (invpcid): Add Oword.
1646         * i386-tbl.h: Re-generate.
1647
1648 2018-06-01  Alan Modra  <amodra@gmail.com>
1649
1650         * sysdep.h (_bfd_error_handler): Don't declare.
1651         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1652         * rl78-decode.opc: Likewise.
1653         * msp430-decode.c: Regenerate.
1654         * rl78-decode.c: Regenerate.
1655
1656 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1657
1658         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1659         * i386-init.h : Regenerated.
1660
1661 2018-05-25  Alan Modra  <amodra@gmail.com>
1662
1663         * Makefile.in: Regenerate.
1664         * po/POTFILES.in: Regenerate.
1665
1666 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1667
1668         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1669         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1670         (insert_bab, extract_bab, insert_btab, extract_btab,
1671         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1672         (BAT, BBA VBA RBS XB6S): Delete macros.
1673         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1674         (BB, BD, RBX, XC6): Update for new macros.
1675         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1676         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1677         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1678         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1679
1680 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1681
1682         * Makefile.am: Add support for s12z architecture.
1683         * configure.ac: Likewise.
1684         * disassemble.c: Likewise.
1685         * disassemble.h: Likewise.
1686         * Makefile.in: Regenerate.
1687         * configure: Regenerate.
1688         * s12z-dis.c: New file.
1689         * s12z.h: New file.
1690
1691 2018-05-18  Alan Modra  <amodra@gmail.com>
1692
1693         * nfp-dis.c: Don't #include libbfd.h.
1694         (init_nfp3200_priv): Use bfd_get_section_contents.
1695         (nit_nfp6000_mecsr_sec): Likewise.
1696
1697 2018-05-17  Nick Clifton  <nickc@redhat.com>
1698
1699         * po/zh_CN.po: Updated simplified Chinese translation.
1700
1701 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1702
1703         PR binutils/23109
1704         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1705         * aarch64-dis-2.c: Regenerate.
1706
1707 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1708
1709         PR binutils/21446
1710         * aarch64-asm.c (opintl.h): Include.
1711         (aarch64_ins_sysreg): Enforce read/write constraints.
1712         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1713         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1714         (F_REG_READ, F_REG_WRITE): New.
1715         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1716         AARCH64_OPND_SYSREG.
1717         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1718         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1719         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1720         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1721         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1722         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1723         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1724         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1725         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1726         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1727         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1728         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1729         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1730         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1731         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1732         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1733         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1734
1735 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1736
1737         PR binutils/21446
1738         * aarch64-dis.c (no_notes: New.
1739         (parse_aarch64_dis_option): Support notes.
1740         (aarch64_decode_insn, print_operands): Likewise.
1741         (print_aarch64_disassembler_options): Document notes.
1742         * aarch64-opc.c (aarch64_print_operand): Support notes.
1743
1744 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1745
1746         PR binutils/21446
1747         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1748         and take error struct.
1749         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1750         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1751         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1752         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1753         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1754         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1755         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1756         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1757         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1758         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1759         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1760         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1761         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1762         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1763         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1764         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1765         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1766         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1767         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1768         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1769         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1770         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1771         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1772         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1773         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1774         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1775         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1776         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1777         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1778         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1779         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1780         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1781         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1782         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1783         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1784         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1785         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1786         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1787         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1788         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1789         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1790         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1791         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1792         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1793         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1794         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1795         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1796         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1797         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1798         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1799         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1800         (determine_disassembling_preference, aarch64_decode_insn,
1801         print_insn_aarch64_word, print_insn_data): Take errors struct.
1802         (print_insn_aarch64): Use errors.
1803         * aarch64-asm-2.c: Regenerate.
1804         * aarch64-dis-2.c: Regenerate.
1805         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1806         boolean in aarch64_insert_operan.
1807         (print_operand_extractor): Likewise.
1808         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1809
1810 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1811
1812         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1813
1814 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1815
1816         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1817
1818 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1819
1820         * cr16-opc.c (cr16_instruction): Comment typo fix.
1821         * hppa-dis.c (print_insn_hppa): Likewise.
1822
1823 2018-05-08  Jim Wilson  <jimw@sifive.com>
1824
1825         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1826         (match_c_slli64, match_srxi_as_c_srxi): New.
1827         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1828         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1829         <c.slli, c.srli, c.srai>: Use match_s_slli.
1830         <c.slli64, c.srli64, c.srai64>: New.
1831
1832 2018-05-08  Alan Modra  <amodra@gmail.com>
1833
1834         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1835         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1836         partition opcode space for index lookup.
1837
1838 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1839
1840         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1841         <insn_length>: ...with this.  Update usage.
1842         Remove duplicate call to *info->memory_error_func.
1843
1844 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1845             H.J. Lu  <hongjiu.lu@intel.com>
1846
1847         * i386-dis.c (Gva): New.
1848         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1849         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1850         (prefix_table): New instructions (see prefix above).
1851         (mod_table): New instructions (see prefix above).
1852         (OP_G): Handle va_mode.
1853         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1854         CPU_MOVDIR64B_FLAGS.
1855         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1856         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1857         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1858         * i386-opc.tbl: Add movidir{i,64b}.
1859         * i386-init.h: Regenerated.
1860         * i386-tbl.h: Likewise.
1861
1862 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1863
1864         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1865         AddrPrefixOpReg.
1866         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1867         (AddrPrefixOpReg): This.
1868         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1869         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1870
1871 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1872
1873         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1874         (vle_num_opcodes): Likewise.
1875         (spe2_num_opcodes): Likewise.
1876         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1877         initialization loop.
1878         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1879         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1880         only once.
1881
1882 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1883
1884         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1885
1886 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1887
1888         Makefile.am: Added nfp-dis.c.
1889         configure.ac: Added bfd_nfp_arch.
1890         disassemble.h: Added print_insn_nfp prototype.
1891         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1892         nfp-dis.c: New, for NFP support.
1893         po/POTFILES.in: Added nfp-dis.c to the list.
1894         Makefile.in: Regenerate.
1895         configure: Regenerate.
1896
1897 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1898
1899         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1900         templates into their base ones.
1901         * i386-tlb.h: Re-generate.
1902
1903 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1904
1905         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1906         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1907         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1908         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1909         * i386-init.h: Re-generate.
1910
1911 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1912
1913         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1914         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1915         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1916         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1917         comment.
1918         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1919         and CpuRegMask.
1920         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1921         CpuRegMask: Delete.
1922         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1923         cpuregzmm, and cpuregmask.
1924         * i386-init.h: Re-generate.
1925         * i386-tbl.h: Re-generate.
1926
1927 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1928
1929         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1930         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1931         * i386-init.h: Re-generate.
1932
1933 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1934
1935         * i386-gen.c (VexImmExt): Delete.
1936         * i386-opc.h (VexImmExt, veximmext): Delete.
1937         * i386-opc.tbl: Drop all VexImmExt uses.
1938         * i386-tlb.h: Re-generate.
1939
1940 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1941
1942         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1943         register-only forms.
1944         * i386-tlb.h: Re-generate.
1945
1946 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1947
1948         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1949
1950 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1951
1952         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1953         PREFIX_0F1C.
1954         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1955         (cpu_flags): Add CpuCLDEMOTE.
1956         * i386-init.h: Regenerate.
1957         * i386-opc.h (enum): Add CpuCLDEMOTE,
1958         (i386_cpu_flags): Add cpucldemote.
1959         * i386-opc.tbl: Add cldemote.
1960         * i386-tbl.h: Regenerate.
1961
1962 2018-04-16  Alan Modra  <amodra@gmail.com>
1963
1964         * Makefile.am: Remove sh5 and sh64 support.
1965         * configure.ac: Likewise.
1966         * disassemble.c: Likewise.
1967         * disassemble.h: Likewise.
1968         * sh-dis.c: Likewise.
1969         * sh64-dis.c: Delete.
1970         * sh64-opc.c: Delete.
1971         * sh64-opc.h: Delete.
1972         * Makefile.in: Regenerate.
1973         * configure: Regenerate.
1974         * po/POTFILES.in: Regenerate.
1975
1976 2018-04-16  Alan Modra  <amodra@gmail.com>
1977
1978         * Makefile.am: Remove w65 support.
1979         * configure.ac: Likewise.
1980         * disassemble.c: Likewise.
1981         * disassemble.h: Likewise.
1982         * w65-dis.c: Delete.
1983         * w65-opc.h: Delete.
1984         * Makefile.in: Regenerate.
1985         * configure: Regenerate.
1986         * po/POTFILES.in: Regenerate.
1987
1988 2018-04-16  Alan Modra  <amodra@gmail.com>
1989
1990         * configure.ac: Remove we32k support.
1991         * configure: Regenerate.
1992
1993 2018-04-16  Alan Modra  <amodra@gmail.com>
1994
1995         * Makefile.am: Remove m88k support.
1996         * configure.ac: Likewise.
1997         * disassemble.c: Likewise.
1998         * disassemble.h: Likewise.
1999         * m88k-dis.c: Delete.
2000         * Makefile.in: Regenerate.
2001         * configure: Regenerate.
2002         * po/POTFILES.in: Regenerate.
2003
2004 2018-04-16  Alan Modra  <amodra@gmail.com>
2005
2006         * Makefile.am: Remove i370 support.
2007         * configure.ac: Likewise.
2008         * disassemble.c: Likewise.
2009         * disassemble.h: Likewise.
2010         * i370-dis.c: Delete.
2011         * i370-opc.c: Delete.
2012         * Makefile.in: Regenerate.
2013         * configure: Regenerate.
2014         * po/POTFILES.in: Regenerate.
2015
2016 2018-04-16  Alan Modra  <amodra@gmail.com>
2017
2018         * Makefile.am: Remove h8500 support.
2019         * configure.ac: Likewise.
2020         * disassemble.c: Likewise.
2021         * disassemble.h: Likewise.
2022         * h8500-dis.c: Delete.
2023         * h8500-opc.h: Delete.
2024         * Makefile.in: Regenerate.
2025         * configure: Regenerate.
2026         * po/POTFILES.in: Regenerate.
2027
2028 2018-04-16  Alan Modra  <amodra@gmail.com>
2029
2030         * configure.ac: Remove tahoe support.
2031         * configure: Regenerate.
2032
2033 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
2034
2035         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2036         umwait.
2037         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2038         64-bit mode.
2039         * i386-tbl.h: Regenerated.
2040
2041 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2042
2043         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2044         PREFIX_MOD_1_0FAE_REG_6.
2045         (va_mode): New.
2046         (OP_E_register): Use va_mode.
2047         * i386-dis-evex.h (prefix_table):
2048         New instructions (see prefixes above).
2049         * i386-gen.c (cpu_flag_init): Add WAITPKG.
2050         (cpu_flags): Likewise.
2051         * i386-opc.h (enum): Likewise.
2052         (i386_cpu_flags): Likewise.
2053         * i386-opc.tbl: Add umonitor, umwait, tpause.
2054         * i386-init.h: Regenerate.
2055         * i386-tbl.h: Likewise.
2056
2057 2018-04-11  Alan Modra  <amodra@gmail.com>
2058
2059         * opcodes/i860-dis.c: Delete.
2060         * opcodes/i960-dis.c: Delete.
2061         * Makefile.am: Remove i860 and i960 support.
2062         * configure.ac: Likewise.
2063         * disassemble.c: Likewise.
2064         * disassemble.h: Likewise.
2065         * Makefile.in: Regenerate.
2066         * configure: Regenerate.
2067         * po/POTFILES.in: Regenerate.
2068
2069 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
2070
2071         PR binutils/23025
2072         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2073         to 0.
2074         (print_insn): Clear vex instead of vex.evex.
2075
2076 2018-04-04  Nick Clifton  <nickc@redhat.com>
2077
2078         * po/es.po: Updated Spanish translation.
2079
2080 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2081
2082         * i386-gen.c (opcode_modifiers): Delete VecESize.
2083         * i386-opc.h (VecESize): Delete.
2084         (struct i386_opcode_modifier): Delete vecesize.
2085         * i386-opc.tbl: Drop VecESize.
2086         * i386-tlb.h: Re-generate.
2087
2088 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2089
2090         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2091         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2092         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2093         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2094         * i386-tlb.h: Re-generate.
2095
2096 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2097
2098         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2099         Fold AVX512 forms
2100         * i386-tlb.h: Re-generate.
2101
2102 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2103
2104         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2105         (vex_len_table): Drop Y for vcvt*2si.
2106         (putop): Replace plain 'Y' handling by abort().
2107
2108 2018-03-28  Nick Clifton  <nickc@redhat.com>
2109
2110         PR 22988
2111         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2112         instructions with only a base address register.
2113         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2114         handle AARHC64_OPND_SVE_ADDR_R.
2115         (aarch64_print_operand): Likewise.
2116         * aarch64-asm-2.c: Regenerate.
2117         * aarch64_dis-2.c: Regenerate.
2118         * aarch64-opc-2.c: Regenerate.
2119
2120 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2121
2122         * i386-opc.tbl: Drop VecESize from register only insn forms and
2123         memory forms not allowing broadcast.
2124         * i386-tlb.h: Re-generate.
2125
2126 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2127
2128         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2129         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2130         sha256*): Drop Disp<N>.
2131
2132 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2133
2134         * i386-dis.c (EbndS, bnd_swap_mode): New.
2135         (prefix_table): Use EbndS.
2136         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2137         * i386-opc.tbl (bndmov): Move misplaced Load.
2138         * i386-tlb.h: Re-generate.
2139
2140 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2141
2142         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2143         templates allowing memory operands and folded ones for register
2144         only flavors.
2145         * i386-tlb.h: Re-generate.
2146
2147 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2148
2149         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2150         256-bit templates. Drop redundant leftover Disp<N>.
2151         * i386-tlb.h: Re-generate.
2152
2153 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
2154
2155         * riscv-opc.c (riscv_insn_types): New.
2156
2157 2018-03-13  Nick Clifton  <nickc@redhat.com>
2158
2159         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2160
2161 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2162
2163         * i386-opc.tbl: Add Optimize to clr.
2164         * i386-tbl.h: Regenerated.
2165
2166 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2167
2168         * i386-gen.c (opcode_modifiers): Remove OldGcc.
2169         * i386-opc.h (OldGcc): Removed.
2170         (i386_opcode_modifier): Remove oldgcc.
2171         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2172         instructions for old (<= 2.8.1) versions of gcc.
2173         * i386-tbl.h: Regenerated.
2174
2175 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2176
2177         * i386-opc.h (EVEXDYN): New.
2178         * i386-opc.tbl: Fold various AVX512VL templates.
2179         * i386-tlb.h: Re-generate.
2180
2181 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2182
2183         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2184         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2185         vpexpandd, vpexpandq): Fold AFX512VF templates.
2186         * i386-tlb.h: Re-generate.
2187
2188 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2189
2190         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2191         Fold 128- and 256-bit VEX-encoded templates.
2192         * i386-tlb.h: Re-generate.
2193
2194 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2195
2196         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2197         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2198         vpexpandd, vpexpandq): Fold AVX512F templates.
2199         * i386-tlb.h: Re-generate.
2200
2201 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2202
2203         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2204         64-bit templates. Drop Disp<N>.
2205         * i386-tlb.h: Re-generate.
2206
2207 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2208
2209         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2210         and 256-bit templates.
2211         * i386-tlb.h: Re-generate.
2212
2213 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2214
2215         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2216         * i386-tlb.h: Re-generate.
2217
2218 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2219
2220         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2221         Drop NoAVX.
2222         * i386-tlb.h: Re-generate.
2223
2224 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2225
2226         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2227         * i386-tlb.h: Re-generate.
2228
2229 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2230
2231         * i386-gen.c (opcode_modifiers): Delete FloatD.
2232         * i386-opc.h (FloatD): Delete.
2233         (struct i386_opcode_modifier): Delete floatd.
2234         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2235         FloatD by D.
2236         * i386-tlb.h: Re-generate.
2237
2238 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2239
2240         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2241
2242 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2243
2244         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2245         * i386-tlb.h: Re-generate.
2246
2247 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2248
2249         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2250         forms.
2251         * i386-tlb.h: Re-generate.
2252
2253 2018-03-07  Alan Modra  <amodra@gmail.com>
2254
2255         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2256         bfd_arch_rs6000.
2257         * disassemble.h (print_insn_rs6000): Delete.
2258         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2259         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2260         (print_insn_rs6000): Delete.
2261
2262 2018-03-03  Alan Modra  <amodra@gmail.com>
2263
2264         * sysdep.h (opcodes_error_handler): Define.
2265         (_bfd_error_handler): Declare.
2266         * Makefile.am: Remove stray #.
2267         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2268         EDIT" comment.
2269         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2270         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2271         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2272         opcodes_error_handler to print errors.  Standardize error messages.
2273         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2274         and include opintl.h.
2275         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2276         * i386-gen.c: Standardize error messages.
2277         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2278         * Makefile.in: Regenerate.
2279         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2280         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2281         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2282         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2283         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2284         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2285         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2286         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2287         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2288         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2289         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2290         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2291         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2292
2293 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2294
2295         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2296         vpsub[bwdq] instructions.
2297         * i386-tbl.h: Regenerated.
2298
2299 2018-03-01  Alan Modra  <amodra@gmail.com>
2300
2301         * configure.ac (ALL_LINGUAS): Sort.
2302         * configure: Regenerate.
2303
2304 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2305
2306         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2307         macro by assignements.
2308
2309 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2310
2311         PR gas/22871
2312         * i386-gen.c (opcode_modifiers): Add Optimize.
2313         * i386-opc.h (Optimize): New enum.
2314         (i386_opcode_modifier): Add optimize.
2315         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2316         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2317         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2318         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2319         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2320         vpxord and vpxorq.
2321         * i386-tbl.h: Regenerated.
2322
2323 2018-02-26  Alan Modra  <amodra@gmail.com>
2324
2325         * crx-dis.c (getregliststring): Allocate a large enough buffer
2326         to silence false positive gcc8 warning.
2327
2328 2018-02-22  Shea Levy <shea@shealevy.com>
2329
2330         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2331
2332 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2333
2334         * i386-opc.tbl: Add {rex},
2335         * i386-tbl.h: Regenerated.
2336
2337 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2338
2339         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2340         (mips16_opcodes): Replace `M' with `m' for "restore".
2341
2342 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2343
2344         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2345
2346 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2347
2348         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2349         variable to `function_index'.
2350
2351 2018-02-13  Nick Clifton  <nickc@redhat.com>
2352
2353         PR 22823
2354         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2355         about truncation of printing.
2356
2357 2018-02-12  Henry Wong <henry@stuffedcow.net>
2358
2359         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2360
2361 2018-02-05  Nick Clifton  <nickc@redhat.com>
2362
2363         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2364
2365 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2366
2367         * i386-dis.c (enum): Add pconfig.
2368         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2369         (cpu_flags): Add CpuPCONFIG.
2370         * i386-opc.h (enum): Add CpuPCONFIG.
2371         (i386_cpu_flags): Add cpupconfig.
2372         * i386-opc.tbl: Add PCONFIG instruction.
2373         * i386-init.h: Regenerate.
2374         * i386-tbl.h: Likewise.
2375
2376 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2377
2378         * i386-dis.c (enum): Add PREFIX_0F09.
2379         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2380         (cpu_flags): Add CpuWBNOINVD.
2381         * i386-opc.h (enum): Add CpuWBNOINVD.
2382         (i386_cpu_flags): Add cpuwbnoinvd.
2383         * i386-opc.tbl: Add WBNOINVD instruction.
2384         * i386-init.h: Regenerate.
2385         * i386-tbl.h: Likewise.
2386
2387 2018-01-17  Jim Wilson  <jimw@sifive.com>
2388
2389         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2390
2391 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2392
2393         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2394         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2395         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2396         (cpu_flags): Add CpuIBT, CpuSHSTK.
2397         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2398         (i386_cpu_flags): Add cpuibt, cpushstk.
2399         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2400         * i386-init.h: Regenerate.
2401         * i386-tbl.h: Likewise.
2402
2403 2018-01-16  Nick Clifton  <nickc@redhat.com>
2404
2405         * po/pt_BR.po: Updated Brazilian Portugese translation.
2406         * po/de.po: Updated German translation.
2407
2408 2018-01-15  Jim Wilson  <jimw@sifive.com>
2409
2410         * riscv-opc.c (match_c_nop): New.
2411         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2412
2413 2018-01-15  Nick Clifton  <nickc@redhat.com>
2414
2415         * po/uk.po: Updated Ukranian translation.
2416
2417 2018-01-13  Nick Clifton  <nickc@redhat.com>
2418
2419         * po/opcodes.pot: Regenerated.
2420
2421 2018-01-13  Nick Clifton  <nickc@redhat.com>
2422
2423         * configure: Regenerate.
2424
2425 2018-01-13  Nick Clifton  <nickc@redhat.com>
2426
2427         2.30 branch created.
2428
2429 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2430
2431         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2432         * i386-tbl.h: Regenerate.
2433
2434 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2435
2436         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2437         * i386-tbl.h: Re-generate.
2438
2439 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2440
2441         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2442         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2443         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2444         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2445         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2446         Disp8MemShift of AVX512VL forms.
2447         * i386-tbl.h: Re-generate.
2448
2449 2018-01-09  Jim Wilson  <jimw@sifive.com>
2450
2451         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2452         then the hi_addr value is zero.
2453
2454 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2455
2456         * arm-dis.c (arm_opcodes): Add csdb.
2457         (thumb32_opcodes): Add csdb.
2458
2459 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2460
2461         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2462         * aarch64-asm-2.c: Regenerate.
2463         * aarch64-dis-2.c: Regenerate.
2464         * aarch64-opc-2.c: Regenerate.
2465
2466 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2467
2468         PR gas/22681
2469         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2470         Remove AVX512 vmovd with 64-bit operands.
2471         * i386-tbl.h: Regenerated.
2472
2473 2018-01-05  Jim Wilson  <jimw@sifive.com>
2474
2475         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2476         jalr.
2477
2478 2018-01-03  Alan Modra  <amodra@gmail.com>
2479
2480         Update year range in copyright notice of all files.
2481
2482 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2483
2484         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2485         and OPERAND_TYPE_REGZMM entries.
2486
2487 For older changes see ChangeLog-2017
2488 \f
2489 Copyright (C) 2018 Free Software Foundation, Inc.
2490
2491 Copying and distribution of this file, with or without modification,
2492 are permitted in any medium without royalty provided the copyright
2493 notice and this notice are preserved.
2494
2495 Local Variables:
2496 mode: change-log
2497 left-margin: 8
2498 fill-column: 74
2499 version-control: never
2500 End: