opcodes/ChangeLog

   1 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
   2
   3         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
   4         * i386-dis-evex.h (evex_table): Updated.
   5         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
   6         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
   7         (cpu_flags): Add CpuAVX512_4VNNIW.
   8         * i386-opc.h (enum): (AVX512_4VNNIW): New.
   9         (i386_cpu_flags): Add cpuavx512_4vnniw.
  10         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
  11         * i386-init.h: Regenerate.
  12         * i386-tbl.h: Ditto.
  13
  14 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  15
  16         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
  17         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
  18         * i386-dis-evex.h (evex_table): Updated.
  19         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
  20         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  21         (cpu_flags): Add CpuAVX512_4FMAPS.
  22         (opcode_modifiers): Add ImplicitQuadGroup modifier.
  23         * i386-opc.h (AVX512_4FMAP): New.
  24         (i386_cpu_flags): Add cpuavx512_4fmaps.
  25         (ImplicitQuadGroup): New.
  26         (i386_opcode_modifier): Add implicitquadgroup.
  27         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
  28         * i386-init.h: Regenerate.
  29         * i386-tbl.h: Ditto.
  30
  31 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
  32             Andrew Waterman <andrew@sifive.com>
  33
  34         Add support for RISC-V architecture.
  35         * configure.ac: Add entry for bfd_riscv_arch.
  36         * configure: Regenerate.
  37         * disassemble.c (disassembler): Add support for riscv.
  38         (disassembler_usage): Likewise.
  39         * riscv-dis.c: New file.
  40         * riscv-opc.c: New file.
  41
  42 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
  43
  44         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
  45         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
  46         (rm_table): Update the RM_0FAE_REG_7 entry.
  47         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
  48         (cpu_flags): Remove CpuPCOMMIT.
  49         * i386-opc.h (CpuPCOMMIT): Removed.
  50         (i386_cpu_flags): Remove cpupcommit.
  51         * i386-opc.tbl: Remove pcommit.
  52         * i386-init.h: Regenerated.
  53         * i386-tbl.h: Likewise.
  54
  55 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
  56
  57         PR binutis/20705
  58         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
  59         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
  60         32-bit mode.  Don't check vex.register_specifier in 32-bit
  61         mode.
  62         (OP_VEX): Check for invalid mask registers.
  63
  64 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
  65
  66         PR binutis/20699
  67         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
  68         sizeflag.
  69
  70 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
  71
  72         PR binutis/20704
  73         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
  74
  75 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
  76
  77         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
  78         local variable to `index_regno'.
  79
  80 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
  81
  82         * arc-tbl.h: Removed any "inv.+" instructions from the table.
  83
  84 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
  85
  86         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
  87         usage on ISA basis.
  88
  89 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
  90
  91         PR target/20666
  92         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
  93
  94 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
  95
  96         PR target/20667
  97         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
  98         available.
  99
 100 2016-10-07  Alan Modra  <amodra@gmail.com>
 101
 102         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 103
 104 2016-10-06  Alan Modra  <amodra@gmail.com>
 105
 106         * aarch64-opc.c: Spell fall through comments consistently.
 107         * i386-dis.c: Likewise.
 108         * aarch64-dis.c: Add missing fall through comments.
 109         * aarch64-opc.c: Likewise.
 110         * arc-dis.c: Likewise.
 111         * arm-dis.c: Likewise.
 112         * i386-dis.c: Likewise.
 113         * m68k-dis.c: Likewise.
 114         * mep-asm.c: Likewise.
 115         * ns32k-dis.c: Likewise.
 116         * sh-dis.c: Likewise.
 117         * tic4x-dis.c: Likewise.
 118         * tic6x-dis.c: Likewise.
 119         * vax-dis.c: Likewise.
 120
 121 2016-10-06  Alan Modra  <amodra@gmail.com>
 122
 123         * arc-ext.c (create_map): Add missing break.
 124         * msp430-decode.opc (encode_as): Likewise.
 125         * msp430-decode.c: Regenerate.
 126
 127 2016-10-06  Alan Modra  <amodra@gmail.com>
 128
 129         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 130         * crx-dis.c (print_insn_crx): Likewise.
 131
 132 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 133
 134         PR binutils/20657
 135         * i386-dis.c (putop): Don't assign alt twice.
 136
 137 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 138
 139         PR target/20553
 140         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 141
 142 2016-09-29  Alan Modra  <amodra@gmail.com>
 143
 144         * ppc-opc.c (L): Make compulsory.
 145         (LOPT): New, optional form of L.
 146         (HTM_R): Define as LOPT.
 147         (L0, L1): Delete.
 148         (L32OPT): New, optional for 32-bit L.
 149         (L2OPT): New, 2-bit L for dcbf.
 150         (SVC_LEC): Update.
 151         (L2): Define.
 152         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 153         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 154         <dcbf>: Use L2OPT.
 155         <tlbiel, tlbie>: Use LOPT.
 156         <wclr, wclrall>: Use L2.
 157
 158 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 159
 160         * Makefile.in: Regenerate.
 161         * configure: Likewise.
 162
 163 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 164
 165         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 166         (EXTINSN2OP): Use EXTINSN2OPF.
 167         (bspeekm, bspop, modapp): New extension instructions.
 168         * arc-opc.c (F_DNZ_ND): Define.
 169         (F_DNZ_D): Likewise.
 170         (F_SIZEB1): Changed.
 171         (C_DNZ_D): Define.
 172         (C_HARD): Changed.
 173         * arc-tbl.h (dbnz): New instruction.
 174         (prealloc): Allow it for ARC EM.
 175         (xbfu): Likewise.
 176
 177 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 178
 179         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 180         after commas in addresses.
 181         (aarch64_print_operand): Likewise.
 182
 183 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 184
 185         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 186         rather than "should be" or "expected to be" in error messages.
 187
 188 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 189
 190         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 191         (print_mnemonic_name): ...here.
 192         (print_comment): New function.
 193         (print_aarch64_insn): Call it.
 194         * aarch64-opc.c (aarch64_conds): Add SVE names.
 195         (aarch64_print_operand): Print alternative condition names in
 196         a comment.
 197
 198 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 199
 200         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 201         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 202         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 203         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 204         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 205         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 206         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 207         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 208         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 209         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 210         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 211         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 212         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 213         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 214         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 215         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 216         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 217         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 218         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 219         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 220         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 221         (aarch64_feature_sve): New variable.
 222         (SVE): New macro.
 223         (_SVE_INSN): Likewise.
 224         (aarch64_opcode_table): Add SVE instructions.
 225         * aarch64-opc.h (extract_fields): Declare.
 226         * aarch64-opc-2.c: Regenerate.
 227         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 228         * aarch64-asm-2.c: Regenerate.
 229         * aarch64-dis.c (extract_fields): Make global.
 230         (do_misc_decoding): Handle the new SVE aarch64_ops.
 231         * aarch64-dis-2.c: Regenerate.
 232
 233 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 234
 235         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 236         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 237         aarch64_field_kinds.
 238         * aarch64-opc.c (fields): Add corresponding entries.
 239         * aarch64-asm.c (aarch64_get_variant): New function.
 240         (aarch64_encode_variant_using_iclass): Likewise.
 241         (aarch64_opcode_encode): Call it.
 242         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 243         (aarch64_opcode_decode): Call it.
 244
 245 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 246
 247         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 248         and FP register operands.
 249         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 250         (FLD_SVE_Vn): New aarch64_field_kinds.
 251         * aarch64-opc.c (fields): Add corresponding entries.
 252         (aarch64_print_operand): Handle the new SVE core and FP register
 253         operands.
 254         * aarch64-opc-2.c: Regenerate.
 255         * aarch64-asm-2.c: Likewise.
 256         * aarch64-dis-2.c: Likewise.
 257
 258 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 259
 260         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 261         immediate operands.
 262         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 263         * aarch64-opc.c (fields): Add corresponding entry.
 264         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 265         operands.
 266         (aarch64_print_operand): Likewise.
 267         * aarch64-opc-2.c: Regenerate.
 268         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 269         (ins_sve_float_zero_one): New inserters.
 270         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 271         (aarch64_ins_sve_float_half_two): Likewise.
 272         (aarch64_ins_sve_float_zero_one): Likewise.
 273         * aarch64-asm-2.c: Regenerate.
 274         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 275         (ext_sve_float_zero_one): New extractors.
 276         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 277         (aarch64_ext_sve_float_half_two): Likewise.
 278         (aarch64_ext_sve_float_zero_one): Likewise.
 279         * aarch64-dis-2.c: Regenerate.
 280
 281 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 282
 283         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 284         integer immediate operands.
 285         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 286         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 287         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 288         * aarch64-opc.c (fields): Add corresponding entries.
 289         (operand_general_constraint_met_p): Handle the new SVE integer
 290         immediate operands.
 291         (aarch64_print_operand): Likewise.
 292         (aarch64_sve_dupm_mov_immediate_p): New function.
 293         * aarch64-opc-2.c: Regenerate.
 294         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 295         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 296         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 297         (aarch64_ins_limm): ...here.
 298         (aarch64_ins_inv_limm): New function.
 299         (aarch64_ins_sve_aimm): Likewise.
 300         (aarch64_ins_sve_asimm): Likewise.
 301         (aarch64_ins_sve_limm_mov): Likewise.
 302         (aarch64_ins_sve_shlimm): Likewise.
 303         (aarch64_ins_sve_shrimm): Likewise.
 304         * aarch64-asm-2.c: Regenerate.
 305         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 306         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 307         * aarch64-dis.c (decode_limm): New function, split out from...
 308         (aarch64_ext_limm): ...here.
 309         (aarch64_ext_inv_limm): New function.
 310         (decode_sve_aimm): Likewise.
 311         (aarch64_ext_sve_aimm): Likewise.
 312         (aarch64_ext_sve_asimm): Likewise.
 313         (aarch64_ext_sve_limm_mov): Likewise.
 314         (aarch64_top_bit): Likewise.
 315         (aarch64_ext_sve_shlimm): Likewise.
 316         (aarch64_ext_sve_shrimm): Likewise.
 317         * aarch64-dis-2.c: Regenerate.
 318
 319 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 320
 321         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 322         operands.
 323         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 324         the AARCH64_MOD_MUL_VL entry.
 325         (value_aligned_p): Cope with non-power-of-two alignments.
 326         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 327         (print_immediate_offset_address): Likewise.
 328         (aarch64_print_operand): Likewise.
 329         * aarch64-opc-2.c: Regenerate.
 330         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 331         (ins_sve_addr_ri_s9xvl): New inserters.
 332         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 333         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 334         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 335         * aarch64-asm-2.c: Regenerate.
 336         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 337         (ext_sve_addr_ri_s9xvl): New extractors.
 338         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 339         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 340         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 341         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 342         * aarch64-dis-2.c: Regenerate.
 343
 344 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 345
 346         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 347         address operands.
 348         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 349         (FLD_SVE_xs_22): New aarch64_field_kinds.
 350         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 351         (get_operand_specific_data): New function.
 352         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 353         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 354         (operand_general_constraint_met_p): Handle the new SVE address
 355         operands.
 356         (sve_reg): New array.
 357         (get_addr_sve_reg_name): New function.
 358         (aarch64_print_operand): Handle the new SVE address operands.
 359         * aarch64-opc-2.c: Regenerate.
 360         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 361         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 362         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 363         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 364         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 365         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 366         (aarch64_ins_sve_addr_zi_u5): Likewise.
 367         (aarch64_ins_sve_addr_zz): Likewise.
 368         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 369         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 370         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 371         * aarch64-asm-2.c: Regenerate.
 372         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 373         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 374         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 375         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 376         (aarch64_ext_sve_addr_ri_u6): Likewise.
 377         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 378         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 379         (aarch64_ext_sve_addr_zi_u5): Likewise.
 380         (aarch64_ext_sve_addr_zz): Likewise.
 381         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 382         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 383         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 384         * aarch64-dis-2.c: Regenerate.
 385
 386 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 387
 388         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 389         AARCH64_OPND_SVE_PATTERN_SCALED.
 390         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 391         * aarch64-opc.c (fields): Add a corresponding entry.
 392         (set_multiplier_out_of_range_error): New function.
 393         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 394         (operand_general_constraint_met_p): Handle
 395         AARCH64_OPND_SVE_PATTERN_SCALED.
 396         (print_register_offset_address): Use PRIi64 to print the
 397         shift amount.
 398         (aarch64_print_operand): Likewise.  Handle
 399         AARCH64_OPND_SVE_PATTERN_SCALED.
 400         * aarch64-opc-2.c: Regenerate.
 401         * aarch64-asm.h (ins_sve_scale): New inserter.
 402         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 403         * aarch64-asm-2.c: Regenerate.
 404         * aarch64-dis.h (ext_sve_scale): New inserter.
 405         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 406         * aarch64-dis-2.c: Regenerate.
 407
 408 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 409
 410         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 411         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 412         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 413         (FLD_SVE_prfop): Likewise.
 414         * aarch64-opc.c: Include libiberty.h.
 415         (aarch64_sve_pattern_array): New variable.
 416         (aarch64_sve_prfop_array): Likewise.
 417         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 418         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 419         AARCH64_OPND_SVE_PRFOP.
 420         * aarch64-asm-2.c: Regenerate.
 421         * aarch64-dis-2.c: Likewise.
 422         * aarch64-opc-2.c: Likewise.
 423
 424 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 425
 426         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 427         AARCH64_OPND_QLF_P_[ZM].
 428         (aarch64_print_operand): Print /z and /m where appropriate.
 429
 430 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 431
 432         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 433         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 434         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 435         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 436         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 437         * aarch64-opc.c (fields): Add corresponding entries here.
 438         (operand_general_constraint_met_p): Check that SVE register lists
 439         have the correct length.  Check the ranges of SVE index registers.
 440         Check for cases where p8-p15 are used in 3-bit predicate fields.
 441         (aarch64_print_operand): Handle the new SVE operands.
 442         * aarch64-opc-2.c: Regenerate.
 443         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 444         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 445         (aarch64_ins_sve_reglist): Likewise.
 446         * aarch64-asm-2.c: Regenerate.
 447         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 448         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 449         (aarch64_ext_sve_reglist): Likewise.
 450         * aarch64-dis-2.c: Regenerate.
 451
 452 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 453
 454         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 455         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 456         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 457         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 458         tied operands.
 459
 460 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 461
 462         * aarch64-opc.c (get_offset_int_reg_name): New function.
 463         (print_immediate_offset_address): Likewise.
 464         (print_register_offset_address): Take the base and offset
 465         registers as parameters.
 466         (aarch64_print_operand): Update caller accordingly.  Use
 467         print_immediate_offset_address.
 468
 469 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 470
 471         * aarch64-opc.c (BANK): New macro.
 472         (R32, R64): Take a register number as argument
 473         (int_reg): Use BANK.
 474
 475 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 476
 477         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 478         (aarch64_print_operand): Update accordingly.
 479
 480 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 481
 482         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 483         for FPIMM.
 484         * aarch64-asm.h (ins_fpimm): New inserter.
 485         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 486         * aarch64-asm-2.c: Regenerate.
 487         * aarch64-dis.h (ext_fpimm): New extractor.
 488         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 489         (aarch64_ext_fpimm): New function.
 490         * aarch64-dis-2.c: Regenerate.
 491
 492 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 493
 494         * aarch64-asm.c: Include libiberty.h.
 495         (insert_fields): New function.
 496         (aarch64_ins_imm): Use it.
 497         * aarch64-dis.c (extract_fields): New function.
 498         (aarch64_ext_imm): Use it.
 499
 500 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 501
 502         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 503         with an esize parameter.
 504         (operand_general_constraint_met_p): Update accordingly.
 505         Fix misindented code.
 506         * aarch64-asm.c (aarch64_ins_limm): Update call to
 507         aarch64_logical_immediate_p.
 508
 509 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 510
 511         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 512
 513 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 514
 515         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 516
 517 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 518
 519         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 520
 521 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 522
 523         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 524         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 525         xor3>: Delete mnemonics.
 526         <cp_abort>: Rename mnemonic from ...
 527         <cpabort>: ...to this.
 528         <setb>: Change to a X form instruction.
 529         <sync>: Change to 1 operand form.
 530         <copy>: Delete mnemonic.
 531         <copy_first>: Rename mnemonic from ...
 532         <copy>: ...to this.
 533         <paste, paste.>: Delete mnemonics.
 534         <paste_last>: Rename mnemonic from ...
 535         <paste.>: ...to this.
 536
 537 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 538
 539         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 540
 541 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 542
 543         * s390-mkopc.c (main): Support alternate arch strings.
 544
 545 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 546
 547         * s390-opc.txt: Fix kmctr instruction type.
 548
 549 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 550
 551         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 552         * i386-init.h: Regenerated.
 553
 554 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 555
 556         * opcodes/arc-dis.c (print_insn_arc): Changed.
 557
 558 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 559
 560         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 561         camellia_fl.
 562
 563 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 564
 565         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 566         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 567         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 568
 569 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 570
 571         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 572         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 573         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 574         PREFIX_MOD_3_0FAE_REG_4.
 575         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 576         PREFIX_MOD_3_0FAE_REG_4.
 577         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 578         (cpu_flags): Add CpuPTWRITE.
 579         * i386-opc.h (CpuPTWRITE): New.
 580         (i386_cpu_flags): Add cpuptwrite.
 581         * i386-opc.tbl: Add ptwrite instruction.
 582         * i386-init.h: Regenerated.
 583         * i386-tbl.h: Likewise.
 584
 585 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 586
 587         * arc-dis.h: Wrap around in extern "C".
 588
 589 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 590
 591         * aarch64-tbl.h (V8_2_INSN): New macro.
 592         (aarch64_opcode_table): Use it.
 593
 594 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 595
 596         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 597         CORE_INSN, __FP_INSN and SIMD_INSN.
 598
 599 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 600
 601         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 602         (aarch64_opcode_table): Update uses accordingly.
 603
 604 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 605         Kwok Cheung Yeung  <kcy@codesourcery.com>
 606
 607         opcodes/
 608         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 609         'e_cmplwi' to 'e_cmpli' instead.
 610         (OPVUPRT, OPVUPRT_MASK): Define.
 611         (powerpc_opcodes): Add E200Z4 insns.
 612         (vle_opcodes): Add context save/restore insns.
 613
 614 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 615
 616         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 617         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 618         "j".
 619
 620 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 621
 622         * arc-nps400-tbl.h: Change block comments to GNU format.
 623         * arc-dis.c: Add new globals addrtypenames,
 624         addrtypenames_max, and addtypeunknown.
 625         (get_addrtype): New function.
 626         (print_insn_arc): Print colons and address types when
 627         required.
 628         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 629         define insert and extract functions for all address types.
 630         (arc_operands): Add operands for colon and all address
 631         types.
 632         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 633         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 634         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 635         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 636         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 637         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 638
 639 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 640
 641         * configure: Regenerated.
 642
 643 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 644
 645         * arc-dis.c (skipclass): New structure.
 646         (decodelist): New variable.
 647         (is_compatible_p): New function.
 648         (new_element): Likewise.
 649         (skip_class_p): Likewise.
 650         (find_format_from_table): Use skip_class_p function.
 651         (find_format): Decode first the extension instructions.
 652         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 653         e_flags.
 654         (parse_option): New function.
 655         (parse_disassembler_options): Likewise.
 656         (print_arc_disassembler_options): Likewise.
 657         (print_insn_arc): Use parse_disassembler_options function.  Proper
 658         select ARCv2 cpu variant.
 659         * disassemble.c (disassembler_usage): Add ARC disassembler
 660         options.
 661
 662 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 663
 664         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 665         annotation from the "nal" entry and reorder it beyond "bltzal".
 666
 667 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 668
 669         * sparc-opc.c (ldtxa): New macro.
 670         (sparc_opcodes): Use the macro defined above to add entries for
 671         the LDTXA instructions.
 672         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 673         instruction.
 674
 675 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 676
 677         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 678         and "jmpc".
 679
 680 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 681
 682         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 683         (movzb): Adjust to cover all permitted suffixes.
 684         (movzw): New.
 685         * i386-tbl.h: Re-generate.
 686
 687 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 688
 689         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 690         (lgdt): Remove Tbyte from non-64-bit variant.
 691         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 692         xsaves64, xsavec64): Remove Disp16.
 693         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 694         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 695         64-bit variants.
 696         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 697         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 698         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 699         64-bit variants.
 700         * i386-tbl.h: Re-generate.
 701
 702 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 703
 704         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 705         * i386-tbl.h: Re-generate.
 706
 707 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 708
 709         * arm-dis.c (print_insn): Fix typo in comment.
 710
 711 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 712
 713         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 714         range of ldst_elemlist operands.
 715         (print_register_list): Use PRIi64 to print the index.
 716         (aarch64_print_operand): Likewise.
 717
 718 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 719
 720         * mcore-opc.h: Remove sentinal.
 721         * mcore-dis.c (print_insn_mcore): Adjust.
 722
 723 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 724
 725         * arc-opc.c: Correct description of availability of NPS400
 726         features.
 727
 728 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 729
 730         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 731         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 732         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 733         xor3>: New mnemonics.
 734         <setb>: Change to a VX form instruction.
 735         (insert_sh6): Add support for rldixor.
 736         (extract_sh6): Likewise.
 737
 738 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 739
 740         * arc-ext.h: Wrap in extern C.
 741
 742 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 743
 744         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 745         Use same method for determining instruction length on ARC700 and
 746         NPS-400.
 747         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 748         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 749         with the NPS400 subclass.
 750         * arc-opc.c: Likewise.
 751
 752 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 753
 754         * sparc-opc.c (rdasr): New macro.
 755         (wrasr): Likewise.
 756         (rdpr): Likewise.
 757         (wrpr): Likewise.
 758         (rdhpr): Likewise.
 759         (wrhpr): Likewise.
 760         (sparc_opcodes): Use the macros above to fix and expand the
 761         definition of read/write instructions from/to
 762         asr/privileged/hyperprivileged instructions.
 763         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 764         %hva_mask_nz.  Prefer softint_set and softint_clear over
 765         set_softint and clear_softint.
 766         (print_insn_sparc): Support %ver in Rd.
 767
 768 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 769
 770         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 771         architecture according to the hardware capabilities they require.
 772
 773 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 774
 775         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 776         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 777         bfd_mach_sparc_v9{c,d,e,v,m}.
 778         * sparc-opc.c (MASK_V9C): Define.
 779         (MASK_V9D): Likewise.
 780         (MASK_V9E): Likewise.
 781         (MASK_V9V): Likewise.
 782         (MASK_V9M): Likewise.
 783         (v6): Add MASK_V9{C,D,E,V,M}.
 784         (v6notlet): Likewise.
 785         (v7): Likewise.
 786         (v8): Likewise.
 787         (v9): Likewise.
 788         (v9andleon): Likewise.
 789         (v9a): Likewise.
 790         (v9b): Likewise.
 791         (v9c): Define.
 792         (v9d): Likewise.
 793         (v9e): Likewise.
 794         (v9v): Likewise.
 795         (v9m): Likewise.
 796         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 797
 798 2016-06-15  Nick Clifton  <nickc@redhat.com>
 799
 800         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 801         constants to match expected behaviour.
 802         (nds32_parse_opcode): Likewise.  Also for whitespace.
 803
 804 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 805
 806         * arc-opc.c (extract_rhv1): Extract value from insn.
 807
 808 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 809
 810         * arc-nps400-tbl.h: Add ldbit instruction.
 811         * arc-opc.c: Add flag classes required for ldbit.
 812
 813 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 814
 815         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 816         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 817         support the above instructions.
 818
 819 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 820
 821         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 822         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 823         csma, cbba, zncv, and hofs.
 824         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 825         support the above instructions.
 826
 827 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 828
 829         * arc-nps400-tbl.h: Add andab and orab instructions.
 830
 831 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 832
 833         * arc-nps400-tbl.h: Add addl-like instructions.
 834
 835 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 836
 837         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 838
 839 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 840
 841         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 842         instructions.
 843
 844 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 845
 846         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 847         variable.
 848         (init_disasm): Handle new command line option "insnlength".
 849         (print_s390_disassembler_options): Mention new option in help
 850         output.
 851         (print_insn_s390): Use the encoded insn length when dumping
 852         unknown instructions.
 853
 854 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 855
 856         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 857          to the address and set as symbol address for LDS/ STS immediate operands.
 858
 859 2016-06-07  Alan Modra  <amodra@gmail.com>
 860
 861         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 862         cpu for "vle" to e500.
 863         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 864         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 865         (PPCNONE): Delete, substitute throughout.
 866         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 867         except for major opcode 4 and 31.
 868         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 869
 870 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 871
 872         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 873         ARM_EXT_RAS in relevant entries.
 874
 875 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 876
 877         PR binutils/20196
 878         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 879         opcodes for E6500.
 880
 881 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 882
 883         PR binutis/18386
 884         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 885         (indir_v_mode): New.
 886         Add comments for '&'.
 887         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 888         (putop): Handle '&'.
 889         (intel_operand_size): Handle indir_v_mode.
 890         (OP_E_register): Likewise.
 891         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 892         64-bit indirect call/jmp for AMD64.
 893         * i386-tbl.h: Regenerated
 894
 895 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 896
 897         * arc-dis.c (struct arc_operand_iterator): New structure.
 898         (find_format_from_table): All the old content from find_format,
 899         with some minor adjustments, and parameter renaming.
 900         (find_format_long_instructions): New function.
 901         (find_format): Rewritten.
 902         (arc_insn_length): Add LSB parameter.
 903         (extract_operand_value): New function.
 904         (operand_iterator_next): New function.
 905         (print_insn_arc): Use new functions to find opcode, and iterator
 906         over operands.
 907         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 908         (extract_nps_3bit_dst_short): New function.
 909         (insert_nps_3bit_src2_short): New function.
 910         (extract_nps_3bit_src2_short): New function.
 911         (insert_nps_bitop1_size): New function.
 912         (extract_nps_bitop1_size): New function.
 913         (insert_nps_bitop2_size): New function.
 914         (extract_nps_bitop2_size): New function.
 915         (insert_nps_bitop_mod4_msb): New function.
 916         (extract_nps_bitop_mod4_msb): New function.
 917         (insert_nps_bitop_mod4_lsb): New function.
 918         (extract_nps_bitop_mod4_lsb): New function.
 919         (insert_nps_bitop_dst_pos3_pos4): New function.
 920         (extract_nps_bitop_dst_pos3_pos4): New function.
 921         (insert_nps_bitop_ins_ext): New function.
 922         (extract_nps_bitop_ins_ext): New function.
 923         (arc_operands): Add new operands.
 924         (arc_long_opcodes): New global array.
 925         (arc_num_long_opcodes): New global.
 926         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 927
 928 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 929
 930         * nds32-asm.h: Add extern "C".
 931         * sh-opc.h: Likewise.
 932
 933 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 934
 935         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 936         0,b,limm to the rflt instruction.
 937
 938 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 939
 940         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 941         constant.
 942
 943 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 944
 945         PR gas/20145
 946         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 947         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 948         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 949         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 950         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 951         * i386-init.h: Regenerated.
 952
 953 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 954
 955         PR gas/20145
 956         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 957         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 958         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 959         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 960         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 961         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 962         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 963         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 964         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 965         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 966         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 967         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 968         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 969         CpuRegMask for AVX512.
 970         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 971         and CpuRegMask.
 972         (set_bitfield_from_cpu_flag_init): New function.
 973         (set_bitfield): Remove const on f.  Call
 974         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 975         * i386-opc.h (CpuRegMMX): New.
 976         (CpuRegXMM): Likewise.
 977         (CpuRegYMM): Likewise.
 978         (CpuRegZMM): Likewise.
 979         (CpuRegMask): Likewise.
 980         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 981         and cpuregmask.
 982         * i386-init.h: Regenerated.
 983         * i386-tbl.h: Likewise.
 984
 985 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 986
 987         PR gas/20154
 988         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 989         (opcode_modifiers): Add AMD64 and Intel64.
 990         (main): Properly verify CpuMax.
 991         * i386-opc.h (CpuAMD64): Removed.
 992         (CpuIntel64): Likewise.
 993         (CpuMax): Set to CpuNo64.
 994         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 995         (AMD64): New.
 996         (Intel64): Likewise.
 997         (i386_opcode_modifier): Add amd64 and intel64.
 998         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 999         on call and jmp.
1000         * i386-init.h: Regenerated.
1001         * i386-tbl.h: Likewise.
1002
1003 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1004
1005         PR gas/20154
1006         * i386-gen.c (main): Fail if CpuMax is incorrect.
1007         * i386-opc.h (CpuMax): Set to CpuIntel64.
1008         * i386-tbl.h: Regenerated.
1009
1010 2016-05-27  Nick Clifton  <nickc@redhat.com>
1011
1012         PR target/20150
1013         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1014         (msp430dis_opcode_unsigned): New function.
1015         (msp430dis_opcode_signed): New function.
1016         (msp430_singleoperand): Use the new opcode reading functions.
1017         Only disassenmble bytes if they were successfully read.
1018         (msp430_doubleoperand): Likewise.
1019         (msp430_branchinstr): Likewise.
1020         (msp430x_callx_instr): Likewise.
1021         (print_insn_msp430): Check that it is safe to read bytes before
1022         attempting disassembly.  Use the new opcode reading functions.
1023
1024 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1025
1026         * ppc-opc.c (CY): New define.  Document it.
1027         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1028
1029 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1030
1031         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1032         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1033         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1034         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1035         CPU_ANY_AVX_FLAGS.
1036         * i386-init.h: Regenerated.
1037
1038 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1039
1040         PR gas/20141
1041         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1042         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1043         * i386-init.h: Regenerated.
1044
1045 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1046
1047         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1048         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1049         * i386-init.h: Regenerated.
1050
1051 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1052
1053         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1054         information.
1055         (print_insn_arc): Set insn_type information.
1056         * arc-opc.c (C_CC): Add F_CLASS_COND.
1057         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1058         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1059         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1060         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1061         (brne, brne_s, jeq_s, jne_s): Likewise.
1062
1063 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1064
1065         * arc-tbl.h (neg): New instruction variant.
1066
1067 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1068
1069         * arc-dis.c (find_format, find_format, get_auxreg)
1070         (print_insn_arc): Changed.
1071         * arc-ext.h (INSERT_XOP): Likewise.
1072
1073 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1074
1075         * tic54x-dis.c (sprint_mmr): Adjust.
1076         * tic54x-opc.c: Likewise.
1077
1078 2016-05-19  Alan Modra  <amodra@gmail.com>
1079
1080         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1081
1082 2016-05-19  Alan Modra  <amodra@gmail.com>
1083
1084         * ppc-opc.c: Formatting.
1085         (NSISIGNOPT): Define.
1086         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1087
1088 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1089
1090         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1091         replacing references to `micromips_ase' throughout.
1092         (_print_insn_mips): Don't use file-level microMIPS annotation to
1093         determine the disassembly mode with the symbol table.
1094
1095 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1096
1097         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1098
1099 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1100
1101         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1102         mips64r6.
1103         * mips-opc.c (D34): New macro.
1104         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1105
1106 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1107
1108         * i386-dis.c (prefix_table): Add RDPID instruction.
1109         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1110         (cpu_flags): Add RDPID bitfield.
1111         * i386-opc.h (enum): Add RDPID element.
1112         (i386_cpu_flags): Add RDPID field.
1113         * i386-opc.tbl: Add RDPID instruction.
1114         * i386-init.h: Regenerate.
1115         * i386-tbl.h: Regenerate.
1116
1117 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1118
1119         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1120         branch type of a symbol.
1121         (print_insn): Likewise.
1122
1123 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1124
1125         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1126         Mainline Security Extensions instructions.
1127         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1128         Extensions instructions.
1129         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1130         instructions.
1131         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1132         special registers.
1133
1134 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1135
1136         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1137
1138 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1139
1140         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1141         (arcExtMap_genOpcode): Likewise.
1142         * arc-opc.c (arg_32bit_rc): Define new variable.
1143         (arg_32bit_u6): Likewise.
1144         (arg_32bit_limm): Likewise.
1145
1146 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1147
1148         * aarch64-gen.c (VERIFIER): Define.
1149         * aarch64-opc.c (VERIFIER): Define.
1150         (verify_ldpsw): Use static linkage.
1151         * aarch64-opc.h (verify_ldpsw): Remove.
1152         * aarch64-tbl.h: Use VERIFIER for verifiers.
1153
1154 2016-04-28  Nick Clifton  <nickc@redhat.com>
1155
1156         PR target/19722
1157         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1158         * aarch64-opc.c (verify_ldpsw): New function.
1159         * aarch64-opc.h (verify_ldpsw): New prototype.
1160         * aarch64-tbl.h: Add initialiser for verifier field.
1161         (LDPSW): Set verifier to verify_ldpsw.
1162
1163 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1164
1165         PR binutils/19983
1166         PR binutils/19984
1167         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1168         smaller than address size.
1169
1170 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1171
1172         * alpha-dis.c: Regenerate.
1173         * crx-dis.c: Likewise.
1174         * disassemble.c: Likewise.
1175         * epiphany-opc.c: Likewise.
1176         * fr30-opc.c: Likewise.
1177         * frv-opc.c: Likewise.
1178         * ip2k-opc.c: Likewise.
1179         * iq2000-opc.c: Likewise.
1180         * lm32-opc.c: Likewise.
1181         * lm32-opinst.c: Likewise.
1182         * m32c-opc.c: Likewise.
1183         * m32r-opc.c: Likewise.
1184         * m32r-opinst.c: Likewise.
1185         * mep-opc.c: Likewise.
1186         * mt-opc.c: Likewise.
1187         * or1k-opc.c: Likewise.
1188         * or1k-opinst.c: Likewise.
1189         * tic80-opc.c: Likewise.
1190         * xc16x-opc.c: Likewise.
1191         * xstormy16-opc.c: Likewise.
1192
1193 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1194
1195         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1196         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1197         calcsd, and calcxd instructions.
1198         * arc-opc.c (insert_nps_bitop_size): Delete.
1199         (extract_nps_bitop_size): Delete.
1200         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1201         (extract_nps_qcmp_m3): Define.
1202         (extract_nps_qcmp_m2): Define.
1203         (extract_nps_qcmp_m1): Define.
1204         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1205         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1206         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1207         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1208         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1209         NPS_QCMP_M3.
1210
1211 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1212
1213         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1214
1215 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1216
1217         * Makefile.in: Regenerated with automake 1.11.6.
1218         * aclocal.m4: Likewise.
1219
1220 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1221
1222         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1223         instructions.
1224         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1225         (extract_nps_cmem_uimm16): New function.
1226         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1227
1228 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1229
1230         * arc-dis.c (arc_insn_length): New function.
1231         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1232         (find_format): Change insnLen parameter to unsigned.
1233
1234 2016-04-13  Nick Clifton  <nickc@redhat.com>
1235
1236         PR target/19937
1237         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1238         the LD.B and LD.BU instructions.
1239
1240 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1241
1242         * arc-dis.c (find_format): Check for extension flags.
1243         (print_flags): New function.
1244         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1245         .extAuxRegister.
1246         * arc-ext.c (arcExtMap_coreRegName): Use
1247         LAST_EXTENSION_CORE_REGISTER.
1248         (arcExtMap_coreReadWrite): Likewise.
1249         (dump_ARC_extmap): Update printing.
1250         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1251         (arc_aux_regs): Add cpu field.
1252         * arc-regs.h: Add cpu field, lower case name aux registers.
1253
1254 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1255
1256         * arc-tbl.h: Add rtsc, sleep with no arguments.
1257
1258 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1259
1260         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1261         Initialize.
1262         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1263         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1264         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1265         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1266         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1267         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1268         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1269         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1270         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1271         (arc_opcode arc_opcodes): Null terminate the array.
1272         (arc_num_opcodes): Remove.
1273         * arc-ext.h (INSERT_XOP): Define.
1274         (extInstruction_t): Likewise.
1275         (arcExtMap_instName): Delete.
1276         (arcExtMap_insn): New function.
1277         (arcExtMap_genOpcode): Likewise.
1278         * arc-ext.c (ExtInstruction): Remove.
1279         (create_map): Zero initialize instruction fields.
1280         (arcExtMap_instName): Remove.
1281         (arcExtMap_insn): New function.
1282         (dump_ARC_extmap): More info while debuging.
1283         (arcExtMap_genOpcode): New function.
1284         * arc-dis.c (find_format): New function.
1285         (print_insn_arc): Use find_format.
1286         (arc_get_disassembler): Enable dump_ARC_extmap only when
1287         debugging.
1288
1289 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1290
1291         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1292         instruction bits out.
1293
1294 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1295
1296         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1297         * arc-opc.c (arc_flag_operands): Add new flags.
1298         (arc_flag_classes): Add new classes.
1299
1300 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1301
1302         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1303
1304 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1305
1306         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1307         encode1, rflt, crc16, and crc32 instructions.
1308         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1309         (arc_flag_classes): Add C_NPS_R.
1310         (insert_nps_bitop_size_2b): New function.
1311         (extract_nps_bitop_size_2b): Likewise.
1312         (insert_nps_bitop_uimm8): Likewise.
1313         (extract_nps_bitop_uimm8): Likewise.
1314         (arc_operands): Add new operand entries.
1315
1316 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1317
1318         * arc-regs.h: Add a new subclass field.  Add double assist
1319         accumulator register values.
1320         * arc-tbl.h: Use DPA subclass to mark the double assist
1321         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1322         * arc-opc.c (RSP): Define instead of SP.
1323         (arc_aux_regs): Add the subclass field.
1324
1325 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1326
1327         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1328
1329 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1330
1331         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1332         NPS_R_SRC1.
1333
1334 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1335
1336         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1337         issues.  No functional changes.
1338
1339 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1340
1341         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1342         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1343         (RTT): Remove duplicate.
1344         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1345         (PCT_CONFIG*): Remove.
1346         (D1L, D1H, D2H, D2L): Define.
1347
1348 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1349
1350         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1351
1352 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1353
1354         * arc-tbl.h (invld07): Remove.
1355         * arc-ext-tbl.h: New file.
1356         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1357         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1358
1359 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1360
1361         Fix -Wstack-usage warnings.
1362         * aarch64-dis.c (print_operands): Substitute size.
1363         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1364
1365 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1366
1367         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1368         to get a proper diagnostic when an invalid ASR register is used.
1369
1370 2016-03-22  Nick Clifton  <nickc@redhat.com>
1371
1372         * configure: Regenerate.
1373
1374 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1375
1376         * arc-nps400-tbl.h: New file.
1377         * arc-opc.c: Add top level comment.
1378         (insert_nps_3bit_dst): New function.
1379         (extract_nps_3bit_dst): New function.
1380         (insert_nps_3bit_src2): New function.
1381         (extract_nps_3bit_src2): New function.
1382         (insert_nps_bitop_size): New function.
1383         (extract_nps_bitop_size): New function.
1384         (arc_flag_operands): Add nps400 entries.
1385         (arc_flag_classes): Add nps400 entries.
1386         (arc_operands): Add nps400 entries.
1387         (arc_opcodes): Add nps400 include.
1388
1389 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1390
1391         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1392         the new class enum values.
1393
1394 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1395
1396         * arc-dis.c (print_insn_arc): Handle nps400.
1397
1398 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1399
1400         * arc-opc.c (BASE): Delete.
1401
1402 2016-03-18  Nick Clifton  <nickc@redhat.com>
1403
1404         PR target/19721
1405         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1406         of MOV insn that aliases an ORR insn.
1407
1408 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1409
1410         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1411
1412 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1413
1414         * mcore-opc.h: Add const qualifiers.
1415         * microblaze-opc.h (struct op_code_struct): Likewise.
1416         * sh-opc.h: Likewise.
1417         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1418         (tic4x_print_op): Likewise.
1419
1420 2016-03-02  Alan Modra  <amodra@gmail.com>
1421
1422         * or1k-desc.h: Regenerate.
1423         * fr30-ibld.c: Regenerate.
1424         * rl78-decode.c: Regenerate.
1425
1426 2016-03-01  Nick Clifton  <nickc@redhat.com>
1427
1428         PR target/19747
1429         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1430
1431 2016-02-24  Renlin Li  <renlin.li@arm.com>
1432
1433         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1434         (print_insn_coprocessor): Support fp16 instructions.
1435
1436 2016-02-24  Renlin Li  <renlin.li@arm.com>
1437
1438         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1439         vminnm, vrint(mpna).
1440
1441 2016-02-24  Renlin Li  <renlin.li@arm.com>
1442
1443         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1444         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1445
1446 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1447
1448         * i386-dis.c (print_insn): Parenthesize expression to prevent
1449         truncated addresses.
1450         (OP_J): Likewise.
1451
1452 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1453             Janek van Oirschot  <jvanoirs@synopsys.com>
1454
1455         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1456         variable.
1457
1458 2016-02-04  Nick Clifton  <nickc@redhat.com>
1459
1460         PR target/19561
1461         * msp430-dis.c (print_insn_msp430): Add a special case for
1462         decoding an RRC instruction with the ZC bit set in the extension
1463         word.
1464
1465 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1466
1467         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1468         * epiphany-ibld.c: Regenerate.
1469         * fr30-ibld.c: Regenerate.
1470         * frv-ibld.c: Regenerate.
1471         * ip2k-ibld.c: Regenerate.
1472         * iq2000-ibld.c: Regenerate.
1473         * lm32-ibld.c: Regenerate.
1474         * m32c-ibld.c: Regenerate.
1475         * m32r-ibld.c: Regenerate.
1476         * mep-ibld.c: Regenerate.
1477         * mt-ibld.c: Regenerate.
1478         * or1k-ibld.c: Regenerate.
1479         * xc16x-ibld.c: Regenerate.
1480         * xstormy16-ibld.c: Regenerate.
1481
1482 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1483
1484         * epiphany-dis.c: Regenerated from latest cpu files.
1485
1486 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1487
1488         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1489         test bit.
1490
1491 2016-01-25  Renlin Li  <renlin.li@arm.com>
1492
1493         * arm-dis.c (mapping_symbol_for_insn): New function.
1494         (find_ifthen_state): Call mapping_symbol_for_insn().
1495
1496 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1497
1498         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1499         of MSR UAO immediate operand.
1500
1501 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1502
1503         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1504         instruction support.
1505
1506 2016-01-17  Alan Modra  <amodra@gmail.com>
1507
1508         * configure: Regenerate.
1509
1510 2016-01-14  Nick Clifton  <nickc@redhat.com>
1511
1512         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1513         instructions that can support stack pointer operations.
1514         * rl78-decode.c: Regenerate.
1515         * rl78-dis.c: Fix display of stack pointer in MOVW based
1516         instructions.
1517
1518 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1519
1520         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1521         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1522         erxtatus_el1 and erxaddr_el1.
1523
1524 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1525
1526         * arm-dis.c (arm_opcodes): Add "esb".
1527         (thumb_opcodes): Likewise.
1528
1529 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1530
1531         * ppc-opc.c <xscmpnedp>: Delete.
1532         <xvcmpnedp>: Likewise.
1533         <xvcmpnedp.>: Likewise.
1534         <xvcmpnesp>: Likewise.
1535         <xvcmpnesp.>: Likewise.
1536
1537 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1538
1539         PR gas/13050
1540         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1541         addition to ISA_A.
1542
1543 2016-01-01  Alan Modra  <amodra@gmail.com>
1544
1545         Update year range in copyright notice of all files.
1546
1547 For older changes see ChangeLog-2015
1548 \f
1549 Copyright (C) 2016 Free Software Foundation, Inc.
1550
1551 Copying and distribution of this file, with or without modification,
1552 are permitted in any medium without royalty provided the copyright
1553 notice and this notice are preserved.
1554
1555 Local Variables:
1556 mode: change-log
1557 left-margin: 8
1558 fill-column: 74
1559 version-control: never
1560 End: