opcodes/ChangeLog

   1 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
   4         address operands.
   5         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
   6         (FLD_SVE_xs_22): New aarch64_field_kinds.
   7         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
   8         (get_operand_specific_data): New function.
   9         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
  10         FLD_SVE_xs_14 and FLD_SVE_xs_22.
  11         (operand_general_constraint_met_p): Handle the new SVE address
  12         operands.
  13         (sve_reg): New array.
  14         (get_addr_sve_reg_name): New function.
  15         (aarch64_print_operand): Handle the new SVE address operands.
  16         * aarch64-opc-2.c: Regenerate.
  17         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
  18         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
  19         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
  20         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
  21         (aarch64_ins_sve_addr_rr_lsl): Likewise.
  22         (aarch64_ins_sve_addr_rz_xtw): Likewise.
  23         (aarch64_ins_sve_addr_zi_u5): Likewise.
  24         (aarch64_ins_sve_addr_zz): Likewise.
  25         (aarch64_ins_sve_addr_zz_lsl): Likewise.
  26         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
  27         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
  28         * aarch64-asm-2.c: Regenerate.
  29         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
  30         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
  31         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
  32         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
  33         (aarch64_ext_sve_addr_ri_u6): Likewise.
  34         (aarch64_ext_sve_addr_rr_lsl): Likewise.
  35         (aarch64_ext_sve_addr_rz_xtw): Likewise.
  36         (aarch64_ext_sve_addr_zi_u5): Likewise.
  37         (aarch64_ext_sve_addr_zz): Likewise.
  38         (aarch64_ext_sve_addr_zz_lsl): Likewise.
  39         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
  40         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
  41         * aarch64-dis-2.c: Regenerate.
  42
  43 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  44
  45         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
  46         AARCH64_OPND_SVE_PATTERN_SCALED.
  47         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
  48         * aarch64-opc.c (fields): Add a corresponding entry.
  49         (set_multiplier_out_of_range_error): New function.
  50         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
  51         (operand_general_constraint_met_p): Handle
  52         AARCH64_OPND_SVE_PATTERN_SCALED.
  53         (print_register_offset_address): Use PRIi64 to print the
  54         shift amount.
  55         (aarch64_print_operand): Likewise.  Handle
  56         AARCH64_OPND_SVE_PATTERN_SCALED.
  57         * aarch64-opc-2.c: Regenerate.
  58         * aarch64-asm.h (ins_sve_scale): New inserter.
  59         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
  60         * aarch64-asm-2.c: Regenerate.
  61         * aarch64-dis.h (ext_sve_scale): New inserter.
  62         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
  63         * aarch64-dis-2.c: Regenerate.
  64
  65 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  66
  67         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
  68         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
  69         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
  70         (FLD_SVE_prfop): Likewise.
  71         * aarch64-opc.c: Include libiberty.h.
  72         (aarch64_sve_pattern_array): New variable.
  73         (aarch64_sve_prfop_array): Likewise.
  74         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
  75         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
  76         AARCH64_OPND_SVE_PRFOP.
  77         * aarch64-asm-2.c: Regenerate.
  78         * aarch64-dis-2.c: Likewise.
  79         * aarch64-opc-2.c: Likewise.
  80
  81 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  82
  83         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
  84         AARCH64_OPND_QLF_P_[ZM].
  85         (aarch64_print_operand): Print /z and /m where appropriate.
  86
  87 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  88
  89         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
  90         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
  91         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
  92         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
  93         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
  94         * aarch64-opc.c (fields): Add corresponding entries here.
  95         (operand_general_constraint_met_p): Check that SVE register lists
  96         have the correct length.  Check the ranges of SVE index registers.
  97         Check for cases where p8-p15 are used in 3-bit predicate fields.
  98         (aarch64_print_operand): Handle the new SVE operands.
  99         * aarch64-opc-2.c: Regenerate.
 100         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 101         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 102         (aarch64_ins_sve_reglist): Likewise.
 103         * aarch64-asm-2.c: Regenerate.
 104         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 105         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 106         (aarch64_ext_sve_reglist): Likewise.
 107         * aarch64-dis-2.c: Regenerate.
 108
 109 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 110
 111         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 112         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 113         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 114         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 115         tied operands.
 116
 117 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 118
 119         * aarch64-opc.c (get_offset_int_reg_name): New function.
 120         (print_immediate_offset_address): Likewise.
 121         (print_register_offset_address): Take the base and offset
 122         registers as parameters.
 123         (aarch64_print_operand): Update caller accordingly.  Use
 124         print_immediate_offset_address.
 125
 126 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 127
 128         * aarch64-opc.c (BANK): New macro.
 129         (R32, R64): Take a register number as argument
 130         (int_reg): Use BANK.
 131
 132 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 133
 134         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 135         (aarch64_print_operand): Update accordingly.
 136
 137 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 138
 139         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 140         for FPIMM.
 141         * aarch64-asm.h (ins_fpimm): New inserter.
 142         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 143         * aarch64-asm-2.c: Regenerate.
 144         * aarch64-dis.h (ext_fpimm): New extractor.
 145         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 146         (aarch64_ext_fpimm): New function.
 147         * aarch64-dis-2.c: Regenerate.
 148
 149 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 150
 151         * aarch64-asm.c: Include libiberty.h.
 152         (insert_fields): New function.
 153         (aarch64_ins_imm): Use it.
 154         * aarch64-dis.c (extract_fields): New function.
 155         (aarch64_ext_imm): Use it.
 156
 157 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 158
 159         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 160         with an esize parameter.
 161         (operand_general_constraint_met_p): Update accordingly.
 162         Fix misindented code.
 163         * aarch64-asm.c (aarch64_ins_limm): Update call to
 164         aarch64_logical_immediate_p.
 165
 166 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 167
 168         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 169
 170 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 171
 172         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 173
 174 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 175
 176         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 177
 178 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 179
 180         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 181         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 182         xor3>: Delete mnemonics.
 183         <cp_abort>: Rename mnemonic from ...
 184         <cpabort>: ...to this.
 185         <setb>: Change to a X form instruction.
 186         <sync>: Change to 1 operand form.
 187         <copy>: Delete mnemonic.
 188         <copy_first>: Rename mnemonic from ...
 189         <copy>: ...to this.
 190         <paste, paste.>: Delete mnemonics.
 191         <paste_last>: Rename mnemonic from ...
 192         <paste.>: ...to this.
 193
 194 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 195
 196         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 197
 198 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 199
 200         * s390-mkopc.c (main): Support alternate arch strings.
 201
 202 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 203
 204         * s390-opc.txt: Fix kmctr instruction type.
 205
 206 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 207
 208         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 209         * i386-init.h: Regenerated.
 210
 211 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 212
 213         * opcodes/arc-dis.c (print_insn_arc): Changed.
 214
 215 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 216
 217         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 218         camellia_fl.
 219
 220 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 221
 222         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 223         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 224         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 225
 226 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 227
 228         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 229         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 230         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 231         PREFIX_MOD_3_0FAE_REG_4.
 232         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 233         PREFIX_MOD_3_0FAE_REG_4.
 234         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 235         (cpu_flags): Add CpuPTWRITE.
 236         * i386-opc.h (CpuPTWRITE): New.
 237         (i386_cpu_flags): Add cpuptwrite.
 238         * i386-opc.tbl: Add ptwrite instruction.
 239         * i386-init.h: Regenerated.
 240         * i386-tbl.h: Likewise.
 241
 242 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 243
 244         * arc-dis.h: Wrap around in extern "C".
 245
 246 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 247
 248         * aarch64-tbl.h (V8_2_INSN): New macro.
 249         (aarch64_opcode_table): Use it.
 250
 251 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 252
 253         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 254         CORE_INSN, __FP_INSN and SIMD_INSN.
 255
 256 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 257
 258         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 259         (aarch64_opcode_table): Update uses accordingly.
 260
 261 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 262         Kwok Cheung Yeung  <kcy@codesourcery.com>
 263
 264         opcodes/
 265         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 266         'e_cmplwi' to 'e_cmpli' instead.
 267         (OPVUPRT, OPVUPRT_MASK): Define.
 268         (powerpc_opcodes): Add E200Z4 insns.
 269         (vle_opcodes): Add context save/restore insns.
 270
 271 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 272
 273         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 274         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 275         "j".
 276
 277 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 278
 279         * arc-nps400-tbl.h: Change block comments to GNU format.
 280         * arc-dis.c: Add new globals addrtypenames,
 281         addrtypenames_max, and addtypeunknown.
 282         (get_addrtype): New function.
 283         (print_insn_arc): Print colons and address types when
 284         required.
 285         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 286         define insert and extract functions for all address types.
 287         (arc_operands): Add operands for colon and all address
 288         types.
 289         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 290         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 291         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 292         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 293         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 294         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 295
 296 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 297
 298         * configure: Regenerated.
 299
 300 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 301
 302         * arc-dis.c (skipclass): New structure.
 303         (decodelist): New variable.
 304         (is_compatible_p): New function.
 305         (new_element): Likewise.
 306         (skip_class_p): Likewise.
 307         (find_format_from_table): Use skip_class_p function.
 308         (find_format): Decode first the extension instructions.
 309         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 310         e_flags.
 311         (parse_option): New function.
 312         (parse_disassembler_options): Likewise.
 313         (print_arc_disassembler_options): Likewise.
 314         (print_insn_arc): Use parse_disassembler_options function.  Proper
 315         select ARCv2 cpu variant.
 316         * disassemble.c (disassembler_usage): Add ARC disassembler
 317         options.
 318
 319 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 320
 321         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 322         annotation from the "nal" entry and reorder it beyond "bltzal".
 323
 324 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 325
 326         * sparc-opc.c (ldtxa): New macro.
 327         (sparc_opcodes): Use the macro defined above to add entries for
 328         the LDTXA instructions.
 329         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 330         instruction.
 331
 332 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 333
 334         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 335         and "jmpc".
 336
 337 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 338
 339         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 340         (movzb): Adjust to cover all permitted suffixes.
 341         (movzw): New.
 342         * i386-tbl.h: Re-generate.
 343
 344 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 345
 346         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 347         (lgdt): Remove Tbyte from non-64-bit variant.
 348         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 349         xsaves64, xsavec64): Remove Disp16.
 350         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 351         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 352         64-bit variants.
 353         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 354         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 355         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 356         64-bit variants.
 357         * i386-tbl.h: Re-generate.
 358
 359 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 360
 361         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 362         * i386-tbl.h: Re-generate.
 363
 364 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 365
 366         * arm-dis.c (print_insn): Fix typo in comment.
 367
 368 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 369
 370         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 371         range of ldst_elemlist operands.
 372         (print_register_list): Use PRIi64 to print the index.
 373         (aarch64_print_operand): Likewise.
 374
 375 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 376
 377         * mcore-opc.h: Remove sentinal.
 378         * mcore-dis.c (print_insn_mcore): Adjust.
 379
 380 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 381
 382         * arc-opc.c: Correct description of availability of NPS400
 383         features.
 384
 385 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 386
 387         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 388         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 389         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 390         xor3>: New mnemonics.
 391         <setb>: Change to a VX form instruction.
 392         (insert_sh6): Add support for rldixor.
 393         (extract_sh6): Likewise.
 394
 395 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 396
 397         * arc-ext.h: Wrap in extern C.
 398
 399 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 400
 401         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 402         Use same method for determining instruction length on ARC700 and
 403         NPS-400.
 404         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 405         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 406         with the NPS400 subclass.
 407         * arc-opc.c: Likewise.
 408
 409 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 410
 411         * sparc-opc.c (rdasr): New macro.
 412         (wrasr): Likewise.
 413         (rdpr): Likewise.
 414         (wrpr): Likewise.
 415         (rdhpr): Likewise.
 416         (wrhpr): Likewise.
 417         (sparc_opcodes): Use the macros above to fix and expand the
 418         definition of read/write instructions from/to
 419         asr/privileged/hyperprivileged instructions.
 420         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 421         %hva_mask_nz.  Prefer softint_set and softint_clear over
 422         set_softint and clear_softint.
 423         (print_insn_sparc): Support %ver in Rd.
 424
 425 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 426
 427         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 428         architecture according to the hardware capabilities they require.
 429
 430 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 431
 432         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 433         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 434         bfd_mach_sparc_v9{c,d,e,v,m}.
 435         * sparc-opc.c (MASK_V9C): Define.
 436         (MASK_V9D): Likewise.
 437         (MASK_V9E): Likewise.
 438         (MASK_V9V): Likewise.
 439         (MASK_V9M): Likewise.
 440         (v6): Add MASK_V9{C,D,E,V,M}.
 441         (v6notlet): Likewise.
 442         (v7): Likewise.
 443         (v8): Likewise.
 444         (v9): Likewise.
 445         (v9andleon): Likewise.
 446         (v9a): Likewise.
 447         (v9b): Likewise.
 448         (v9c): Define.
 449         (v9d): Likewise.
 450         (v9e): Likewise.
 451         (v9v): Likewise.
 452         (v9m): Likewise.
 453         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 454
 455 2016-06-15  Nick Clifton  <nickc@redhat.com>
 456
 457         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 458         constants to match expected behaviour.
 459         (nds32_parse_opcode): Likewise.  Also for whitespace.
 460
 461 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 462
 463         * arc-opc.c (extract_rhv1): Extract value from insn.
 464
 465 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 466
 467         * arc-nps400-tbl.h: Add ldbit instruction.
 468         * arc-opc.c: Add flag classes required for ldbit.
 469
 470 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 471
 472         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 473         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 474         support the above instructions.
 475
 476 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 477
 478         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 479         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 480         csma, cbba, zncv, and hofs.
 481         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 482         support the above instructions.
 483
 484 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 485
 486         * arc-nps400-tbl.h: Add andab and orab instructions.
 487
 488 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 489
 490         * arc-nps400-tbl.h: Add addl-like instructions.
 491
 492 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 493
 494         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 495
 496 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 497
 498         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 499         instructions.
 500
 501 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 502
 503         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 504         variable.
 505         (init_disasm): Handle new command line option "insnlength".
 506         (print_s390_disassembler_options): Mention new option in help
 507         output.
 508         (print_insn_s390): Use the encoded insn length when dumping
 509         unknown instructions.
 510
 511 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 512
 513         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 514          to the address and set as symbol address for LDS/ STS immediate operands.
 515
 516 2016-06-07  Alan Modra  <amodra@gmail.com>
 517
 518         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 519         cpu for "vle" to e500.
 520         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 521         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 522         (PPCNONE): Delete, substitute throughout.
 523         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 524         except for major opcode 4 and 31.
 525         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 526
 527 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 528
 529         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 530         ARM_EXT_RAS in relevant entries.
 531
 532 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 533
 534         PR binutils/20196
 535         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 536         opcodes for E6500.
 537
 538 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 539
 540         PR binutis/18386
 541         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 542         (indir_v_mode): New.
 543         Add comments for '&'.
 544         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 545         (putop): Handle '&'.
 546         (intel_operand_size): Handle indir_v_mode.
 547         (OP_E_register): Likewise.
 548         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 549         64-bit indirect call/jmp for AMD64.
 550         * i386-tbl.h: Regenerated
 551
 552 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 553
 554         * arc-dis.c (struct arc_operand_iterator): New structure.
 555         (find_format_from_table): All the old content from find_format,
 556         with some minor adjustments, and parameter renaming.
 557         (find_format_long_instructions): New function.
 558         (find_format): Rewritten.
 559         (arc_insn_length): Add LSB parameter.
 560         (extract_operand_value): New function.
 561         (operand_iterator_next): New function.
 562         (print_insn_arc): Use new functions to find opcode, and iterator
 563         over operands.
 564         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 565         (extract_nps_3bit_dst_short): New function.
 566         (insert_nps_3bit_src2_short): New function.
 567         (extract_nps_3bit_src2_short): New function.
 568         (insert_nps_bitop1_size): New function.
 569         (extract_nps_bitop1_size): New function.
 570         (insert_nps_bitop2_size): New function.
 571         (extract_nps_bitop2_size): New function.
 572         (insert_nps_bitop_mod4_msb): New function.
 573         (extract_nps_bitop_mod4_msb): New function.
 574         (insert_nps_bitop_mod4_lsb): New function.
 575         (extract_nps_bitop_mod4_lsb): New function.
 576         (insert_nps_bitop_dst_pos3_pos4): New function.
 577         (extract_nps_bitop_dst_pos3_pos4): New function.
 578         (insert_nps_bitop_ins_ext): New function.
 579         (extract_nps_bitop_ins_ext): New function.
 580         (arc_operands): Add new operands.
 581         (arc_long_opcodes): New global array.
 582         (arc_num_long_opcodes): New global.
 583         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 584
 585 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 586
 587         * nds32-asm.h: Add extern "C".
 588         * sh-opc.h: Likewise.
 589
 590 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 591
 592         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 593         0,b,limm to the rflt instruction.
 594
 595 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 596
 597         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 598         constant.
 599
 600 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 601
 602         PR gas/20145
 603         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 604         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 605         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 606         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 607         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 608         * i386-init.h: Regenerated.
 609
 610 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 611
 612         PR gas/20145
 613         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 614         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 615         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 616         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 617         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 618         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 619         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 620         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 621         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 622         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 623         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 624         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 625         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 626         CpuRegMask for AVX512.
 627         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 628         and CpuRegMask.
 629         (set_bitfield_from_cpu_flag_init): New function.
 630         (set_bitfield): Remove const on f.  Call
 631         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 632         * i386-opc.h (CpuRegMMX): New.
 633         (CpuRegXMM): Likewise.
 634         (CpuRegYMM): Likewise.
 635         (CpuRegZMM): Likewise.
 636         (CpuRegMask): Likewise.
 637         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 638         and cpuregmask.
 639         * i386-init.h: Regenerated.
 640         * i386-tbl.h: Likewise.
 641
 642 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 643
 644         PR gas/20154
 645         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 646         (opcode_modifiers): Add AMD64 and Intel64.
 647         (main): Properly verify CpuMax.
 648         * i386-opc.h (CpuAMD64): Removed.
 649         (CpuIntel64): Likewise.
 650         (CpuMax): Set to CpuNo64.
 651         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 652         (AMD64): New.
 653         (Intel64): Likewise.
 654         (i386_opcode_modifier): Add amd64 and intel64.
 655         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 656         on call and jmp.
 657         * i386-init.h: Regenerated.
 658         * i386-tbl.h: Likewise.
 659
 660 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 661
 662         PR gas/20154
 663         * i386-gen.c (main): Fail if CpuMax is incorrect.
 664         * i386-opc.h (CpuMax): Set to CpuIntel64.
 665         * i386-tbl.h: Regenerated.
 666
 667 2016-05-27  Nick Clifton  <nickc@redhat.com>
 668
 669         PR target/20150
 670         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 671         (msp430dis_opcode_unsigned): New function.
 672         (msp430dis_opcode_signed): New function.
 673         (msp430_singleoperand): Use the new opcode reading functions.
 674         Only disassenmble bytes if they were successfully read.
 675         (msp430_doubleoperand): Likewise.
 676         (msp430_branchinstr): Likewise.
 677         (msp430x_callx_instr): Likewise.
 678         (print_insn_msp430): Check that it is safe to read bytes before
 679         attempting disassembly.  Use the new opcode reading functions.
 680
 681 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 682
 683         * ppc-opc.c (CY): New define.  Document it.
 684         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 685
 686 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 687
 688         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 689         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 690         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 691         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 692         CPU_ANY_AVX_FLAGS.
 693         * i386-init.h: Regenerated.
 694
 695 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 696
 697         PR gas/20141
 698         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 699         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 700         * i386-init.h: Regenerated.
 701
 702 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 703
 704         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 705         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 706         * i386-init.h: Regenerated.
 707
 708 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 709
 710         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 711         information.
 712         (print_insn_arc): Set insn_type information.
 713         * arc-opc.c (C_CC): Add F_CLASS_COND.
 714         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 715         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 716         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 717         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 718         (brne, brne_s, jeq_s, jne_s): Likewise.
 719
 720 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 721
 722         * arc-tbl.h (neg): New instruction variant.
 723
 724 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 725
 726         * arc-dis.c (find_format, find_format, get_auxreg)
 727         (print_insn_arc): Changed.
 728         * arc-ext.h (INSERT_XOP): Likewise.
 729
 730 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 731
 732         * tic54x-dis.c (sprint_mmr): Adjust.
 733         * tic54x-opc.c: Likewise.
 734
 735 2016-05-19  Alan Modra  <amodra@gmail.com>
 736
 737         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 738
 739 2016-05-19  Alan Modra  <amodra@gmail.com>
 740
 741         * ppc-opc.c: Formatting.
 742         (NSISIGNOPT): Define.
 743         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 744
 745 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 746
 747         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 748         replacing references to `micromips_ase' throughout.
 749         (_print_insn_mips): Don't use file-level microMIPS annotation to
 750         determine the disassembly mode with the symbol table.
 751
 752 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 753
 754         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 755
 756 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 757
 758         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 759         mips64r6.
 760         * mips-opc.c (D34): New macro.
 761         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 762
 763 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 764
 765         * i386-dis.c (prefix_table): Add RDPID instruction.
 766         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 767         (cpu_flags): Add RDPID bitfield.
 768         * i386-opc.h (enum): Add RDPID element.
 769         (i386_cpu_flags): Add RDPID field.
 770         * i386-opc.tbl: Add RDPID instruction.
 771         * i386-init.h: Regenerate.
 772         * i386-tbl.h: Regenerate.
 773
 774 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 775
 776         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 777         branch type of a symbol.
 778         (print_insn): Likewise.
 779
 780 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 781
 782         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 783         Mainline Security Extensions instructions.
 784         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 785         Extensions instructions.
 786         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 787         instructions.
 788         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 789         special registers.
 790
 791 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 792
 793         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 794
 795 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 796
 797         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 798         (arcExtMap_genOpcode): Likewise.
 799         * arc-opc.c (arg_32bit_rc): Define new variable.
 800         (arg_32bit_u6): Likewise.
 801         (arg_32bit_limm): Likewise.
 802
 803 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 804
 805         * aarch64-gen.c (VERIFIER): Define.
 806         * aarch64-opc.c (VERIFIER): Define.
 807         (verify_ldpsw): Use static linkage.
 808         * aarch64-opc.h (verify_ldpsw): Remove.
 809         * aarch64-tbl.h: Use VERIFIER for verifiers.
 810
 811 2016-04-28  Nick Clifton  <nickc@redhat.com>
 812
 813         PR target/19722
 814         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 815         * aarch64-opc.c (verify_ldpsw): New function.
 816         * aarch64-opc.h (verify_ldpsw): New prototype.
 817         * aarch64-tbl.h: Add initialiser for verifier field.
 818         (LDPSW): Set verifier to verify_ldpsw.
 819
 820 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 821
 822         PR binutils/19983
 823         PR binutils/19984
 824         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 825         smaller than address size.
 826
 827 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 828
 829         * alpha-dis.c: Regenerate.
 830         * crx-dis.c: Likewise.
 831         * disassemble.c: Likewise.
 832         * epiphany-opc.c: Likewise.
 833         * fr30-opc.c: Likewise.
 834         * frv-opc.c: Likewise.
 835         * ip2k-opc.c: Likewise.
 836         * iq2000-opc.c: Likewise.
 837         * lm32-opc.c: Likewise.
 838         * lm32-opinst.c: Likewise.
 839         * m32c-opc.c: Likewise.
 840         * m32r-opc.c: Likewise.
 841         * m32r-opinst.c: Likewise.
 842         * mep-opc.c: Likewise.
 843         * mt-opc.c: Likewise.
 844         * or1k-opc.c: Likewise.
 845         * or1k-opinst.c: Likewise.
 846         * tic80-opc.c: Likewise.
 847         * xc16x-opc.c: Likewise.
 848         * xstormy16-opc.c: Likewise.
 849
 850 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 851
 852         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 853         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 854         calcsd, and calcxd instructions.
 855         * arc-opc.c (insert_nps_bitop_size): Delete.
 856         (extract_nps_bitop_size): Delete.
 857         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 858         (extract_nps_qcmp_m3): Define.
 859         (extract_nps_qcmp_m2): Define.
 860         (extract_nps_qcmp_m1): Define.
 861         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 862         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 863         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 864         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 865         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 866         NPS_QCMP_M3.
 867
 868 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 869
 870         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 871
 872 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 873
 874         * Makefile.in: Regenerated with automake 1.11.6.
 875         * aclocal.m4: Likewise.
 876
 877 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 878
 879         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 880         instructions.
 881         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 882         (extract_nps_cmem_uimm16): New function.
 883         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 884
 885 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 886
 887         * arc-dis.c (arc_insn_length): New function.
 888         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 889         (find_format): Change insnLen parameter to unsigned.
 890
 891 2016-04-13  Nick Clifton  <nickc@redhat.com>
 892
 893         PR target/19937
 894         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 895         the LD.B and LD.BU instructions.
 896
 897 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 898
 899         * arc-dis.c (find_format): Check for extension flags.
 900         (print_flags): New function.
 901         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 902         .extAuxRegister.
 903         * arc-ext.c (arcExtMap_coreRegName): Use
 904         LAST_EXTENSION_CORE_REGISTER.
 905         (arcExtMap_coreReadWrite): Likewise.
 906         (dump_ARC_extmap): Update printing.
 907         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 908         (arc_aux_regs): Add cpu field.
 909         * arc-regs.h: Add cpu field, lower case name aux registers.
 910
 911 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 912
 913         * arc-tbl.h: Add rtsc, sleep with no arguments.
 914
 915 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 916
 917         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 918         Initialize.
 919         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 920         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 921         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 922         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 923         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 924         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 925         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 926         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 927         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 928         (arc_opcode arc_opcodes): Null terminate the array.
 929         (arc_num_opcodes): Remove.
 930         * arc-ext.h (INSERT_XOP): Define.
 931         (extInstruction_t): Likewise.
 932         (arcExtMap_instName): Delete.
 933         (arcExtMap_insn): New function.
 934         (arcExtMap_genOpcode): Likewise.
 935         * arc-ext.c (ExtInstruction): Remove.
 936         (create_map): Zero initialize instruction fields.
 937         (arcExtMap_instName): Remove.
 938         (arcExtMap_insn): New function.
 939         (dump_ARC_extmap): More info while debuging.
 940         (arcExtMap_genOpcode): New function.
 941         * arc-dis.c (find_format): New function.
 942         (print_insn_arc): Use find_format.
 943         (arc_get_disassembler): Enable dump_ARC_extmap only when
 944         debugging.
 945
 946 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 947
 948         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 949         instruction bits out.
 950
 951 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 952
 953         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 954         * arc-opc.c (arc_flag_operands): Add new flags.
 955         (arc_flag_classes): Add new classes.
 956
 957 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 958
 959         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 960
 961 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 962
 963         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 964         encode1, rflt, crc16, and crc32 instructions.
 965         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 966         (arc_flag_classes): Add C_NPS_R.
 967         (insert_nps_bitop_size_2b): New function.
 968         (extract_nps_bitop_size_2b): Likewise.
 969         (insert_nps_bitop_uimm8): Likewise.
 970         (extract_nps_bitop_uimm8): Likewise.
 971         (arc_operands): Add new operand entries.
 972
 973 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 974
 975         * arc-regs.h: Add a new subclass field.  Add double assist
 976         accumulator register values.
 977         * arc-tbl.h: Use DPA subclass to mark the double assist
 978         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 979         * arc-opc.c (RSP): Define instead of SP.
 980         (arc_aux_regs): Add the subclass field.
 981
 982 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 983
 984         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 985
 986 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 987
 988         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 989         NPS_R_SRC1.
 990
 991 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 992
 993         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 994         issues.  No functional changes.
 995
 996 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 997
 998         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 999         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1000         (RTT): Remove duplicate.
1001         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1002         (PCT_CONFIG*): Remove.
1003         (D1L, D1H, D2H, D2L): Define.
1004
1005 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1006
1007         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1008
1009 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1010
1011         * arc-tbl.h (invld07): Remove.
1012         * arc-ext-tbl.h: New file.
1013         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1014         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1015
1016 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1017
1018         Fix -Wstack-usage warnings.
1019         * aarch64-dis.c (print_operands): Substitute size.
1020         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1021
1022 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1023
1024         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1025         to get a proper diagnostic when an invalid ASR register is used.
1026
1027 2016-03-22  Nick Clifton  <nickc@redhat.com>
1028
1029         * configure: Regenerate.
1030
1031 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1032
1033         * arc-nps400-tbl.h: New file.
1034         * arc-opc.c: Add top level comment.
1035         (insert_nps_3bit_dst): New function.
1036         (extract_nps_3bit_dst): New function.
1037         (insert_nps_3bit_src2): New function.
1038         (extract_nps_3bit_src2): New function.
1039         (insert_nps_bitop_size): New function.
1040         (extract_nps_bitop_size): New function.
1041         (arc_flag_operands): Add nps400 entries.
1042         (arc_flag_classes): Add nps400 entries.
1043         (arc_operands): Add nps400 entries.
1044         (arc_opcodes): Add nps400 include.
1045
1046 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1047
1048         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1049         the new class enum values.
1050
1051 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1052
1053         * arc-dis.c (print_insn_arc): Handle nps400.
1054
1055 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1056
1057         * arc-opc.c (BASE): Delete.
1058
1059 2016-03-18  Nick Clifton  <nickc@redhat.com>
1060
1061         PR target/19721
1062         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1063         of MOV insn that aliases an ORR insn.
1064
1065 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1066
1067         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1068
1069 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1070
1071         * mcore-opc.h: Add const qualifiers.
1072         * microblaze-opc.h (struct op_code_struct): Likewise.
1073         * sh-opc.h: Likewise.
1074         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1075         (tic4x_print_op): Likewise.
1076
1077 2016-03-02  Alan Modra  <amodra@gmail.com>
1078
1079         * or1k-desc.h: Regenerate.
1080         * fr30-ibld.c: Regenerate.
1081         * rl78-decode.c: Regenerate.
1082
1083 2016-03-01  Nick Clifton  <nickc@redhat.com>
1084
1085         PR target/19747
1086         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1087
1088 2016-02-24  Renlin Li  <renlin.li@arm.com>
1089
1090         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1091         (print_insn_coprocessor): Support fp16 instructions.
1092
1093 2016-02-24  Renlin Li  <renlin.li@arm.com>
1094
1095         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1096         vminnm, vrint(mpna).
1097
1098 2016-02-24  Renlin Li  <renlin.li@arm.com>
1099
1100         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1101         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1102
1103 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1104
1105         * i386-dis.c (print_insn): Parenthesize expression to prevent
1106         truncated addresses.
1107         (OP_J): Likewise.
1108
1109 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1110             Janek van Oirschot  <jvanoirs@synopsys.com>
1111
1112         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1113         variable.
1114
1115 2016-02-04  Nick Clifton  <nickc@redhat.com>
1116
1117         PR target/19561
1118         * msp430-dis.c (print_insn_msp430): Add a special case for
1119         decoding an RRC instruction with the ZC bit set in the extension
1120         word.
1121
1122 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1123
1124         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1125         * epiphany-ibld.c: Regenerate.
1126         * fr30-ibld.c: Regenerate.
1127         * frv-ibld.c: Regenerate.
1128         * ip2k-ibld.c: Regenerate.
1129         * iq2000-ibld.c: Regenerate.
1130         * lm32-ibld.c: Regenerate.
1131         * m32c-ibld.c: Regenerate.
1132         * m32r-ibld.c: Regenerate.
1133         * mep-ibld.c: Regenerate.
1134         * mt-ibld.c: Regenerate.
1135         * or1k-ibld.c: Regenerate.
1136         * xc16x-ibld.c: Regenerate.
1137         * xstormy16-ibld.c: Regenerate.
1138
1139 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1140
1141         * epiphany-dis.c: Regenerated from latest cpu files.
1142
1143 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1144
1145         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1146         test bit.
1147
1148 2016-01-25  Renlin Li  <renlin.li@arm.com>
1149
1150         * arm-dis.c (mapping_symbol_for_insn): New function.
1151         (find_ifthen_state): Call mapping_symbol_for_insn().
1152
1153 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1154
1155         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1156         of MSR UAO immediate operand.
1157
1158 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1159
1160         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1161         instruction support.
1162
1163 2016-01-17  Alan Modra  <amodra@gmail.com>
1164
1165         * configure: Regenerate.
1166
1167 2016-01-14  Nick Clifton  <nickc@redhat.com>
1168
1169         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1170         instructions that can support stack pointer operations.
1171         * rl78-decode.c: Regenerate.
1172         * rl78-dis.c: Fix display of stack pointer in MOVW based
1173         instructions.
1174
1175 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1176
1177         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1178         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1179         erxtatus_el1 and erxaddr_el1.
1180
1181 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1182
1183         * arm-dis.c (arm_opcodes): Add "esb".
1184         (thumb_opcodes): Likewise.
1185
1186 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1187
1188         * ppc-opc.c <xscmpnedp>: Delete.
1189         <xvcmpnedp>: Likewise.
1190         <xvcmpnedp.>: Likewise.
1191         <xvcmpnesp>: Likewise.
1192         <xvcmpnesp.>: Likewise.
1193
1194 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1195
1196         PR gas/13050
1197         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1198         addition to ISA_A.
1199
1200 2016-01-01  Alan Modra  <amodra@gmail.com>
1201
1202         Update year range in copyright notice of all files.
1203
1204 For older changes see ChangeLog-2015
1205 \f
1206 Copyright (C) 2016 Free Software Foundation, Inc.
1207
1208 Copying and distribution of this file, with or without modification,
1209 are permitted in any medium without royalty provided the copyright
1210 notice and this notice are preserved.
1211
1212 Local Variables:
1213 mode: change-log
1214 left-margin: 8
1215 fill-column: 74
1216 version-control: never
1217 End: