opcodes/ChangeLog

   1 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
   4         to separate `extend' and its uninterpreted argument output.
   5         Separate hexadecimal halves of undecoded extended instructions
   6         output.
   7
   8 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
   9
  10         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
  11         indentation space across.
  12
  13 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  14
  15         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
  16         adjustment for PC-relative operations following MIPS16e compact
  17         jumps or undefined RR/J(AL)R(C) encodings.
  18
  19 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  20
  21         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
  22         variable to `reglane_index'.
  23
  24 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
  25
  26         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
  27
  28 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  29
  30         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
  31
  32 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  33
  34         * mips16-opc.c (mips16_opcodes): Update comment naming structure
  35         members.
  36
  37 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  38
  39         * mips-dis.c (print_mips_disassembler_options): Reformat output.
  40
  41 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  42
  43         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
  44         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
  45
  46 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  47
  48         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
  49
  50 2016-12-01  Nick Clifton  <nickc@redhat.com>
  51
  52         PR binutils/20893
  53         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
  54         opcode designator.
  55
  56 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  57
  58         * arc-opc.c (insert_ra_chk): New function.
  59         (insert_rb_chk): Likewise.
  60         (insert_rad): Update text error message.
  61         (insert_rcd): Likewise.
  62         (insert_rhv2): Likewise.
  63         (insert_r0): Likewise.
  64         (insert_r1): Likewise.
  65         (insert_r2): Likewise.
  66         (insert_r3): Likewise.
  67         (insert_sp): Likewise.
  68         (insert_gp): Likewise.
  69         (insert_pcl): Likewise.
  70         (insert_blink): Likewise.
  71         (insert_ilink1): Likewise.
  72         (insert_ilink2): Likewise.
  73         (insert_ras): Likewise.
  74         (insert_rbs): Likewise.
  75         (insert_rcs): Likewise.
  76         (insert_simm3s): Likewise.
  77         (insert_rrange): Likewise.
  78         (insert_fpel): Likewise.
  79         (insert_blinkel): Likewise.
  80         (insert_pcel): Likewise.
  81         (insert_nps_3bit_dst): Likewise.
  82         (insert_nps_3bit_dst_short): Likewise.
  83         (insert_nps_3bit_src2_short): Likewise.
  84         (insert_nps_bitop_size_2b): Likewise.
  85         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
  86         (RA_CHK): Define.
  87         (RB): Adjust.
  88         (RB_CHK): Define.
  89         (RC): Adjust.
  90         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
  91         * arc-tbl.h (div, divu): All instructions are DIVREM class.
  92         Change first insn argument to check for LP_COUNT usage.
  93         (rem): Likewise.
  94         (ld, ldd): All instructions are LOAD class.  Change first insn
  95         argument to check for LP_COUNT usage.
  96         (st, std): All instructions are STORE class.
  97         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
  98         Change first insn argument to check for LP_COUNT usage.
  99         (mov): All instructions are MOVE class.  Change first insn
 100         argument to check for LP_COUNT usage.
 101
 102 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 103
 104         * arc-dis.c (is_compatible_p): Remove function.
 105         (skip_this_opcode): Don't add any decoding class to decode list.
 106         Remove warning.
 107         (find_format_from_table): Go through all opcodes, and warn if we
 108         use a guessed mnemonic.
 109
 110 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 111             Amit Pawar  <amit.pawar@amd.com>
 112
 113         PR binutils/20637
 114         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 115         instructions.
 116
 117 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 118
 119         * configure: Regenerate.
 120
 121 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 122
 123         * sparc-opc.c (HWS_V8): Definition moved from
 124         gas/config/tc-sparc.c.
 125         (HWS_V9): Likewise.
 126         (HWS_VA): Likewise.
 127         (HWS_VB): Likewise.
 128         (HWS_VC): Likewise.
 129         (HWS_VD): Likewise.
 130         (HWS_VE): Likewise.
 131         (HWS_VV): Likewise.
 132         (HWS_VM): Likewise.
 133         (HWS2_VM): Likewise.
 134         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 135         existing entries.
 136
 137 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 138
 139         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 140         instructions.
 141
 142 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 143
 144         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 145         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 146         (aarch64_opcode_table): Add fcmla and fcadd.
 147         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 148         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 149         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 150         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 151         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 152         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 153         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 154         (operand_general_constraint_met_p): Rotate and index range check.
 155         (aarch64_print_operand): Handle rotate operand.
 156         * aarch64-asm-2.c: Regenerate.
 157         * aarch64-dis-2.c: Likewise.
 158         * aarch64-opc-2.c: Likewise.
 159
 160 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 161
 162         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 163         * aarch64-asm-2.c: Regenerate.
 164         * aarch64-dis-2.c: Regenerate.
 165         * aarch64-opc-2.c: Regenerate.
 166
 167 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 168
 169         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 170         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 171         * aarch64-asm-2.c: Regenerate.
 172         * aarch64-dis-2.c: Regenerate.
 173         * aarch64-opc-2.c: Regenerate.
 174
 175 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 176
 177         * aarch64-tbl.h (QL_X1NIL): New.
 178         (arch64_opcode_table): Add ldraa, ldrab.
 179         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 180         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 181         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 182         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 183         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 184         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 185         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 186         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 187         (aarch64_print_operand): Likewise.
 188         * aarch64-asm-2.c: Regenerate.
 189         * aarch64-dis-2.c: Regenerate.
 190         * aarch64-opc-2.c: Regenerate.
 191
 192 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 193
 194         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 195         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 196         * aarch64-asm-2.c: Regenerate.
 197         * aarch64-dis-2.c: Regenerate.
 198         * aarch64-opc-2.c: Regenerate.
 199
 200 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 201
 202         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 203         (AARCH64_OPERANDS): Add Rm_SP.
 204         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 205         * aarch64-asm-2.c: Regenerate.
 206         * aarch64-dis-2.c: Regenerate.
 207         * aarch64-opc-2.c: Regenerate.
 208
 209 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 210
 211         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 212         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 213         autdzb, xpaci, xpacd.
 214         * aarch64-asm-2.c: Regenerate.
 215         * aarch64-dis-2.c: Regenerate.
 216         * aarch64-opc-2.c: Regenerate.
 217
 218 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 219
 220         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 221         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 222         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 223         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 224
 225 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 226
 227         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 228         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 229         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 230         autibsp.
 231         * aarch64-asm-2.c: Regenerate.
 232         * aarch64-dis-2.c: Regenerate.
 233
 234 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 235
 236         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 237
 238 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 239
 240         PR binutils/20799
 241         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 242         * i386-dis.c (EdqwS): Removed.
 243         (dqw_swap_mode): Likewise.
 244         (intel_operand_size): Don't check dqw_swap_mode.
 245         (OP_E_register): Likewise.
 246         (OP_E_memory): Likewise.
 247         (OP_G): Likewise.
 248         (OP_EX): Likewise.
 249         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 250         * i386-tbl.h: Regerated.
 251
 252 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 253
 254         * i386-opc.tbl: Merge AVX512F vmovq.
 255         * i386-tbl.h: Regerated.
 256
 257 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 258
 259         PR binutils/20701
 260         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 261         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 262         (three_byte_table): Remove THREE_BYTE_0F7A.
 263
 264 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 265
 266         PR binutils/20775
 267         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 268         (FGRPd9_4): Replace 1 with 2.
 269         (FGRPd9_5): Replace 2 with 3.
 270         (FGRPd9_6): Replace 3 with 4.
 271         (FGRPd9_7): Replace 4 with 5.
 272         (FGRPda_5): Replace 5 with 6.
 273         (FGRPdb_4): Replace 6 with 7.
 274         (FGRPde_3): Replace 7 with 8.
 275         (FGRPdf_4): Replace 8 with 9.
 276         (fgrps): Add an entry for Bad_Opcode.
 277
 278 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 279
 280         * arc-opc.c (arc_flag_operands): Add F_DI14.
 281         (arc_flag_classes): Add C_DI14.
 282         * arc-nps400-tbl.h: Add new exc instructions.
 283
 284 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 285
 286         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 287         major opcode 0xa.
 288         * arc-nps-400-tbl.h: Add dcmac instruction.
 289         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 290         (insert_nps_rbdouble_64): Added.
 291         (extract_nps_rbdouble_64): Added.
 292         (insert_nps_proto_size): Added.
 293         (extract_nps_proto_size): Added.
 294
 295 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 296
 297         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 298         relating to long instruction processing, add new limm field.
 299         (OPCODE): Rename to...
 300         (OPCODE_32BIT_INSN): ...this.
 301         (OPCODE_AC): Delete.
 302         (skip_this_opcode): Handle different instruction lengths, update
 303         macro name.
 304         (special_flag_p): Update parameter type.
 305         (find_format_from_table): Update for more instruction lengths.
 306         (find_format_long_instructions): Delete.
 307         (find_format): Update for more instruction lengths.
 308         (arc_insn_length): Likewise.
 309         (extract_operand_value): Update for more instruction lengths.
 310         (operand_iterator_next): Remove code relating to long
 311         instructions.
 312         (arc_opcode_to_insn_type): New function.
 313         (print_insn_arc):Update for more instructions lengths.
 314         * arc-ext.c (extInstruction_t): Change argument type.
 315         * arc-ext.h (extInstruction_t): Change argument type.
 316         * arc-fxi.h: Change type unsigned to unsigned long long
 317         extensively throughout.
 318         * arc-nps400-tbl.h: Add long instructions taken from
 319         arc_long_opcodes table in arc-opc.c.
 320         * arc-opc.c: Update parameter types on insert/extract handlers.
 321         (arc_long_opcodes): Delete.
 322         (arc_num_long_opcodes): Delete.
 323         (arc_opcode_len): Update for more instruction lengths.
 324
 325 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 326
 327         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 328
 329 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 330
 331         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 332         with arc_opcode_len.
 333         (find_format_long_instructions): Likewise.
 334         * arc-opc.c (arc_opcode_len): New function.
 335
 336 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 337
 338         * arc-nps400-tbl.h: Fix some instruction masks.
 339
 340 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 341
 342         * i386-dis.c (REG_82): Removed.
 343         (X86_64_82_REG_0): Likewise.
 344         (X86_64_82_REG_1): Likewise.
 345         (X86_64_82_REG_2): Likewise.
 346         (X86_64_82_REG_3): Likewise.
 347         (X86_64_82_REG_4): Likewise.
 348         (X86_64_82_REG_5): Likewise.
 349         (X86_64_82_REG_6): Likewise.
 350         (X86_64_82_REG_7): Likewise.
 351         (X86_64_82): New.
 352         (dis386): Use X86_64_82 instead of REG_82.
 353         (reg_table): Remove REG_82.
 354         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 355         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 356         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 357         X86_64_82_REG_7.
 358
 359 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 360
 361         PR binutils/20754
 362         * i386-dis.c (REG_82): New.
 363         (X86_64_82_REG_0): Likewise.
 364         (X86_64_82_REG_1): Likewise.
 365         (X86_64_82_REG_2): Likewise.
 366         (X86_64_82_REG_3): Likewise.
 367         (X86_64_82_REG_4): Likewise.
 368         (X86_64_82_REG_5): Likewise.
 369         (X86_64_82_REG_6): Likewise.
 370         (X86_64_82_REG_7): Likewise.
 371         (dis386): Use REG_82.
 372         (reg_table): Add REG_82.
 373         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 374         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 375         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 376
 377 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 378
 379         * i386-dis.c (REG_82): Renamed to ...
 380         (REG_83): This.
 381         (dis386): Updated.
 382         (reg_table): Likewise.
 383
 384 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 385
 386         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 387         * i386-dis-evex.h (evex_table): Updated.
 388         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 389         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 390         (cpu_flags): Add CpuAVX512_4VNNIW.
 391         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 392         (i386_cpu_flags): Add cpuavx512_4vnniw.
 393         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 394         * i386-init.h: Regenerate.
 395         * i386-tbl.h: Ditto.
 396
 397 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 398
 399         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 400         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 401         * i386-dis-evex.h (evex_table): Updated.
 402         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 403         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 404         (cpu_flags): Add CpuAVX512_4FMAPS.
 405         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 406         * i386-opc.h (AVX512_4FMAP): New.
 407         (i386_cpu_flags): Add cpuavx512_4fmaps.
 408         (ImplicitQuadGroup): New.
 409         (i386_opcode_modifier): Add implicitquadgroup.
 410         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 411         * i386-init.h: Regenerate.
 412         * i386-tbl.h: Ditto.
 413
 414 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 415             Andrew Waterman <andrew@sifive.com>
 416
 417         Add support for RISC-V architecture.
 418         * configure.ac: Add entry for bfd_riscv_arch.
 419         * configure: Regenerate.
 420         * disassemble.c (disassembler): Add support for riscv.
 421         (disassembler_usage): Likewise.
 422         * riscv-dis.c: New file.
 423         * riscv-opc.c: New file.
 424
 425 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 426
 427         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 428         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 429         (rm_table): Update the RM_0FAE_REG_7 entry.
 430         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 431         (cpu_flags): Remove CpuPCOMMIT.
 432         * i386-opc.h (CpuPCOMMIT): Removed.
 433         (i386_cpu_flags): Remove cpupcommit.
 434         * i386-opc.tbl: Remove pcommit.
 435         * i386-init.h: Regenerated.
 436         * i386-tbl.h: Likewise.
 437
 438 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 439
 440         PR binutis/20705
 441         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 442         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 443         32-bit mode.  Don't check vex.register_specifier in 32-bit
 444         mode.
 445         (OP_VEX): Check for invalid mask registers.
 446
 447 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 448
 449         PR binutis/20699
 450         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 451         sizeflag.
 452
 453 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 454
 455         PR binutis/20704
 456         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 457
 458 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 459
 460         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 461         local variable to `index_regno'.
 462
 463 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 464
 465         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 466
 467 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 468
 469         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 470         usage on ISA basis.
 471
 472 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 473
 474         PR target/20666
 475         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 476
 477 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 478
 479         PR target/20667
 480         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 481         available.
 482
 483 2016-10-07  Alan Modra  <amodra@gmail.com>
 484
 485         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 486
 487 2016-10-06  Alan Modra  <amodra@gmail.com>
 488
 489         * aarch64-opc.c: Spell fall through comments consistently.
 490         * i386-dis.c: Likewise.
 491         * aarch64-dis.c: Add missing fall through comments.
 492         * aarch64-opc.c: Likewise.
 493         * arc-dis.c: Likewise.
 494         * arm-dis.c: Likewise.
 495         * i386-dis.c: Likewise.
 496         * m68k-dis.c: Likewise.
 497         * mep-asm.c: Likewise.
 498         * ns32k-dis.c: Likewise.
 499         * sh-dis.c: Likewise.
 500         * tic4x-dis.c: Likewise.
 501         * tic6x-dis.c: Likewise.
 502         * vax-dis.c: Likewise.
 503
 504 2016-10-06  Alan Modra  <amodra@gmail.com>
 505
 506         * arc-ext.c (create_map): Add missing break.
 507         * msp430-decode.opc (encode_as): Likewise.
 508         * msp430-decode.c: Regenerate.
 509
 510 2016-10-06  Alan Modra  <amodra@gmail.com>
 511
 512         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 513         * crx-dis.c (print_insn_crx): Likewise.
 514
 515 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 516
 517         PR binutils/20657
 518         * i386-dis.c (putop): Don't assign alt twice.
 519
 520 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 521
 522         PR target/20553
 523         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 524
 525 2016-09-29  Alan Modra  <amodra@gmail.com>
 526
 527         * ppc-opc.c (L): Make compulsory.
 528         (LOPT): New, optional form of L.
 529         (HTM_R): Define as LOPT.
 530         (L0, L1): Delete.
 531         (L32OPT): New, optional for 32-bit L.
 532         (L2OPT): New, 2-bit L for dcbf.
 533         (SVC_LEC): Update.
 534         (L2): Define.
 535         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 536         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 537         <dcbf>: Use L2OPT.
 538         <tlbiel, tlbie>: Use LOPT.
 539         <wclr, wclrall>: Use L2.
 540
 541 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 542
 543         * Makefile.in: Regenerate.
 544         * configure: Likewise.
 545
 546 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 547
 548         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 549         (EXTINSN2OP): Use EXTINSN2OPF.
 550         (bspeekm, bspop, modapp): New extension instructions.
 551         * arc-opc.c (F_DNZ_ND): Define.
 552         (F_DNZ_D): Likewise.
 553         (F_SIZEB1): Changed.
 554         (C_DNZ_D): Define.
 555         (C_HARD): Changed.
 556         * arc-tbl.h (dbnz): New instruction.
 557         (prealloc): Allow it for ARC EM.
 558         (xbfu): Likewise.
 559
 560 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 561
 562         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 563         after commas in addresses.
 564         (aarch64_print_operand): Likewise.
 565
 566 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 567
 568         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 569         rather than "should be" or "expected to be" in error messages.
 570
 571 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 572
 573         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 574         (print_mnemonic_name): ...here.
 575         (print_comment): New function.
 576         (print_aarch64_insn): Call it.
 577         * aarch64-opc.c (aarch64_conds): Add SVE names.
 578         (aarch64_print_operand): Print alternative condition names in
 579         a comment.
 580
 581 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 582
 583         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 584         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 585         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 586         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 587         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 588         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 589         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 590         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 591         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 592         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 593         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 594         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 595         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 596         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 597         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 598         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 599         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 600         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 601         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 602         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 603         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 604         (aarch64_feature_sve): New variable.
 605         (SVE): New macro.
 606         (_SVE_INSN): Likewise.
 607         (aarch64_opcode_table): Add SVE instructions.
 608         * aarch64-opc.h (extract_fields): Declare.
 609         * aarch64-opc-2.c: Regenerate.
 610         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 611         * aarch64-asm-2.c: Regenerate.
 612         * aarch64-dis.c (extract_fields): Make global.
 613         (do_misc_decoding): Handle the new SVE aarch64_ops.
 614         * aarch64-dis-2.c: Regenerate.
 615
 616 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 617
 618         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 619         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 620         aarch64_field_kinds.
 621         * aarch64-opc.c (fields): Add corresponding entries.
 622         * aarch64-asm.c (aarch64_get_variant): New function.
 623         (aarch64_encode_variant_using_iclass): Likewise.
 624         (aarch64_opcode_encode): Call it.
 625         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 626         (aarch64_opcode_decode): Call it.
 627
 628 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 629
 630         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 631         and FP register operands.
 632         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 633         (FLD_SVE_Vn): New aarch64_field_kinds.
 634         * aarch64-opc.c (fields): Add corresponding entries.
 635         (aarch64_print_operand): Handle the new SVE core and FP register
 636         operands.
 637         * aarch64-opc-2.c: Regenerate.
 638         * aarch64-asm-2.c: Likewise.
 639         * aarch64-dis-2.c: Likewise.
 640
 641 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 642
 643         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 644         immediate operands.
 645         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 646         * aarch64-opc.c (fields): Add corresponding entry.
 647         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 648         operands.
 649         (aarch64_print_operand): Likewise.
 650         * aarch64-opc-2.c: Regenerate.
 651         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 652         (ins_sve_float_zero_one): New inserters.
 653         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 654         (aarch64_ins_sve_float_half_two): Likewise.
 655         (aarch64_ins_sve_float_zero_one): Likewise.
 656         * aarch64-asm-2.c: Regenerate.
 657         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 658         (ext_sve_float_zero_one): New extractors.
 659         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 660         (aarch64_ext_sve_float_half_two): Likewise.
 661         (aarch64_ext_sve_float_zero_one): Likewise.
 662         * aarch64-dis-2.c: Regenerate.
 663
 664 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 665
 666         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 667         integer immediate operands.
 668         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 669         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 670         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 671         * aarch64-opc.c (fields): Add corresponding entries.
 672         (operand_general_constraint_met_p): Handle the new SVE integer
 673         immediate operands.
 674         (aarch64_print_operand): Likewise.
 675         (aarch64_sve_dupm_mov_immediate_p): New function.
 676         * aarch64-opc-2.c: Regenerate.
 677         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 678         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 679         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 680         (aarch64_ins_limm): ...here.
 681         (aarch64_ins_inv_limm): New function.
 682         (aarch64_ins_sve_aimm): Likewise.
 683         (aarch64_ins_sve_asimm): Likewise.
 684         (aarch64_ins_sve_limm_mov): Likewise.
 685         (aarch64_ins_sve_shlimm): Likewise.
 686         (aarch64_ins_sve_shrimm): Likewise.
 687         * aarch64-asm-2.c: Regenerate.
 688         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 689         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 690         * aarch64-dis.c (decode_limm): New function, split out from...
 691         (aarch64_ext_limm): ...here.
 692         (aarch64_ext_inv_limm): New function.
 693         (decode_sve_aimm): Likewise.
 694         (aarch64_ext_sve_aimm): Likewise.
 695         (aarch64_ext_sve_asimm): Likewise.
 696         (aarch64_ext_sve_limm_mov): Likewise.
 697         (aarch64_top_bit): Likewise.
 698         (aarch64_ext_sve_shlimm): Likewise.
 699         (aarch64_ext_sve_shrimm): Likewise.
 700         * aarch64-dis-2.c: Regenerate.
 701
 702 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 703
 704         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 705         operands.
 706         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 707         the AARCH64_MOD_MUL_VL entry.
 708         (value_aligned_p): Cope with non-power-of-two alignments.
 709         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 710         (print_immediate_offset_address): Likewise.
 711         (aarch64_print_operand): Likewise.
 712         * aarch64-opc-2.c: Regenerate.
 713         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 714         (ins_sve_addr_ri_s9xvl): New inserters.
 715         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 716         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 717         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 718         * aarch64-asm-2.c: Regenerate.
 719         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 720         (ext_sve_addr_ri_s9xvl): New extractors.
 721         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 722         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 723         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 724         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 725         * aarch64-dis-2.c: Regenerate.
 726
 727 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 728
 729         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 730         address operands.
 731         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 732         (FLD_SVE_xs_22): New aarch64_field_kinds.
 733         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 734         (get_operand_specific_data): New function.
 735         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 736         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 737         (operand_general_constraint_met_p): Handle the new SVE address
 738         operands.
 739         (sve_reg): New array.
 740         (get_addr_sve_reg_name): New function.
 741         (aarch64_print_operand): Handle the new SVE address operands.
 742         * aarch64-opc-2.c: Regenerate.
 743         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 744         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 745         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 746         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 747         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 748         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 749         (aarch64_ins_sve_addr_zi_u5): Likewise.
 750         (aarch64_ins_sve_addr_zz): Likewise.
 751         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 752         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 753         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 754         * aarch64-asm-2.c: Regenerate.
 755         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 756         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 757         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 758         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 759         (aarch64_ext_sve_addr_ri_u6): Likewise.
 760         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 761         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 762         (aarch64_ext_sve_addr_zi_u5): Likewise.
 763         (aarch64_ext_sve_addr_zz): Likewise.
 764         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 765         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 766         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 767         * aarch64-dis-2.c: Regenerate.
 768
 769 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 770
 771         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 772         AARCH64_OPND_SVE_PATTERN_SCALED.
 773         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 774         * aarch64-opc.c (fields): Add a corresponding entry.
 775         (set_multiplier_out_of_range_error): New function.
 776         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 777         (operand_general_constraint_met_p): Handle
 778         AARCH64_OPND_SVE_PATTERN_SCALED.
 779         (print_register_offset_address): Use PRIi64 to print the
 780         shift amount.
 781         (aarch64_print_operand): Likewise.  Handle
 782         AARCH64_OPND_SVE_PATTERN_SCALED.
 783         * aarch64-opc-2.c: Regenerate.
 784         * aarch64-asm.h (ins_sve_scale): New inserter.
 785         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 786         * aarch64-asm-2.c: Regenerate.
 787         * aarch64-dis.h (ext_sve_scale): New inserter.
 788         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 789         * aarch64-dis-2.c: Regenerate.
 790
 791 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 792
 793         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 794         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 795         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 796         (FLD_SVE_prfop): Likewise.
 797         * aarch64-opc.c: Include libiberty.h.
 798         (aarch64_sve_pattern_array): New variable.
 799         (aarch64_sve_prfop_array): Likewise.
 800         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 801         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 802         AARCH64_OPND_SVE_PRFOP.
 803         * aarch64-asm-2.c: Regenerate.
 804         * aarch64-dis-2.c: Likewise.
 805         * aarch64-opc-2.c: Likewise.
 806
 807 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 808
 809         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 810         AARCH64_OPND_QLF_P_[ZM].
 811         (aarch64_print_operand): Print /z and /m where appropriate.
 812
 813 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 814
 815         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 816         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 817         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 818         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 819         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 820         * aarch64-opc.c (fields): Add corresponding entries here.
 821         (operand_general_constraint_met_p): Check that SVE register lists
 822         have the correct length.  Check the ranges of SVE index registers.
 823         Check for cases where p8-p15 are used in 3-bit predicate fields.
 824         (aarch64_print_operand): Handle the new SVE operands.
 825         * aarch64-opc-2.c: Regenerate.
 826         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 827         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 828         (aarch64_ins_sve_reglist): Likewise.
 829         * aarch64-asm-2.c: Regenerate.
 830         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 831         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 832         (aarch64_ext_sve_reglist): Likewise.
 833         * aarch64-dis-2.c: Regenerate.
 834
 835 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 836
 837         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 838         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 839         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 840         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 841         tied operands.
 842
 843 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 844
 845         * aarch64-opc.c (get_offset_int_reg_name): New function.
 846         (print_immediate_offset_address): Likewise.
 847         (print_register_offset_address): Take the base and offset
 848         registers as parameters.
 849         (aarch64_print_operand): Update caller accordingly.  Use
 850         print_immediate_offset_address.
 851
 852 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 853
 854         * aarch64-opc.c (BANK): New macro.
 855         (R32, R64): Take a register number as argument
 856         (int_reg): Use BANK.
 857
 858 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 859
 860         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 861         (aarch64_print_operand): Update accordingly.
 862
 863 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 864
 865         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 866         for FPIMM.
 867         * aarch64-asm.h (ins_fpimm): New inserter.
 868         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 869         * aarch64-asm-2.c: Regenerate.
 870         * aarch64-dis.h (ext_fpimm): New extractor.
 871         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 872         (aarch64_ext_fpimm): New function.
 873         * aarch64-dis-2.c: Regenerate.
 874
 875 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 876
 877         * aarch64-asm.c: Include libiberty.h.
 878         (insert_fields): New function.
 879         (aarch64_ins_imm): Use it.
 880         * aarch64-dis.c (extract_fields): New function.
 881         (aarch64_ext_imm): Use it.
 882
 883 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 884
 885         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 886         with an esize parameter.
 887         (operand_general_constraint_met_p): Update accordingly.
 888         Fix misindented code.
 889         * aarch64-asm.c (aarch64_ins_limm): Update call to
 890         aarch64_logical_immediate_p.
 891
 892 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 893
 894         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 895
 896 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 897
 898         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 899
 900 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 901
 902         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 903
 904 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 905
 906         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 907         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 908         xor3>: Delete mnemonics.
 909         <cp_abort>: Rename mnemonic from ...
 910         <cpabort>: ...to this.
 911         <setb>: Change to a X form instruction.
 912         <sync>: Change to 1 operand form.
 913         <copy>: Delete mnemonic.
 914         <copy_first>: Rename mnemonic from ...
 915         <copy>: ...to this.
 916         <paste, paste.>: Delete mnemonics.
 917         <paste_last>: Rename mnemonic from ...
 918         <paste.>: ...to this.
 919
 920 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 921
 922         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 923
 924 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 925
 926         * s390-mkopc.c (main): Support alternate arch strings.
 927
 928 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 929
 930         * s390-opc.txt: Fix kmctr instruction type.
 931
 932 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 933
 934         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 935         * i386-init.h: Regenerated.
 936
 937 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 938
 939         * opcodes/arc-dis.c (print_insn_arc): Changed.
 940
 941 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 942
 943         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 944         camellia_fl.
 945
 946 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 947
 948         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 949         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 950         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 951
 952 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 953
 954         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 955         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 956         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 957         PREFIX_MOD_3_0FAE_REG_4.
 958         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 959         PREFIX_MOD_3_0FAE_REG_4.
 960         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 961         (cpu_flags): Add CpuPTWRITE.
 962         * i386-opc.h (CpuPTWRITE): New.
 963         (i386_cpu_flags): Add cpuptwrite.
 964         * i386-opc.tbl: Add ptwrite instruction.
 965         * i386-init.h: Regenerated.
 966         * i386-tbl.h: Likewise.
 967
 968 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 969
 970         * arc-dis.h: Wrap around in extern "C".
 971
 972 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 973
 974         * aarch64-tbl.h (V8_2_INSN): New macro.
 975         (aarch64_opcode_table): Use it.
 976
 977 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 978
 979         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 980         CORE_INSN, __FP_INSN and SIMD_INSN.
 981
 982 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 983
 984         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 985         (aarch64_opcode_table): Update uses accordingly.
 986
 987 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 988         Kwok Cheung Yeung  <kcy@codesourcery.com>
 989
 990         opcodes/
 991         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 992         'e_cmplwi' to 'e_cmpli' instead.
 993         (OPVUPRT, OPVUPRT_MASK): Define.
 994         (powerpc_opcodes): Add E200Z4 insns.
 995         (vle_opcodes): Add context save/restore insns.
 996
 997 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 998
 999         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1000         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1001         "j".
1002
1003 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1004
1005         * arc-nps400-tbl.h: Change block comments to GNU format.
1006         * arc-dis.c: Add new globals addrtypenames,
1007         addrtypenames_max, and addtypeunknown.
1008         (get_addrtype): New function.
1009         (print_insn_arc): Print colons and address types when
1010         required.
1011         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1012         define insert and extract functions for all address types.
1013         (arc_operands): Add operands for colon and all address
1014         types.
1015         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1016         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1017         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1018         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1019         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1020         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1021
1022 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1023
1024         * configure: Regenerated.
1025
1026 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1027
1028         * arc-dis.c (skipclass): New structure.
1029         (decodelist): New variable.
1030         (is_compatible_p): New function.
1031         (new_element): Likewise.
1032         (skip_class_p): Likewise.
1033         (find_format_from_table): Use skip_class_p function.
1034         (find_format): Decode first the extension instructions.
1035         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1036         e_flags.
1037         (parse_option): New function.
1038         (parse_disassembler_options): Likewise.
1039         (print_arc_disassembler_options): Likewise.
1040         (print_insn_arc): Use parse_disassembler_options function.  Proper
1041         select ARCv2 cpu variant.
1042         * disassemble.c (disassembler_usage): Add ARC disassembler
1043         options.
1044
1045 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1046
1047         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1048         annotation from the "nal" entry and reorder it beyond "bltzal".
1049
1050 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1051
1052         * sparc-opc.c (ldtxa): New macro.
1053         (sparc_opcodes): Use the macro defined above to add entries for
1054         the LDTXA instructions.
1055         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1056         instruction.
1057
1058 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1059
1060         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1061         and "jmpc".
1062
1063 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1066         (movzb): Adjust to cover all permitted suffixes.
1067         (movzw): New.
1068         * i386-tbl.h: Re-generate.
1069
1070 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1071
1072         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1073         (lgdt): Remove Tbyte from non-64-bit variant.
1074         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1075         xsaves64, xsavec64): Remove Disp16.
1076         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1077         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1078         64-bit variants.
1079         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1080         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1081         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1082         64-bit variants.
1083         * i386-tbl.h: Re-generate.
1084
1085 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1086
1087         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1088         * i386-tbl.h: Re-generate.
1089
1090 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1091
1092         * arm-dis.c (print_insn): Fix typo in comment.
1093
1094 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1095
1096         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1097         range of ldst_elemlist operands.
1098         (print_register_list): Use PRIi64 to print the index.
1099         (aarch64_print_operand): Likewise.
1100
1101 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1102
1103         * mcore-opc.h: Remove sentinal.
1104         * mcore-dis.c (print_insn_mcore): Adjust.
1105
1106 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1107
1108         * arc-opc.c: Correct description of availability of NPS400
1109         features.
1110
1111 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1112
1113         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1114         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1115         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1116         xor3>: New mnemonics.
1117         <setb>: Change to a VX form instruction.
1118         (insert_sh6): Add support for rldixor.
1119         (extract_sh6): Likewise.
1120
1121 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1122
1123         * arc-ext.h: Wrap in extern C.
1124
1125 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1126
1127         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1128         Use same method for determining instruction length on ARC700 and
1129         NPS-400.
1130         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1131         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1132         with the NPS400 subclass.
1133         * arc-opc.c: Likewise.
1134
1135 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1136
1137         * sparc-opc.c (rdasr): New macro.
1138         (wrasr): Likewise.
1139         (rdpr): Likewise.
1140         (wrpr): Likewise.
1141         (rdhpr): Likewise.
1142         (wrhpr): Likewise.
1143         (sparc_opcodes): Use the macros above to fix and expand the
1144         definition of read/write instructions from/to
1145         asr/privileged/hyperprivileged instructions.
1146         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1147         %hva_mask_nz.  Prefer softint_set and softint_clear over
1148         set_softint and clear_softint.
1149         (print_insn_sparc): Support %ver in Rd.
1150
1151 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1152
1153         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1154         architecture according to the hardware capabilities they require.
1155
1156 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1157
1158         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1159         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1160         bfd_mach_sparc_v9{c,d,e,v,m}.
1161         * sparc-opc.c (MASK_V9C): Define.
1162         (MASK_V9D): Likewise.
1163         (MASK_V9E): Likewise.
1164         (MASK_V9V): Likewise.
1165         (MASK_V9M): Likewise.
1166         (v6): Add MASK_V9{C,D,E,V,M}.
1167         (v6notlet): Likewise.
1168         (v7): Likewise.
1169         (v8): Likewise.
1170         (v9): Likewise.
1171         (v9andleon): Likewise.
1172         (v9a): Likewise.
1173         (v9b): Likewise.
1174         (v9c): Define.
1175         (v9d): Likewise.
1176         (v9e): Likewise.
1177         (v9v): Likewise.
1178         (v9m): Likewise.
1179         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1180
1181 2016-06-15  Nick Clifton  <nickc@redhat.com>
1182
1183         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1184         constants to match expected behaviour.
1185         (nds32_parse_opcode): Likewise.  Also for whitespace.
1186
1187 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1188
1189         * arc-opc.c (extract_rhv1): Extract value from insn.
1190
1191 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1192
1193         * arc-nps400-tbl.h: Add ldbit instruction.
1194         * arc-opc.c: Add flag classes required for ldbit.
1195
1196 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1197
1198         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1199         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1200         support the above instructions.
1201
1202 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1203
1204         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1205         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1206         csma, cbba, zncv, and hofs.
1207         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1208         support the above instructions.
1209
1210 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1211
1212         * arc-nps400-tbl.h: Add andab and orab instructions.
1213
1214 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1215
1216         * arc-nps400-tbl.h: Add addl-like instructions.
1217
1218 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1219
1220         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1221
1222 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1223
1224         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1225         instructions.
1226
1227 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1228
1229         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1230         variable.
1231         (init_disasm): Handle new command line option "insnlength".
1232         (print_s390_disassembler_options): Mention new option in help
1233         output.
1234         (print_insn_s390): Use the encoded insn length when dumping
1235         unknown instructions.
1236
1237 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1238
1239         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1240          to the address and set as symbol address for LDS/ STS immediate operands.
1241
1242 2016-06-07  Alan Modra  <amodra@gmail.com>
1243
1244         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1245         cpu for "vle" to e500.
1246         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1247         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1248         (PPCNONE): Delete, substitute throughout.
1249         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1250         except for major opcode 4 and 31.
1251         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1252
1253 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1254
1255         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1256         ARM_EXT_RAS in relevant entries.
1257
1258 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1259
1260         PR binutils/20196
1261         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1262         opcodes for E6500.
1263
1264 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1265
1266         PR binutis/18386
1267         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1268         (indir_v_mode): New.
1269         Add comments for '&'.
1270         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1271         (putop): Handle '&'.
1272         (intel_operand_size): Handle indir_v_mode.
1273         (OP_E_register): Likewise.
1274         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1275         64-bit indirect call/jmp for AMD64.
1276         * i386-tbl.h: Regenerated
1277
1278 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1279
1280         * arc-dis.c (struct arc_operand_iterator): New structure.
1281         (find_format_from_table): All the old content from find_format,
1282         with some minor adjustments, and parameter renaming.
1283         (find_format_long_instructions): New function.
1284         (find_format): Rewritten.
1285         (arc_insn_length): Add LSB parameter.
1286         (extract_operand_value): New function.
1287         (operand_iterator_next): New function.
1288         (print_insn_arc): Use new functions to find opcode, and iterator
1289         over operands.
1290         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1291         (extract_nps_3bit_dst_short): New function.
1292         (insert_nps_3bit_src2_short): New function.
1293         (extract_nps_3bit_src2_short): New function.
1294         (insert_nps_bitop1_size): New function.
1295         (extract_nps_bitop1_size): New function.
1296         (insert_nps_bitop2_size): New function.
1297         (extract_nps_bitop2_size): New function.
1298         (insert_nps_bitop_mod4_msb): New function.
1299         (extract_nps_bitop_mod4_msb): New function.
1300         (insert_nps_bitop_mod4_lsb): New function.
1301         (extract_nps_bitop_mod4_lsb): New function.
1302         (insert_nps_bitop_dst_pos3_pos4): New function.
1303         (extract_nps_bitop_dst_pos3_pos4): New function.
1304         (insert_nps_bitop_ins_ext): New function.
1305         (extract_nps_bitop_ins_ext): New function.
1306         (arc_operands): Add new operands.
1307         (arc_long_opcodes): New global array.
1308         (arc_num_long_opcodes): New global.
1309         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1310
1311 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1312
1313         * nds32-asm.h: Add extern "C".
1314         * sh-opc.h: Likewise.
1315
1316 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1317
1318         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1319         0,b,limm to the rflt instruction.
1320
1321 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1322
1323         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1324         constant.
1325
1326 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1327
1328         PR gas/20145
1329         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1330         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1331         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1332         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1333         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1334         * i386-init.h: Regenerated.
1335
1336 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1337
1338         PR gas/20145
1339         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1340         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1341         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1342         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1343         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1344         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1345         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1346         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1347         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1348         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1349         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1350         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1351         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1352         CpuRegMask for AVX512.
1353         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1354         and CpuRegMask.
1355         (set_bitfield_from_cpu_flag_init): New function.
1356         (set_bitfield): Remove const on f.  Call
1357         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1358         * i386-opc.h (CpuRegMMX): New.
1359         (CpuRegXMM): Likewise.
1360         (CpuRegYMM): Likewise.
1361         (CpuRegZMM): Likewise.
1362         (CpuRegMask): Likewise.
1363         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1364         and cpuregmask.
1365         * i386-init.h: Regenerated.
1366         * i386-tbl.h: Likewise.
1367
1368 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1369
1370         PR gas/20154
1371         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1372         (opcode_modifiers): Add AMD64 and Intel64.
1373         (main): Properly verify CpuMax.
1374         * i386-opc.h (CpuAMD64): Removed.
1375         (CpuIntel64): Likewise.
1376         (CpuMax): Set to CpuNo64.
1377         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1378         (AMD64): New.
1379         (Intel64): Likewise.
1380         (i386_opcode_modifier): Add amd64 and intel64.
1381         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1382         on call and jmp.
1383         * i386-init.h: Regenerated.
1384         * i386-tbl.h: Likewise.
1385
1386 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1387
1388         PR gas/20154
1389         * i386-gen.c (main): Fail if CpuMax is incorrect.
1390         * i386-opc.h (CpuMax): Set to CpuIntel64.
1391         * i386-tbl.h: Regenerated.
1392
1393 2016-05-27  Nick Clifton  <nickc@redhat.com>
1394
1395         PR target/20150
1396         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1397         (msp430dis_opcode_unsigned): New function.
1398         (msp430dis_opcode_signed): New function.
1399         (msp430_singleoperand): Use the new opcode reading functions.
1400         Only disassenmble bytes if they were successfully read.
1401         (msp430_doubleoperand): Likewise.
1402         (msp430_branchinstr): Likewise.
1403         (msp430x_callx_instr): Likewise.
1404         (print_insn_msp430): Check that it is safe to read bytes before
1405         attempting disassembly.  Use the new opcode reading functions.
1406
1407 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1408
1409         * ppc-opc.c (CY): New define.  Document it.
1410         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1411
1412 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1413
1414         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1415         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1416         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1417         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1418         CPU_ANY_AVX_FLAGS.
1419         * i386-init.h: Regenerated.
1420
1421 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1422
1423         PR gas/20141
1424         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1425         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1426         * i386-init.h: Regenerated.
1427
1428 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1429
1430         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1431         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1432         * i386-init.h: Regenerated.
1433
1434 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1435
1436         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1437         information.
1438         (print_insn_arc): Set insn_type information.
1439         * arc-opc.c (C_CC): Add F_CLASS_COND.
1440         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1441         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1442         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1443         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1444         (brne, brne_s, jeq_s, jne_s): Likewise.
1445
1446 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1447
1448         * arc-tbl.h (neg): New instruction variant.
1449
1450 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1451
1452         * arc-dis.c (find_format, find_format, get_auxreg)
1453         (print_insn_arc): Changed.
1454         * arc-ext.h (INSERT_XOP): Likewise.
1455
1456 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1457
1458         * tic54x-dis.c (sprint_mmr): Adjust.
1459         * tic54x-opc.c: Likewise.
1460
1461 2016-05-19  Alan Modra  <amodra@gmail.com>
1462
1463         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1464
1465 2016-05-19  Alan Modra  <amodra@gmail.com>
1466
1467         * ppc-opc.c: Formatting.
1468         (NSISIGNOPT): Define.
1469         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1470
1471 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1472
1473         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1474         replacing references to `micromips_ase' throughout.
1475         (_print_insn_mips): Don't use file-level microMIPS annotation to
1476         determine the disassembly mode with the symbol table.
1477
1478 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1479
1480         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1481
1482 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1483
1484         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1485         mips64r6.
1486         * mips-opc.c (D34): New macro.
1487         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1488
1489 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1490
1491         * i386-dis.c (prefix_table): Add RDPID instruction.
1492         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1493         (cpu_flags): Add RDPID bitfield.
1494         * i386-opc.h (enum): Add RDPID element.
1495         (i386_cpu_flags): Add RDPID field.
1496         * i386-opc.tbl: Add RDPID instruction.
1497         * i386-init.h: Regenerate.
1498         * i386-tbl.h: Regenerate.
1499
1500 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1501
1502         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1503         branch type of a symbol.
1504         (print_insn): Likewise.
1505
1506 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1507
1508         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1509         Mainline Security Extensions instructions.
1510         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1511         Extensions instructions.
1512         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1513         instructions.
1514         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1515         special registers.
1516
1517 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1518
1519         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1520
1521 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1522
1523         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1524         (arcExtMap_genOpcode): Likewise.
1525         * arc-opc.c (arg_32bit_rc): Define new variable.
1526         (arg_32bit_u6): Likewise.
1527         (arg_32bit_limm): Likewise.
1528
1529 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1530
1531         * aarch64-gen.c (VERIFIER): Define.
1532         * aarch64-opc.c (VERIFIER): Define.
1533         (verify_ldpsw): Use static linkage.
1534         * aarch64-opc.h (verify_ldpsw): Remove.
1535         * aarch64-tbl.h: Use VERIFIER for verifiers.
1536
1537 2016-04-28  Nick Clifton  <nickc@redhat.com>
1538
1539         PR target/19722
1540         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1541         * aarch64-opc.c (verify_ldpsw): New function.
1542         * aarch64-opc.h (verify_ldpsw): New prototype.
1543         * aarch64-tbl.h: Add initialiser for verifier field.
1544         (LDPSW): Set verifier to verify_ldpsw.
1545
1546 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1547
1548         PR binutils/19983
1549         PR binutils/19984
1550         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1551         smaller than address size.
1552
1553 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1554
1555         * alpha-dis.c: Regenerate.
1556         * crx-dis.c: Likewise.
1557         * disassemble.c: Likewise.
1558         * epiphany-opc.c: Likewise.
1559         * fr30-opc.c: Likewise.
1560         * frv-opc.c: Likewise.
1561         * ip2k-opc.c: Likewise.
1562         * iq2000-opc.c: Likewise.
1563         * lm32-opc.c: Likewise.
1564         * lm32-opinst.c: Likewise.
1565         * m32c-opc.c: Likewise.
1566         * m32r-opc.c: Likewise.
1567         * m32r-opinst.c: Likewise.
1568         * mep-opc.c: Likewise.
1569         * mt-opc.c: Likewise.
1570         * or1k-opc.c: Likewise.
1571         * or1k-opinst.c: Likewise.
1572         * tic80-opc.c: Likewise.
1573         * xc16x-opc.c: Likewise.
1574         * xstormy16-opc.c: Likewise.
1575
1576 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1577
1578         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1579         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1580         calcsd, and calcxd instructions.
1581         * arc-opc.c (insert_nps_bitop_size): Delete.
1582         (extract_nps_bitop_size): Delete.
1583         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1584         (extract_nps_qcmp_m3): Define.
1585         (extract_nps_qcmp_m2): Define.
1586         (extract_nps_qcmp_m1): Define.
1587         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1588         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1589         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1590         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1591         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1592         NPS_QCMP_M3.
1593
1594 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1595
1596         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1597
1598 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1599
1600         * Makefile.in: Regenerated with automake 1.11.6.
1601         * aclocal.m4: Likewise.
1602
1603 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1604
1605         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1606         instructions.
1607         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1608         (extract_nps_cmem_uimm16): New function.
1609         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1610
1611 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1612
1613         * arc-dis.c (arc_insn_length): New function.
1614         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1615         (find_format): Change insnLen parameter to unsigned.
1616
1617 2016-04-13  Nick Clifton  <nickc@redhat.com>
1618
1619         PR target/19937
1620         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1621         the LD.B and LD.BU instructions.
1622
1623 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1624
1625         * arc-dis.c (find_format): Check for extension flags.
1626         (print_flags): New function.
1627         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1628         .extAuxRegister.
1629         * arc-ext.c (arcExtMap_coreRegName): Use
1630         LAST_EXTENSION_CORE_REGISTER.
1631         (arcExtMap_coreReadWrite): Likewise.
1632         (dump_ARC_extmap): Update printing.
1633         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1634         (arc_aux_regs): Add cpu field.
1635         * arc-regs.h: Add cpu field, lower case name aux registers.
1636
1637 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1638
1639         * arc-tbl.h: Add rtsc, sleep with no arguments.
1640
1641 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1642
1643         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1644         Initialize.
1645         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1646         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1647         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1648         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1649         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1650         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1651         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1652         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1653         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1654         (arc_opcode arc_opcodes): Null terminate the array.
1655         (arc_num_opcodes): Remove.
1656         * arc-ext.h (INSERT_XOP): Define.
1657         (extInstruction_t): Likewise.
1658         (arcExtMap_instName): Delete.
1659         (arcExtMap_insn): New function.
1660         (arcExtMap_genOpcode): Likewise.
1661         * arc-ext.c (ExtInstruction): Remove.
1662         (create_map): Zero initialize instruction fields.
1663         (arcExtMap_instName): Remove.
1664         (arcExtMap_insn): New function.
1665         (dump_ARC_extmap): More info while debuging.
1666         (arcExtMap_genOpcode): New function.
1667         * arc-dis.c (find_format): New function.
1668         (print_insn_arc): Use find_format.
1669         (arc_get_disassembler): Enable dump_ARC_extmap only when
1670         debugging.
1671
1672 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1673
1674         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1675         instruction bits out.
1676
1677 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1678
1679         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1680         * arc-opc.c (arc_flag_operands): Add new flags.
1681         (arc_flag_classes): Add new classes.
1682
1683 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1684
1685         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1686
1687 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1688
1689         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1690         encode1, rflt, crc16, and crc32 instructions.
1691         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1692         (arc_flag_classes): Add C_NPS_R.
1693         (insert_nps_bitop_size_2b): New function.
1694         (extract_nps_bitop_size_2b): Likewise.
1695         (insert_nps_bitop_uimm8): Likewise.
1696         (extract_nps_bitop_uimm8): Likewise.
1697         (arc_operands): Add new operand entries.
1698
1699 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1700
1701         * arc-regs.h: Add a new subclass field.  Add double assist
1702         accumulator register values.
1703         * arc-tbl.h: Use DPA subclass to mark the double assist
1704         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1705         * arc-opc.c (RSP): Define instead of SP.
1706         (arc_aux_regs): Add the subclass field.
1707
1708 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1709
1710         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1711
1712 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1713
1714         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1715         NPS_R_SRC1.
1716
1717 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1718
1719         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1720         issues.  No functional changes.
1721
1722 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1723
1724         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1725         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1726         (RTT): Remove duplicate.
1727         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1728         (PCT_CONFIG*): Remove.
1729         (D1L, D1H, D2H, D2L): Define.
1730
1731 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1732
1733         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1734
1735 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1736
1737         * arc-tbl.h (invld07): Remove.
1738         * arc-ext-tbl.h: New file.
1739         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1740         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1741
1742 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1743
1744         Fix -Wstack-usage warnings.
1745         * aarch64-dis.c (print_operands): Substitute size.
1746         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1747
1748 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1749
1750         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1751         to get a proper diagnostic when an invalid ASR register is used.
1752
1753 2016-03-22  Nick Clifton  <nickc@redhat.com>
1754
1755         * configure: Regenerate.
1756
1757 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1758
1759         * arc-nps400-tbl.h: New file.
1760         * arc-opc.c: Add top level comment.
1761         (insert_nps_3bit_dst): New function.
1762         (extract_nps_3bit_dst): New function.
1763         (insert_nps_3bit_src2): New function.
1764         (extract_nps_3bit_src2): New function.
1765         (insert_nps_bitop_size): New function.
1766         (extract_nps_bitop_size): New function.
1767         (arc_flag_operands): Add nps400 entries.
1768         (arc_flag_classes): Add nps400 entries.
1769         (arc_operands): Add nps400 entries.
1770         (arc_opcodes): Add nps400 include.
1771
1772 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1773
1774         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1775         the new class enum values.
1776
1777 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1778
1779         * arc-dis.c (print_insn_arc): Handle nps400.
1780
1781 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1782
1783         * arc-opc.c (BASE): Delete.
1784
1785 2016-03-18  Nick Clifton  <nickc@redhat.com>
1786
1787         PR target/19721
1788         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1789         of MOV insn that aliases an ORR insn.
1790
1791 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1792
1793         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1794
1795 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1796
1797         * mcore-opc.h: Add const qualifiers.
1798         * microblaze-opc.h (struct op_code_struct): Likewise.
1799         * sh-opc.h: Likewise.
1800         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1801         (tic4x_print_op): Likewise.
1802
1803 2016-03-02  Alan Modra  <amodra@gmail.com>
1804
1805         * or1k-desc.h: Regenerate.
1806         * fr30-ibld.c: Regenerate.
1807         * rl78-decode.c: Regenerate.
1808
1809 2016-03-01  Nick Clifton  <nickc@redhat.com>
1810
1811         PR target/19747
1812         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1813
1814 2016-02-24  Renlin Li  <renlin.li@arm.com>
1815
1816         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1817         (print_insn_coprocessor): Support fp16 instructions.
1818
1819 2016-02-24  Renlin Li  <renlin.li@arm.com>
1820
1821         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1822         vminnm, vrint(mpna).
1823
1824 2016-02-24  Renlin Li  <renlin.li@arm.com>
1825
1826         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1827         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1828
1829 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1830
1831         * i386-dis.c (print_insn): Parenthesize expression to prevent
1832         truncated addresses.
1833         (OP_J): Likewise.
1834
1835 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1836             Janek van Oirschot  <jvanoirs@synopsys.com>
1837
1838         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1839         variable.
1840
1841 2016-02-04  Nick Clifton  <nickc@redhat.com>
1842
1843         PR target/19561
1844         * msp430-dis.c (print_insn_msp430): Add a special case for
1845         decoding an RRC instruction with the ZC bit set in the extension
1846         word.
1847
1848 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1849
1850         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1851         * epiphany-ibld.c: Regenerate.
1852         * fr30-ibld.c: Regenerate.
1853         * frv-ibld.c: Regenerate.
1854         * ip2k-ibld.c: Regenerate.
1855         * iq2000-ibld.c: Regenerate.
1856         * lm32-ibld.c: Regenerate.
1857         * m32c-ibld.c: Regenerate.
1858         * m32r-ibld.c: Regenerate.
1859         * mep-ibld.c: Regenerate.
1860         * mt-ibld.c: Regenerate.
1861         * or1k-ibld.c: Regenerate.
1862         * xc16x-ibld.c: Regenerate.
1863         * xstormy16-ibld.c: Regenerate.
1864
1865 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1866
1867         * epiphany-dis.c: Regenerated from latest cpu files.
1868
1869 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1870
1871         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1872         test bit.
1873
1874 2016-01-25  Renlin Li  <renlin.li@arm.com>
1875
1876         * arm-dis.c (mapping_symbol_for_insn): New function.
1877         (find_ifthen_state): Call mapping_symbol_for_insn().
1878
1879 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1880
1881         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1882         of MSR UAO immediate operand.
1883
1884 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1885
1886         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1887         instruction support.
1888
1889 2016-01-17  Alan Modra  <amodra@gmail.com>
1890
1891         * configure: Regenerate.
1892
1893 2016-01-14  Nick Clifton  <nickc@redhat.com>
1894
1895         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1896         instructions that can support stack pointer operations.
1897         * rl78-decode.c: Regenerate.
1898         * rl78-dis.c: Fix display of stack pointer in MOVW based
1899         instructions.
1900
1901 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1902
1903         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1904         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1905         erxtatus_el1 and erxaddr_el1.
1906
1907 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1908
1909         * arm-dis.c (arm_opcodes): Add "esb".
1910         (thumb_opcodes): Likewise.
1911
1912 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1913
1914         * ppc-opc.c <xscmpnedp>: Delete.
1915         <xvcmpnedp>: Likewise.
1916         <xvcmpnedp.>: Likewise.
1917         <xvcmpnesp>: Likewise.
1918         <xvcmpnesp.>: Likewise.
1919
1920 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1921
1922         PR gas/13050
1923         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1924         addition to ISA_A.
1925
1926 2016-01-01  Alan Modra  <amodra@gmail.com>
1927
1928         Update year range in copyright notice of all files.
1929
1930 For older changes see ChangeLog-2015
1931 \f
1932 Copyright (C) 2016 Free Software Foundation, Inc.
1933
1934 Copying and distribution of this file, with or without modification,
1935 are permitted in any medium without royalty provided the copyright
1936 notice and this notice are preserved.
1937
1938 Local Variables:
1939 mode: change-log
1940 left-margin: 8
1941 fill-column: 74
1942 version-control: never
1943 End: