opcodes/ChangeLog

   1 2018-12-03  Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
   2
   3         PR 23193
   4         PR 19721
   5         * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
   6         encoding as MOV if the shift operation is a left shift of zero.
   7
   8 2018-11-29  Jim Wilson  <jimw@sifive.com>
   9
  10         * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
  11         (c.unimp): New.
  12
  13 2018-11-27  Jim Wilson  <jimw@sifive.com>
  14
  15         * riscv-opc.c (ciw): Fix whitespace to align columns.
  16         (ca): New.
  17
  18 2018-11-21  John Darrington  <john@darrington.wattle.id.au>
  19
  20         * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
  21         if the postbyte matches the appropriate pattern.
  22
  23 2018-11-13  Francois H. Theron <francois.theron@netronome.com>
  24
  25         * nfp-dis.c: Fix crc[] disassembly if operands are swapped.
  26
  27 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  28
  29         * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
  30         IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
  31         IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
  32         CIGDVAC and GZVA.
  33         (aarch64_sys_ins_reg_supported_p): New check for above.
  34
  35 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  36
  37         * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
  38         TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
  39         RGSR_EL1 and GCR_EL1.
  40         (aarch64_sys_reg_supported_p): New check for above.
  41         (aarch64_pstatefields): New entry for TCO.
  42         (aarch64_pstatefield_supported_p): New check for above.
  43
  44 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  45
  46         * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
  47         * aarch64-asm.h (ins_addr_simple_2): Declare the above.
  48         * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
  49         * aarch64-dis.h (ext_addr_simple_2): Declare the above.
  50         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
  51         AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
  52         (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
  53         * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
  54         (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
  55         * aarch64-asm-2.c: Regenerated.
  56         * aarch64-dis-2.c: Regenerated.
  57         * aarch64-opc-2.c: Regenerated.
  58
  59 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  60
  61         * aarch64-tbl.h (QL_LDG): New.
  62         (aarch64_opcode_table): Add ldg.
  63         * aarch64-asm-2.c: Regenerated.
  64         * aarch64-dis-2.c: Regenerated.
  65         * aarch64-opc-2.c: Regenerated.
  66
  67 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  68
  69         * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
  70         for AARCH64_OPND_QLF_imm_tag.
  71         (operand_general_constraint_met_p): Add case for
  72         AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
  73         (aarch64_print_operand): Likewise.
  74         * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
  75         (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
  76         for both offset and pre/post indexed versions.
  77         (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
  78         * aarch64-asm-2.c: Regenerated.
  79         * aarch64-dis-2.c: Regenerated.
  80         * aarch64-opc-2.c: Regenerated.
  81
  82 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  83
  84         * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
  85         * aarch64-asm-2.c: Regenerated.
  86         * aarch64-dis-2.c: Regenerated.
  87         * aarch64-opc-2.c: Regenerated.
  88
  89 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  90
  91         * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
  92         (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
  93         * aarch64-opc.c (fields): Add entry for imm4_3.
  94         (operand_general_constraint_met_p): Add cases for
  95         AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
  96         (aarch64_print_operand): Likewise.
  97         * aarch64-tbl.h (QL_ADDG): New.
  98         (aarch64_opcode_table): Add addg, subg, irg and gmi.
  99         (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
 100         * aarch64-asm.c (aarch64_ins_imm): Add case for
 101         operand_need_shift_by_four.
 102         * aarch64-asm-2.c: Regenerated.
 103         * aarch64-dis-2.c: Regenerated.
 104         * aarch64-opc-2.c: Regenerated.
 105
 106 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
 107
 108         * aarch64-tbl.h (aarch64_feature_memtag): New.
 109         (MEMTAG, MEMTAG_INSN): New.
 110
 111 2018-11-06  Sudakshina Das  <sudi.das@arm.com>
 112
 113         * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
 114         with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
 115
 116 2018-11-06  Alan Modra  <amodra@gmail.com>
 117
 118         * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
 119         (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
 120         (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
 121         (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
 122         Don't return zero on error, insert mask bits instead.
 123         (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
 124         (insert_sh6, extract_sh6): Delete dead code.
 125         (insert_sprbat, insert_sprg): Use unsigned comparisions.
 126         (powerpc_operands <OIMM>): Set shift count rather than using
 127         PPC_OPSHIFT_INV.
 128         <SE_SDH, SE_SDW>: Likewise.  Don't use insert/extract functions.
 129
 130 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
 133         vpbroadcast{d,q} with GPR operand.
 134
 135 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
 138         * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
 139         cases up one level in the hierarchy.
 140
 141 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 142
 143         * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
 144         MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
 145         (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
 146         into MOD_VEX_0F93_P_3_LEN_0.
 147         (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
 148         operand cases up one level in the hierarchy.
 149
 150 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 151
 152         * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
 153         VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
 154         EVEX_W_0F3A22_P_2): Delete.
 155         (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
 156         entries up one level in the hierarchy.
 157         (OP_E_memory): Handle dq_mode when determining Disp8 shift
 158         value.
 159         * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
 160         entries up one level in the hierarchy.
 161         * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
 162         VexWIG for AVX flavors.
 163         * i386-tbl.h: Re-generate.
 164
 165 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 166
 167         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
 168         vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
 169         vcvtusi2ss, kmovd): Drop VexW=1.
 170         * i386-tbl.h: Re-generate.
 171
 172 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 173
 174         * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
 175         EVex512, EVexLIG, EVexDYN): New.
 176         (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
 177         insns): Use Vex128 instead of Vex=3 (aka VexLIG).
 178         (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
 179         of EVex=4 (aka EVexLIG).
 180         * i386-tbl.h: Re-generate.
 181
 182 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 183
 184         * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
 185         (vpmaxub): Re-order attributes on AVX512BW flavor.
 186         * i386-tbl.h: Re-generate.
 187
 188 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 189
 190         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
 191         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
 192         Vex=1 on AVX / AVX2 flavors.
 193         (vpmaxub): Re-order attributes on AVX512BW flavor.
 194         * i386-tbl.h: Re-generate.
 195
 196 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-opc.tbl (VexW0, VexW1): New.
 199         (vphadd*, vphsub*): Use VexW0 on XOP variants.
 200         * i386-tbl.h: Re-generate.
 201
 202 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
 203
 204         * s12z-dis.c (decode_possible_symbol): Add fallback case.
 205         (rel_15_7): Likewise.
 206
 207 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
 208
 209         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
 210         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
 211         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
 212
 213 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
 214
 215         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
 216         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
 217
 218 2018-10-10  Jan Beulich  <jbeulich@suse.com>
 219
 220         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
 221         Size64. Add Size.
 222         * i386-opc.h (Size16, Size32, Size64): Delete.
 223         (Size): New.
 224         (SIZE16, SIZE32, SIZE64): Define.
 225         (struct i386_opcode_modifier): Drop size16, size32, and size64.
 226         Add size.
 227         * i386-opc.tbl (Size16, Size32, Size64): Define.
 228         * i386-tbl.h: Re-generate.
 229
 230 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 231
 232         * aarch64-opc.c (operand_general_constraint_met_p): Add
 233         SSBS in the check for one-bit immediate.
 234         (aarch64_sys_regs): New entry for SSBS.
 235         (aarch64_sys_reg_supported_p): New check for above.
 236         (aarch64_pstatefields): New entry for SSBS.
 237         (aarch64_pstatefield_supported_p): New check for above.
 238
 239 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 240
 241         * aarch64-opc.c (aarch64_sys_regs): New entries for
 242         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
 243         (aarch64_sys_reg_supported_p): New checks for above.
 244
 245 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 246
 247         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
 248         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
 249         with the hint immediate.
 250         * aarch64-opc.c (aarch64_hint_options): New entries for
 251         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
 252         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
 253         while checking for HINT_OPD_F_NOPRINT flag.
 254         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
 255         extract value.
 256         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
 257         (aarch64_opcode_table): Add entry for BTI.
 258         (AARCH64_OPERANDS): Add new description for BTI targets.
 259         * aarch64-asm-2.c: Regenerate.
 260         * aarch64-dis-2.c: Regenerate.
 261         * aarch64-opc-2.c: Regenerate.
 262
 263 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 264
 265         * aarch64-opc.c (aarch64_sys_regs): New entries for
 266         rndr and rndrrs.
 267         (aarch64_sys_reg_supported_p): New check for above.
 268
 269 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 270
 271         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
 272         (aarch64_sys_ins_reg_supported_p): New check for above.
 273
 274 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 275
 276         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
 277         AARCH64_OPND_SYSREG_SR.
 278         * aarch64-opc.c (aarch64_print_operand): Likewise.
 279         (aarch64_sys_regs_sr): Define table.
 280         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
 281         AARCH64_FEATURE_PREDRES.
 282         * aarch64-tbl.h (aarch64_feature_predres): New.
 283         (PREDRES, PREDRES_INSN): New.
 284         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
 285         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
 286         * aarch64-asm-2.c: Regenerate.
 287         * aarch64-dis-2.c: Regenerate.
 288         * aarch64-opc-2.c: Regenerate.
 289
 290 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 291
 292         * aarch64-tbl.h (aarch64_feature_sb): New.
 293         (SB, SB_INSN): New.
 294         (aarch64_opcode_table): Add entry for sb.
 295         * aarch64-asm-2.c: Regenerate.
 296         * aarch64-dis-2.c: Regenerate.
 297         * aarch64-opc-2.c: Regenerate.
 298
 299 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 300
 301         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 302         (aarch64_feature_frintts): New.
 303         (FLAGMANIP, FRINTTS): New.
 304         (aarch64_opcode_table): Add entries for xaflag, axflag
 305         and frint[32,64][x,z] instructions.
 306         * aarch64-asm-2.c: Regenerate.
 307         * aarch64-dis-2.c: Regenerate.
 308         * aarch64-opc-2.c: Regenerate.
 309
 310 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 311
 312         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 313         (ARMV8_5, V8_5_INSN): New.
 314
 315 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 316
 317         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 318
 319 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 320
 321         * i386-dis.c (rm_table): Add enclv.
 322         * i386-opc.tbl: Add enclv.
 323         * i386-tbl.h: Regenerated.
 324
 325 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 326
 327         * arm-dis.c (arm_opcodes): Add sb.
 328         (thumb32_opcodes): Likewise.
 329
 330 2018-10-05  Richard Henderson  <rth@twiddle.net>
 331             Stafford Horne  <shorne@gmail.com>
 332
 333         * or1k-desc.c: Regenerate.
 334         * or1k-desc.h: Regenerate.
 335         * or1k-opc.c: Regenerate.
 336         * or1k-opc.h: Regenerate.
 337         * or1k-opinst.c: Regenerate.
 338
 339 2018-10-05  Richard Henderson  <rth@twiddle.net>
 340
 341         * or1k-asm.c: Regenerated.
 342         * or1k-desc.c: Regenerated.
 343         * or1k-desc.h: Regenerated.
 344         * or1k-dis.c: Regenerated.
 345         * or1k-ibld.c: Regenerated.
 346         * or1k-opc.c: Regenerated.
 347         * or1k-opc.h: Regenerated.
 348         * or1k-opinst.c: Regenerated.
 349
 350 2018-10-05  Richard Henderson  <rth@twiddle.net>
 351
 352         * or1k-asm.c: Regenerate.
 353
 354 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 355
 356         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 357         * aarch64-dis.c (print_operands): Refactor to take notes.
 358         (print_verifier_notes): New.
 359         (print_aarch64_insn): Apply constraint verifier.
 360         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 361         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 362
 363 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 364
 365         * aarch64-opc.c (init_insn_block): New.
 366         (verify_constraints, aarch64_is_destructive_by_operands): New.
 367         * aarch64-opc.h (verify_constraints): New.
 368
 369 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 370
 371         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 372         * aarch64-opc.c (verify_ldpsw): Update arguments.
 373
 374 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 375
 376         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 377         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 378
 379 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 380
 381         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 382         * aarch64-dis.c (insn_sequence): New.
 383
 384 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 385
 386         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 387         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 388         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 389         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 390         constraints.
 391         (_SVE_INSNC): New.
 392         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 393         constraints.
 394         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 395         F_SCAN flags.
 396         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 397         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 398         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 399         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 400         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 401         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 402         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 403
 404 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 405
 406         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 407
 408 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 409
 410         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 411         are used when extracting signed fields and converting them to
 412         potentially 64-bit types.
 413
 414 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 415
 416         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 417         * Makefile.in: Re-generate.
 418         * aclocal.m4: Re-generate.
 419         * configure: Re-generate.
 420         * configure.ac: Remove check for -Wno-missing-field-initializers.
 421         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 422         (csky_v2_opcodes): Likewise.
 423
 424 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 425
 426         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 427
 428 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 429
 430         * nds32-asm.c (operand_fields): Remove the unused fields.
 431         (nds32_opcodes): Remove the unused instructions.
 432         * nds32-dis.c (nds32_ex9_info): Removed.
 433         (nds32_parse_opcode): Updated.
 434         (print_insn_nds32): Likewise.
 435         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 436         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 437         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 438         build_opcode_hash_table): New functions.
 439         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 440         nds32_opcode_table): New.
 441         (hw_ktabs): Declare it to a pointer rather than an array.
 442         (build_hash_table): Removed.
 443         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 444         SYN_ROPT and upadte HW_GPR and HW_INT.
 445         * nds32-dis.c (keywords): Remove const.
 446         (match_field): New function.
 447         (nds32_parse_opcode): Updated.
 448         * disassemble.c (disassemble_init_for_target):
 449         Add disassemble_init_nds32.
 450         * nds32-dis.c (eum map_type): New.
 451         (nds32_private_data): Likewise.
 452         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 453         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 454         (print_insn_nds32): Updated.
 455         * nds32-asm.c (parse_aext_reg): Add new parameter.
 456         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 457         are allowed to use.
 458         All callers changed.
 459         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 460         (operand_fields): Add new fields.
 461         (nds32_opcodes): Add new instructions.
 462         (keyword_aridxi_mx): New keyword.
 463         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 464         and NASM_ATTR_ZOL.
 465         (ALU2_1, ALU2_2, ALU2_3): New macros.
 466         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 467
 468 2018-09-17  Kito Cheng  <kito@andestech.com>
 469
 470         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 471
 472 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 473
 474         PR gas/23670
 475         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 476         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 477         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 478         (EVEX_LEN_0F7E_P_1): Likewise.
 479         (EVEX_LEN_0F7E_P_2): Likewise.
 480         (EVEX_LEN_0FD6_P_2): Likewise.
 481         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 482         (EVEX_LEN_TABLE): Likewise.
 483         (EVEX_LEN_0F6E_P_2): New enum.
 484         (EVEX_LEN_0F7E_P_1): Likewise.
 485         (EVEX_LEN_0F7E_P_2): Likewise.
 486         (EVEX_LEN_0FD6_P_2): Likewise.
 487         (evex_len_table): New.
 488         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 489         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 490         * i386-tbl.h: Regenerated.
 491
 492 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 493
 494         PR gas/23665
 495         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 496         VEX_LEN_0F7E_P_2 entries.
 497         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 498         * i386-tbl.h: Regenerated.
 499
 500 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 501
 502         * i386-dis.c (VZERO_Fixup): Removed.
 503         (VZERO): Likewise.
 504         (VEX_LEN_0F10_P_1): Likewise.
 505         (VEX_LEN_0F10_P_3): Likewise.
 506         (VEX_LEN_0F11_P_1): Likewise.
 507         (VEX_LEN_0F11_P_3): Likewise.
 508         (VEX_LEN_0F2E_P_0): Likewise.
 509         (VEX_LEN_0F2E_P_2): Likewise.
 510         (VEX_LEN_0F2F_P_0): Likewise.
 511         (VEX_LEN_0F2F_P_2): Likewise.
 512         (VEX_LEN_0F51_P_1): Likewise.
 513         (VEX_LEN_0F51_P_3): Likewise.
 514         (VEX_LEN_0F52_P_1): Likewise.
 515         (VEX_LEN_0F53_P_1): Likewise.
 516         (VEX_LEN_0F58_P_1): Likewise.
 517         (VEX_LEN_0F58_P_3): Likewise.
 518         (VEX_LEN_0F59_P_1): Likewise.
 519         (VEX_LEN_0F59_P_3): Likewise.
 520         (VEX_LEN_0F5A_P_1): Likewise.
 521         (VEX_LEN_0F5A_P_3): Likewise.
 522         (VEX_LEN_0F5C_P_1): Likewise.
 523         (VEX_LEN_0F5C_P_3): Likewise.
 524         (VEX_LEN_0F5D_P_1): Likewise.
 525         (VEX_LEN_0F5D_P_3): Likewise.
 526         (VEX_LEN_0F5E_P_1): Likewise.
 527         (VEX_LEN_0F5E_P_3): Likewise.
 528         (VEX_LEN_0F5F_P_1): Likewise.
 529         (VEX_LEN_0F5F_P_3): Likewise.
 530         (VEX_LEN_0FC2_P_1): Likewise.
 531         (VEX_LEN_0FC2_P_3): Likewise.
 532         (VEX_LEN_0F3A0A_P_2): Likewise.
 533         (VEX_LEN_0F3A0B_P_2): Likewise.
 534         (VEX_W_0F10_P_0): Likewise.
 535         (VEX_W_0F10_P_1): Likewise.
 536         (VEX_W_0F10_P_2): Likewise.
 537         (VEX_W_0F10_P_3): Likewise.
 538         (VEX_W_0F11_P_0): Likewise.
 539         (VEX_W_0F11_P_1): Likewise.
 540         (VEX_W_0F11_P_2): Likewise.
 541         (VEX_W_0F11_P_3): Likewise.
 542         (VEX_W_0F12_P_0_M_0): Likewise.
 543         (VEX_W_0F12_P_0_M_1): Likewise.
 544         (VEX_W_0F12_P_1): Likewise.
 545         (VEX_W_0F12_P_2): Likewise.
 546         (VEX_W_0F12_P_3): Likewise.
 547         (VEX_W_0F13_M_0): Likewise.
 548         (VEX_W_0F14): Likewise.
 549         (VEX_W_0F15): Likewise.
 550         (VEX_W_0F16_P_0_M_0): Likewise.
 551         (VEX_W_0F16_P_0_M_1): Likewise.
 552         (VEX_W_0F16_P_1): Likewise.
 553         (VEX_W_0F16_P_2): Likewise.
 554         (VEX_W_0F17_M_0): Likewise.
 555         (VEX_W_0F28): Likewise.
 556         (VEX_W_0F29): Likewise.
 557         (VEX_W_0F2B_M_0): Likewise.
 558         (VEX_W_0F2E_P_0): Likewise.
 559         (VEX_W_0F2E_P_2): Likewise.
 560         (VEX_W_0F2F_P_0): Likewise.
 561         (VEX_W_0F2F_P_2): Likewise.
 562         (VEX_W_0F50_M_0): Likewise.
 563         (VEX_W_0F51_P_0): Likewise.
 564         (VEX_W_0F51_P_1): Likewise.
 565         (VEX_W_0F51_P_2): Likewise.
 566         (VEX_W_0F51_P_3): Likewise.
 567         (VEX_W_0F52_P_0): Likewise.
 568         (VEX_W_0F52_P_1): Likewise.
 569         (VEX_W_0F53_P_0): Likewise.
 570         (VEX_W_0F53_P_1): Likewise.
 571         (VEX_W_0F58_P_0): Likewise.
 572         (VEX_W_0F58_P_1): Likewise.
 573         (VEX_W_0F58_P_2): Likewise.
 574         (VEX_W_0F58_P_3): Likewise.
 575         (VEX_W_0F59_P_0): Likewise.
 576         (VEX_W_0F59_P_1): Likewise.
 577         (VEX_W_0F59_P_2): Likewise.
 578         (VEX_W_0F59_P_3): Likewise.
 579         (VEX_W_0F5A_P_0): Likewise.
 580         (VEX_W_0F5A_P_1): Likewise.
 581         (VEX_W_0F5A_P_3): Likewise.
 582         (VEX_W_0F5B_P_0): Likewise.
 583         (VEX_W_0F5B_P_1): Likewise.
 584         (VEX_W_0F5B_P_2): Likewise.
 585         (VEX_W_0F5C_P_0): Likewise.
 586         (VEX_W_0F5C_P_1): Likewise.
 587         (VEX_W_0F5C_P_2): Likewise.
 588         (VEX_W_0F5C_P_3): Likewise.
 589         (VEX_W_0F5D_P_0): Likewise.
 590         (VEX_W_0F5D_P_1): Likewise.
 591         (VEX_W_0F5D_P_2): Likewise.
 592         (VEX_W_0F5D_P_3): Likewise.
 593         (VEX_W_0F5E_P_0): Likewise.
 594         (VEX_W_0F5E_P_1): Likewise.
 595         (VEX_W_0F5E_P_2): Likewise.
 596         (VEX_W_0F5E_P_3): Likewise.
 597         (VEX_W_0F5F_P_0): Likewise.
 598         (VEX_W_0F5F_P_1): Likewise.
 599         (VEX_W_0F5F_P_2): Likewise.
 600         (VEX_W_0F5F_P_3): Likewise.
 601         (VEX_W_0F60_P_2): Likewise.
 602         (VEX_W_0F61_P_2): Likewise.
 603         (VEX_W_0F62_P_2): Likewise.
 604         (VEX_W_0F63_P_2): Likewise.
 605         (VEX_W_0F64_P_2): Likewise.
 606         (VEX_W_0F65_P_2): Likewise.
 607         (VEX_W_0F66_P_2): Likewise.
 608         (VEX_W_0F67_P_2): Likewise.
 609         (VEX_W_0F68_P_2): Likewise.
 610         (VEX_W_0F69_P_2): Likewise.
 611         (VEX_W_0F6A_P_2): Likewise.
 612         (VEX_W_0F6B_P_2): Likewise.
 613         (VEX_W_0F6C_P_2): Likewise.
 614         (VEX_W_0F6D_P_2): Likewise.
 615         (VEX_W_0F6F_P_1): Likewise.
 616         (VEX_W_0F6F_P_2): Likewise.
 617         (VEX_W_0F70_P_1): Likewise.
 618         (VEX_W_0F70_P_2): Likewise.
 619         (VEX_W_0F70_P_3): Likewise.
 620         (VEX_W_0F71_R_2_P_2): Likewise.
 621         (VEX_W_0F71_R_4_P_2): Likewise.
 622         (VEX_W_0F71_R_6_P_2): Likewise.
 623         (VEX_W_0F72_R_2_P_2): Likewise.
 624         (VEX_W_0F72_R_4_P_2): Likewise.
 625         (VEX_W_0F72_R_6_P_2): Likewise.
 626         (VEX_W_0F73_R_2_P_2): Likewise.
 627         (VEX_W_0F73_R_3_P_2): Likewise.
 628         (VEX_W_0F73_R_6_P_2): Likewise.
 629         (VEX_W_0F73_R_7_P_2): Likewise.
 630         (VEX_W_0F74_P_2): Likewise.
 631         (VEX_W_0F75_P_2): Likewise.
 632         (VEX_W_0F76_P_2): Likewise.
 633         (VEX_W_0F77_P_0): Likewise.
 634         (VEX_W_0F7C_P_2): Likewise.
 635         (VEX_W_0F7C_P_3): Likewise.
 636         (VEX_W_0F7D_P_2): Likewise.
 637         (VEX_W_0F7D_P_3): Likewise.
 638         (VEX_W_0F7E_P_1): Likewise.
 639         (VEX_W_0F7F_P_1): Likewise.
 640         (VEX_W_0F7F_P_2): Likewise.
 641         (VEX_W_0FAE_R_2_M_0): Likewise.
 642         (VEX_W_0FAE_R_3_M_0): Likewise.
 643         (VEX_W_0FC2_P_0): Likewise.
 644         (VEX_W_0FC2_P_1): Likewise.
 645         (VEX_W_0FC2_P_2): Likewise.
 646         (VEX_W_0FC2_P_3): Likewise.
 647         (VEX_W_0FD0_P_2): Likewise.
 648         (VEX_W_0FD0_P_3): Likewise.
 649         (VEX_W_0FD1_P_2): Likewise.
 650         (VEX_W_0FD2_P_2): Likewise.
 651         (VEX_W_0FD3_P_2): Likewise.
 652         (VEX_W_0FD4_P_2): Likewise.
 653         (VEX_W_0FD5_P_2): Likewise.
 654         (VEX_W_0FD6_P_2): Likewise.
 655         (VEX_W_0FD7_P_2_M_1): Likewise.
 656         (VEX_W_0FD8_P_2): Likewise.
 657         (VEX_W_0FD9_P_2): Likewise.
 658         (VEX_W_0FDA_P_2): Likewise.
 659         (VEX_W_0FDB_P_2): Likewise.
 660         (VEX_W_0FDC_P_2): Likewise.
 661         (VEX_W_0FDD_P_2): Likewise.
 662         (VEX_W_0FDE_P_2): Likewise.
 663         (VEX_W_0FDF_P_2): Likewise.
 664         (VEX_W_0FE0_P_2): Likewise.
 665         (VEX_W_0FE1_P_2): Likewise.
 666         (VEX_W_0FE2_P_2): Likewise.
 667         (VEX_W_0FE3_P_2): Likewise.
 668         (VEX_W_0FE4_P_2): Likewise.
 669         (VEX_W_0FE5_P_2): Likewise.
 670         (VEX_W_0FE6_P_1): Likewise.
 671         (VEX_W_0FE6_P_2): Likewise.
 672         (VEX_W_0FE6_P_3): Likewise.
 673         (VEX_W_0FE7_P_2_M_0): Likewise.
 674         (VEX_W_0FE8_P_2): Likewise.
 675         (VEX_W_0FE9_P_2): Likewise.
 676         (VEX_W_0FEA_P_2): Likewise.
 677         (VEX_W_0FEB_P_2): Likewise.
 678         (VEX_W_0FEC_P_2): Likewise.
 679         (VEX_W_0FED_P_2): Likewise.
 680         (VEX_W_0FEE_P_2): Likewise.
 681         (VEX_W_0FEF_P_2): Likewise.
 682         (VEX_W_0FF0_P_3_M_0): Likewise.
 683         (VEX_W_0FF1_P_2): Likewise.
 684         (VEX_W_0FF2_P_2): Likewise.
 685         (VEX_W_0FF3_P_2): Likewise.
 686         (VEX_W_0FF4_P_2): Likewise.
 687         (VEX_W_0FF5_P_2): Likewise.
 688         (VEX_W_0FF6_P_2): Likewise.
 689         (VEX_W_0FF7_P_2): Likewise.
 690         (VEX_W_0FF8_P_2): Likewise.
 691         (VEX_W_0FF9_P_2): Likewise.
 692         (VEX_W_0FFA_P_2): Likewise.
 693         (VEX_W_0FFB_P_2): Likewise.
 694         (VEX_W_0FFC_P_2): Likewise.
 695         (VEX_W_0FFD_P_2): Likewise.
 696         (VEX_W_0FFE_P_2): Likewise.
 697         (VEX_W_0F3800_P_2): Likewise.
 698         (VEX_W_0F3801_P_2): Likewise.
 699         (VEX_W_0F3802_P_2): Likewise.
 700         (VEX_W_0F3803_P_2): Likewise.
 701         (VEX_W_0F3804_P_2): Likewise.
 702         (VEX_W_0F3805_P_2): Likewise.
 703         (VEX_W_0F3806_P_2): Likewise.
 704         (VEX_W_0F3807_P_2): Likewise.
 705         (VEX_W_0F3808_P_2): Likewise.
 706         (VEX_W_0F3809_P_2): Likewise.
 707         (VEX_W_0F380A_P_2): Likewise.
 708         (VEX_W_0F380B_P_2): Likewise.
 709         (VEX_W_0F3817_P_2): Likewise.
 710         (VEX_W_0F381C_P_2): Likewise.
 711         (VEX_W_0F381D_P_2): Likewise.
 712         (VEX_W_0F381E_P_2): Likewise.
 713         (VEX_W_0F3820_P_2): Likewise.
 714         (VEX_W_0F3821_P_2): Likewise.
 715         (VEX_W_0F3822_P_2): Likewise.
 716         (VEX_W_0F3823_P_2): Likewise.
 717         (VEX_W_0F3824_P_2): Likewise.
 718         (VEX_W_0F3825_P_2): Likewise.
 719         (VEX_W_0F3828_P_2): Likewise.
 720         (VEX_W_0F3829_P_2): Likewise.
 721         (VEX_W_0F382A_P_2_M_0): Likewise.
 722         (VEX_W_0F382B_P_2): Likewise.
 723         (VEX_W_0F3830_P_2): Likewise.
 724         (VEX_W_0F3831_P_2): Likewise.
 725         (VEX_W_0F3832_P_2): Likewise.
 726         (VEX_W_0F3833_P_2): Likewise.
 727         (VEX_W_0F3834_P_2): Likewise.
 728         (VEX_W_0F3835_P_2): Likewise.
 729         (VEX_W_0F3837_P_2): Likewise.
 730         (VEX_W_0F3838_P_2): Likewise.
 731         (VEX_W_0F3839_P_2): Likewise.
 732         (VEX_W_0F383A_P_2): Likewise.
 733         (VEX_W_0F383B_P_2): Likewise.
 734         (VEX_W_0F383C_P_2): Likewise.
 735         (VEX_W_0F383D_P_2): Likewise.
 736         (VEX_W_0F383E_P_2): Likewise.
 737         (VEX_W_0F383F_P_2): Likewise.
 738         (VEX_W_0F3840_P_2): Likewise.
 739         (VEX_W_0F3841_P_2): Likewise.
 740         (VEX_W_0F38DB_P_2): Likewise.
 741         (VEX_W_0F3A08_P_2): Likewise.
 742         (VEX_W_0F3A09_P_2): Likewise.
 743         (VEX_W_0F3A0A_P_2): Likewise.
 744         (VEX_W_0F3A0B_P_2): Likewise.
 745         (VEX_W_0F3A0C_P_2): Likewise.
 746         (VEX_W_0F3A0D_P_2): Likewise.
 747         (VEX_W_0F3A0E_P_2): Likewise.
 748         (VEX_W_0F3A0F_P_2): Likewise.
 749         (VEX_W_0F3A21_P_2): Likewise.
 750         (VEX_W_0F3A40_P_2): Likewise.
 751         (VEX_W_0F3A41_P_2): Likewise.
 752         (VEX_W_0F3A42_P_2): Likewise.
 753         (VEX_W_0F3A62_P_2): Likewise.
 754         (VEX_W_0F3A63_P_2): Likewise.
 755         (VEX_W_0F3ADF_P_2): Likewise.
 756         (VEX_LEN_0F77_P_0): New.
 757         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 758         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 759         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 760         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 761         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 762         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 763         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 764         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 765         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 766         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 767         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 768         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 769         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 770         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 771         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 772         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 773         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 774         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 775         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 776         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 777         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 778         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 779         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 780         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 781         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 782         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 783         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 784         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 785         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 786         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 787         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 788         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 789         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 790         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 791         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 792         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 793         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 794         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 795         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 796         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 797         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 798         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 799         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 800         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 801         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 802         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 803         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 804         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 805         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 806         (vex_table): Update VEX 0F28 and 0F29 entries.
 807         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 808         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 809         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 810         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 811         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 812         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 813         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 814         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 815         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 816         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 817         VEX_LEN_0F3A0B_P_2 entries.
 818         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 819         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 820         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 821         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 822         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 823         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 824         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 825         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 826         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 827         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 828         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 829         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 830         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 831         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 832         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 833         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 834         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 835         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 836         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 837         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 838         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 839         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 840         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 841         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 842         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 843         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 844         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 845         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 846         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 847         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 848         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 849         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 850         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 851         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 852         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 853         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 854         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 855         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 856         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 857         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 858         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 859         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 860         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 861         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 862         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 863         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 864         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 865         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 866         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 867         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 868         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 869         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 870         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 871         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 872         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 873         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 874         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 875         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 876         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 877         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 878         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 879         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 880         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 881         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 882         VEX_W_0F3ADF_P_2 entries.
 883         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 884         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 885         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 886
 887 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 888
 889         * i386-opc.tbl (VexWIG): New.
 890         Replace VexW=3 with VexWIG.
 891
 892 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 893
 894         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 895         * i386-tbl.h: Regenerated.
 896
 897 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 898
 899         PR gas/23665
 900         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 901         VEX_LEN_0FD6_P_2 entries.
 902         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 903         * i386-tbl.h: Regenerated.
 904
 905 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 906
 907         PR gas/23642
 908         * i386-opc.h (VEXWIG): New.
 909         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 910         * i386-tbl.h: Regenerated.
 911
 912 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 913
 914         PR binutils/23655
 915         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 916         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 917         * i386-dis.c (EXxEVexR64): New.
 918         (evex_rounding_64_mode): Likewise.
 919         (OP_Rounding): Handle evex_rounding_64_mode.
 920
 921 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 922
 923         PR binutils/23655
 924         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 925         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 926         * i386-dis.c (Edqa): New.
 927         (dqa_mode): Likewise.
 928         (intel_operand_size): Handle dqa_mode as m_mode.
 929         (OP_E_register): Handle dqa_mode as dq_mode.
 930         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 931
 932 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 933
 934         * i386-dis.c (OP_E_memory): Reformat.
 935
 936 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 937
 938         * i386-opc.tbl (crc32): Fold byte and word forms.
 939         * i386-tbl.h: Re-generate.
 940
 941 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 942
 943         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 944         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 945         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 946         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 947         * i386-tbl.h: Regenerated.
 948
 949 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 950
 951         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 952         meaningless.
 953         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 954         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 955         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 956         * i386-tbl.h: Re-generate.
 957
 958 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 959
 960         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 961         AVX512_4VNNIW insns.
 962         * i386-tbl.h: Re-generate.
 963
 964 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 965
 966         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 967         meaningless.
 968         * i386-tbl.h: Re-generate.
 969
 970 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 971
 972         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 973         meaningless.
 974         * i386-tbl.h: Re-generate.
 975
 976 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 977
 978         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 979         meaningless.
 980         * i386-tbl.h: Re-generate.
 981
 982 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 985         meaningless.
 986         * i386-tbl.h: Re-generate.
 987
 988 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 989
 990         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 991         meaningless.
 992         * i386-tbl.h: Re-generate.
 993
 994 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 997         * i386-tbl.h: Re-generate.
 998
 999 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1000
1001         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
1002         * i386-tbl.h: Re-generate.
1003
1004 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1005
1006         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
1007         meaningless.
1008         * i386-tbl.h: Re-generate.
1009
1010 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1011
1012         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
1013         meaningless.
1014         * i386-tbl.h: Re-generate.
1015
1016 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1017
1018         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
1019         * i386-tbl.h: Re-generate.
1020
1021 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1022
1023         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
1024         * i386-tbl.h: Re-generate.
1025
1026 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1027
1028         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
1029         * i386-tbl.h: Re-generate.
1030
1031 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1032
1033         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
1034         meaningless.
1035         * i386-tbl.h: Re-generate.
1036
1037 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1038
1039         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
1040         meaningless.
1041         * i386-tbl.h: Re-generate.
1042
1043 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1044
1045         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1046         meaningless.
1047         * i386-tbl.h: Re-generate.
1048
1049 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1050
1051         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1052         * i386-tbl.h: Re-generate.
1053
1054 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1057         * i386-tbl.h: Re-generate.
1058
1059 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1060
1061         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1062         * i386-tbl.h: Re-generate.
1063
1064 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1065
1066         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1067         (vpbroadcastw, rdpid): Drop NoRex64.
1068         * i386-tbl.h: Re-generate.
1069
1070 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1071
1072         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1073         store templates, adding D.
1074         * i386-tbl.h: Re-generate.
1075
1076 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1077
1078         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1079         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1080         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1081         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1082         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1083         Fold load and store templates where possible, adding D. Drop
1084         IgnoreSize where it was pointlessly present. Drop redundant
1085         *word.
1086         * i386-tbl.h: Re-generate.
1087
1088 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1089
1090         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1091         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1092         (intel_operand_size): Handle v_bndmk_mode.
1093         (OP_E_memory): Likewise. Produce (bad) when also riprel.
1094
1095 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
1096
1097         * disassemble.c (ARCH_s12z): Define if ARCH_all.
1098
1099 2018-08-31  Kito Cheng  <kito@andestech.com>
1100
1101         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1102         compressed floating point instructions.
1103
1104 2018-08-30  Kito Cheng  <kito@andestech.com>
1105
1106         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1107         riscv_opcode.xlen_requirement.
1108         * riscv-opc.c (riscv_opcodes): Update for struct change.
1109
1110 2018-08-29  Martin Aberg  <maberg@gaisler.com>
1111
1112         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1113         psr (PWRPSR) instruction.
1114
1115 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1116
1117         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1118
1119 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1120
1121         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1122
1123 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1124
1125         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1126         loongson3a as an alias of gs464 for compatibility.
1127         * mips-opc.c (mips_opcodes): Change Comments.
1128
1129 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1130
1131         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1132         option.
1133         (print_mips_disassembler_options): Document -M loongson-ext.
1134         * mips-opc.c (LEXT2): New macro.
1135         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1136
1137 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1138
1139          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1140          descriptors.
1141          (parse_mips_ase_option): Handle -M loongson-ext option.
1142          (print_mips_disassembler_options): Document -M loongson-ext.
1143          * mips-opc.c (IL3A): Delete.
1144          * mips-opc.c (LEXT): New macro.
1145          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1146          instructions.
1147
1148 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1149
1150         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1151         descriptors.
1152         (parse_mips_ase_option): Handle -M loongson-cam option.
1153         (print_mips_disassembler_options): Document -M loongson-cam.
1154         * mips-opc.c (LCAM): New macro.
1155         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1156         instructions.
1157
1158 2018-08-21  Alan Modra  <amodra@gmail.com>
1159
1160         * ppc-dis.c (operand_value_powerpc): Init "invalid".
1161         (skip_optional_operands): Count optional operands, and update
1162         ppc_optional_operand_value call.
1163         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1164         (extract_vlensi): Likewise.
1165         (extract_fxm): Return default value for missing optional operand.
1166         (extract_ls, extract_raq, extract_tbr): Likewise.
1167         (insert_sxl, extract_sxl): New functions.
1168         (insert_esync, extract_esync): Remove Power9 handling and simplify.
1169         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1170         flag and extra entry.
1171         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1172         extract_sxl.
1173
1174 2018-08-20  Alan Modra  <amodra@gmail.com>
1175
1176         * sh-opc.h (MASK): Simplify.
1177
1178 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1179
1180         * s12z-dis.c (bm_decode): Deal with cases where the mode is
1181         BM_RESERVED0 or BM_RESERVED1
1182         (bm_rel_decode, bm_n_bytes): Ditto.
1183
1184 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1185
1186         * s12z.h: Delete.
1187
1188 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1189
1190         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1191         address with the addr32 prefix and without base nor index
1192         registers.
1193
1194 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1195
1196         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1197         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1198         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1199         (cpu_flags): Add CpuCMOV and CpuFXSR.
1200         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1201         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1202         * i386-init.h: Regenerated.
1203         * i386-tbl.h: Likewise.
1204
1205 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1206
1207         * arc-regs.h: Update auxiliary registers.
1208
1209 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1210
1211         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1212         (RegIP, RegIZ): Define.
1213         * i386-reg.tbl: Adjust comments.
1214         (rip): Use Qword instead of BaseIndex. Use RegIP.
1215         (eip): Use Dword instead of BaseIndex. Use RegIP.
1216         (riz): Add Qword. Use RegIZ.
1217         (eiz): Add Dword. Use RegIZ.
1218         * i386-tbl.h: Re-generate.
1219
1220 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1221
1222         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1223         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1224         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1225         * i386-tbl.h: Re-generate.
1226
1227 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1228
1229         * i386-gen.c (operand_types): Remove Mem field.
1230         * i386-opc.h (union i386_operand_type): Remove mem field.
1231         * i386-init.h, i386-tbl.h: Re-generate.
1232
1233 2018-08-01  Alan Modra  <amodra@gmail.com>
1234
1235         * po/POTFILES.in: Regenerate.
1236
1237 2018-07-31  Nick Clifton  <nickc@redhat.com>
1238
1239         * po/sv.po: Updated Swedish translation.
1240
1241 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1242
1243         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1244         * i386-init.h, i386-tbl.h: Re-generate.
1245
1246 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1247
1248         * i386-opc.h (ZEROING_MASKING) Rename to ...
1249         (DYNAMIC_MASKING): ... this. Adjust comment.
1250         * i386-opc.tbl (MaskingMorZ): Define.
1251         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1252         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1253         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1254         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1255         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1256         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1257         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1258         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1259         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1260
1261 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1262
1263         * i386-opc.tbl: Use element rather than vector size for AVX512*
1264         scatter/gather insns.
1265         * i386-tbl.h: Re-generate.
1266
1267 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1268
1269         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1270         (cpu_flags): Drop CpuVREX.
1271         * i386-opc.h (CpuVREX): Delete.
1272         (union i386_cpu_flags): Remove cpuvrex.
1273         * i386-init.h, i386-tbl.h: Re-generate.
1274
1275 2018-07-30  Jim Wilson  <jimw@sifive.com>
1276
1277         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1278         fields.
1279         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1280
1281 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1282
1283         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1284         * Makefile.in: Regenerated.
1285         * configure.ac: Add C-SKY.
1286         * configure: Regenerated.
1287         * csky-dis.c: New file.
1288         * csky-opc.h: New file.
1289         * disassemble.c (ARCH_csky): Define.
1290         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1291         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1292
1293 2018-07-27  Alan Modra  <amodra@gmail.com>
1294
1295         * ppc-opc.c (insert_sprbat): Correct function parameter and
1296         return type.
1297         (extract_sprbat): Likewise, variable too.
1298
1299 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1300             Alan Modra  <amodra@gmail.com>
1301
1302         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1303         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1304         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1305         support disjointed BAT.
1306         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1307         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1308         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1309
1310 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1311             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1312
1313         * i386-gen.c (adjust_broadcast_modifier): New function.
1314         (process_i386_opcode_modifier): Add an argument for operands.
1315         Adjust the Broadcast value based on operands.
1316         (output_i386_opcode): Pass operand_types to
1317         process_i386_opcode_modifier.
1318         (process_i386_opcodes): Pass NULL as operands to
1319         process_i386_opcode_modifier.
1320         * i386-opc.h (BYTE_BROADCAST): New.
1321         (WORD_BROADCAST): Likewise.
1322         (DWORD_BROADCAST): Likewise.
1323         (QWORD_BROADCAST): Likewise.
1324         (i386_opcode_modifier): Expand broadcast to 3 bits.
1325         * i386-tbl.h: Regenerated.
1326
1327 2018-07-24  Alan Modra  <amodra@gmail.com>
1328
1329         PR 23430
1330         * or1k-desc.h: Regenerate.
1331
1332 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1333
1334         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1335         vcvtusi2ss, and vcvtusi2sd.
1336         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1337         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1338         * i386-tbl.h: Re-generate.
1339
1340 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1341
1342         * arc-opc.c (extract_w6): Fix extending the sign.
1343
1344 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1345
1346         * arc-tbl.h (vewt): Allow it for ARC EM family.
1347
1348 2018-07-23  Alan Modra  <amodra@gmail.com>
1349
1350         PR 23419
1351         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1352         opcode variants for mtspr/mfspr encodings.
1353
1354 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1355             Maciej W. Rozycki  <macro@mips.com>
1356
1357         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1358         loongson3a descriptors.
1359         (parse_mips_ase_option): Handle -M loongson-mmi option.
1360         (print_mips_disassembler_options): Document -M loongson-mmi.
1361         * mips-opc.c (LMMI): New macro.
1362         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1363         instructions.
1364
1365 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1366
1367         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1368         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1369         IgnoreSize and [XYZ]MMword where applicable.
1370         * i386-tbl.h: Re-generate.
1371
1372 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1373
1374         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1375         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1376         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1377         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1378         * i386-tbl.h: Re-generate.
1379
1380 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1381
1382         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1383         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1384         VPCLMULQDQ templates into their respective AVX512VL counterparts
1385         where possible, using Disp8ShiftVL and CheckRegSize instead of
1386         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1387         * i386-tbl.h: Re-generate.
1388
1389 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1390
1391         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1392         AVX512VL counterparts where possible, using Disp8ShiftVL and
1393         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1394         IgnoreSize) as appropriate.
1395         * i386-tbl.h: Re-generate.
1396
1397 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1398
1399         * i386-opc.tbl: Fold AVX512BW templates into their respective
1400         AVX512VL counterparts where possible, using Disp8ShiftVL and
1401         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1402         IgnoreSize) as appropriate.
1403         * i386-tbl.h: Re-generate.
1404
1405 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1406
1407         * i386-opc.tbl: Fold AVX512CD templates into their respective
1408         AVX512VL counterparts where possible, using Disp8ShiftVL and
1409         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1410         IgnoreSize) as appropriate.
1411         * i386-tbl.h: Re-generate.
1412
1413 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1414
1415         * i386-opc.h (DISP8_SHIFT_VL): New.
1416         * i386-opc.tbl (Disp8ShiftVL):  Define.
1417         (various): Fold AVX512VL templates into their respective
1418         AVX512F counterparts where possible, using Disp8ShiftVL and
1419         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1420         IgnoreSize) as appropriate.
1421         * i386-tbl.h: Re-generate.
1422
1423 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1424
1425         * Makefile.am: Change dependencies and rule for
1426         $(srcdir)/i386-init.h.
1427         * Makefile.in: Re-generate.
1428         * i386-gen.c (process_i386_opcodes): New local variable
1429         "marker". Drop opening of input file. Recognize marker and line
1430         number directives.
1431         * i386-opc.tbl (OPCODE_I386_H): Define.
1432         (i386-opc.h): Include it.
1433         (None): Undefine.
1434
1435 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1436
1437         PR gas/23418
1438         * i386-opc.h (Byte): Update comments.
1439         (Word): Likewise.
1440         (Dword): Likewise.
1441         (Fword): Likewise.
1442         (Qword): Likewise.
1443         (Tbyte): Likewise.
1444         (Xmmword): Likewise.
1445         (Ymmword): Likewise.
1446         (Zmmword): Likewise.
1447         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1448         vcvttps2uqq.
1449         * i386-tbl.h: Regenerated.
1450
1451 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1452
1453         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1454         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1455         * aarch64-asm-2.c: Regenerate.
1456         * aarch64-dis-2.c: Regenerate.
1457         * aarch64-opc-2.c: Regenerate.
1458
1459 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1460
1461         PR binutils/23192
1462         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1463         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1464         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1465         sqdmulh, sqrdmulh): Use Em16.
1466
1467 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1468
1469         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1470         csdb together with them.
1471         (thumb32_opcodes): Likewise.
1472
1473 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1474
1475         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1476         requiring 32-bit registers as operands 2 and 3. Improve
1477         comments.
1478         (mwait, mwaitx): Fold templates. Improve comments.
1479         OPERAND_TYPE_INOUTPORTREG.
1480         * i386-tbl.h: Re-generate.
1481
1482 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1483
1484         * i386-gen.c (operand_type_init): Remove
1485         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1486         OPERAND_TYPE_INOUTPORTREG.
1487         * i386-init.h: Re-generate.
1488
1489 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1490
1491         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1492         (wrssq, wrussq): Add Qword.
1493         * i386-tbl.h: Re-generate.
1494
1495 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1496
1497         * i386-opc.h: Rename OTMax to OTNum.
1498         (OTNumOfUints): Adjust calculation.
1499         (OTUnused): Directly alias to OTNum.
1500
1501 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1502
1503         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1504         `reg_xys'.
1505         (lea_reg_xys): Likewise.
1506         (print_insn_loop_primitive): Rename `reg' local variable to
1507         `reg_dxy'.
1508
1509 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1510
1511         PR binutils/23242
1512         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1513
1514 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1515
1516         PR binutils/23369
1517         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1518         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1519
1520 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1521
1522         PR tdep/8282
1523         * mips-dis.c (mips_option_arg_t): New enumeration.
1524         (mips_options): New variable.
1525         (disassembler_options_mips): New function.
1526         (print_mips_disassembler_options): Reimplement in terms of
1527         `disassembler_options_mips'.
1528         * arm-dis.c (disassembler_options_arm): Adapt to using the
1529         `disasm_options_and_args_t' structure.
1530         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1531         * s390-dis.c (disassembler_options_s390): Likewise.
1532
1533 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1534
1535         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1536         expected result.
1537         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1538         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1539         * testsuite/ld-arm/tls-longplt.d: Likewise.
1540
1541 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1542
1543         PR binutils/23192
1544         * aarch64-asm-2.c: Regenerate.
1545         * aarch64-dis-2.c: Likewise.
1546         * aarch64-opc-2.c: Likewise.
1547         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1548         * aarch64-opc.c (operand_general_constraint_met_p,
1549         aarch64_print_operand): Likewise.
1550         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1551         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1552         fmlal2, fmlsl2.
1553         (AARCH64_OPERANDS): Add Em2.
1554
1555 2018-06-26  Nick Clifton  <nickc@redhat.com>
1556
1557         * po/uk.po: Updated Ukranian translation.
1558         * po/de.po: Updated German translation.
1559         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1560
1561 2018-06-26  Nick Clifton  <nickc@redhat.com>
1562
1563         * nfp-dis.c: Fix spelling mistake.
1564
1565 2018-06-24  Nick Clifton  <nickc@redhat.com>
1566
1567         * configure: Regenerate.
1568         * po/opcodes.pot: Regenerate.
1569
1570 2018-06-24  Nick Clifton  <nickc@redhat.com>
1571
1572         2.31 branch created.
1573
1574 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1575
1576         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1577         * aarch64-asm-2.c: Regenerate.
1578         * aarch64-dis-2.c: Likewise.
1579
1580 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1581
1582         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1583         `-M ginv' option description.
1584
1585 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1586
1587         PR gas/23305
1588         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1589         la and lla.
1590
1591 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1592
1593         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1594         * configure.ac: Remove AC_PREREQ.
1595         * Makefile.in: Re-generate.
1596         * aclocal.m4: Re-generate.
1597         * configure: Re-generate.
1598
1599 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1600
1601         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1602         mips64r6 descriptors.
1603         (parse_mips_ase_option): Handle -Mginv option.
1604         (print_mips_disassembler_options): Document -Mginv.
1605         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1606         (GINV): New macro.
1607         (mips_opcodes): Define ginvi and ginvt.
1608
1609 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1610             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1611
1612         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1613         * mips-opc.c (CRC, CRC64): New macros.
1614         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1615         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1616         crc32cd for CRC64.
1617
1618 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1619
1620         PR 20319
1621         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1622         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1623
1624 2018-06-06  Alan Modra  <amodra@gmail.com>
1625
1626         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1627         setjmp.  Move init for some other vars later too.
1628
1629 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1630
1631         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1632         (dis_private): Add new fields for property section tracking.
1633         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1634         (xtensa_instruction_fits): New functions.
1635         (fetch_data): Bump minimal fetch size to 4.
1636         (print_insn_xtensa): Make struct dis_private static.
1637         Load and prepare property table on section change.
1638         Don't disassemble literals. Don't disassemble instructions that
1639         cross property table boundaries.
1640
1641 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1642
1643         * configure: Regenerated.
1644
1645 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1646
1647         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1648         * i386-tbl.h: Re-generate.
1649
1650 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1651
1652         * i386-opc.tbl (sldt, str): Add NoRex64.
1653         * i386-tbl.h: Re-generate.
1654
1655 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1656
1657         * i386-opc.tbl (invpcid): Add Oword.
1658         * i386-tbl.h: Re-generate.
1659
1660 2018-06-01  Alan Modra  <amodra@gmail.com>
1661
1662         * sysdep.h (_bfd_error_handler): Don't declare.
1663         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1664         * rl78-decode.opc: Likewise.
1665         * msp430-decode.c: Regenerate.
1666         * rl78-decode.c: Regenerate.
1667
1668 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1669
1670         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1671         * i386-init.h : Regenerated.
1672
1673 2018-05-25  Alan Modra  <amodra@gmail.com>
1674
1675         * Makefile.in: Regenerate.
1676         * po/POTFILES.in: Regenerate.
1677
1678 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1679
1680         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1681         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1682         (insert_bab, extract_bab, insert_btab, extract_btab,
1683         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1684         (BAT, BBA VBA RBS XB6S): Delete macros.
1685         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1686         (BB, BD, RBX, XC6): Update for new macros.
1687         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1688         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1689         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1690         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1691
1692 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1693
1694         * Makefile.am: Add support for s12z architecture.
1695         * configure.ac: Likewise.
1696         * disassemble.c: Likewise.
1697         * disassemble.h: Likewise.
1698         * Makefile.in: Regenerate.
1699         * configure: Regenerate.
1700         * s12z-dis.c: New file.
1701         * s12z.h: New file.
1702
1703 2018-05-18  Alan Modra  <amodra@gmail.com>
1704
1705         * nfp-dis.c: Don't #include libbfd.h.
1706         (init_nfp3200_priv): Use bfd_get_section_contents.
1707         (nit_nfp6000_mecsr_sec): Likewise.
1708
1709 2018-05-17  Nick Clifton  <nickc@redhat.com>
1710
1711         * po/zh_CN.po: Updated simplified Chinese translation.
1712
1713 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1714
1715         PR binutils/23109
1716         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1717         * aarch64-dis-2.c: Regenerate.
1718
1719 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1720
1721         PR binutils/21446
1722         * aarch64-asm.c (opintl.h): Include.
1723         (aarch64_ins_sysreg): Enforce read/write constraints.
1724         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1725         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1726         (F_REG_READ, F_REG_WRITE): New.
1727         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1728         AARCH64_OPND_SYSREG.
1729         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1730         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1731         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1732         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1733         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1734         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1735         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1736         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1737         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1738         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1739         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1740         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1741         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1742         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1743         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1744         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1745         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1746
1747 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1748
1749         PR binutils/21446
1750         * aarch64-dis.c (no_notes: New.
1751         (parse_aarch64_dis_option): Support notes.
1752         (aarch64_decode_insn, print_operands): Likewise.
1753         (print_aarch64_disassembler_options): Document notes.
1754         * aarch64-opc.c (aarch64_print_operand): Support notes.
1755
1756 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1757
1758         PR binutils/21446
1759         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1760         and take error struct.
1761         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1762         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1763         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1764         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1765         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1766         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1767         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1768         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1769         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1770         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1771         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1772         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1773         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1774         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1775         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1776         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1777         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1778         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1779         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1780         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1781         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1782         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1783         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1784         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1785         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1786         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1787         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1788         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1789         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1790         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1791         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1792         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1793         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1794         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1795         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1796         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1797         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1798         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1799         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1800         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1801         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1802         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1803         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1804         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1805         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1806         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1807         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1808         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1809         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1810         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1811         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1812         (determine_disassembling_preference, aarch64_decode_insn,
1813         print_insn_aarch64_word, print_insn_data): Take errors struct.
1814         (print_insn_aarch64): Use errors.
1815         * aarch64-asm-2.c: Regenerate.
1816         * aarch64-dis-2.c: Regenerate.
1817         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1818         boolean in aarch64_insert_operan.
1819         (print_operand_extractor): Likewise.
1820         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1821
1822 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1823
1824         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1825
1826 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1827
1828         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1829
1830 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1831
1832         * cr16-opc.c (cr16_instruction): Comment typo fix.
1833         * hppa-dis.c (print_insn_hppa): Likewise.
1834
1835 2018-05-08  Jim Wilson  <jimw@sifive.com>
1836
1837         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1838         (match_c_slli64, match_srxi_as_c_srxi): New.
1839         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1840         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1841         <c.slli, c.srli, c.srai>: Use match_s_slli.
1842         <c.slli64, c.srli64, c.srai64>: New.
1843
1844 2018-05-08  Alan Modra  <amodra@gmail.com>
1845
1846         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1847         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1848         partition opcode space for index lookup.
1849
1850 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1851
1852         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1853         <insn_length>: ...with this.  Update usage.
1854         Remove duplicate call to *info->memory_error_func.
1855
1856 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1857             H.J. Lu  <hongjiu.lu@intel.com>
1858
1859         * i386-dis.c (Gva): New.
1860         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1861         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1862         (prefix_table): New instructions (see prefix above).
1863         (mod_table): New instructions (see prefix above).
1864         (OP_G): Handle va_mode.
1865         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1866         CPU_MOVDIR64B_FLAGS.
1867         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1868         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1869         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1870         * i386-opc.tbl: Add movidir{i,64b}.
1871         * i386-init.h: Regenerated.
1872         * i386-tbl.h: Likewise.
1873
1874 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1875
1876         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1877         AddrPrefixOpReg.
1878         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1879         (AddrPrefixOpReg): This.
1880         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1881         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1882
1883 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1884
1885         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1886         (vle_num_opcodes): Likewise.
1887         (spe2_num_opcodes): Likewise.
1888         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1889         initialization loop.
1890         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1891         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1892         only once.
1893
1894 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1895
1896         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1897
1898 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1899
1900         Makefile.am: Added nfp-dis.c.
1901         configure.ac: Added bfd_nfp_arch.
1902         disassemble.h: Added print_insn_nfp prototype.
1903         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1904         nfp-dis.c: New, for NFP support.
1905         po/POTFILES.in: Added nfp-dis.c to the list.
1906         Makefile.in: Regenerate.
1907         configure: Regenerate.
1908
1909 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1910
1911         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1912         templates into their base ones.
1913         * i386-tlb.h: Re-generate.
1914
1915 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1916
1917         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1918         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1919         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1920         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1921         * i386-init.h: Re-generate.
1922
1923 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1924
1925         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1926         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1927         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1928         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1929         comment.
1930         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1931         and CpuRegMask.
1932         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1933         CpuRegMask: Delete.
1934         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1935         cpuregzmm, and cpuregmask.
1936         * i386-init.h: Re-generate.
1937         * i386-tbl.h: Re-generate.
1938
1939 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1940
1941         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1942         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1943         * i386-init.h: Re-generate.
1944
1945 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1946
1947         * i386-gen.c (VexImmExt): Delete.
1948         * i386-opc.h (VexImmExt, veximmext): Delete.
1949         * i386-opc.tbl: Drop all VexImmExt uses.
1950         * i386-tlb.h: Re-generate.
1951
1952 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1953
1954         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1955         register-only forms.
1956         * i386-tlb.h: Re-generate.
1957
1958 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1959
1960         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1961
1962 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1963
1964         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1965         PREFIX_0F1C.
1966         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1967         (cpu_flags): Add CpuCLDEMOTE.
1968         * i386-init.h: Regenerate.
1969         * i386-opc.h (enum): Add CpuCLDEMOTE,
1970         (i386_cpu_flags): Add cpucldemote.
1971         * i386-opc.tbl: Add cldemote.
1972         * i386-tbl.h: Regenerate.
1973
1974 2018-04-16  Alan Modra  <amodra@gmail.com>
1975
1976         * Makefile.am: Remove sh5 and sh64 support.
1977         * configure.ac: Likewise.
1978         * disassemble.c: Likewise.
1979         * disassemble.h: Likewise.
1980         * sh-dis.c: Likewise.
1981         * sh64-dis.c: Delete.
1982         * sh64-opc.c: Delete.
1983         * sh64-opc.h: Delete.
1984         * Makefile.in: Regenerate.
1985         * configure: Regenerate.
1986         * po/POTFILES.in: Regenerate.
1987
1988 2018-04-16  Alan Modra  <amodra@gmail.com>
1989
1990         * Makefile.am: Remove w65 support.
1991         * configure.ac: Likewise.
1992         * disassemble.c: Likewise.
1993         * disassemble.h: Likewise.
1994         * w65-dis.c: Delete.
1995         * w65-opc.h: Delete.
1996         * Makefile.in: Regenerate.
1997         * configure: Regenerate.
1998         * po/POTFILES.in: Regenerate.
1999
2000 2018-04-16  Alan Modra  <amodra@gmail.com>
2001
2002         * configure.ac: Remove we32k support.
2003         * configure: Regenerate.
2004
2005 2018-04-16  Alan Modra  <amodra@gmail.com>
2006
2007         * Makefile.am: Remove m88k support.
2008         * configure.ac: Likewise.
2009         * disassemble.c: Likewise.
2010         * disassemble.h: Likewise.
2011         * m88k-dis.c: Delete.
2012         * Makefile.in: Regenerate.
2013         * configure: Regenerate.
2014         * po/POTFILES.in: Regenerate.
2015
2016 2018-04-16  Alan Modra  <amodra@gmail.com>
2017
2018         * Makefile.am: Remove i370 support.
2019         * configure.ac: Likewise.
2020         * disassemble.c: Likewise.
2021         * disassemble.h: Likewise.
2022         * i370-dis.c: Delete.
2023         * i370-opc.c: Delete.
2024         * Makefile.in: Regenerate.
2025         * configure: Regenerate.
2026         * po/POTFILES.in: Regenerate.
2027
2028 2018-04-16  Alan Modra  <amodra@gmail.com>
2029
2030         * Makefile.am: Remove h8500 support.
2031         * configure.ac: Likewise.
2032         * disassemble.c: Likewise.
2033         * disassemble.h: Likewise.
2034         * h8500-dis.c: Delete.
2035         * h8500-opc.h: Delete.
2036         * Makefile.in: Regenerate.
2037         * configure: Regenerate.
2038         * po/POTFILES.in: Regenerate.
2039
2040 2018-04-16  Alan Modra  <amodra@gmail.com>
2041
2042         * configure.ac: Remove tahoe support.
2043         * configure: Regenerate.
2044
2045 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
2046
2047         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2048         umwait.
2049         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2050         64-bit mode.
2051         * i386-tbl.h: Regenerated.
2052
2053 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2054
2055         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2056         PREFIX_MOD_1_0FAE_REG_6.
2057         (va_mode): New.
2058         (OP_E_register): Use va_mode.
2059         * i386-dis-evex.h (prefix_table):
2060         New instructions (see prefixes above).
2061         * i386-gen.c (cpu_flag_init): Add WAITPKG.
2062         (cpu_flags): Likewise.
2063         * i386-opc.h (enum): Likewise.
2064         (i386_cpu_flags): Likewise.
2065         * i386-opc.tbl: Add umonitor, umwait, tpause.
2066         * i386-init.h: Regenerate.
2067         * i386-tbl.h: Likewise.
2068
2069 2018-04-11  Alan Modra  <amodra@gmail.com>
2070
2071         * opcodes/i860-dis.c: Delete.
2072         * opcodes/i960-dis.c: Delete.
2073         * Makefile.am: Remove i860 and i960 support.
2074         * configure.ac: Likewise.
2075         * disassemble.c: Likewise.
2076         * disassemble.h: Likewise.
2077         * Makefile.in: Regenerate.
2078         * configure: Regenerate.
2079         * po/POTFILES.in: Regenerate.
2080
2081 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
2082
2083         PR binutils/23025
2084         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2085         to 0.
2086         (print_insn): Clear vex instead of vex.evex.
2087
2088 2018-04-04  Nick Clifton  <nickc@redhat.com>
2089
2090         * po/es.po: Updated Spanish translation.
2091
2092 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2093
2094         * i386-gen.c (opcode_modifiers): Delete VecESize.
2095         * i386-opc.h (VecESize): Delete.
2096         (struct i386_opcode_modifier): Delete vecesize.
2097         * i386-opc.tbl: Drop VecESize.
2098         * i386-tlb.h: Re-generate.
2099
2100 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2101
2102         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2103         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2104         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2105         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2106         * i386-tlb.h: Re-generate.
2107
2108 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2109
2110         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2111         Fold AVX512 forms
2112         * i386-tlb.h: Re-generate.
2113
2114 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2115
2116         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2117         (vex_len_table): Drop Y for vcvt*2si.
2118         (putop): Replace plain 'Y' handling by abort().
2119
2120 2018-03-28  Nick Clifton  <nickc@redhat.com>
2121
2122         PR 22988
2123         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2124         instructions with only a base address register.
2125         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2126         handle AARHC64_OPND_SVE_ADDR_R.
2127         (aarch64_print_operand): Likewise.
2128         * aarch64-asm-2.c: Regenerate.
2129         * aarch64_dis-2.c: Regenerate.
2130         * aarch64-opc-2.c: Regenerate.
2131
2132 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2133
2134         * i386-opc.tbl: Drop VecESize from register only insn forms and
2135         memory forms not allowing broadcast.
2136         * i386-tlb.h: Re-generate.
2137
2138 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2139
2140         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2141         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2142         sha256*): Drop Disp<N>.
2143
2144 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2145
2146         * i386-dis.c (EbndS, bnd_swap_mode): New.
2147         (prefix_table): Use EbndS.
2148         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2149         * i386-opc.tbl (bndmov): Move misplaced Load.
2150         * i386-tlb.h: Re-generate.
2151
2152 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2153
2154         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2155         templates allowing memory operands and folded ones for register
2156         only flavors.
2157         * i386-tlb.h: Re-generate.
2158
2159 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2160
2161         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2162         256-bit templates. Drop redundant leftover Disp<N>.
2163         * i386-tlb.h: Re-generate.
2164
2165 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
2166
2167         * riscv-opc.c (riscv_insn_types): New.
2168
2169 2018-03-13  Nick Clifton  <nickc@redhat.com>
2170
2171         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2172
2173 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2174
2175         * i386-opc.tbl: Add Optimize to clr.
2176         * i386-tbl.h: Regenerated.
2177
2178 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2179
2180         * i386-gen.c (opcode_modifiers): Remove OldGcc.
2181         * i386-opc.h (OldGcc): Removed.
2182         (i386_opcode_modifier): Remove oldgcc.
2183         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2184         instructions for old (<= 2.8.1) versions of gcc.
2185         * i386-tbl.h: Regenerated.
2186
2187 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2188
2189         * i386-opc.h (EVEXDYN): New.
2190         * i386-opc.tbl: Fold various AVX512VL templates.
2191         * i386-tlb.h: Re-generate.
2192
2193 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2194
2195         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2196         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2197         vpexpandd, vpexpandq): Fold AFX512VF templates.
2198         * i386-tlb.h: Re-generate.
2199
2200 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2201
2202         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2203         Fold 128- and 256-bit VEX-encoded templates.
2204         * i386-tlb.h: Re-generate.
2205
2206 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2207
2208         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2209         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2210         vpexpandd, vpexpandq): Fold AVX512F templates.
2211         * i386-tlb.h: Re-generate.
2212
2213 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2214
2215         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2216         64-bit templates. Drop Disp<N>.
2217         * i386-tlb.h: Re-generate.
2218
2219 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2220
2221         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2222         and 256-bit templates.
2223         * i386-tlb.h: Re-generate.
2224
2225 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2226
2227         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2228         * i386-tlb.h: Re-generate.
2229
2230 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2231
2232         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2233         Drop NoAVX.
2234         * i386-tlb.h: Re-generate.
2235
2236 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2237
2238         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2239         * i386-tlb.h: Re-generate.
2240
2241 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2242
2243         * i386-gen.c (opcode_modifiers): Delete FloatD.
2244         * i386-opc.h (FloatD): Delete.
2245         (struct i386_opcode_modifier): Delete floatd.
2246         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2247         FloatD by D.
2248         * i386-tlb.h: Re-generate.
2249
2250 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2251
2252         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2253
2254 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2255
2256         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2257         * i386-tlb.h: Re-generate.
2258
2259 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2260
2261         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2262         forms.
2263         * i386-tlb.h: Re-generate.
2264
2265 2018-03-07  Alan Modra  <amodra@gmail.com>
2266
2267         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2268         bfd_arch_rs6000.
2269         * disassemble.h (print_insn_rs6000): Delete.
2270         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2271         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2272         (print_insn_rs6000): Delete.
2273
2274 2018-03-03  Alan Modra  <amodra@gmail.com>
2275
2276         * sysdep.h (opcodes_error_handler): Define.
2277         (_bfd_error_handler): Declare.
2278         * Makefile.am: Remove stray #.
2279         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2280         EDIT" comment.
2281         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2282         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2283         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2284         opcodes_error_handler to print errors.  Standardize error messages.
2285         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2286         and include opintl.h.
2287         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2288         * i386-gen.c: Standardize error messages.
2289         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2290         * Makefile.in: Regenerate.
2291         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2292         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2293         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2294         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2295         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2296         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2297         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2298         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2299         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2300         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2301         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2302         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2303         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2304
2305 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2306
2307         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2308         vpsub[bwdq] instructions.
2309         * i386-tbl.h: Regenerated.
2310
2311 2018-03-01  Alan Modra  <amodra@gmail.com>
2312
2313         * configure.ac (ALL_LINGUAS): Sort.
2314         * configure: Regenerate.
2315
2316 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2317
2318         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2319         macro by assignements.
2320
2321 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2322
2323         PR gas/22871
2324         * i386-gen.c (opcode_modifiers): Add Optimize.
2325         * i386-opc.h (Optimize): New enum.
2326         (i386_opcode_modifier): Add optimize.
2327         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2328         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2329         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2330         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2331         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2332         vpxord and vpxorq.
2333         * i386-tbl.h: Regenerated.
2334
2335 2018-02-26  Alan Modra  <amodra@gmail.com>
2336
2337         * crx-dis.c (getregliststring): Allocate a large enough buffer
2338         to silence false positive gcc8 warning.
2339
2340 2018-02-22  Shea Levy <shea@shealevy.com>
2341
2342         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2343
2344 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2345
2346         * i386-opc.tbl: Add {rex},
2347         * i386-tbl.h: Regenerated.
2348
2349 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2350
2351         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2352         (mips16_opcodes): Replace `M' with `m' for "restore".
2353
2354 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2355
2356         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2357
2358 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2359
2360         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2361         variable to `function_index'.
2362
2363 2018-02-13  Nick Clifton  <nickc@redhat.com>
2364
2365         PR 22823
2366         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2367         about truncation of printing.
2368
2369 2018-02-12  Henry Wong <henry@stuffedcow.net>
2370
2371         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2372
2373 2018-02-05  Nick Clifton  <nickc@redhat.com>
2374
2375         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2376
2377 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2378
2379         * i386-dis.c (enum): Add pconfig.
2380         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2381         (cpu_flags): Add CpuPCONFIG.
2382         * i386-opc.h (enum): Add CpuPCONFIG.
2383         (i386_cpu_flags): Add cpupconfig.
2384         * i386-opc.tbl: Add PCONFIG instruction.
2385         * i386-init.h: Regenerate.
2386         * i386-tbl.h: Likewise.
2387
2388 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2389
2390         * i386-dis.c (enum): Add PREFIX_0F09.
2391         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2392         (cpu_flags): Add CpuWBNOINVD.
2393         * i386-opc.h (enum): Add CpuWBNOINVD.
2394         (i386_cpu_flags): Add cpuwbnoinvd.
2395         * i386-opc.tbl: Add WBNOINVD instruction.
2396         * i386-init.h: Regenerate.
2397         * i386-tbl.h: Likewise.
2398
2399 2018-01-17  Jim Wilson  <jimw@sifive.com>
2400
2401         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2402
2403 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2404
2405         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2406         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2407         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2408         (cpu_flags): Add CpuIBT, CpuSHSTK.
2409         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2410         (i386_cpu_flags): Add cpuibt, cpushstk.
2411         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2412         * i386-init.h: Regenerate.
2413         * i386-tbl.h: Likewise.
2414
2415 2018-01-16  Nick Clifton  <nickc@redhat.com>
2416
2417         * po/pt_BR.po: Updated Brazilian Portugese translation.
2418         * po/de.po: Updated German translation.
2419
2420 2018-01-15  Jim Wilson  <jimw@sifive.com>
2421
2422         * riscv-opc.c (match_c_nop): New.
2423         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2424
2425 2018-01-15  Nick Clifton  <nickc@redhat.com>
2426
2427         * po/uk.po: Updated Ukranian translation.
2428
2429 2018-01-13  Nick Clifton  <nickc@redhat.com>
2430
2431         * po/opcodes.pot: Regenerated.
2432
2433 2018-01-13  Nick Clifton  <nickc@redhat.com>
2434
2435         * configure: Regenerate.
2436
2437 2018-01-13  Nick Clifton  <nickc@redhat.com>
2438
2439         2.30 branch created.
2440
2441 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2442
2443         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2444         * i386-tbl.h: Regenerate.
2445
2446 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2447
2448         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2449         * i386-tbl.h: Re-generate.
2450
2451 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2452
2453         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2454         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2455         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2456         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2457         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2458         Disp8MemShift of AVX512VL forms.
2459         * i386-tbl.h: Re-generate.
2460
2461 2018-01-09  Jim Wilson  <jimw@sifive.com>
2462
2463         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2464         then the hi_addr value is zero.
2465
2466 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2467
2468         * arm-dis.c (arm_opcodes): Add csdb.
2469         (thumb32_opcodes): Add csdb.
2470
2471 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2472
2473         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2474         * aarch64-asm-2.c: Regenerate.
2475         * aarch64-dis-2.c: Regenerate.
2476         * aarch64-opc-2.c: Regenerate.
2477
2478 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2479
2480         PR gas/22681
2481         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2482         Remove AVX512 vmovd with 64-bit operands.
2483         * i386-tbl.h: Regenerated.
2484
2485 2018-01-05  Jim Wilson  <jimw@sifive.com>
2486
2487         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2488         jalr.
2489
2490 2018-01-03  Alan Modra  <amodra@gmail.com>
2491
2492         Update year range in copyright notice of all files.
2493
2494 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2495
2496         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2497         and OPERAND_TYPE_REGZMM entries.
2498
2499 For older changes see ChangeLog-2017
2500 \f
2501 Copyright (C) 2018 Free Software Foundation, Inc.
2502
2503 Copying and distribution of this file, with or without modification,
2504 are permitted in any medium without royalty provided the copyright
2505 notice and this notice are preserved.
2506
2507 Local Variables:
2508 mode: change-log
2509 left-margin: 8
2510 fill-column: 74
2511 version-control: never
2512 End: