opcodes/ChangeLog

   1 2018-11-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
   4         MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
   5         (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
   6         into MOD_VEX_0F93_P_3_LEN_0.
   7         (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
   8         operand cases up one level in the hierarchy.
   9
  10 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  11
  12         * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
  13         VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
  14         EVEX_W_0F3A22_P_2): Delete.
  15         (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
  16         entries up one level in the hierarchy.
  17         (OP_E_memory): Handle dq_mode when determining Disp8 shift
  18         value.
  19         * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
  20         entries up one level in the hierarchy.
  21         * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
  22         VexWIG for AVX flavors.
  23         * i386-tbl.h: Re-generate.
  24
  25 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
  28         vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
  29         vcvtusi2ss, kmovd): Drop VexW=1.
  30         * i386-tbl.h: Re-generate.
  31
  32 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
  35         EVex512, EVexLIG, EVexDYN): New.
  36         (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
  37         insns): Use Vex128 instead of Vex=3 (aka VexLIG).
  38         (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
  39         of EVex=4 (aka EVexLIG).
  40         * i386-tbl.h: Re-generate.
  41
  42 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
  45         (vpmaxub): Re-order attributes on AVX512BW flavor.
  46         * i386-tbl.h: Re-generate.
  47
  48 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
  51         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
  52         Vex=1 on AVX / AVX2 flavors.
  53         (vpmaxub): Re-order attributes on AVX512BW flavor.
  54         * i386-tbl.h: Re-generate.
  55
  56 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  57
  58         * i386-opc.tbl (VexW0, VexW1): New.
  59         (vphadd*, vphsub*): Use VexW0 on XOP variants.
  60         * i386-tbl.h: Re-generate.
  61
  62 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
  63
  64         * s12z-dis.c (decode_possible_symbol): Add fallback case.
  65         (rel_15_7): Likewise.
  66
  67 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
  68
  69         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
  70         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
  71         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
  72
  73 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
  74
  75         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
  76         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
  77
  78 2018-10-10  Jan Beulich  <jbeulich@suse.com>
  79
  80         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
  81         Size64. Add Size.
  82         * i386-opc.h (Size16, Size32, Size64): Delete.
  83         (Size): New.
  84         (SIZE16, SIZE32, SIZE64): Define.
  85         (struct i386_opcode_modifier): Drop size16, size32, and size64.
  86         Add size.
  87         * i386-opc.tbl (Size16, Size32, Size64): Define.
  88         * i386-tbl.h: Re-generate.
  89
  90 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  91
  92         * aarch64-opc.c (operand_general_constraint_met_p): Add
  93         SSBS in the check for one-bit immediate.
  94         (aarch64_sys_regs): New entry for SSBS.
  95         (aarch64_sys_reg_supported_p): New check for above.
  96         (aarch64_pstatefields): New entry for SSBS.
  97         (aarch64_pstatefield_supported_p): New check for above.
  98
  99 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 100
 101         * aarch64-opc.c (aarch64_sys_regs): New entries for
 102         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
 103         (aarch64_sys_reg_supported_p): New checks for above.
 104
 105 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 106
 107         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
 108         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
 109         with the hint immediate.
 110         * aarch64-opc.c (aarch64_hint_options): New entries for
 111         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
 112         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
 113         while checking for HINT_OPD_F_NOPRINT flag.
 114         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
 115         extract value.
 116         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
 117         (aarch64_opcode_table): Add entry for BTI.
 118         (AARCH64_OPERANDS): Add new description for BTI targets.
 119         * aarch64-asm-2.c: Regenerate.
 120         * aarch64-dis-2.c: Regenerate.
 121         * aarch64-opc-2.c: Regenerate.
 122
 123 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 124
 125         * aarch64-opc.c (aarch64_sys_regs): New entries for
 126         rndr and rndrrs.
 127         (aarch64_sys_reg_supported_p): New check for above.
 128
 129 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 130
 131         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
 132         (aarch64_sys_ins_reg_supported_p): New check for above.
 133
 134 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 135
 136         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
 137         AARCH64_OPND_SYSREG_SR.
 138         * aarch64-opc.c (aarch64_print_operand): Likewise.
 139         (aarch64_sys_regs_sr): Define table.
 140         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
 141         AARCH64_FEATURE_PREDRES.
 142         * aarch64-tbl.h (aarch64_feature_predres): New.
 143         (PREDRES, PREDRES_INSN): New.
 144         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
 145         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
 146         * aarch64-asm-2.c: Regenerate.
 147         * aarch64-dis-2.c: Regenerate.
 148         * aarch64-opc-2.c: Regenerate.
 149
 150 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 151
 152         * aarch64-tbl.h (aarch64_feature_sb): New.
 153         (SB, SB_INSN): New.
 154         (aarch64_opcode_table): Add entry for sb.
 155         * aarch64-asm-2.c: Regenerate.
 156         * aarch64-dis-2.c: Regenerate.
 157         * aarch64-opc-2.c: Regenerate.
 158
 159 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 160
 161         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 162         (aarch64_feature_frintts): New.
 163         (FLAGMANIP, FRINTTS): New.
 164         (aarch64_opcode_table): Add entries for xaflag, axflag
 165         and frint[32,64][x,z] instructions.
 166         * aarch64-asm-2.c: Regenerate.
 167         * aarch64-dis-2.c: Regenerate.
 168         * aarch64-opc-2.c: Regenerate.
 169
 170 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 171
 172         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 173         (ARMV8_5, V8_5_INSN): New.
 174
 175 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 176
 177         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 178
 179 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 180
 181         * i386-dis.c (rm_table): Add enclv.
 182         * i386-opc.tbl: Add enclv.
 183         * i386-tbl.h: Regenerated.
 184
 185 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 186
 187         * arm-dis.c (arm_opcodes): Add sb.
 188         (thumb32_opcodes): Likewise.
 189
 190 2018-10-05  Richard Henderson  <rth@twiddle.net>
 191             Stafford Horne  <shorne@gmail.com>
 192
 193         * or1k-desc.c: Regenerate.
 194         * or1k-desc.h: Regenerate.
 195         * or1k-opc.c: Regenerate.
 196         * or1k-opc.h: Regenerate.
 197         * or1k-opinst.c: Regenerate.
 198
 199 2018-10-05  Richard Henderson  <rth@twiddle.net>
 200
 201         * or1k-asm.c: Regenerated.
 202         * or1k-desc.c: Regenerated.
 203         * or1k-desc.h: Regenerated.
 204         * or1k-dis.c: Regenerated.
 205         * or1k-ibld.c: Regenerated.
 206         * or1k-opc.c: Regenerated.
 207         * or1k-opc.h: Regenerated.
 208         * or1k-opinst.c: Regenerated.
 209
 210 2018-10-05  Richard Henderson  <rth@twiddle.net>
 211
 212         * or1k-asm.c: Regenerate.
 213
 214 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 215
 216         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 217         * aarch64-dis.c (print_operands): Refactor to take notes.
 218         (print_verifier_notes): New.
 219         (print_aarch64_insn): Apply constraint verifier.
 220         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 221         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 222
 223 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 224
 225         * aarch64-opc.c (init_insn_block): New.
 226         (verify_constraints, aarch64_is_destructive_by_operands): New.
 227         * aarch64-opc.h (verify_constraints): New.
 228
 229 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 230
 231         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 232         * aarch64-opc.c (verify_ldpsw): Update arguments.
 233
 234 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 235
 236         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 237         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 238
 239 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 240
 241         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 242         * aarch64-dis.c (insn_sequence): New.
 243
 244 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 245
 246         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 247         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 248         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 249         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 250         constraints.
 251         (_SVE_INSNC): New.
 252         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 253         constraints.
 254         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 255         F_SCAN flags.
 256         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 257         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 258         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 259         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 260         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 261         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 262         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 263
 264 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 265
 266         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 267
 268 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 269
 270         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 271         are used when extracting signed fields and converting them to
 272         potentially 64-bit types.
 273
 274 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 275
 276         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 277         * Makefile.in: Re-generate.
 278         * aclocal.m4: Re-generate.
 279         * configure: Re-generate.
 280         * configure.ac: Remove check for -Wno-missing-field-initializers.
 281         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 282         (csky_v2_opcodes): Likewise.
 283
 284 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 285
 286         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 287
 288 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 289
 290         * nds32-asm.c (operand_fields): Remove the unused fields.
 291         (nds32_opcodes): Remove the unused instructions.
 292         * nds32-dis.c (nds32_ex9_info): Removed.
 293         (nds32_parse_opcode): Updated.
 294         (print_insn_nds32): Likewise.
 295         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 296         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 297         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 298         build_opcode_hash_table): New functions.
 299         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 300         nds32_opcode_table): New.
 301         (hw_ktabs): Declare it to a pointer rather than an array.
 302         (build_hash_table): Removed.
 303         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 304         SYN_ROPT and upadte HW_GPR and HW_INT.
 305         * nds32-dis.c (keywords): Remove const.
 306         (match_field): New function.
 307         (nds32_parse_opcode): Updated.
 308         * disassemble.c (disassemble_init_for_target):
 309         Add disassemble_init_nds32.
 310         * nds32-dis.c (eum map_type): New.
 311         (nds32_private_data): Likewise.
 312         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 313         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 314         (print_insn_nds32): Updated.
 315         * nds32-asm.c (parse_aext_reg): Add new parameter.
 316         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 317         are allowed to use.
 318         All callers changed.
 319         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 320         (operand_fields): Add new fields.
 321         (nds32_opcodes): Add new instructions.
 322         (keyword_aridxi_mx): New keyword.
 323         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 324         and NASM_ATTR_ZOL.
 325         (ALU2_1, ALU2_2, ALU2_3): New macros.
 326         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 327
 328 2018-09-17  Kito Cheng  <kito@andestech.com>
 329
 330         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 331
 332 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 333
 334         PR gas/23670
 335         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 336         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 337         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 338         (EVEX_LEN_0F7E_P_1): Likewise.
 339         (EVEX_LEN_0F7E_P_2): Likewise.
 340         (EVEX_LEN_0FD6_P_2): Likewise.
 341         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 342         (EVEX_LEN_TABLE): Likewise.
 343         (EVEX_LEN_0F6E_P_2): New enum.
 344         (EVEX_LEN_0F7E_P_1): Likewise.
 345         (EVEX_LEN_0F7E_P_2): Likewise.
 346         (EVEX_LEN_0FD6_P_2): Likewise.
 347         (evex_len_table): New.
 348         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 349         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 350         * i386-tbl.h: Regenerated.
 351
 352 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 353
 354         PR gas/23665
 355         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 356         VEX_LEN_0F7E_P_2 entries.
 357         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 358         * i386-tbl.h: Regenerated.
 359
 360 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 361
 362         * i386-dis.c (VZERO_Fixup): Removed.
 363         (VZERO): Likewise.
 364         (VEX_LEN_0F10_P_1): Likewise.
 365         (VEX_LEN_0F10_P_3): Likewise.
 366         (VEX_LEN_0F11_P_1): Likewise.
 367         (VEX_LEN_0F11_P_3): Likewise.
 368         (VEX_LEN_0F2E_P_0): Likewise.
 369         (VEX_LEN_0F2E_P_2): Likewise.
 370         (VEX_LEN_0F2F_P_0): Likewise.
 371         (VEX_LEN_0F2F_P_2): Likewise.
 372         (VEX_LEN_0F51_P_1): Likewise.
 373         (VEX_LEN_0F51_P_3): Likewise.
 374         (VEX_LEN_0F52_P_1): Likewise.
 375         (VEX_LEN_0F53_P_1): Likewise.
 376         (VEX_LEN_0F58_P_1): Likewise.
 377         (VEX_LEN_0F58_P_3): Likewise.
 378         (VEX_LEN_0F59_P_1): Likewise.
 379         (VEX_LEN_0F59_P_3): Likewise.
 380         (VEX_LEN_0F5A_P_1): Likewise.
 381         (VEX_LEN_0F5A_P_3): Likewise.
 382         (VEX_LEN_0F5C_P_1): Likewise.
 383         (VEX_LEN_0F5C_P_3): Likewise.
 384         (VEX_LEN_0F5D_P_1): Likewise.
 385         (VEX_LEN_0F5D_P_3): Likewise.
 386         (VEX_LEN_0F5E_P_1): Likewise.
 387         (VEX_LEN_0F5E_P_3): Likewise.
 388         (VEX_LEN_0F5F_P_1): Likewise.
 389         (VEX_LEN_0F5F_P_3): Likewise.
 390         (VEX_LEN_0FC2_P_1): Likewise.
 391         (VEX_LEN_0FC2_P_3): Likewise.
 392         (VEX_LEN_0F3A0A_P_2): Likewise.
 393         (VEX_LEN_0F3A0B_P_2): Likewise.
 394         (VEX_W_0F10_P_0): Likewise.
 395         (VEX_W_0F10_P_1): Likewise.
 396         (VEX_W_0F10_P_2): Likewise.
 397         (VEX_W_0F10_P_3): Likewise.
 398         (VEX_W_0F11_P_0): Likewise.
 399         (VEX_W_0F11_P_1): Likewise.
 400         (VEX_W_0F11_P_2): Likewise.
 401         (VEX_W_0F11_P_3): Likewise.
 402         (VEX_W_0F12_P_0_M_0): Likewise.
 403         (VEX_W_0F12_P_0_M_1): Likewise.
 404         (VEX_W_0F12_P_1): Likewise.
 405         (VEX_W_0F12_P_2): Likewise.
 406         (VEX_W_0F12_P_3): Likewise.
 407         (VEX_W_0F13_M_0): Likewise.
 408         (VEX_W_0F14): Likewise.
 409         (VEX_W_0F15): Likewise.
 410         (VEX_W_0F16_P_0_M_0): Likewise.
 411         (VEX_W_0F16_P_0_M_1): Likewise.
 412         (VEX_W_0F16_P_1): Likewise.
 413         (VEX_W_0F16_P_2): Likewise.
 414         (VEX_W_0F17_M_0): Likewise.
 415         (VEX_W_0F28): Likewise.
 416         (VEX_W_0F29): Likewise.
 417         (VEX_W_0F2B_M_0): Likewise.
 418         (VEX_W_0F2E_P_0): Likewise.
 419         (VEX_W_0F2E_P_2): Likewise.
 420         (VEX_W_0F2F_P_0): Likewise.
 421         (VEX_W_0F2F_P_2): Likewise.
 422         (VEX_W_0F50_M_0): Likewise.
 423         (VEX_W_0F51_P_0): Likewise.
 424         (VEX_W_0F51_P_1): Likewise.
 425         (VEX_W_0F51_P_2): Likewise.
 426         (VEX_W_0F51_P_3): Likewise.
 427         (VEX_W_0F52_P_0): Likewise.
 428         (VEX_W_0F52_P_1): Likewise.
 429         (VEX_W_0F53_P_0): Likewise.
 430         (VEX_W_0F53_P_1): Likewise.
 431         (VEX_W_0F58_P_0): Likewise.
 432         (VEX_W_0F58_P_1): Likewise.
 433         (VEX_W_0F58_P_2): Likewise.
 434         (VEX_W_0F58_P_3): Likewise.
 435         (VEX_W_0F59_P_0): Likewise.
 436         (VEX_W_0F59_P_1): Likewise.
 437         (VEX_W_0F59_P_2): Likewise.
 438         (VEX_W_0F59_P_3): Likewise.
 439         (VEX_W_0F5A_P_0): Likewise.
 440         (VEX_W_0F5A_P_1): Likewise.
 441         (VEX_W_0F5A_P_3): Likewise.
 442         (VEX_W_0F5B_P_0): Likewise.
 443         (VEX_W_0F5B_P_1): Likewise.
 444         (VEX_W_0F5B_P_2): Likewise.
 445         (VEX_W_0F5C_P_0): Likewise.
 446         (VEX_W_0F5C_P_1): Likewise.
 447         (VEX_W_0F5C_P_2): Likewise.
 448         (VEX_W_0F5C_P_3): Likewise.
 449         (VEX_W_0F5D_P_0): Likewise.
 450         (VEX_W_0F5D_P_1): Likewise.
 451         (VEX_W_0F5D_P_2): Likewise.
 452         (VEX_W_0F5D_P_3): Likewise.
 453         (VEX_W_0F5E_P_0): Likewise.
 454         (VEX_W_0F5E_P_1): Likewise.
 455         (VEX_W_0F5E_P_2): Likewise.
 456         (VEX_W_0F5E_P_3): Likewise.
 457         (VEX_W_0F5F_P_0): Likewise.
 458         (VEX_W_0F5F_P_1): Likewise.
 459         (VEX_W_0F5F_P_2): Likewise.
 460         (VEX_W_0F5F_P_3): Likewise.
 461         (VEX_W_0F60_P_2): Likewise.
 462         (VEX_W_0F61_P_2): Likewise.
 463         (VEX_W_0F62_P_2): Likewise.
 464         (VEX_W_0F63_P_2): Likewise.
 465         (VEX_W_0F64_P_2): Likewise.
 466         (VEX_W_0F65_P_2): Likewise.
 467         (VEX_W_0F66_P_2): Likewise.
 468         (VEX_W_0F67_P_2): Likewise.
 469         (VEX_W_0F68_P_2): Likewise.
 470         (VEX_W_0F69_P_2): Likewise.
 471         (VEX_W_0F6A_P_2): Likewise.
 472         (VEX_W_0F6B_P_2): Likewise.
 473         (VEX_W_0F6C_P_2): Likewise.
 474         (VEX_W_0F6D_P_2): Likewise.
 475         (VEX_W_0F6F_P_1): Likewise.
 476         (VEX_W_0F6F_P_2): Likewise.
 477         (VEX_W_0F70_P_1): Likewise.
 478         (VEX_W_0F70_P_2): Likewise.
 479         (VEX_W_0F70_P_3): Likewise.
 480         (VEX_W_0F71_R_2_P_2): Likewise.
 481         (VEX_W_0F71_R_4_P_2): Likewise.
 482         (VEX_W_0F71_R_6_P_2): Likewise.
 483         (VEX_W_0F72_R_2_P_2): Likewise.
 484         (VEX_W_0F72_R_4_P_2): Likewise.
 485         (VEX_W_0F72_R_6_P_2): Likewise.
 486         (VEX_W_0F73_R_2_P_2): Likewise.
 487         (VEX_W_0F73_R_3_P_2): Likewise.
 488         (VEX_W_0F73_R_6_P_2): Likewise.
 489         (VEX_W_0F73_R_7_P_2): Likewise.
 490         (VEX_W_0F74_P_2): Likewise.
 491         (VEX_W_0F75_P_2): Likewise.
 492         (VEX_W_0F76_P_2): Likewise.
 493         (VEX_W_0F77_P_0): Likewise.
 494         (VEX_W_0F7C_P_2): Likewise.
 495         (VEX_W_0F7C_P_3): Likewise.
 496         (VEX_W_0F7D_P_2): Likewise.
 497         (VEX_W_0F7D_P_3): Likewise.
 498         (VEX_W_0F7E_P_1): Likewise.
 499         (VEX_W_0F7F_P_1): Likewise.
 500         (VEX_W_0F7F_P_2): Likewise.
 501         (VEX_W_0FAE_R_2_M_0): Likewise.
 502         (VEX_W_0FAE_R_3_M_0): Likewise.
 503         (VEX_W_0FC2_P_0): Likewise.
 504         (VEX_W_0FC2_P_1): Likewise.
 505         (VEX_W_0FC2_P_2): Likewise.
 506         (VEX_W_0FC2_P_3): Likewise.
 507         (VEX_W_0FD0_P_2): Likewise.
 508         (VEX_W_0FD0_P_3): Likewise.
 509         (VEX_W_0FD1_P_2): Likewise.
 510         (VEX_W_0FD2_P_2): Likewise.
 511         (VEX_W_0FD3_P_2): Likewise.
 512         (VEX_W_0FD4_P_2): Likewise.
 513         (VEX_W_0FD5_P_2): Likewise.
 514         (VEX_W_0FD6_P_2): Likewise.
 515         (VEX_W_0FD7_P_2_M_1): Likewise.
 516         (VEX_W_0FD8_P_2): Likewise.
 517         (VEX_W_0FD9_P_2): Likewise.
 518         (VEX_W_0FDA_P_2): Likewise.
 519         (VEX_W_0FDB_P_2): Likewise.
 520         (VEX_W_0FDC_P_2): Likewise.
 521         (VEX_W_0FDD_P_2): Likewise.
 522         (VEX_W_0FDE_P_2): Likewise.
 523         (VEX_W_0FDF_P_2): Likewise.
 524         (VEX_W_0FE0_P_2): Likewise.
 525         (VEX_W_0FE1_P_2): Likewise.
 526         (VEX_W_0FE2_P_2): Likewise.
 527         (VEX_W_0FE3_P_2): Likewise.
 528         (VEX_W_0FE4_P_2): Likewise.
 529         (VEX_W_0FE5_P_2): Likewise.
 530         (VEX_W_0FE6_P_1): Likewise.
 531         (VEX_W_0FE6_P_2): Likewise.
 532         (VEX_W_0FE6_P_3): Likewise.
 533         (VEX_W_0FE7_P_2_M_0): Likewise.
 534         (VEX_W_0FE8_P_2): Likewise.
 535         (VEX_W_0FE9_P_2): Likewise.
 536         (VEX_W_0FEA_P_2): Likewise.
 537         (VEX_W_0FEB_P_2): Likewise.
 538         (VEX_W_0FEC_P_2): Likewise.
 539         (VEX_W_0FED_P_2): Likewise.
 540         (VEX_W_0FEE_P_2): Likewise.
 541         (VEX_W_0FEF_P_2): Likewise.
 542         (VEX_W_0FF0_P_3_M_0): Likewise.
 543         (VEX_W_0FF1_P_2): Likewise.
 544         (VEX_W_0FF2_P_2): Likewise.
 545         (VEX_W_0FF3_P_2): Likewise.
 546         (VEX_W_0FF4_P_2): Likewise.
 547         (VEX_W_0FF5_P_2): Likewise.
 548         (VEX_W_0FF6_P_2): Likewise.
 549         (VEX_W_0FF7_P_2): Likewise.
 550         (VEX_W_0FF8_P_2): Likewise.
 551         (VEX_W_0FF9_P_2): Likewise.
 552         (VEX_W_0FFA_P_2): Likewise.
 553         (VEX_W_0FFB_P_2): Likewise.
 554         (VEX_W_0FFC_P_2): Likewise.
 555         (VEX_W_0FFD_P_2): Likewise.
 556         (VEX_W_0FFE_P_2): Likewise.
 557         (VEX_W_0F3800_P_2): Likewise.
 558         (VEX_W_0F3801_P_2): Likewise.
 559         (VEX_W_0F3802_P_2): Likewise.
 560         (VEX_W_0F3803_P_2): Likewise.
 561         (VEX_W_0F3804_P_2): Likewise.
 562         (VEX_W_0F3805_P_2): Likewise.
 563         (VEX_W_0F3806_P_2): Likewise.
 564         (VEX_W_0F3807_P_2): Likewise.
 565         (VEX_W_0F3808_P_2): Likewise.
 566         (VEX_W_0F3809_P_2): Likewise.
 567         (VEX_W_0F380A_P_2): Likewise.
 568         (VEX_W_0F380B_P_2): Likewise.
 569         (VEX_W_0F3817_P_2): Likewise.
 570         (VEX_W_0F381C_P_2): Likewise.
 571         (VEX_W_0F381D_P_2): Likewise.
 572         (VEX_W_0F381E_P_2): Likewise.
 573         (VEX_W_0F3820_P_2): Likewise.
 574         (VEX_W_0F3821_P_2): Likewise.
 575         (VEX_W_0F3822_P_2): Likewise.
 576         (VEX_W_0F3823_P_2): Likewise.
 577         (VEX_W_0F3824_P_2): Likewise.
 578         (VEX_W_0F3825_P_2): Likewise.
 579         (VEX_W_0F3828_P_2): Likewise.
 580         (VEX_W_0F3829_P_2): Likewise.
 581         (VEX_W_0F382A_P_2_M_0): Likewise.
 582         (VEX_W_0F382B_P_2): Likewise.
 583         (VEX_W_0F3830_P_2): Likewise.
 584         (VEX_W_0F3831_P_2): Likewise.
 585         (VEX_W_0F3832_P_2): Likewise.
 586         (VEX_W_0F3833_P_2): Likewise.
 587         (VEX_W_0F3834_P_2): Likewise.
 588         (VEX_W_0F3835_P_2): Likewise.
 589         (VEX_W_0F3837_P_2): Likewise.
 590         (VEX_W_0F3838_P_2): Likewise.
 591         (VEX_W_0F3839_P_2): Likewise.
 592         (VEX_W_0F383A_P_2): Likewise.
 593         (VEX_W_0F383B_P_2): Likewise.
 594         (VEX_W_0F383C_P_2): Likewise.
 595         (VEX_W_0F383D_P_2): Likewise.
 596         (VEX_W_0F383E_P_2): Likewise.
 597         (VEX_W_0F383F_P_2): Likewise.
 598         (VEX_W_0F3840_P_2): Likewise.
 599         (VEX_W_0F3841_P_2): Likewise.
 600         (VEX_W_0F38DB_P_2): Likewise.
 601         (VEX_W_0F3A08_P_2): Likewise.
 602         (VEX_W_0F3A09_P_2): Likewise.
 603         (VEX_W_0F3A0A_P_2): Likewise.
 604         (VEX_W_0F3A0B_P_2): Likewise.
 605         (VEX_W_0F3A0C_P_2): Likewise.
 606         (VEX_W_0F3A0D_P_2): Likewise.
 607         (VEX_W_0F3A0E_P_2): Likewise.
 608         (VEX_W_0F3A0F_P_2): Likewise.
 609         (VEX_W_0F3A21_P_2): Likewise.
 610         (VEX_W_0F3A40_P_2): Likewise.
 611         (VEX_W_0F3A41_P_2): Likewise.
 612         (VEX_W_0F3A42_P_2): Likewise.
 613         (VEX_W_0F3A62_P_2): Likewise.
 614         (VEX_W_0F3A63_P_2): Likewise.
 615         (VEX_W_0F3ADF_P_2): Likewise.
 616         (VEX_LEN_0F77_P_0): New.
 617         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 618         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 619         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 620         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 621         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 622         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 623         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 624         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 625         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 626         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 627         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 628         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 629         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 630         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 631         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 632         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 633         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 634         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 635         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 636         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 637         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 638         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 639         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 640         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 641         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 642         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 643         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 644         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 645         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 646         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 647         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 648         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 649         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 650         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 651         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 652         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 653         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 654         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 655         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 656         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 657         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 658         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 659         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 660         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 661         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 662         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 663         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 664         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 665         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 666         (vex_table): Update VEX 0F28 and 0F29 entries.
 667         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 668         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 669         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 670         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 671         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 672         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 673         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 674         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 675         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 676         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 677         VEX_LEN_0F3A0B_P_2 entries.
 678         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 679         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 680         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 681         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 682         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 683         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 684         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 685         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 686         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 687         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 688         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 689         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 690         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 691         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 692         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 693         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 694         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 695         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 696         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 697         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 698         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 699         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 700         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 701         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 702         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 703         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 704         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 705         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 706         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 707         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 708         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 709         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 710         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 711         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 712         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 713         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 714         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 715         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 716         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 717         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 718         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 719         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 720         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 721         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 722         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 723         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 724         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 725         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 726         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 727         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 728         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 729         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 730         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 731         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 732         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 733         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 734         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 735         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 736         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 737         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 738         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 739         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 740         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 741         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 742         VEX_W_0F3ADF_P_2 entries.
 743         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 744         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 745         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 746
 747 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 748
 749         * i386-opc.tbl (VexWIG): New.
 750         Replace VexW=3 with VexWIG.
 751
 752 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 753
 754         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 755         * i386-tbl.h: Regenerated.
 756
 757 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 758
 759         PR gas/23665
 760         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 761         VEX_LEN_0FD6_P_2 entries.
 762         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 763         * i386-tbl.h: Regenerated.
 764
 765 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 766
 767         PR gas/23642
 768         * i386-opc.h (VEXWIG): New.
 769         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 770         * i386-tbl.h: Regenerated.
 771
 772 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 773
 774         PR binutils/23655
 775         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 776         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 777         * i386-dis.c (EXxEVexR64): New.
 778         (evex_rounding_64_mode): Likewise.
 779         (OP_Rounding): Handle evex_rounding_64_mode.
 780
 781 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 782
 783         PR binutils/23655
 784         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 785         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 786         * i386-dis.c (Edqa): New.
 787         (dqa_mode): Likewise.
 788         (intel_operand_size): Handle dqa_mode as m_mode.
 789         (OP_E_register): Handle dqa_mode as dq_mode.
 790         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 791
 792 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 793
 794         * i386-dis.c (OP_E_memory): Reformat.
 795
 796 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 797
 798         * i386-opc.tbl (crc32): Fold byte and word forms.
 799         * i386-tbl.h: Re-generate.
 800
 801 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 802
 803         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 804         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 805         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 806         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 807         * i386-tbl.h: Regenerated.
 808
 809 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 810
 811         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 812         meaningless.
 813         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 814         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 815         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 816         * i386-tbl.h: Re-generate.
 817
 818 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 819
 820         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 821         AVX512_4VNNIW insns.
 822         * i386-tbl.h: Re-generate.
 823
 824 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 825
 826         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 827         meaningless.
 828         * i386-tbl.h: Re-generate.
 829
 830 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 831
 832         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 833         meaningless.
 834         * i386-tbl.h: Re-generate.
 835
 836 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 837
 838         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 839         meaningless.
 840         * i386-tbl.h: Re-generate.
 841
 842 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 843
 844         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 845         meaningless.
 846         * i386-tbl.h: Re-generate.
 847
 848 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 849
 850         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 851         meaningless.
 852         * i386-tbl.h: Re-generate.
 853
 854 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 855
 856         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 857         * i386-tbl.h: Re-generate.
 858
 859 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 860
 861         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 862         * i386-tbl.h: Re-generate.
 863
 864 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 865
 866         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 867         meaningless.
 868         * i386-tbl.h: Re-generate.
 869
 870 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 871
 872         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 873         meaningless.
 874         * i386-tbl.h: Re-generate.
 875
 876 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 877
 878         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 879         * i386-tbl.h: Re-generate.
 880
 881 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 882
 883         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 884         * i386-tbl.h: Re-generate.
 885
 886 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 887
 888         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 889         * i386-tbl.h: Re-generate.
 890
 891 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 892
 893         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 894         meaningless.
 895         * i386-tbl.h: Re-generate.
 896
 897 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 898
 899         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 900         meaningless.
 901         * i386-tbl.h: Re-generate.
 902
 903 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 904
 905         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 906         meaningless.
 907         * i386-tbl.h: Re-generate.
 908
 909 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 910
 911         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 912         * i386-tbl.h: Re-generate.
 913
 914 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 915
 916         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 917         * i386-tbl.h: Re-generate.
 918
 919 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 920
 921         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 922         * i386-tbl.h: Re-generate.
 923
 924 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 925
 926         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 927         (vpbroadcastw, rdpid): Drop NoRex64.
 928         * i386-tbl.h: Re-generate.
 929
 930 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 931
 932         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 933         store templates, adding D.
 934         * i386-tbl.h: Re-generate.
 935
 936 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 937
 938         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 939         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 940         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 941         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 942         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 943         Fold load and store templates where possible, adding D. Drop
 944         IgnoreSize where it was pointlessly present. Drop redundant
 945         *word.
 946         * i386-tbl.h: Re-generate.
 947
 948 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 949
 950         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 951         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 952         (intel_operand_size): Handle v_bndmk_mode.
 953         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 954
 955 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 956
 957         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 958
 959 2018-08-31  Kito Cheng  <kito@andestech.com>
 960
 961         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 962         compressed floating point instructions.
 963
 964 2018-08-30  Kito Cheng  <kito@andestech.com>
 965
 966         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 967         riscv_opcode.xlen_requirement.
 968         * riscv-opc.c (riscv_opcodes): Update for struct change.
 969
 970 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 971
 972         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 973         psr (PWRPSR) instruction.
 974
 975 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 976
 977         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 978
 979 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 980
 981         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 982
 983 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 984
 985         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 986         loongson3a as an alias of gs464 for compatibility.
 987         * mips-opc.c (mips_opcodes): Change Comments.
 988
 989 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 990
 991         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 992         option.
 993         (print_mips_disassembler_options): Document -M loongson-ext.
 994         * mips-opc.c (LEXT2): New macro.
 995         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 996
 997 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 998
 999          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1000          descriptors.
1001          (parse_mips_ase_option): Handle -M loongson-ext option.
1002          (print_mips_disassembler_options): Document -M loongson-ext.
1003          * mips-opc.c (IL3A): Delete.
1004          * mips-opc.c (LEXT): New macro.
1005          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1006          instructions.
1007
1008 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1009
1010         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1011         descriptors.
1012         (parse_mips_ase_option): Handle -M loongson-cam option.
1013         (print_mips_disassembler_options): Document -M loongson-cam.
1014         * mips-opc.c (LCAM): New macro.
1015         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1016         instructions.
1017
1018 2018-08-21  Alan Modra  <amodra@gmail.com>
1019
1020         * ppc-dis.c (operand_value_powerpc): Init "invalid".
1021         (skip_optional_operands): Count optional operands, and update
1022         ppc_optional_operand_value call.
1023         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1024         (extract_vlensi): Likewise.
1025         (extract_fxm): Return default value for missing optional operand.
1026         (extract_ls, extract_raq, extract_tbr): Likewise.
1027         (insert_sxl, extract_sxl): New functions.
1028         (insert_esync, extract_esync): Remove Power9 handling and simplify.
1029         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1030         flag and extra entry.
1031         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1032         extract_sxl.
1033
1034 2018-08-20  Alan Modra  <amodra@gmail.com>
1035
1036         * sh-opc.h (MASK): Simplify.
1037
1038 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1039
1040         * s12z-dis.c (bm_decode): Deal with cases where the mode is
1041         BM_RESERVED0 or BM_RESERVED1
1042         (bm_rel_decode, bm_n_bytes): Ditto.
1043
1044 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1045
1046         * s12z.h: Delete.
1047
1048 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1049
1050         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1051         address with the addr32 prefix and without base nor index
1052         registers.
1053
1054 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1055
1056         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1057         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1058         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1059         (cpu_flags): Add CpuCMOV and CpuFXSR.
1060         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1061         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1062         * i386-init.h: Regenerated.
1063         * i386-tbl.h: Likewise.
1064
1065 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1066
1067         * arc-regs.h: Update auxiliary registers.
1068
1069 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1070
1071         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1072         (RegIP, RegIZ): Define.
1073         * i386-reg.tbl: Adjust comments.
1074         (rip): Use Qword instead of BaseIndex. Use RegIP.
1075         (eip): Use Dword instead of BaseIndex. Use RegIP.
1076         (riz): Add Qword. Use RegIZ.
1077         (eiz): Add Dword. Use RegIZ.
1078         * i386-tbl.h: Re-generate.
1079
1080 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1081
1082         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1083         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1084         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1085         * i386-tbl.h: Re-generate.
1086
1087 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1088
1089         * i386-gen.c (operand_types): Remove Mem field.
1090         * i386-opc.h (union i386_operand_type): Remove mem field.
1091         * i386-init.h, i386-tbl.h: Re-generate.
1092
1093 2018-08-01  Alan Modra  <amodra@gmail.com>
1094
1095         * po/POTFILES.in: Regenerate.
1096
1097 2018-07-31  Nick Clifton  <nickc@redhat.com>
1098
1099         * po/sv.po: Updated Swedish translation.
1100
1101 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1102
1103         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1104         * i386-init.h, i386-tbl.h: Re-generate.
1105
1106 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1107
1108         * i386-opc.h (ZEROING_MASKING) Rename to ...
1109         (DYNAMIC_MASKING): ... this. Adjust comment.
1110         * i386-opc.tbl (MaskingMorZ): Define.
1111         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1112         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1113         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1114         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1115         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1116         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1117         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1118         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1119         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1120
1121 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1122
1123         * i386-opc.tbl: Use element rather than vector size for AVX512*
1124         scatter/gather insns.
1125         * i386-tbl.h: Re-generate.
1126
1127 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1128
1129         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1130         (cpu_flags): Drop CpuVREX.
1131         * i386-opc.h (CpuVREX): Delete.
1132         (union i386_cpu_flags): Remove cpuvrex.
1133         * i386-init.h, i386-tbl.h: Re-generate.
1134
1135 2018-07-30  Jim Wilson  <jimw@sifive.com>
1136
1137         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1138         fields.
1139         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1140
1141 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1142
1143         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1144         * Makefile.in: Regenerated.
1145         * configure.ac: Add C-SKY.
1146         * configure: Regenerated.
1147         * csky-dis.c: New file.
1148         * csky-opc.h: New file.
1149         * disassemble.c (ARCH_csky): Define.
1150         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1151         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1152
1153 2018-07-27  Alan Modra  <amodra@gmail.com>
1154
1155         * ppc-opc.c (insert_sprbat): Correct function parameter and
1156         return type.
1157         (extract_sprbat): Likewise, variable too.
1158
1159 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1160             Alan Modra  <amodra@gmail.com>
1161
1162         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1163         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1164         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1165         support disjointed BAT.
1166         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1167         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1168         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1169
1170 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1171             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1172
1173         * i386-gen.c (adjust_broadcast_modifier): New function.
1174         (process_i386_opcode_modifier): Add an argument for operands.
1175         Adjust the Broadcast value based on operands.
1176         (output_i386_opcode): Pass operand_types to
1177         process_i386_opcode_modifier.
1178         (process_i386_opcodes): Pass NULL as operands to
1179         process_i386_opcode_modifier.
1180         * i386-opc.h (BYTE_BROADCAST): New.
1181         (WORD_BROADCAST): Likewise.
1182         (DWORD_BROADCAST): Likewise.
1183         (QWORD_BROADCAST): Likewise.
1184         (i386_opcode_modifier): Expand broadcast to 3 bits.
1185         * i386-tbl.h: Regenerated.
1186
1187 2018-07-24  Alan Modra  <amodra@gmail.com>
1188
1189         PR 23430
1190         * or1k-desc.h: Regenerate.
1191
1192 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1193
1194         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1195         vcvtusi2ss, and vcvtusi2sd.
1196         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1197         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1198         * i386-tbl.h: Re-generate.
1199
1200 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1201
1202         * arc-opc.c (extract_w6): Fix extending the sign.
1203
1204 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1205
1206         * arc-tbl.h (vewt): Allow it for ARC EM family.
1207
1208 2018-07-23  Alan Modra  <amodra@gmail.com>
1209
1210         PR 23419
1211         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1212         opcode variants for mtspr/mfspr encodings.
1213
1214 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1215             Maciej W. Rozycki  <macro@mips.com>
1216
1217         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1218         loongson3a descriptors.
1219         (parse_mips_ase_option): Handle -M loongson-mmi option.
1220         (print_mips_disassembler_options): Document -M loongson-mmi.
1221         * mips-opc.c (LMMI): New macro.
1222         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1223         instructions.
1224
1225 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1226
1227         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1228         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1229         IgnoreSize and [XYZ]MMword where applicable.
1230         * i386-tbl.h: Re-generate.
1231
1232 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1233
1234         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1235         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1236         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1237         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1238         * i386-tbl.h: Re-generate.
1239
1240 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1241
1242         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1243         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1244         VPCLMULQDQ templates into their respective AVX512VL counterparts
1245         where possible, using Disp8ShiftVL and CheckRegSize instead of
1246         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1247         * i386-tbl.h: Re-generate.
1248
1249 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1250
1251         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1252         AVX512VL counterparts where possible, using Disp8ShiftVL and
1253         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1254         IgnoreSize) as appropriate.
1255         * i386-tbl.h: Re-generate.
1256
1257 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1258
1259         * i386-opc.tbl: Fold AVX512BW templates into their respective
1260         AVX512VL counterparts where possible, using Disp8ShiftVL and
1261         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1262         IgnoreSize) as appropriate.
1263         * i386-tbl.h: Re-generate.
1264
1265 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1266
1267         * i386-opc.tbl: Fold AVX512CD templates into their respective
1268         AVX512VL counterparts where possible, using Disp8ShiftVL and
1269         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1270         IgnoreSize) as appropriate.
1271         * i386-tbl.h: Re-generate.
1272
1273 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1274
1275         * i386-opc.h (DISP8_SHIFT_VL): New.
1276         * i386-opc.tbl (Disp8ShiftVL):  Define.
1277         (various): Fold AVX512VL templates into their respective
1278         AVX512F counterparts where possible, using Disp8ShiftVL and
1279         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1280         IgnoreSize) as appropriate.
1281         * i386-tbl.h: Re-generate.
1282
1283 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1284
1285         * Makefile.am: Change dependencies and rule for
1286         $(srcdir)/i386-init.h.
1287         * Makefile.in: Re-generate.
1288         * i386-gen.c (process_i386_opcodes): New local variable
1289         "marker". Drop opening of input file. Recognize marker and line
1290         number directives.
1291         * i386-opc.tbl (OPCODE_I386_H): Define.
1292         (i386-opc.h): Include it.
1293         (None): Undefine.
1294
1295 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1296
1297         PR gas/23418
1298         * i386-opc.h (Byte): Update comments.
1299         (Word): Likewise.
1300         (Dword): Likewise.
1301         (Fword): Likewise.
1302         (Qword): Likewise.
1303         (Tbyte): Likewise.
1304         (Xmmword): Likewise.
1305         (Ymmword): Likewise.
1306         (Zmmword): Likewise.
1307         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1308         vcvttps2uqq.
1309         * i386-tbl.h: Regenerated.
1310
1311 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1312
1313         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1314         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1315         * aarch64-asm-2.c: Regenerate.
1316         * aarch64-dis-2.c: Regenerate.
1317         * aarch64-opc-2.c: Regenerate.
1318
1319 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1320
1321         PR binutils/23192
1322         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1323         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1324         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1325         sqdmulh, sqrdmulh): Use Em16.
1326
1327 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1328
1329         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1330         csdb together with them.
1331         (thumb32_opcodes): Likewise.
1332
1333 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1334
1335         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1336         requiring 32-bit registers as operands 2 and 3. Improve
1337         comments.
1338         (mwait, mwaitx): Fold templates. Improve comments.
1339         OPERAND_TYPE_INOUTPORTREG.
1340         * i386-tbl.h: Re-generate.
1341
1342 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1343
1344         * i386-gen.c (operand_type_init): Remove
1345         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1346         OPERAND_TYPE_INOUTPORTREG.
1347         * i386-init.h: Re-generate.
1348
1349 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1350
1351         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1352         (wrssq, wrussq): Add Qword.
1353         * i386-tbl.h: Re-generate.
1354
1355 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1356
1357         * i386-opc.h: Rename OTMax to OTNum.
1358         (OTNumOfUints): Adjust calculation.
1359         (OTUnused): Directly alias to OTNum.
1360
1361 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1362
1363         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1364         `reg_xys'.
1365         (lea_reg_xys): Likewise.
1366         (print_insn_loop_primitive): Rename `reg' local variable to
1367         `reg_dxy'.
1368
1369 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1370
1371         PR binutils/23242
1372         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1373
1374 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1375
1376         PR binutils/23369
1377         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1378         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1379
1380 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1381
1382         PR tdep/8282
1383         * mips-dis.c (mips_option_arg_t): New enumeration.
1384         (mips_options): New variable.
1385         (disassembler_options_mips): New function.
1386         (print_mips_disassembler_options): Reimplement in terms of
1387         `disassembler_options_mips'.
1388         * arm-dis.c (disassembler_options_arm): Adapt to using the
1389         `disasm_options_and_args_t' structure.
1390         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1391         * s390-dis.c (disassembler_options_s390): Likewise.
1392
1393 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1394
1395         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1396         expected result.
1397         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1398         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1399         * testsuite/ld-arm/tls-longplt.d: Likewise.
1400
1401 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1402
1403         PR binutils/23192
1404         * aarch64-asm-2.c: Regenerate.
1405         * aarch64-dis-2.c: Likewise.
1406         * aarch64-opc-2.c: Likewise.
1407         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1408         * aarch64-opc.c (operand_general_constraint_met_p,
1409         aarch64_print_operand): Likewise.
1410         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1411         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1412         fmlal2, fmlsl2.
1413         (AARCH64_OPERANDS): Add Em2.
1414
1415 2018-06-26  Nick Clifton  <nickc@redhat.com>
1416
1417         * po/uk.po: Updated Ukranian translation.
1418         * po/de.po: Updated German translation.
1419         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1420
1421 2018-06-26  Nick Clifton  <nickc@redhat.com>
1422
1423         * nfp-dis.c: Fix spelling mistake.
1424
1425 2018-06-24  Nick Clifton  <nickc@redhat.com>
1426
1427         * configure: Regenerate.
1428         * po/opcodes.pot: Regenerate.
1429
1430 2018-06-24  Nick Clifton  <nickc@redhat.com>
1431
1432         2.31 branch created.
1433
1434 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1435
1436         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1437         * aarch64-asm-2.c: Regenerate.
1438         * aarch64-dis-2.c: Likewise.
1439
1440 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1441
1442         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1443         `-M ginv' option description.
1444
1445 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1446
1447         PR gas/23305
1448         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1449         la and lla.
1450
1451 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1452
1453         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1454         * configure.ac: Remove AC_PREREQ.
1455         * Makefile.in: Re-generate.
1456         * aclocal.m4: Re-generate.
1457         * configure: Re-generate.
1458
1459 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1460
1461         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1462         mips64r6 descriptors.
1463         (parse_mips_ase_option): Handle -Mginv option.
1464         (print_mips_disassembler_options): Document -Mginv.
1465         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1466         (GINV): New macro.
1467         (mips_opcodes): Define ginvi and ginvt.
1468
1469 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1470             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1471
1472         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1473         * mips-opc.c (CRC, CRC64): New macros.
1474         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1475         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1476         crc32cd for CRC64.
1477
1478 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1479
1480         PR 20319
1481         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1482         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1483
1484 2018-06-06  Alan Modra  <amodra@gmail.com>
1485
1486         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1487         setjmp.  Move init for some other vars later too.
1488
1489 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1490
1491         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1492         (dis_private): Add new fields for property section tracking.
1493         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1494         (xtensa_instruction_fits): New functions.
1495         (fetch_data): Bump minimal fetch size to 4.
1496         (print_insn_xtensa): Make struct dis_private static.
1497         Load and prepare property table on section change.
1498         Don't disassemble literals. Don't disassemble instructions that
1499         cross property table boundaries.
1500
1501 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1502
1503         * configure: Regenerated.
1504
1505 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1506
1507         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1508         * i386-tbl.h: Re-generate.
1509
1510 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1511
1512         * i386-opc.tbl (sldt, str): Add NoRex64.
1513         * i386-tbl.h: Re-generate.
1514
1515 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1516
1517         * i386-opc.tbl (invpcid): Add Oword.
1518         * i386-tbl.h: Re-generate.
1519
1520 2018-06-01  Alan Modra  <amodra@gmail.com>
1521
1522         * sysdep.h (_bfd_error_handler): Don't declare.
1523         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1524         * rl78-decode.opc: Likewise.
1525         * msp430-decode.c: Regenerate.
1526         * rl78-decode.c: Regenerate.
1527
1528 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1529
1530         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1531         * i386-init.h : Regenerated.
1532
1533 2018-05-25  Alan Modra  <amodra@gmail.com>
1534
1535         * Makefile.in: Regenerate.
1536         * po/POTFILES.in: Regenerate.
1537
1538 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1539
1540         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1541         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1542         (insert_bab, extract_bab, insert_btab, extract_btab,
1543         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1544         (BAT, BBA VBA RBS XB6S): Delete macros.
1545         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1546         (BB, BD, RBX, XC6): Update for new macros.
1547         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1548         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1549         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1550         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1551
1552 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1553
1554         * Makefile.am: Add support for s12z architecture.
1555         * configure.ac: Likewise.
1556         * disassemble.c: Likewise.
1557         * disassemble.h: Likewise.
1558         * Makefile.in: Regenerate.
1559         * configure: Regenerate.
1560         * s12z-dis.c: New file.
1561         * s12z.h: New file.
1562
1563 2018-05-18  Alan Modra  <amodra@gmail.com>
1564
1565         * nfp-dis.c: Don't #include libbfd.h.
1566         (init_nfp3200_priv): Use bfd_get_section_contents.
1567         (nit_nfp6000_mecsr_sec): Likewise.
1568
1569 2018-05-17  Nick Clifton  <nickc@redhat.com>
1570
1571         * po/zh_CN.po: Updated simplified Chinese translation.
1572
1573 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1574
1575         PR binutils/23109
1576         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1577         * aarch64-dis-2.c: Regenerate.
1578
1579 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1580
1581         PR binutils/21446
1582         * aarch64-asm.c (opintl.h): Include.
1583         (aarch64_ins_sysreg): Enforce read/write constraints.
1584         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1585         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1586         (F_REG_READ, F_REG_WRITE): New.
1587         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1588         AARCH64_OPND_SYSREG.
1589         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1590         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1591         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1592         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1593         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1594         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1595         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1596         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1597         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1598         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1599         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1600         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1601         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1602         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1603         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1604         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1605         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1606
1607 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1608
1609         PR binutils/21446
1610         * aarch64-dis.c (no_notes: New.
1611         (parse_aarch64_dis_option): Support notes.
1612         (aarch64_decode_insn, print_operands): Likewise.
1613         (print_aarch64_disassembler_options): Document notes.
1614         * aarch64-opc.c (aarch64_print_operand): Support notes.
1615
1616 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1617
1618         PR binutils/21446
1619         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1620         and take error struct.
1621         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1622         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1623         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1624         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1625         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1626         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1627         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1628         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1629         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1630         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1631         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1632         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1633         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1634         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1635         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1636         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1637         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1638         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1639         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1640         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1641         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1642         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1643         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1644         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1645         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1646         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1647         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1648         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1649         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1650         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1651         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1652         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1653         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1654         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1655         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1656         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1657         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1658         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1659         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1660         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1661         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1662         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1663         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1664         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1665         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1666         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1667         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1668         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1669         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1670         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1671         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1672         (determine_disassembling_preference, aarch64_decode_insn,
1673         print_insn_aarch64_word, print_insn_data): Take errors struct.
1674         (print_insn_aarch64): Use errors.
1675         * aarch64-asm-2.c: Regenerate.
1676         * aarch64-dis-2.c: Regenerate.
1677         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1678         boolean in aarch64_insert_operan.
1679         (print_operand_extractor): Likewise.
1680         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1681
1682 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1683
1684         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1685
1686 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1687
1688         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1689
1690 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1691
1692         * cr16-opc.c (cr16_instruction): Comment typo fix.
1693         * hppa-dis.c (print_insn_hppa): Likewise.
1694
1695 2018-05-08  Jim Wilson  <jimw@sifive.com>
1696
1697         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1698         (match_c_slli64, match_srxi_as_c_srxi): New.
1699         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1700         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1701         <c.slli, c.srli, c.srai>: Use match_s_slli.
1702         <c.slli64, c.srli64, c.srai64>: New.
1703
1704 2018-05-08  Alan Modra  <amodra@gmail.com>
1705
1706         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1707         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1708         partition opcode space for index lookup.
1709
1710 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1711
1712         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1713         <insn_length>: ...with this.  Update usage.
1714         Remove duplicate call to *info->memory_error_func.
1715
1716 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1717             H.J. Lu  <hongjiu.lu@intel.com>
1718
1719         * i386-dis.c (Gva): New.
1720         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1721         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1722         (prefix_table): New instructions (see prefix above).
1723         (mod_table): New instructions (see prefix above).
1724         (OP_G): Handle va_mode.
1725         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1726         CPU_MOVDIR64B_FLAGS.
1727         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1728         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1729         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1730         * i386-opc.tbl: Add movidir{i,64b}.
1731         * i386-init.h: Regenerated.
1732         * i386-tbl.h: Likewise.
1733
1734 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1735
1736         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1737         AddrPrefixOpReg.
1738         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1739         (AddrPrefixOpReg): This.
1740         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1741         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1742
1743 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1744
1745         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1746         (vle_num_opcodes): Likewise.
1747         (spe2_num_opcodes): Likewise.
1748         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1749         initialization loop.
1750         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1751         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1752         only once.
1753
1754 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1755
1756         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1757
1758 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1759
1760         Makefile.am: Added nfp-dis.c.
1761         configure.ac: Added bfd_nfp_arch.
1762         disassemble.h: Added print_insn_nfp prototype.
1763         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1764         nfp-dis.c: New, for NFP support.
1765         po/POTFILES.in: Added nfp-dis.c to the list.
1766         Makefile.in: Regenerate.
1767         configure: Regenerate.
1768
1769 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1770
1771         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1772         templates into their base ones.
1773         * i386-tlb.h: Re-generate.
1774
1775 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1776
1777         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1778         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1779         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1780         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1781         * i386-init.h: Re-generate.
1782
1783 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1784
1785         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1786         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1787         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1788         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1789         comment.
1790         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1791         and CpuRegMask.
1792         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1793         CpuRegMask: Delete.
1794         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1795         cpuregzmm, and cpuregmask.
1796         * i386-init.h: Re-generate.
1797         * i386-tbl.h: Re-generate.
1798
1799 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1800
1801         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1802         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1803         * i386-init.h: Re-generate.
1804
1805 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1806
1807         * i386-gen.c (VexImmExt): Delete.
1808         * i386-opc.h (VexImmExt, veximmext): Delete.
1809         * i386-opc.tbl: Drop all VexImmExt uses.
1810         * i386-tlb.h: Re-generate.
1811
1812 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1813
1814         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1815         register-only forms.
1816         * i386-tlb.h: Re-generate.
1817
1818 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1819
1820         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1821
1822 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1823
1824         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1825         PREFIX_0F1C.
1826         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1827         (cpu_flags): Add CpuCLDEMOTE.
1828         * i386-init.h: Regenerate.
1829         * i386-opc.h (enum): Add CpuCLDEMOTE,
1830         (i386_cpu_flags): Add cpucldemote.
1831         * i386-opc.tbl: Add cldemote.
1832         * i386-tbl.h: Regenerate.
1833
1834 2018-04-16  Alan Modra  <amodra@gmail.com>
1835
1836         * Makefile.am: Remove sh5 and sh64 support.
1837         * configure.ac: Likewise.
1838         * disassemble.c: Likewise.
1839         * disassemble.h: Likewise.
1840         * sh-dis.c: Likewise.
1841         * sh64-dis.c: Delete.
1842         * sh64-opc.c: Delete.
1843         * sh64-opc.h: Delete.
1844         * Makefile.in: Regenerate.
1845         * configure: Regenerate.
1846         * po/POTFILES.in: Regenerate.
1847
1848 2018-04-16  Alan Modra  <amodra@gmail.com>
1849
1850         * Makefile.am: Remove w65 support.
1851         * configure.ac: Likewise.
1852         * disassemble.c: Likewise.
1853         * disassemble.h: Likewise.
1854         * w65-dis.c: Delete.
1855         * w65-opc.h: Delete.
1856         * Makefile.in: Regenerate.
1857         * configure: Regenerate.
1858         * po/POTFILES.in: Regenerate.
1859
1860 2018-04-16  Alan Modra  <amodra@gmail.com>
1861
1862         * configure.ac: Remove we32k support.
1863         * configure: Regenerate.
1864
1865 2018-04-16  Alan Modra  <amodra@gmail.com>
1866
1867         * Makefile.am: Remove m88k support.
1868         * configure.ac: Likewise.
1869         * disassemble.c: Likewise.
1870         * disassemble.h: Likewise.
1871         * m88k-dis.c: Delete.
1872         * Makefile.in: Regenerate.
1873         * configure: Regenerate.
1874         * po/POTFILES.in: Regenerate.
1875
1876 2018-04-16  Alan Modra  <amodra@gmail.com>
1877
1878         * Makefile.am: Remove i370 support.
1879         * configure.ac: Likewise.
1880         * disassemble.c: Likewise.
1881         * disassemble.h: Likewise.
1882         * i370-dis.c: Delete.
1883         * i370-opc.c: Delete.
1884         * Makefile.in: Regenerate.
1885         * configure: Regenerate.
1886         * po/POTFILES.in: Regenerate.
1887
1888 2018-04-16  Alan Modra  <amodra@gmail.com>
1889
1890         * Makefile.am: Remove h8500 support.
1891         * configure.ac: Likewise.
1892         * disassemble.c: Likewise.
1893         * disassemble.h: Likewise.
1894         * h8500-dis.c: Delete.
1895         * h8500-opc.h: Delete.
1896         * Makefile.in: Regenerate.
1897         * configure: Regenerate.
1898         * po/POTFILES.in: Regenerate.
1899
1900 2018-04-16  Alan Modra  <amodra@gmail.com>
1901
1902         * configure.ac: Remove tahoe support.
1903         * configure: Regenerate.
1904
1905 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1906
1907         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1908         umwait.
1909         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1910         64-bit mode.
1911         * i386-tbl.h: Regenerated.
1912
1913 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1914
1915         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1916         PREFIX_MOD_1_0FAE_REG_6.
1917         (va_mode): New.
1918         (OP_E_register): Use va_mode.
1919         * i386-dis-evex.h (prefix_table):
1920         New instructions (see prefixes above).
1921         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1922         (cpu_flags): Likewise.
1923         * i386-opc.h (enum): Likewise.
1924         (i386_cpu_flags): Likewise.
1925         * i386-opc.tbl: Add umonitor, umwait, tpause.
1926         * i386-init.h: Regenerate.
1927         * i386-tbl.h: Likewise.
1928
1929 2018-04-11  Alan Modra  <amodra@gmail.com>
1930
1931         * opcodes/i860-dis.c: Delete.
1932         * opcodes/i960-dis.c: Delete.
1933         * Makefile.am: Remove i860 and i960 support.
1934         * configure.ac: Likewise.
1935         * disassemble.c: Likewise.
1936         * disassemble.h: Likewise.
1937         * Makefile.in: Regenerate.
1938         * configure: Regenerate.
1939         * po/POTFILES.in: Regenerate.
1940
1941 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1942
1943         PR binutils/23025
1944         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1945         to 0.
1946         (print_insn): Clear vex instead of vex.evex.
1947
1948 2018-04-04  Nick Clifton  <nickc@redhat.com>
1949
1950         * po/es.po: Updated Spanish translation.
1951
1952 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1953
1954         * i386-gen.c (opcode_modifiers): Delete VecESize.
1955         * i386-opc.h (VecESize): Delete.
1956         (struct i386_opcode_modifier): Delete vecesize.
1957         * i386-opc.tbl: Drop VecESize.
1958         * i386-tlb.h: Re-generate.
1959
1960 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1961
1962         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1963         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1964         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1965         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1966         * i386-tlb.h: Re-generate.
1967
1968 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1969
1970         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1971         Fold AVX512 forms
1972         * i386-tlb.h: Re-generate.
1973
1974 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1975
1976         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1977         (vex_len_table): Drop Y for vcvt*2si.
1978         (putop): Replace plain 'Y' handling by abort().
1979
1980 2018-03-28  Nick Clifton  <nickc@redhat.com>
1981
1982         PR 22988
1983         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1984         instructions with only a base address register.
1985         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1986         handle AARHC64_OPND_SVE_ADDR_R.
1987         (aarch64_print_operand): Likewise.
1988         * aarch64-asm-2.c: Regenerate.
1989         * aarch64_dis-2.c: Regenerate.
1990         * aarch64-opc-2.c: Regenerate.
1991
1992 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1993
1994         * i386-opc.tbl: Drop VecESize from register only insn forms and
1995         memory forms not allowing broadcast.
1996         * i386-tlb.h: Re-generate.
1997
1998 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1999
2000         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2001         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2002         sha256*): Drop Disp<N>.
2003
2004 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2005
2006         * i386-dis.c (EbndS, bnd_swap_mode): New.
2007         (prefix_table): Use EbndS.
2008         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2009         * i386-opc.tbl (bndmov): Move misplaced Load.
2010         * i386-tlb.h: Re-generate.
2011
2012 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2013
2014         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2015         templates allowing memory operands and folded ones for register
2016         only flavors.
2017         * i386-tlb.h: Re-generate.
2018
2019 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2020
2021         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2022         256-bit templates. Drop redundant leftover Disp<N>.
2023         * i386-tlb.h: Re-generate.
2024
2025 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
2026
2027         * riscv-opc.c (riscv_insn_types): New.
2028
2029 2018-03-13  Nick Clifton  <nickc@redhat.com>
2030
2031         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2032
2033 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2034
2035         * i386-opc.tbl: Add Optimize to clr.
2036         * i386-tbl.h: Regenerated.
2037
2038 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2039
2040         * i386-gen.c (opcode_modifiers): Remove OldGcc.
2041         * i386-opc.h (OldGcc): Removed.
2042         (i386_opcode_modifier): Remove oldgcc.
2043         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2044         instructions for old (<= 2.8.1) versions of gcc.
2045         * i386-tbl.h: Regenerated.
2046
2047 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2048
2049         * i386-opc.h (EVEXDYN): New.
2050         * i386-opc.tbl: Fold various AVX512VL templates.
2051         * i386-tlb.h: Re-generate.
2052
2053 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2054
2055         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2056         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2057         vpexpandd, vpexpandq): Fold AFX512VF templates.
2058         * i386-tlb.h: Re-generate.
2059
2060 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2061
2062         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2063         Fold 128- and 256-bit VEX-encoded templates.
2064         * i386-tlb.h: Re-generate.
2065
2066 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2067
2068         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2069         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2070         vpexpandd, vpexpandq): Fold AVX512F templates.
2071         * i386-tlb.h: Re-generate.
2072
2073 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2074
2075         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2076         64-bit templates. Drop Disp<N>.
2077         * i386-tlb.h: Re-generate.
2078
2079 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2080
2081         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2082         and 256-bit templates.
2083         * i386-tlb.h: Re-generate.
2084
2085 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2086
2087         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2088         * i386-tlb.h: Re-generate.
2089
2090 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2091
2092         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2093         Drop NoAVX.
2094         * i386-tlb.h: Re-generate.
2095
2096 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2097
2098         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2099         * i386-tlb.h: Re-generate.
2100
2101 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2102
2103         * i386-gen.c (opcode_modifiers): Delete FloatD.
2104         * i386-opc.h (FloatD): Delete.
2105         (struct i386_opcode_modifier): Delete floatd.
2106         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2107         FloatD by D.
2108         * i386-tlb.h: Re-generate.
2109
2110 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2111
2112         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2113
2114 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2115
2116         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2117         * i386-tlb.h: Re-generate.
2118
2119 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2120
2121         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2122         forms.
2123         * i386-tlb.h: Re-generate.
2124
2125 2018-03-07  Alan Modra  <amodra@gmail.com>
2126
2127         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2128         bfd_arch_rs6000.
2129         * disassemble.h (print_insn_rs6000): Delete.
2130         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2131         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2132         (print_insn_rs6000): Delete.
2133
2134 2018-03-03  Alan Modra  <amodra@gmail.com>
2135
2136         * sysdep.h (opcodes_error_handler): Define.
2137         (_bfd_error_handler): Declare.
2138         * Makefile.am: Remove stray #.
2139         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2140         EDIT" comment.
2141         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2142         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2143         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2144         opcodes_error_handler to print errors.  Standardize error messages.
2145         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2146         and include opintl.h.
2147         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2148         * i386-gen.c: Standardize error messages.
2149         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2150         * Makefile.in: Regenerate.
2151         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2152         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2153         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2154         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2155         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2156         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2157         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2158         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2159         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2160         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2161         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2162         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2163         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2164
2165 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2166
2167         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2168         vpsub[bwdq] instructions.
2169         * i386-tbl.h: Regenerated.
2170
2171 2018-03-01  Alan Modra  <amodra@gmail.com>
2172
2173         * configure.ac (ALL_LINGUAS): Sort.
2174         * configure: Regenerate.
2175
2176 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2177
2178         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2179         macro by assignements.
2180
2181 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2182
2183         PR gas/22871
2184         * i386-gen.c (opcode_modifiers): Add Optimize.
2185         * i386-opc.h (Optimize): New enum.
2186         (i386_opcode_modifier): Add optimize.
2187         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2188         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2189         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2190         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2191         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2192         vpxord and vpxorq.
2193         * i386-tbl.h: Regenerated.
2194
2195 2018-02-26  Alan Modra  <amodra@gmail.com>
2196
2197         * crx-dis.c (getregliststring): Allocate a large enough buffer
2198         to silence false positive gcc8 warning.
2199
2200 2018-02-22  Shea Levy <shea@shealevy.com>
2201
2202         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2203
2204 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2205
2206         * i386-opc.tbl: Add {rex},
2207         * i386-tbl.h: Regenerated.
2208
2209 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2210
2211         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2212         (mips16_opcodes): Replace `M' with `m' for "restore".
2213
2214 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2215
2216         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2217
2218 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2219
2220         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2221         variable to `function_index'.
2222
2223 2018-02-13  Nick Clifton  <nickc@redhat.com>
2224
2225         PR 22823
2226         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2227         about truncation of printing.
2228
2229 2018-02-12  Henry Wong <henry@stuffedcow.net>
2230
2231         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2232
2233 2018-02-05  Nick Clifton  <nickc@redhat.com>
2234
2235         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2236
2237 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2238
2239         * i386-dis.c (enum): Add pconfig.
2240         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2241         (cpu_flags): Add CpuPCONFIG.
2242         * i386-opc.h (enum): Add CpuPCONFIG.
2243         (i386_cpu_flags): Add cpupconfig.
2244         * i386-opc.tbl: Add PCONFIG instruction.
2245         * i386-init.h: Regenerate.
2246         * i386-tbl.h: Likewise.
2247
2248 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2249
2250         * i386-dis.c (enum): Add PREFIX_0F09.
2251         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2252         (cpu_flags): Add CpuWBNOINVD.
2253         * i386-opc.h (enum): Add CpuWBNOINVD.
2254         (i386_cpu_flags): Add cpuwbnoinvd.
2255         * i386-opc.tbl: Add WBNOINVD instruction.
2256         * i386-init.h: Regenerate.
2257         * i386-tbl.h: Likewise.
2258
2259 2018-01-17  Jim Wilson  <jimw@sifive.com>
2260
2261         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2262
2263 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2264
2265         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2266         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2267         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2268         (cpu_flags): Add CpuIBT, CpuSHSTK.
2269         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2270         (i386_cpu_flags): Add cpuibt, cpushstk.
2271         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2272         * i386-init.h: Regenerate.
2273         * i386-tbl.h: Likewise.
2274
2275 2018-01-16  Nick Clifton  <nickc@redhat.com>
2276
2277         * po/pt_BR.po: Updated Brazilian Portugese translation.
2278         * po/de.po: Updated German translation.
2279
2280 2018-01-15  Jim Wilson  <jimw@sifive.com>
2281
2282         * riscv-opc.c (match_c_nop): New.
2283         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2284
2285 2018-01-15  Nick Clifton  <nickc@redhat.com>
2286
2287         * po/uk.po: Updated Ukranian translation.
2288
2289 2018-01-13  Nick Clifton  <nickc@redhat.com>
2290
2291         * po/opcodes.pot: Regenerated.
2292
2293 2018-01-13  Nick Clifton  <nickc@redhat.com>
2294
2295         * configure: Regenerate.
2296
2297 2018-01-13  Nick Clifton  <nickc@redhat.com>
2298
2299         2.30 branch created.
2300
2301 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2302
2303         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2304         * i386-tbl.h: Regenerate.
2305
2306 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2307
2308         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2309         * i386-tbl.h: Re-generate.
2310
2311 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2312
2313         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2314         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2315         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2316         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2317         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2318         Disp8MemShift of AVX512VL forms.
2319         * i386-tbl.h: Re-generate.
2320
2321 2018-01-09  Jim Wilson  <jimw@sifive.com>
2322
2323         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2324         then the hi_addr value is zero.
2325
2326 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2327
2328         * arm-dis.c (arm_opcodes): Add csdb.
2329         (thumb32_opcodes): Add csdb.
2330
2331 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2332
2333         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2334         * aarch64-asm-2.c: Regenerate.
2335         * aarch64-dis-2.c: Regenerate.
2336         * aarch64-opc-2.c: Regenerate.
2337
2338 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2339
2340         PR gas/22681
2341         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2342         Remove AVX512 vmovd with 64-bit operands.
2343         * i386-tbl.h: Regenerated.
2344
2345 2018-01-05  Jim Wilson  <jimw@sifive.com>
2346
2347         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2348         jalr.
2349
2350 2018-01-03  Alan Modra  <amodra@gmail.com>
2351
2352         Update year range in copyright notice of all files.
2353
2354 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2355
2356         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2357         and OPERAND_TYPE_REGZMM entries.
2358
2359 For older changes see ChangeLog-2017
2360 \f
2361 Copyright (C) 2018 Free Software Foundation, Inc.
2362
2363 Copying and distribution of this file, with or without modification,
2364 are permitted in any medium without royalty provided the copyright
2365 notice and this notice are preserved.
2366
2367 Local Variables:
2368 mode: change-log
2369 left-margin: 8
2370 fill-column: 74
2371 version-control: never
2372 End: