opcodes/ChangeLog

   1 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
   2
   3         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
   4         are used when extracting signed fields and converting them to
   5         potentially 64-bit types.
   6
   7 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
   8
   9         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
  10         * Makefile.in: Re-generate.
  11         * aclocal.m4: Re-generate.
  12         * configure: Re-generate.
  13         * configure.ac: Remove check for -Wno-missing-field-initializers.
  14         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
  15         (csky_v2_opcodes): Likewise.
  16
  17 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
  18
  19         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
  20
  21 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
  22
  23         * nds32-asm.c (operand_fields): Remove the unused fields.
  24         (nds32_opcodes): Remove the unused instructions.
  25         * nds32-dis.c (nds32_ex9_info): Removed.
  26         (nds32_parse_opcode): Updated.
  27         (print_insn_nds32): Likewise.
  28         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
  29         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
  30         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
  31         build_opcode_hash_table): New functions.
  32         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
  33         nds32_opcode_table): New.
  34         (hw_ktabs): Declare it to a pointer rather than an array.
  35         (build_hash_table): Removed.
  36         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
  37         SYN_ROPT and upadte HW_GPR and HW_INT.
  38         * nds32-dis.c (keywords): Remove const.
  39         (match_field): New function.
  40         (nds32_parse_opcode): Updated.
  41         * disassemble.c (disassemble_init_for_target):
  42         Add disassemble_init_nds32.
  43         * nds32-dis.c (eum map_type): New.
  44         (nds32_private_data): Likewise.
  45         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
  46         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
  47         (print_insn_nds32): Updated.
  48         * nds32-asm.c (parse_aext_reg): Add new parameter.
  49         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
  50         are allowed to use.
  51         All callers changed.
  52         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
  53         (operand_fields): Add new fields.
  54         (nds32_opcodes): Add new instructions.
  55         (keyword_aridxi_mx): New keyword.
  56         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
  57         and NASM_ATTR_ZOL.
  58         (ALU2_1, ALU2_2, ALU2_3): New macros.
  59         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
  60
  61 2018-09-17  Kito Cheng  <kito@andestech.com>
  62
  63         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
  64
  65 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         PR gas/23670
  68         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
  69         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
  70         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
  71         (EVEX_LEN_0F7E_P_1): Likewise.
  72         (EVEX_LEN_0F7E_P_2): Likewise.
  73         (EVEX_LEN_0FD6_P_2): Likewise.
  74         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
  75         (EVEX_LEN_TABLE): Likewise.
  76         (EVEX_LEN_0F6E_P_2): New enum.
  77         (EVEX_LEN_0F7E_P_1): Likewise.
  78         (EVEX_LEN_0F7E_P_2): Likewise.
  79         (EVEX_LEN_0FD6_P_2): Likewise.
  80         (evex_len_table): New.
  81         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
  82         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
  83         * i386-tbl.h: Regenerated.
  84
  85 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
  86
  87         PR gas/23665
  88         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
  89         VEX_LEN_0F7E_P_2 entries.
  90         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
  91         * i386-tbl.h: Regenerated.
  92
  93 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
  94
  95         * i386-dis.c (VZERO_Fixup): Removed.
  96         (VZERO): Likewise.
  97         (VEX_LEN_0F10_P_1): Likewise.
  98         (VEX_LEN_0F10_P_3): Likewise.
  99         (VEX_LEN_0F11_P_1): Likewise.
 100         (VEX_LEN_0F11_P_3): Likewise.
 101         (VEX_LEN_0F2E_P_0): Likewise.
 102         (VEX_LEN_0F2E_P_2): Likewise.
 103         (VEX_LEN_0F2F_P_0): Likewise.
 104         (VEX_LEN_0F2F_P_2): Likewise.
 105         (VEX_LEN_0F51_P_1): Likewise.
 106         (VEX_LEN_0F51_P_3): Likewise.
 107         (VEX_LEN_0F52_P_1): Likewise.
 108         (VEX_LEN_0F53_P_1): Likewise.
 109         (VEX_LEN_0F58_P_1): Likewise.
 110         (VEX_LEN_0F58_P_3): Likewise.
 111         (VEX_LEN_0F59_P_1): Likewise.
 112         (VEX_LEN_0F59_P_3): Likewise.
 113         (VEX_LEN_0F5A_P_1): Likewise.
 114         (VEX_LEN_0F5A_P_3): Likewise.
 115         (VEX_LEN_0F5C_P_1): Likewise.
 116         (VEX_LEN_0F5C_P_3): Likewise.
 117         (VEX_LEN_0F5D_P_1): Likewise.
 118         (VEX_LEN_0F5D_P_3): Likewise.
 119         (VEX_LEN_0F5E_P_1): Likewise.
 120         (VEX_LEN_0F5E_P_3): Likewise.
 121         (VEX_LEN_0F5F_P_1): Likewise.
 122         (VEX_LEN_0F5F_P_3): Likewise.
 123         (VEX_LEN_0FC2_P_1): Likewise.
 124         (VEX_LEN_0FC2_P_3): Likewise.
 125         (VEX_LEN_0F3A0A_P_2): Likewise.
 126         (VEX_LEN_0F3A0B_P_2): Likewise.
 127         (VEX_W_0F10_P_0): Likewise.
 128         (VEX_W_0F10_P_1): Likewise.
 129         (VEX_W_0F10_P_2): Likewise.
 130         (VEX_W_0F10_P_3): Likewise.
 131         (VEX_W_0F11_P_0): Likewise.
 132         (VEX_W_0F11_P_1): Likewise.
 133         (VEX_W_0F11_P_2): Likewise.
 134         (VEX_W_0F11_P_3): Likewise.
 135         (VEX_W_0F12_P_0_M_0): Likewise.
 136         (VEX_W_0F12_P_0_M_1): Likewise.
 137         (VEX_W_0F12_P_1): Likewise.
 138         (VEX_W_0F12_P_2): Likewise.
 139         (VEX_W_0F12_P_3): Likewise.
 140         (VEX_W_0F13_M_0): Likewise.
 141         (VEX_W_0F14): Likewise.
 142         (VEX_W_0F15): Likewise.
 143         (VEX_W_0F16_P_0_M_0): Likewise.
 144         (VEX_W_0F16_P_0_M_1): Likewise.
 145         (VEX_W_0F16_P_1): Likewise.
 146         (VEX_W_0F16_P_2): Likewise.
 147         (VEX_W_0F17_M_0): Likewise.
 148         (VEX_W_0F28): Likewise.
 149         (VEX_W_0F29): Likewise.
 150         (VEX_W_0F2B_M_0): Likewise.
 151         (VEX_W_0F2E_P_0): Likewise.
 152         (VEX_W_0F2E_P_2): Likewise.
 153         (VEX_W_0F2F_P_0): Likewise.
 154         (VEX_W_0F2F_P_2): Likewise.
 155         (VEX_W_0F50_M_0): Likewise.
 156         (VEX_W_0F51_P_0): Likewise.
 157         (VEX_W_0F51_P_1): Likewise.
 158         (VEX_W_0F51_P_2): Likewise.
 159         (VEX_W_0F51_P_3): Likewise.
 160         (VEX_W_0F52_P_0): Likewise.
 161         (VEX_W_0F52_P_1): Likewise.
 162         (VEX_W_0F53_P_0): Likewise.
 163         (VEX_W_0F53_P_1): Likewise.
 164         (VEX_W_0F58_P_0): Likewise.
 165         (VEX_W_0F58_P_1): Likewise.
 166         (VEX_W_0F58_P_2): Likewise.
 167         (VEX_W_0F58_P_3): Likewise.
 168         (VEX_W_0F59_P_0): Likewise.
 169         (VEX_W_0F59_P_1): Likewise.
 170         (VEX_W_0F59_P_2): Likewise.
 171         (VEX_W_0F59_P_3): Likewise.
 172         (VEX_W_0F5A_P_0): Likewise.
 173         (VEX_W_0F5A_P_1): Likewise.
 174         (VEX_W_0F5A_P_3): Likewise.
 175         (VEX_W_0F5B_P_0): Likewise.
 176         (VEX_W_0F5B_P_1): Likewise.
 177         (VEX_W_0F5B_P_2): Likewise.
 178         (VEX_W_0F5C_P_0): Likewise.
 179         (VEX_W_0F5C_P_1): Likewise.
 180         (VEX_W_0F5C_P_2): Likewise.
 181         (VEX_W_0F5C_P_3): Likewise.
 182         (VEX_W_0F5D_P_0): Likewise.
 183         (VEX_W_0F5D_P_1): Likewise.
 184         (VEX_W_0F5D_P_2): Likewise.
 185         (VEX_W_0F5D_P_3): Likewise.
 186         (VEX_W_0F5E_P_0): Likewise.
 187         (VEX_W_0F5E_P_1): Likewise.
 188         (VEX_W_0F5E_P_2): Likewise.
 189         (VEX_W_0F5E_P_3): Likewise.
 190         (VEX_W_0F5F_P_0): Likewise.
 191         (VEX_W_0F5F_P_1): Likewise.
 192         (VEX_W_0F5F_P_2): Likewise.
 193         (VEX_W_0F5F_P_3): Likewise.
 194         (VEX_W_0F60_P_2): Likewise.
 195         (VEX_W_0F61_P_2): Likewise.
 196         (VEX_W_0F62_P_2): Likewise.
 197         (VEX_W_0F63_P_2): Likewise.
 198         (VEX_W_0F64_P_2): Likewise.
 199         (VEX_W_0F65_P_2): Likewise.
 200         (VEX_W_0F66_P_2): Likewise.
 201         (VEX_W_0F67_P_2): Likewise.
 202         (VEX_W_0F68_P_2): Likewise.
 203         (VEX_W_0F69_P_2): Likewise.
 204         (VEX_W_0F6A_P_2): Likewise.
 205         (VEX_W_0F6B_P_2): Likewise.
 206         (VEX_W_0F6C_P_2): Likewise.
 207         (VEX_W_0F6D_P_2): Likewise.
 208         (VEX_W_0F6F_P_1): Likewise.
 209         (VEX_W_0F6F_P_2): Likewise.
 210         (VEX_W_0F70_P_1): Likewise.
 211         (VEX_W_0F70_P_2): Likewise.
 212         (VEX_W_0F70_P_3): Likewise.
 213         (VEX_W_0F71_R_2_P_2): Likewise.
 214         (VEX_W_0F71_R_4_P_2): Likewise.
 215         (VEX_W_0F71_R_6_P_2): Likewise.
 216         (VEX_W_0F72_R_2_P_2): Likewise.
 217         (VEX_W_0F72_R_4_P_2): Likewise.
 218         (VEX_W_0F72_R_6_P_2): Likewise.
 219         (VEX_W_0F73_R_2_P_2): Likewise.
 220         (VEX_W_0F73_R_3_P_2): Likewise.
 221         (VEX_W_0F73_R_6_P_2): Likewise.
 222         (VEX_W_0F73_R_7_P_2): Likewise.
 223         (VEX_W_0F74_P_2): Likewise.
 224         (VEX_W_0F75_P_2): Likewise.
 225         (VEX_W_0F76_P_2): Likewise.
 226         (VEX_W_0F77_P_0): Likewise.
 227         (VEX_W_0F7C_P_2): Likewise.
 228         (VEX_W_0F7C_P_3): Likewise.
 229         (VEX_W_0F7D_P_2): Likewise.
 230         (VEX_W_0F7D_P_3): Likewise.
 231         (VEX_W_0F7E_P_1): Likewise.
 232         (VEX_W_0F7F_P_1): Likewise.
 233         (VEX_W_0F7F_P_2): Likewise.
 234         (VEX_W_0FAE_R_2_M_0): Likewise.
 235         (VEX_W_0FAE_R_3_M_0): Likewise.
 236         (VEX_W_0FC2_P_0): Likewise.
 237         (VEX_W_0FC2_P_1): Likewise.
 238         (VEX_W_0FC2_P_2): Likewise.
 239         (VEX_W_0FC2_P_3): Likewise.
 240         (VEX_W_0FD0_P_2): Likewise.
 241         (VEX_W_0FD0_P_3): Likewise.
 242         (VEX_W_0FD1_P_2): Likewise.
 243         (VEX_W_0FD2_P_2): Likewise.
 244         (VEX_W_0FD3_P_2): Likewise.
 245         (VEX_W_0FD4_P_2): Likewise.
 246         (VEX_W_0FD5_P_2): Likewise.
 247         (VEX_W_0FD6_P_2): Likewise.
 248         (VEX_W_0FD7_P_2_M_1): Likewise.
 249         (VEX_W_0FD8_P_2): Likewise.
 250         (VEX_W_0FD9_P_2): Likewise.
 251         (VEX_W_0FDA_P_2): Likewise.
 252         (VEX_W_0FDB_P_2): Likewise.
 253         (VEX_W_0FDC_P_2): Likewise.
 254         (VEX_W_0FDD_P_2): Likewise.
 255         (VEX_W_0FDE_P_2): Likewise.
 256         (VEX_W_0FDF_P_2): Likewise.
 257         (VEX_W_0FE0_P_2): Likewise.
 258         (VEX_W_0FE1_P_2): Likewise.
 259         (VEX_W_0FE2_P_2): Likewise.
 260         (VEX_W_0FE3_P_2): Likewise.
 261         (VEX_W_0FE4_P_2): Likewise.
 262         (VEX_W_0FE5_P_2): Likewise.
 263         (VEX_W_0FE6_P_1): Likewise.
 264         (VEX_W_0FE6_P_2): Likewise.
 265         (VEX_W_0FE6_P_3): Likewise.
 266         (VEX_W_0FE7_P_2_M_0): Likewise.
 267         (VEX_W_0FE8_P_2): Likewise.
 268         (VEX_W_0FE9_P_2): Likewise.
 269         (VEX_W_0FEA_P_2): Likewise.
 270         (VEX_W_0FEB_P_2): Likewise.
 271         (VEX_W_0FEC_P_2): Likewise.
 272         (VEX_W_0FED_P_2): Likewise.
 273         (VEX_W_0FEE_P_2): Likewise.
 274         (VEX_W_0FEF_P_2): Likewise.
 275         (VEX_W_0FF0_P_3_M_0): Likewise.
 276         (VEX_W_0FF1_P_2): Likewise.
 277         (VEX_W_0FF2_P_2): Likewise.
 278         (VEX_W_0FF3_P_2): Likewise.
 279         (VEX_W_0FF4_P_2): Likewise.
 280         (VEX_W_0FF5_P_2): Likewise.
 281         (VEX_W_0FF6_P_2): Likewise.
 282         (VEX_W_0FF7_P_2): Likewise.
 283         (VEX_W_0FF8_P_2): Likewise.
 284         (VEX_W_0FF9_P_2): Likewise.
 285         (VEX_W_0FFA_P_2): Likewise.
 286         (VEX_W_0FFB_P_2): Likewise.
 287         (VEX_W_0FFC_P_2): Likewise.
 288         (VEX_W_0FFD_P_2): Likewise.
 289         (VEX_W_0FFE_P_2): Likewise.
 290         (VEX_W_0F3800_P_2): Likewise.
 291         (VEX_W_0F3801_P_2): Likewise.
 292         (VEX_W_0F3802_P_2): Likewise.
 293         (VEX_W_0F3803_P_2): Likewise.
 294         (VEX_W_0F3804_P_2): Likewise.
 295         (VEX_W_0F3805_P_2): Likewise.
 296         (VEX_W_0F3806_P_2): Likewise.
 297         (VEX_W_0F3807_P_2): Likewise.
 298         (VEX_W_0F3808_P_2): Likewise.
 299         (VEX_W_0F3809_P_2): Likewise.
 300         (VEX_W_0F380A_P_2): Likewise.
 301         (VEX_W_0F380B_P_2): Likewise.
 302         (VEX_W_0F3817_P_2): Likewise.
 303         (VEX_W_0F381C_P_2): Likewise.
 304         (VEX_W_0F381D_P_2): Likewise.
 305         (VEX_W_0F381E_P_2): Likewise.
 306         (VEX_W_0F3820_P_2): Likewise.
 307         (VEX_W_0F3821_P_2): Likewise.
 308         (VEX_W_0F3822_P_2): Likewise.
 309         (VEX_W_0F3823_P_2): Likewise.
 310         (VEX_W_0F3824_P_2): Likewise.
 311         (VEX_W_0F3825_P_2): Likewise.
 312         (VEX_W_0F3828_P_2): Likewise.
 313         (VEX_W_0F3829_P_2): Likewise.
 314         (VEX_W_0F382A_P_2_M_0): Likewise.
 315         (VEX_W_0F382B_P_2): Likewise.
 316         (VEX_W_0F3830_P_2): Likewise.
 317         (VEX_W_0F3831_P_2): Likewise.
 318         (VEX_W_0F3832_P_2): Likewise.
 319         (VEX_W_0F3833_P_2): Likewise.
 320         (VEX_W_0F3834_P_2): Likewise.
 321         (VEX_W_0F3835_P_2): Likewise.
 322         (VEX_W_0F3837_P_2): Likewise.
 323         (VEX_W_0F3838_P_2): Likewise.
 324         (VEX_W_0F3839_P_2): Likewise.
 325         (VEX_W_0F383A_P_2): Likewise.
 326         (VEX_W_0F383B_P_2): Likewise.
 327         (VEX_W_0F383C_P_2): Likewise.
 328         (VEX_W_0F383D_P_2): Likewise.
 329         (VEX_W_0F383E_P_2): Likewise.
 330         (VEX_W_0F383F_P_2): Likewise.
 331         (VEX_W_0F3840_P_2): Likewise.
 332         (VEX_W_0F3841_P_2): Likewise.
 333         (VEX_W_0F38DB_P_2): Likewise.
 334         (VEX_W_0F3A08_P_2): Likewise.
 335         (VEX_W_0F3A09_P_2): Likewise.
 336         (VEX_W_0F3A0A_P_2): Likewise.
 337         (VEX_W_0F3A0B_P_2): Likewise.
 338         (VEX_W_0F3A0C_P_2): Likewise.
 339         (VEX_W_0F3A0D_P_2): Likewise.
 340         (VEX_W_0F3A0E_P_2): Likewise.
 341         (VEX_W_0F3A0F_P_2): Likewise.
 342         (VEX_W_0F3A21_P_2): Likewise.
 343         (VEX_W_0F3A40_P_2): Likewise.
 344         (VEX_W_0F3A41_P_2): Likewise.
 345         (VEX_W_0F3A42_P_2): Likewise.
 346         (VEX_W_0F3A62_P_2): Likewise.
 347         (VEX_W_0F3A63_P_2): Likewise.
 348         (VEX_W_0F3ADF_P_2): Likewise.
 349         (VEX_LEN_0F77_P_0): New.
 350         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 351         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 352         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 353         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 354         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 355         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 356         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 357         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 358         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 359         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 360         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 361         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 362         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 363         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 364         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 365         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 366         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 367         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 368         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 369         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 370         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 371         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 372         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 373         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 374         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 375         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 376         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 377         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 378         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 379         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 380         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 381         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 382         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 383         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 384         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 385         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 386         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 387         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 388         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 389         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 390         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 391         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 392         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 393         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 394         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 395         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 396         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 397         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 398         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 399         (vex_table): Update VEX 0F28 and 0F29 entries.
 400         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 401         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 402         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 403         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 404         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 405         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 406         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 407         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 408         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 409         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 410         VEX_LEN_0F3A0B_P_2 entries.
 411         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 412         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 413         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 414         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 415         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 416         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 417         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 418         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 419         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 420         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 421         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 422         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 423         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 424         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 425         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 426         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 427         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 428         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 429         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 430         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 431         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 432         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 433         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 434         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 435         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 436         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 437         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 438         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 439         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 440         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 441         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 442         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 443         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 444         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 445         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 446         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 447         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 448         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 449         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 450         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 451         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 452         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 453         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 454         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 455         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 456         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 457         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 458         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 459         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 460         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 461         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 462         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 463         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 464         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 465         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 466         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 467         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 468         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 469         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 470         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 471         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 472         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 473         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 474         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 475         VEX_W_0F3ADF_P_2 entries.
 476         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 477         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 478         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 479
 480 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 481
 482         * i386-opc.tbl (VexWIG): New.
 483         Replace VexW=3 with VexWIG.
 484
 485 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 486
 487         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 488         * i386-tbl.h: Regenerated.
 489
 490 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 491
 492         PR gas/23665
 493         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 494         VEX_LEN_0FD6_P_2 entries.
 495         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 496         * i386-tbl.h: Regenerated.
 497
 498 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 499
 500         PR gas/23642
 501         * i386-opc.h (VEXWIG): New.
 502         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 503         * i386-tbl.h: Regenerated.
 504
 505 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 506
 507         PR binutils/23655
 508         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 509         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 510         * i386-dis.c (EXxEVexR64): New.
 511         (evex_rounding_64_mode): Likewise.
 512         (OP_Rounding): Handle evex_rounding_64_mode.
 513
 514 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 515
 516         PR binutils/23655
 517         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 518         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 519         * i386-dis.c (Edqa): New.
 520         (dqa_mode): Likewise.
 521         (intel_operand_size): Handle dqa_mode as m_mode.
 522         (OP_E_register): Handle dqa_mode as dq_mode.
 523         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 524
 525 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 526
 527         * i386-dis.c (OP_E_memory): Reformat.
 528
 529 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 530
 531         * i386-opc.tbl (crc32): Fold byte and word forms.
 532         * i386-tbl.h: Re-generate.
 533
 534 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 535
 536         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 537         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 538         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 539         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 540         * i386-tbl.h: Regenerated.
 541
 542 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 543
 544         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 545         meaningless.
 546         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 547         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 548         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 549         * i386-tbl.h: Re-generate.
 550
 551 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 552
 553         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 554         AVX512_4VNNIW insns.
 555         * i386-tbl.h: Re-generate.
 556
 557 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 558
 559         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 560         meaningless.
 561         * i386-tbl.h: Re-generate.
 562
 563 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 564
 565         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 566         meaningless.
 567         * i386-tbl.h: Re-generate.
 568
 569 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 570
 571         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 572         meaningless.
 573         * i386-tbl.h: Re-generate.
 574
 575 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 576
 577         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 578         meaningless.
 579         * i386-tbl.h: Re-generate.
 580
 581 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 582
 583         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 584         meaningless.
 585         * i386-tbl.h: Re-generate.
 586
 587 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 588
 589         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 590         * i386-tbl.h: Re-generate.
 591
 592 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 595         * i386-tbl.h: Re-generate.
 596
 597 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 600         meaningless.
 601         * i386-tbl.h: Re-generate.
 602
 603 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 606         meaningless.
 607         * i386-tbl.h: Re-generate.
 608
 609 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 612         * i386-tbl.h: Re-generate.
 613
 614 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 615
 616         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 617         * i386-tbl.h: Re-generate.
 618
 619 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 620
 621         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 622         * i386-tbl.h: Re-generate.
 623
 624 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 625
 626         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 627         meaningless.
 628         * i386-tbl.h: Re-generate.
 629
 630 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 631
 632         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 633         meaningless.
 634         * i386-tbl.h: Re-generate.
 635
 636 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 637
 638         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 639         meaningless.
 640         * i386-tbl.h: Re-generate.
 641
 642 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 643
 644         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 645         * i386-tbl.h: Re-generate.
 646
 647 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 648
 649         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 650         * i386-tbl.h: Re-generate.
 651
 652 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 655         * i386-tbl.h: Re-generate.
 656
 657 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 660         (vpbroadcastw, rdpid): Drop NoRex64.
 661         * i386-tbl.h: Re-generate.
 662
 663 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 664
 665         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 666         store templates, adding D.
 667         * i386-tbl.h: Re-generate.
 668
 669 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 670
 671         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 672         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 673         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 674         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 675         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 676         Fold load and store templates where possible, adding D. Drop
 677         IgnoreSize where it was pointlessly present. Drop redundant
 678         *word.
 679         * i386-tbl.h: Re-generate.
 680
 681 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 682
 683         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 684         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 685         (intel_operand_size): Handle v_bndmk_mode.
 686         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 687
 688 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 689
 690         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 691
 692 2018-08-31  Kito Cheng  <kito@andestech.com>
 693
 694         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 695         compressed floating point instructions.
 696
 697 2018-08-30  Kito Cheng  <kito@andestech.com>
 698
 699         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 700         riscv_opcode.xlen_requirement.
 701         * riscv-opc.c (riscv_opcodes): Update for struct change.
 702
 703 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 704
 705         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 706         psr (PWRPSR) instruction.
 707
 708 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 709
 710         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 711
 712 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 713
 714         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 715
 716 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 717
 718         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 719         loongson3a as an alias of gs464 for compatibility.
 720         * mips-opc.c (mips_opcodes): Change Comments.
 721
 722 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 723
 724         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 725         option.
 726         (print_mips_disassembler_options): Document -M loongson-ext.
 727         * mips-opc.c (LEXT2): New macro.
 728         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 729
 730 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 731
 732          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 733          descriptors.
 734          (parse_mips_ase_option): Handle -M loongson-ext option.
 735          (print_mips_disassembler_options): Document -M loongson-ext.
 736          * mips-opc.c (IL3A): Delete.
 737          * mips-opc.c (LEXT): New macro.
 738          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 739          instructions.
 740
 741 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 742
 743         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 744         descriptors.
 745         (parse_mips_ase_option): Handle -M loongson-cam option.
 746         (print_mips_disassembler_options): Document -M loongson-cam.
 747         * mips-opc.c (LCAM): New macro.
 748         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 749         instructions.
 750
 751 2018-08-21  Alan Modra  <amodra@gmail.com>
 752
 753         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 754         (skip_optional_operands): Count optional operands, and update
 755         ppc_optional_operand_value call.
 756         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 757         (extract_vlensi): Likewise.
 758         (extract_fxm): Return default value for missing optional operand.
 759         (extract_ls, extract_raq, extract_tbr): Likewise.
 760         (insert_sxl, extract_sxl): New functions.
 761         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 762         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 763         flag and extra entry.
 764         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 765         extract_sxl.
 766
 767 2018-08-20  Alan Modra  <amodra@gmail.com>
 768
 769         * sh-opc.h (MASK): Simplify.
 770
 771 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 772
 773         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 774         BM_RESERVED0 or BM_RESERVED1
 775         (bm_rel_decode, bm_n_bytes): Ditto.
 776
 777 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 778
 779         * s12z.h: Delete.
 780
 781 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 782
 783         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 784         address with the addr32 prefix and without base nor index
 785         registers.
 786
 787 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 788
 789         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 790         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 791         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 792         (cpu_flags): Add CpuCMOV and CpuFXSR.
 793         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 794         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 795         * i386-init.h: Regenerated.
 796         * i386-tbl.h: Likewise.
 797
 798 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 799
 800         * arc-regs.h: Update auxiliary registers.
 801
 802 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 803
 804         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 805         (RegIP, RegIZ): Define.
 806         * i386-reg.tbl: Adjust comments.
 807         (rip): Use Qword instead of BaseIndex. Use RegIP.
 808         (eip): Use Dword instead of BaseIndex. Use RegIP.
 809         (riz): Add Qword. Use RegIZ.
 810         (eiz): Add Dword. Use RegIZ.
 811         * i386-tbl.h: Re-generate.
 812
 813 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 814
 815         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 816         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 817         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 818         * i386-tbl.h: Re-generate.
 819
 820 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 821
 822         * i386-gen.c (operand_types): Remove Mem field.
 823         * i386-opc.h (union i386_operand_type): Remove mem field.
 824         * i386-init.h, i386-tbl.h: Re-generate.
 825
 826 2018-08-01  Alan Modra  <amodra@gmail.com>
 827
 828         * po/POTFILES.in: Regenerate.
 829
 830 2018-07-31  Nick Clifton  <nickc@redhat.com>
 831
 832         * po/sv.po: Updated Swedish translation.
 833
 834 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 835
 836         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 837         * i386-init.h, i386-tbl.h: Re-generate.
 838
 839 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 840
 841         * i386-opc.h (ZEROING_MASKING) Rename to ...
 842         (DYNAMIC_MASKING): ... this. Adjust comment.
 843         * i386-opc.tbl (MaskingMorZ): Define.
 844         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 845         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 846         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 847         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 848         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 849         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 850         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 851         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 852         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 853
 854 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 855
 856         * i386-opc.tbl: Use element rather than vector size for AVX512*
 857         scatter/gather insns.
 858         * i386-tbl.h: Re-generate.
 859
 860 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 861
 862         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 863         (cpu_flags): Drop CpuVREX.
 864         * i386-opc.h (CpuVREX): Delete.
 865         (union i386_cpu_flags): Remove cpuvrex.
 866         * i386-init.h, i386-tbl.h: Re-generate.
 867
 868 2018-07-30  Jim Wilson  <jimw@sifive.com>
 869
 870         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 871         fields.
 872         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 873
 874 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 875
 876         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 877         * Makefile.in: Regenerated.
 878         * configure.ac: Add C-SKY.
 879         * configure: Regenerated.
 880         * csky-dis.c: New file.
 881         * csky-opc.h: New file.
 882         * disassemble.c (ARCH_csky): Define.
 883         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 884         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 885
 886 2018-07-27  Alan Modra  <amodra@gmail.com>
 887
 888         * ppc-opc.c (insert_sprbat): Correct function parameter and
 889         return type.
 890         (extract_sprbat): Likewise, variable too.
 891
 892 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 893             Alan Modra  <amodra@gmail.com>
 894
 895         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 896         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 897         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 898         support disjointed BAT.
 899         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 900         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 901         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 902
 903 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 904             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 905
 906         * i386-gen.c (adjust_broadcast_modifier): New function.
 907         (process_i386_opcode_modifier): Add an argument for operands.
 908         Adjust the Broadcast value based on operands.
 909         (output_i386_opcode): Pass operand_types to
 910         process_i386_opcode_modifier.
 911         (process_i386_opcodes): Pass NULL as operands to
 912         process_i386_opcode_modifier.
 913         * i386-opc.h (BYTE_BROADCAST): New.
 914         (WORD_BROADCAST): Likewise.
 915         (DWORD_BROADCAST): Likewise.
 916         (QWORD_BROADCAST): Likewise.
 917         (i386_opcode_modifier): Expand broadcast to 3 bits.
 918         * i386-tbl.h: Regenerated.
 919
 920 2018-07-24  Alan Modra  <amodra@gmail.com>
 921
 922         PR 23430
 923         * or1k-desc.h: Regenerate.
 924
 925 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 926
 927         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 928         vcvtusi2ss, and vcvtusi2sd.
 929         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 930         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 931         * i386-tbl.h: Re-generate.
 932
 933 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 934
 935         * arc-opc.c (extract_w6): Fix extending the sign.
 936
 937 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 938
 939         * arc-tbl.h (vewt): Allow it for ARC EM family.
 940
 941 2018-07-23  Alan Modra  <amodra@gmail.com>
 942
 943         PR 23419
 944         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 945         opcode variants for mtspr/mfspr encodings.
 946
 947 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 948             Maciej W. Rozycki  <macro@mips.com>
 949
 950         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 951         loongson3a descriptors.
 952         (parse_mips_ase_option): Handle -M loongson-mmi option.
 953         (print_mips_disassembler_options): Document -M loongson-mmi.
 954         * mips-opc.c (LMMI): New macro.
 955         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 956         instructions.
 957
 958 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 959
 960         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 961         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 962         IgnoreSize and [XYZ]MMword where applicable.
 963         * i386-tbl.h: Re-generate.
 964
 965 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 966
 967         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 968         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 969         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 970         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 971         * i386-tbl.h: Re-generate.
 972
 973 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 974
 975         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 976         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 977         VPCLMULQDQ templates into their respective AVX512VL counterparts
 978         where possible, using Disp8ShiftVL and CheckRegSize instead of
 979         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 980         * i386-tbl.h: Re-generate.
 981
 982 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 985         AVX512VL counterparts where possible, using Disp8ShiftVL and
 986         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 987         IgnoreSize) as appropriate.
 988         * i386-tbl.h: Re-generate.
 989
 990 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 991
 992         * i386-opc.tbl: Fold AVX512BW templates into their respective
 993         AVX512VL counterparts where possible, using Disp8ShiftVL and
 994         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 995         IgnoreSize) as appropriate.
 996         * i386-tbl.h: Re-generate.
 997
 998 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 999
1000         * i386-opc.tbl: Fold AVX512CD templates into their respective
1001         AVX512VL counterparts where possible, using Disp8ShiftVL and
1002         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1003         IgnoreSize) as appropriate.
1004         * i386-tbl.h: Re-generate.
1005
1006 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1007
1008         * i386-opc.h (DISP8_SHIFT_VL): New.
1009         * i386-opc.tbl (Disp8ShiftVL):  Define.
1010         (various): Fold AVX512VL templates into their respective
1011         AVX512F counterparts where possible, using Disp8ShiftVL and
1012         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1013         IgnoreSize) as appropriate.
1014         * i386-tbl.h: Re-generate.
1015
1016 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1017
1018         * Makefile.am: Change dependencies and rule for
1019         $(srcdir)/i386-init.h.
1020         * Makefile.in: Re-generate.
1021         * i386-gen.c (process_i386_opcodes): New local variable
1022         "marker". Drop opening of input file. Recognize marker and line
1023         number directives.
1024         * i386-opc.tbl (OPCODE_I386_H): Define.
1025         (i386-opc.h): Include it.
1026         (None): Undefine.
1027
1028 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1029
1030         PR gas/23418
1031         * i386-opc.h (Byte): Update comments.
1032         (Word): Likewise.
1033         (Dword): Likewise.
1034         (Fword): Likewise.
1035         (Qword): Likewise.
1036         (Tbyte): Likewise.
1037         (Xmmword): Likewise.
1038         (Ymmword): Likewise.
1039         (Zmmword): Likewise.
1040         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1041         vcvttps2uqq.
1042         * i386-tbl.h: Regenerated.
1043
1044 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1045
1046         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1047         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1048         * aarch64-asm-2.c: Regenerate.
1049         * aarch64-dis-2.c: Regenerate.
1050         * aarch64-opc-2.c: Regenerate.
1051
1052 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1053
1054         PR binutils/23192
1055         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1056         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1057         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1058         sqdmulh, sqrdmulh): Use Em16.
1059
1060 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1061
1062         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1063         csdb together with them.
1064         (thumb32_opcodes): Likewise.
1065
1066 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1067
1068         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1069         requiring 32-bit registers as operands 2 and 3. Improve
1070         comments.
1071         (mwait, mwaitx): Fold templates. Improve comments.
1072         OPERAND_TYPE_INOUTPORTREG.
1073         * i386-tbl.h: Re-generate.
1074
1075 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1076
1077         * i386-gen.c (operand_type_init): Remove
1078         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1079         OPERAND_TYPE_INOUTPORTREG.
1080         * i386-init.h: Re-generate.
1081
1082 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1083
1084         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1085         (wrssq, wrussq): Add Qword.
1086         * i386-tbl.h: Re-generate.
1087
1088 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1089
1090         * i386-opc.h: Rename OTMax to OTNum.
1091         (OTNumOfUints): Adjust calculation.
1092         (OTUnused): Directly alias to OTNum.
1093
1094 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1095
1096         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1097         `reg_xys'.
1098         (lea_reg_xys): Likewise.
1099         (print_insn_loop_primitive): Rename `reg' local variable to
1100         `reg_dxy'.
1101
1102 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1103
1104         PR binutils/23242
1105         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1106
1107 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1108
1109         PR binutils/23369
1110         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1111         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1112
1113 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1114
1115         PR tdep/8282
1116         * mips-dis.c (mips_option_arg_t): New enumeration.
1117         (mips_options): New variable.
1118         (disassembler_options_mips): New function.
1119         (print_mips_disassembler_options): Reimplement in terms of
1120         `disassembler_options_mips'.
1121         * arm-dis.c (disassembler_options_arm): Adapt to using the
1122         `disasm_options_and_args_t' structure.
1123         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1124         * s390-dis.c (disassembler_options_s390): Likewise.
1125
1126 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1127
1128         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1129         expected result.
1130         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1131         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1132         * testsuite/ld-arm/tls-longplt.d: Likewise.
1133
1134 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1135
1136         PR binutils/23192
1137         * aarch64-asm-2.c: Regenerate.
1138         * aarch64-dis-2.c: Likewise.
1139         * aarch64-opc-2.c: Likewise.
1140         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1141         * aarch64-opc.c (operand_general_constraint_met_p,
1142         aarch64_print_operand): Likewise.
1143         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1144         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1145         fmlal2, fmlsl2.
1146         (AARCH64_OPERANDS): Add Em2.
1147
1148 2018-06-26  Nick Clifton  <nickc@redhat.com>
1149
1150         * po/uk.po: Updated Ukranian translation.
1151         * po/de.po: Updated German translation.
1152         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1153
1154 2018-06-26  Nick Clifton  <nickc@redhat.com>
1155
1156         * nfp-dis.c: Fix spelling mistake.
1157
1158 2018-06-24  Nick Clifton  <nickc@redhat.com>
1159
1160         * configure: Regenerate.
1161         * po/opcodes.pot: Regenerate.
1162
1163 2018-06-24  Nick Clifton  <nickc@redhat.com>
1164
1165         2.31 branch created.
1166
1167 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1168
1169         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1170         * aarch64-asm-2.c: Regenerate.
1171         * aarch64-dis-2.c: Likewise.
1172
1173 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1174
1175         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1176         `-M ginv' option description.
1177
1178 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1179
1180         PR gas/23305
1181         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1182         la and lla.
1183
1184 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1185
1186         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1187         * configure.ac: Remove AC_PREREQ.
1188         * Makefile.in: Re-generate.
1189         * aclocal.m4: Re-generate.
1190         * configure: Re-generate.
1191
1192 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1193
1194         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1195         mips64r6 descriptors.
1196         (parse_mips_ase_option): Handle -Mginv option.
1197         (print_mips_disassembler_options): Document -Mginv.
1198         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1199         (GINV): New macro.
1200         (mips_opcodes): Define ginvi and ginvt.
1201
1202 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1203             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1204
1205         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1206         * mips-opc.c (CRC, CRC64): New macros.
1207         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1208         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1209         crc32cd for CRC64.
1210
1211 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1212
1213         PR 20319
1214         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1215         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1216
1217 2018-06-06  Alan Modra  <amodra@gmail.com>
1218
1219         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1220         setjmp.  Move init for some other vars later too.
1221
1222 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1223
1224         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1225         (dis_private): Add new fields for property section tracking.
1226         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1227         (xtensa_instruction_fits): New functions.
1228         (fetch_data): Bump minimal fetch size to 4.
1229         (print_insn_xtensa): Make struct dis_private static.
1230         Load and prepare property table on section change.
1231         Don't disassemble literals. Don't disassemble instructions that
1232         cross property table boundaries.
1233
1234 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1235
1236         * configure: Regenerated.
1237
1238 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1239
1240         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1241         * i386-tbl.h: Re-generate.
1242
1243 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1244
1245         * i386-opc.tbl (sldt, str): Add NoRex64.
1246         * i386-tbl.h: Re-generate.
1247
1248 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1249
1250         * i386-opc.tbl (invpcid): Add Oword.
1251         * i386-tbl.h: Re-generate.
1252
1253 2018-06-01  Alan Modra  <amodra@gmail.com>
1254
1255         * sysdep.h (_bfd_error_handler): Don't declare.
1256         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1257         * rl78-decode.opc: Likewise.
1258         * msp430-decode.c: Regenerate.
1259         * rl78-decode.c: Regenerate.
1260
1261 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1262
1263         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1264         * i386-init.h : Regenerated.
1265
1266 2018-05-25  Alan Modra  <amodra@gmail.com>
1267
1268         * Makefile.in: Regenerate.
1269         * po/POTFILES.in: Regenerate.
1270
1271 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1272
1273         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1274         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1275         (insert_bab, extract_bab, insert_btab, extract_btab,
1276         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1277         (BAT, BBA VBA RBS XB6S): Delete macros.
1278         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1279         (BB, BD, RBX, XC6): Update for new macros.
1280         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1281         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1282         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1283         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1284
1285 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1286
1287         * Makefile.am: Add support for s12z architecture.
1288         * configure.ac: Likewise.
1289         * disassemble.c: Likewise.
1290         * disassemble.h: Likewise.
1291         * Makefile.in: Regenerate.
1292         * configure: Regenerate.
1293         * s12z-dis.c: New file.
1294         * s12z.h: New file.
1295
1296 2018-05-18  Alan Modra  <amodra@gmail.com>
1297
1298         * nfp-dis.c: Don't #include libbfd.h.
1299         (init_nfp3200_priv): Use bfd_get_section_contents.
1300         (nit_nfp6000_mecsr_sec): Likewise.
1301
1302 2018-05-17  Nick Clifton  <nickc@redhat.com>
1303
1304         * po/zh_CN.po: Updated simplified Chinese translation.
1305
1306 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1307
1308         PR binutils/23109
1309         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1310         * aarch64-dis-2.c: Regenerate.
1311
1312 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1313
1314         PR binutils/21446
1315         * aarch64-asm.c (opintl.h): Include.
1316         (aarch64_ins_sysreg): Enforce read/write constraints.
1317         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1318         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1319         (F_REG_READ, F_REG_WRITE): New.
1320         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1321         AARCH64_OPND_SYSREG.
1322         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1323         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1324         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1325         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1326         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1327         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1328         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1329         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1330         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1331         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1332         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1333         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1334         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1335         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1336         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1337         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1338         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1339
1340 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1341
1342         PR binutils/21446
1343         * aarch64-dis.c (no_notes: New.
1344         (parse_aarch64_dis_option): Support notes.
1345         (aarch64_decode_insn, print_operands): Likewise.
1346         (print_aarch64_disassembler_options): Document notes.
1347         * aarch64-opc.c (aarch64_print_operand): Support notes.
1348
1349 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1350
1351         PR binutils/21446
1352         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1353         and take error struct.
1354         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1355         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1356         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1357         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1358         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1359         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1360         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1361         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1362         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1363         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1364         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1365         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1366         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1367         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1368         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1369         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1370         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1371         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1372         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1373         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1374         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1375         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1376         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1377         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1378         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1379         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1380         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1381         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1382         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1383         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1384         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1385         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1386         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1387         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1388         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1389         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1390         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1391         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1392         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1393         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1394         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1395         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1396         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1397         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1398         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1399         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1400         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1401         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1402         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1403         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1404         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1405         (determine_disassembling_preference, aarch64_decode_insn,
1406         print_insn_aarch64_word, print_insn_data): Take errors struct.
1407         (print_insn_aarch64): Use errors.
1408         * aarch64-asm-2.c: Regenerate.
1409         * aarch64-dis-2.c: Regenerate.
1410         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1411         boolean in aarch64_insert_operan.
1412         (print_operand_extractor): Likewise.
1413         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1414
1415 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1416
1417         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1418
1419 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1420
1421         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1422
1423 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1424
1425         * cr16-opc.c (cr16_instruction): Comment typo fix.
1426         * hppa-dis.c (print_insn_hppa): Likewise.
1427
1428 2018-05-08  Jim Wilson  <jimw@sifive.com>
1429
1430         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1431         (match_c_slli64, match_srxi_as_c_srxi): New.
1432         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1433         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1434         <c.slli, c.srli, c.srai>: Use match_s_slli.
1435         <c.slli64, c.srli64, c.srai64>: New.
1436
1437 2018-05-08  Alan Modra  <amodra@gmail.com>
1438
1439         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1440         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1441         partition opcode space for index lookup.
1442
1443 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1444
1445         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1446         <insn_length>: ...with this.  Update usage.
1447         Remove duplicate call to *info->memory_error_func.
1448
1449 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1450             H.J. Lu  <hongjiu.lu@intel.com>
1451
1452         * i386-dis.c (Gva): New.
1453         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1454         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1455         (prefix_table): New instructions (see prefix above).
1456         (mod_table): New instructions (see prefix above).
1457         (OP_G): Handle va_mode.
1458         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1459         CPU_MOVDIR64B_FLAGS.
1460         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1461         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1462         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1463         * i386-opc.tbl: Add movidir{i,64b}.
1464         * i386-init.h: Regenerated.
1465         * i386-tbl.h: Likewise.
1466
1467 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1468
1469         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1470         AddrPrefixOpReg.
1471         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1472         (AddrPrefixOpReg): This.
1473         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1474         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1475
1476 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1477
1478         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1479         (vle_num_opcodes): Likewise.
1480         (spe2_num_opcodes): Likewise.
1481         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1482         initialization loop.
1483         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1484         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1485         only once.
1486
1487 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1488
1489         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1490
1491 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1492
1493         Makefile.am: Added nfp-dis.c.
1494         configure.ac: Added bfd_nfp_arch.
1495         disassemble.h: Added print_insn_nfp prototype.
1496         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1497         nfp-dis.c: New, for NFP support.
1498         po/POTFILES.in: Added nfp-dis.c to the list.
1499         Makefile.in: Regenerate.
1500         configure: Regenerate.
1501
1502 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1503
1504         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1505         templates into their base ones.
1506         * i386-tlb.h: Re-generate.
1507
1508 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1509
1510         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1511         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1512         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1513         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1514         * i386-init.h: Re-generate.
1515
1516 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1517
1518         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1519         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1520         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1521         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1522         comment.
1523         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1524         and CpuRegMask.
1525         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1526         CpuRegMask: Delete.
1527         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1528         cpuregzmm, and cpuregmask.
1529         * i386-init.h: Re-generate.
1530         * i386-tbl.h: Re-generate.
1531
1532 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1533
1534         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1535         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1536         * i386-init.h: Re-generate.
1537
1538 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1539
1540         * i386-gen.c (VexImmExt): Delete.
1541         * i386-opc.h (VexImmExt, veximmext): Delete.
1542         * i386-opc.tbl: Drop all VexImmExt uses.
1543         * i386-tlb.h: Re-generate.
1544
1545 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1546
1547         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1548         register-only forms.
1549         * i386-tlb.h: Re-generate.
1550
1551 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1552
1553         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1554
1555 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1556
1557         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1558         PREFIX_0F1C.
1559         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1560         (cpu_flags): Add CpuCLDEMOTE.
1561         * i386-init.h: Regenerate.
1562         * i386-opc.h (enum): Add CpuCLDEMOTE,
1563         (i386_cpu_flags): Add cpucldemote.
1564         * i386-opc.tbl: Add cldemote.
1565         * i386-tbl.h: Regenerate.
1566
1567 2018-04-16  Alan Modra  <amodra@gmail.com>
1568
1569         * Makefile.am: Remove sh5 and sh64 support.
1570         * configure.ac: Likewise.
1571         * disassemble.c: Likewise.
1572         * disassemble.h: Likewise.
1573         * sh-dis.c: Likewise.
1574         * sh64-dis.c: Delete.
1575         * sh64-opc.c: Delete.
1576         * sh64-opc.h: Delete.
1577         * Makefile.in: Regenerate.
1578         * configure: Regenerate.
1579         * po/POTFILES.in: Regenerate.
1580
1581 2018-04-16  Alan Modra  <amodra@gmail.com>
1582
1583         * Makefile.am: Remove w65 support.
1584         * configure.ac: Likewise.
1585         * disassemble.c: Likewise.
1586         * disassemble.h: Likewise.
1587         * w65-dis.c: Delete.
1588         * w65-opc.h: Delete.
1589         * Makefile.in: Regenerate.
1590         * configure: Regenerate.
1591         * po/POTFILES.in: Regenerate.
1592
1593 2018-04-16  Alan Modra  <amodra@gmail.com>
1594
1595         * configure.ac: Remove we32k support.
1596         * configure: Regenerate.
1597
1598 2018-04-16  Alan Modra  <amodra@gmail.com>
1599
1600         * Makefile.am: Remove m88k support.
1601         * configure.ac: Likewise.
1602         * disassemble.c: Likewise.
1603         * disassemble.h: Likewise.
1604         * m88k-dis.c: Delete.
1605         * Makefile.in: Regenerate.
1606         * configure: Regenerate.
1607         * po/POTFILES.in: Regenerate.
1608
1609 2018-04-16  Alan Modra  <amodra@gmail.com>
1610
1611         * Makefile.am: Remove i370 support.
1612         * configure.ac: Likewise.
1613         * disassemble.c: Likewise.
1614         * disassemble.h: Likewise.
1615         * i370-dis.c: Delete.
1616         * i370-opc.c: Delete.
1617         * Makefile.in: Regenerate.
1618         * configure: Regenerate.
1619         * po/POTFILES.in: Regenerate.
1620
1621 2018-04-16  Alan Modra  <amodra@gmail.com>
1622
1623         * Makefile.am: Remove h8500 support.
1624         * configure.ac: Likewise.
1625         * disassemble.c: Likewise.
1626         * disassemble.h: Likewise.
1627         * h8500-dis.c: Delete.
1628         * h8500-opc.h: Delete.
1629         * Makefile.in: Regenerate.
1630         * configure: Regenerate.
1631         * po/POTFILES.in: Regenerate.
1632
1633 2018-04-16  Alan Modra  <amodra@gmail.com>
1634
1635         * configure.ac: Remove tahoe support.
1636         * configure: Regenerate.
1637
1638 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1639
1640         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1641         umwait.
1642         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1643         64-bit mode.
1644         * i386-tbl.h: Regenerated.
1645
1646 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1647
1648         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1649         PREFIX_MOD_1_0FAE_REG_6.
1650         (va_mode): New.
1651         (OP_E_register): Use va_mode.
1652         * i386-dis-evex.h (prefix_table):
1653         New instructions (see prefixes above).
1654         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1655         (cpu_flags): Likewise.
1656         * i386-opc.h (enum): Likewise.
1657         (i386_cpu_flags): Likewise.
1658         * i386-opc.tbl: Add umonitor, umwait, tpause.
1659         * i386-init.h: Regenerate.
1660         * i386-tbl.h: Likewise.
1661
1662 2018-04-11  Alan Modra  <amodra@gmail.com>
1663
1664         * opcodes/i860-dis.c: Delete.
1665         * opcodes/i960-dis.c: Delete.
1666         * Makefile.am: Remove i860 and i960 support.
1667         * configure.ac: Likewise.
1668         * disassemble.c: Likewise.
1669         * disassemble.h: Likewise.
1670         * Makefile.in: Regenerate.
1671         * configure: Regenerate.
1672         * po/POTFILES.in: Regenerate.
1673
1674 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1675
1676         PR binutils/23025
1677         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1678         to 0.
1679         (print_insn): Clear vex instead of vex.evex.
1680
1681 2018-04-04  Nick Clifton  <nickc@redhat.com>
1682
1683         * po/es.po: Updated Spanish translation.
1684
1685 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1686
1687         * i386-gen.c (opcode_modifiers): Delete VecESize.
1688         * i386-opc.h (VecESize): Delete.
1689         (struct i386_opcode_modifier): Delete vecesize.
1690         * i386-opc.tbl: Drop VecESize.
1691         * i386-tlb.h: Re-generate.
1692
1693 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1694
1695         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1696         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1697         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1698         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1699         * i386-tlb.h: Re-generate.
1700
1701 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1702
1703         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1704         Fold AVX512 forms
1705         * i386-tlb.h: Re-generate.
1706
1707 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1708
1709         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1710         (vex_len_table): Drop Y for vcvt*2si.
1711         (putop): Replace plain 'Y' handling by abort().
1712
1713 2018-03-28  Nick Clifton  <nickc@redhat.com>
1714
1715         PR 22988
1716         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1717         instructions with only a base address register.
1718         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1719         handle AARHC64_OPND_SVE_ADDR_R.
1720         (aarch64_print_operand): Likewise.
1721         * aarch64-asm-2.c: Regenerate.
1722         * aarch64_dis-2.c: Regenerate.
1723         * aarch64-opc-2.c: Regenerate.
1724
1725 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1726
1727         * i386-opc.tbl: Drop VecESize from register only insn forms and
1728         memory forms not allowing broadcast.
1729         * i386-tlb.h: Re-generate.
1730
1731 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1732
1733         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1734         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1735         sha256*): Drop Disp<N>.
1736
1737 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1738
1739         * i386-dis.c (EbndS, bnd_swap_mode): New.
1740         (prefix_table): Use EbndS.
1741         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1742         * i386-opc.tbl (bndmov): Move misplaced Load.
1743         * i386-tlb.h: Re-generate.
1744
1745 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1746
1747         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1748         templates allowing memory operands and folded ones for register
1749         only flavors.
1750         * i386-tlb.h: Re-generate.
1751
1752 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1753
1754         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1755         256-bit templates. Drop redundant leftover Disp<N>.
1756         * i386-tlb.h: Re-generate.
1757
1758 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1759
1760         * riscv-opc.c (riscv_insn_types): New.
1761
1762 2018-03-13  Nick Clifton  <nickc@redhat.com>
1763
1764         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1765
1766 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1767
1768         * i386-opc.tbl: Add Optimize to clr.
1769         * i386-tbl.h: Regenerated.
1770
1771 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1772
1773         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1774         * i386-opc.h (OldGcc): Removed.
1775         (i386_opcode_modifier): Remove oldgcc.
1776         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1777         instructions for old (<= 2.8.1) versions of gcc.
1778         * i386-tbl.h: Regenerated.
1779
1780 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1781
1782         * i386-opc.h (EVEXDYN): New.
1783         * i386-opc.tbl: Fold various AVX512VL templates.
1784         * i386-tlb.h: Re-generate.
1785
1786 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1787
1788         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1789         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1790         vpexpandd, vpexpandq): Fold AFX512VF templates.
1791         * i386-tlb.h: Re-generate.
1792
1793 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1794
1795         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1796         Fold 128- and 256-bit VEX-encoded templates.
1797         * i386-tlb.h: Re-generate.
1798
1799 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1800
1801         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1802         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1803         vpexpandd, vpexpandq): Fold AVX512F templates.
1804         * i386-tlb.h: Re-generate.
1805
1806 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1807
1808         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1809         64-bit templates. Drop Disp<N>.
1810         * i386-tlb.h: Re-generate.
1811
1812 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1813
1814         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1815         and 256-bit templates.
1816         * i386-tlb.h: Re-generate.
1817
1818 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1819
1820         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1821         * i386-tlb.h: Re-generate.
1822
1823 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1824
1825         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1826         Drop NoAVX.
1827         * i386-tlb.h: Re-generate.
1828
1829 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1830
1831         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1832         * i386-tlb.h: Re-generate.
1833
1834 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1835
1836         * i386-gen.c (opcode_modifiers): Delete FloatD.
1837         * i386-opc.h (FloatD): Delete.
1838         (struct i386_opcode_modifier): Delete floatd.
1839         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1840         FloatD by D.
1841         * i386-tlb.h: Re-generate.
1842
1843 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1844
1845         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1846
1847 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1848
1849         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1850         * i386-tlb.h: Re-generate.
1851
1852 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1853
1854         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1855         forms.
1856         * i386-tlb.h: Re-generate.
1857
1858 2018-03-07  Alan Modra  <amodra@gmail.com>
1859
1860         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1861         bfd_arch_rs6000.
1862         * disassemble.h (print_insn_rs6000): Delete.
1863         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1864         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1865         (print_insn_rs6000): Delete.
1866
1867 2018-03-03  Alan Modra  <amodra@gmail.com>
1868
1869         * sysdep.h (opcodes_error_handler): Define.
1870         (_bfd_error_handler): Declare.
1871         * Makefile.am: Remove stray #.
1872         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1873         EDIT" comment.
1874         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1875         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1876         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1877         opcodes_error_handler to print errors.  Standardize error messages.
1878         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1879         and include opintl.h.
1880         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1881         * i386-gen.c: Standardize error messages.
1882         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1883         * Makefile.in: Regenerate.
1884         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1885         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1886         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1887         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1888         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1889         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1890         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1891         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1892         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1893         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1894         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1895         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1896         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1897
1898 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1899
1900         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1901         vpsub[bwdq] instructions.
1902         * i386-tbl.h: Regenerated.
1903
1904 2018-03-01  Alan Modra  <amodra@gmail.com>
1905
1906         * configure.ac (ALL_LINGUAS): Sort.
1907         * configure: Regenerate.
1908
1909 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1910
1911         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1912         macro by assignements.
1913
1914 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1915
1916         PR gas/22871
1917         * i386-gen.c (opcode_modifiers): Add Optimize.
1918         * i386-opc.h (Optimize): New enum.
1919         (i386_opcode_modifier): Add optimize.
1920         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1921         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1922         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1923         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1924         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1925         vpxord and vpxorq.
1926         * i386-tbl.h: Regenerated.
1927
1928 2018-02-26  Alan Modra  <amodra@gmail.com>
1929
1930         * crx-dis.c (getregliststring): Allocate a large enough buffer
1931         to silence false positive gcc8 warning.
1932
1933 2018-02-22  Shea Levy <shea@shealevy.com>
1934
1935         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1936
1937 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1938
1939         * i386-opc.tbl: Add {rex},
1940         * i386-tbl.h: Regenerated.
1941
1942 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1943
1944         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1945         (mips16_opcodes): Replace `M' with `m' for "restore".
1946
1947 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1948
1949         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1950
1951 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1952
1953         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1954         variable to `function_index'.
1955
1956 2018-02-13  Nick Clifton  <nickc@redhat.com>
1957
1958         PR 22823
1959         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1960         about truncation of printing.
1961
1962 2018-02-12  Henry Wong <henry@stuffedcow.net>
1963
1964         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1965
1966 2018-02-05  Nick Clifton  <nickc@redhat.com>
1967
1968         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1969
1970 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1971
1972         * i386-dis.c (enum): Add pconfig.
1973         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1974         (cpu_flags): Add CpuPCONFIG.
1975         * i386-opc.h (enum): Add CpuPCONFIG.
1976         (i386_cpu_flags): Add cpupconfig.
1977         * i386-opc.tbl: Add PCONFIG instruction.
1978         * i386-init.h: Regenerate.
1979         * i386-tbl.h: Likewise.
1980
1981 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1982
1983         * i386-dis.c (enum): Add PREFIX_0F09.
1984         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1985         (cpu_flags): Add CpuWBNOINVD.
1986         * i386-opc.h (enum): Add CpuWBNOINVD.
1987         (i386_cpu_flags): Add cpuwbnoinvd.
1988         * i386-opc.tbl: Add WBNOINVD instruction.
1989         * i386-init.h: Regenerate.
1990         * i386-tbl.h: Likewise.
1991
1992 2018-01-17  Jim Wilson  <jimw@sifive.com>
1993
1994         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1995
1996 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1997
1998         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1999         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2000         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2001         (cpu_flags): Add CpuIBT, CpuSHSTK.
2002         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2003         (i386_cpu_flags): Add cpuibt, cpushstk.
2004         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2005         * i386-init.h: Regenerate.
2006         * i386-tbl.h: Likewise.
2007
2008 2018-01-16  Nick Clifton  <nickc@redhat.com>
2009
2010         * po/pt_BR.po: Updated Brazilian Portugese translation.
2011         * po/de.po: Updated German translation.
2012
2013 2018-01-15  Jim Wilson  <jimw@sifive.com>
2014
2015         * riscv-opc.c (match_c_nop): New.
2016         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2017
2018 2018-01-15  Nick Clifton  <nickc@redhat.com>
2019
2020         * po/uk.po: Updated Ukranian translation.
2021
2022 2018-01-13  Nick Clifton  <nickc@redhat.com>
2023
2024         * po/opcodes.pot: Regenerated.
2025
2026 2018-01-13  Nick Clifton  <nickc@redhat.com>
2027
2028         * configure: Regenerate.
2029
2030 2018-01-13  Nick Clifton  <nickc@redhat.com>
2031
2032         2.30 branch created.
2033
2034 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2035
2036         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2037         * i386-tbl.h: Regenerate.
2038
2039 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2040
2041         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2042         * i386-tbl.h: Re-generate.
2043
2044 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2045
2046         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2047         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2048         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2049         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2050         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2051         Disp8MemShift of AVX512VL forms.
2052         * i386-tbl.h: Re-generate.
2053
2054 2018-01-09  Jim Wilson  <jimw@sifive.com>
2055
2056         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2057         then the hi_addr value is zero.
2058
2059 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2060
2061         * arm-dis.c (arm_opcodes): Add csdb.
2062         (thumb32_opcodes): Add csdb.
2063
2064 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2065
2066         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2067         * aarch64-asm-2.c: Regenerate.
2068         * aarch64-dis-2.c: Regenerate.
2069         * aarch64-opc-2.c: Regenerate.
2070
2071 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2072
2073         PR gas/22681
2074         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2075         Remove AVX512 vmovd with 64-bit operands.
2076         * i386-tbl.h: Regenerated.
2077
2078 2018-01-05  Jim Wilson  <jimw@sifive.com>
2079
2080         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2081         jalr.
2082
2083 2018-01-03  Alan Modra  <amodra@gmail.com>
2084
2085         Update year range in copyright notice of all files.
2086
2087 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2088
2089         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2090         and OPERAND_TYPE_REGZMM entries.
2091
2092 For older changes see ChangeLog-2017
2093 \f
2094 Copyright (C) 2018 Free Software Foundation, Inc.
2095
2096 Copying and distribution of this file, with or without modification,
2097 are permitted in any medium without royalty provided the copyright
2098 notice and this notice are preserved.
2099
2100 Local Variables:
2101 mode: change-log
2102 left-margin: 8
2103 fill-column: 74
2104 version-control: never
2105 End: