opcodes/ChangeLog

   1 2019-10-22  Nick Clifton  <nickc@redhat.com>
   2
   3         * rx-dis.c (get_size_name): New function.  Provides safe
   4         access to name array.
   5         (get_opsize_name): Likewise.
   6         (print_insn_rx): Use the accessor functions.
   7
   8 2019-10-16  Nick Clifton  <nickc@redhat.com>
   9
  10         * rx-dis.c (get_register_name): New function.  Provides safe
  11         access to name array.
  12         (get_condition_name, get_flag_name, get_double_register_name)
  13         (get_double_register_high_name, get_double_register_low_name)
  14         (get_double_control_register_name, get_double_condition_name):
  15         Likewise.
  16         (print_insn_rx): Use the accessor functions.
  17
  18 2019-10-09  Nick Clifton  <nickc@redhat.com>
  19
  20         PR 25041
  21         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
  22         instructions.
  23
  24 2019-10-07  Jan Beulich  <jbeulich@suse.com>
  25
  26         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
  27         (cmpsd): Likewise. Move EsSeg to other operand.
  28         * opcodes/i386-tbl.h: Re-generate.
  29
  30 2019-09-23  Alan Modra  <amodra@gmail.com>
  31
  32         * m68k-dis.c: Include cpu-m68k.h
  33
  34 2019-09-23  Alan Modra  <amodra@gmail.com>
  35
  36         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
  37         "elf/mips.h" earlier.
  38
  39 2018-09-20  Jan Beulich  <jbeulich@suse.com>
  40
  41         PR gas/25012
  42         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
  43         with SReg operand.
  44         * i386-tbl.h: Re-generate.
  45
  46 2019-09-18  Alan Modra  <amodra@gmail.com>
  47
  48         * arc-ext.c: Update throughout for bfd section macro changes.
  49
  50 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
  51
  52         * Makefile.in: Re-generate.
  53         * configure: Re-generate.
  54
  55 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
  56
  57         * riscv-opc.c (riscv_opcodes): Change subset field
  58         to insn_class field for all instructions.
  59         (riscv_insn_types): Likewise.
  60
  61 2019-09-16  Phil Blundell  <pb@pbcl.net>
  62
  63         * configure: Regenerated.
  64
  65 2019-09-10  Miod Vallat  <miod@online.fr>
  66
  67         PR 24982
  68         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
  69
  70 2019-09-09  Phil Blundell  <pb@pbcl.net>
  71
  72         binutils 2.33 branch created.
  73
  74 2019-09-03  Nick Clifton  <nickc@redhat.com>
  75
  76         PR 24961
  77         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
  78         greater than zero before indexing via (bufcnt -1).
  79
  80 2019-09-03  Nick Clifton  <nickc@redhat.com>
  81
  82         PR 24958
  83         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
  84         (MAX_SPEC_REG_NAME_LEN): Define.
  85         (struct mmix_dis_info): Use defined constants for array lengths.
  86         (get_reg_name): New function.
  87         (get_sprec_reg_name): New function.
  88         (print_insn_mmix): Use new functions.
  89
  90 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  91
  92         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
  93         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
  94         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
  95
  96 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
  97
  98         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
  99         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 100         (aarch64_sys_reg_supported_p): Update checks for the above.
 101
 102 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 103
 104         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 105         cases MVE_SQRSHRL and MVE_UQRSHLL.
 106         (print_insn_mve): Add case for specifier 'k' to check
 107         specific bit of the instruction.
 108
 109 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 110
 111         PR 24854
 112         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 113         encountering an unknown machine type.
 114         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 115         cases return -1 rather than calling abort.
 116
 117 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 120         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 121         IgnoreSize.
 122         * i386-tbl.h: Re-generate.
 123
 124 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 125
 126         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 127         instructions.
 128
 129 2019-07-30  Mel Chen <mel.chen@sifive.com>
 130
 131         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 132         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 133
 134         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 135         fscsr.
 136
 137 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 138
 139         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 140         and MPY class instructions.
 141         (parse_option): Add nps400 option.
 142         (print_arc_disassembler_options): Add nps400 info.
 143
 144 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 145
 146         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 147         (bspop): Likewise.
 148         (modapp): Likewise.
 149         * arc-opc.c (RAD_CHK): Add.
 150         * arc-tbl.h: Regenerate.
 151
 152 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 153
 154         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 155         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 156
 157 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 158
 159         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 160         instructions as UNPREDICTABLE.
 161
 162 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 163
 164         * bpf-desc.c: Regenerated.
 165
 166 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-gen.c (static_assert): Define.
 169         (main): Use it.
 170         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 171         (Opcode_Modifier_Num): ... this.
 172         (Mem): Delete.
 173
 174 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-gen.c (operand_types): Move RegMem ...
 177         (opcode_modifiers): ... here.
 178         * i386-opc.h (RegMem): Move to opcode modifer enum.
 179         (union i386_operand_type): Move regmem field ...
 180         (struct i386_opcode_modifier): ... here.
 181         * i386-opc.tbl (RegMem): Define.
 182         (mov, movq): Move RegMem on segment, control, debug, and test
 183         register flavors.
 184         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 185         to non-SSE2AVX flavor.
 186         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 187         Move RegMem on register only flavors. Drop IgnoreSize from
 188         legacy encoding flavors.
 189         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 190         flavors.
 191         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 192         register only flavors.
 193         (vmovd): Move RegMem and drop IgnoreSize on register only
 194         flavor. Change opcode and operand order to store form.
 195         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 196
 197 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 200         entries.
 201         * i386-opc.h (SReg2, SReg3): Replace by ...
 202         (SReg): ... this.
 203         (union i386_operand_type): Replace sreg fields.
 204         * i386-opc.tbl (mov, ): Use SReg.
 205         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 206         register flavors.
 207         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 208         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 209
 210 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 211
 212         * bpf-desc.c: Regenerate.
 213         * bpf-opc.c: Likewise.
 214         * bpf-opc.h: Likewise.
 215
 216 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 217
 218         * bpf-desc.c: Regenerate.
 219         * bpf-opc.c: Likewise.
 220
 221 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 222
 223         * arm-dis.c (print_insn_coprocessor): Rename index to
 224         index_operand.
 225
 226 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 227
 228         * riscv-opc.c (riscv_insn_types): Add r4 type.
 229
 230         * riscv-opc.c (riscv_insn_types): Add b and j type.
 231
 232         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 233         format for sb type and correct s type.
 234
 235 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 236
 237         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 238         SVE FMOV alias of FCPY.
 239
 240 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 241
 242         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 243         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 244
 245 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 246
 247         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 248         registers in an instruction prefixed by MOVPRFX.
 249
 250 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 251
 252         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 253         sve_size_13 icode to account for variant behaviour of
 254         pmull{t,b}.
 255         * aarch64-dis-2.c: Regenerate.
 256         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 257         sve_size_13 icode to account for variant behaviour of
 258         pmull{t,b}.
 259         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 260         (OP_SVE_VVV_Q_D): Add new qualifier.
 261         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 262         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 263         AES and those not.
 264
 265 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 266
 267         * opcodes/i386-gen.c (operand_type_init): Remove
 268         OPERAND_TYPE_VEC_IMM4 entry.
 269         (operand_types): Remove Vec_Imm4.
 270         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 271         (union i386_operand_type): Remove vec_imm4.
 272         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 273         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 274
 275 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 276
 277         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 278         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 279         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 280         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 281         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 282         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 283         * i386-tbl.h: Re-generate.
 284
 285 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 288         register operands.
 289         * i386-tbl.h: Re-generate.
 290
 291 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 292
 293         * i386-opc.tbl (C): New.
 294         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 295         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 296         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 297         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 298         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 299         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 300         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 301         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 302         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 303         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 304         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 305         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 306         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 307         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 308         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 309         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 310         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 311         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 312         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 313         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 314         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 315         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 316         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 317         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 318         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 319         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 320         flavors.
 321         * i386-tbl.h: Re-generate.
 322
 323 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 324
 325         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 326         register operands.
 327         * i386-tbl.h: Re-generate.
 328
 329 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 330
 331         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 332         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 333         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 334         * i386-tbl.h: Re-generate.
 335
 336 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 339         Disp8MemShift from register only templates.
 340         * i386-tbl.h: Re-generate.
 341
 342 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 343
 344         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 345         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 346         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 347         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 348         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 349         EVEX_W_0F11_P_3_M_1): Delete.
 350         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 351         EVEX_W_0F11_P_3): New.
 352         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 353         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 354         MOD_EVEX_0F11_PREFIX_3 table entries.
 355         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 356         PREFIX_EVEX_0F11 table entries.
 357         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 358         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 359         EVEX_W_0F11_P_3_M_{0,1} table entries.
 360
 361 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 362
 363         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 364         Delete.
 365
 366 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 367
 368         PR binutils/24719
 369         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 370         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 371         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 372         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 373         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 374         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 375         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 376         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 377         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 378         PREFIX_EVEX_0F38C6_REG_6 entries.
 379         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 380         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 381         EVEX_W_0F38C7_R_6_P_2 entries.
 382         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 383         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 384         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 385         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 386         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 387         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 388         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 389
 390 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 393         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 394         VEX_LEN_0F2D_P_3): Delete.
 395         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 396         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 397         (prefix_table): ... here.
 398
 399 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 400
 401         * i386-dis.c (Iq): Delete.
 402         (Id): New.
 403         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 404         TBM insns.
 405         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 406         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 407         (OP_E_memory): Also honor needindex when deciding whether an
 408         address size prefix needs printing.
 409         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 410
 411 2019-06-26  Jim Wilson  <jimw@sifive.com>
 412
 413         PR binutils/24739
 414         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 415         Set info->display_endian to info->endian_code.
 416
 417 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 418
 419         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 420         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 421         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 422         OPERAND_TYPE_ACC64 entries.
 423         * i386-init.h: Re-generate.
 424
 425 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 426
 427         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 428         Delete.
 429         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 430         of dqa_mode.
 431         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 432         entries here.
 433         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 434         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 435
 436 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 437
 438         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 439         variables.
 440
 441 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 442
 443         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 444         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 445         movnti.
 446         * i386-opc.tbl (movnti): Add IgnoreSize.
 447         * i386-tbl.h: Re-generate.
 448
 449 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 450
 451         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 452         * i386-tbl.h: Re-generate.
 453
 454 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 455
 456         * i386-dis-evex.h: Break into ...
 457         * i386-dis-evex-len.h: New file.
 458         * i386-dis-evex-mod.h: Likewise.
 459         * i386-dis-evex-prefix.h: Likewise.
 460         * i386-dis-evex-reg.h: Likewise.
 461         * i386-dis-evex-w.h: Likewise.
 462         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 463         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 464         i386-dis-evex-mod.h.
 465
 466 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 467
 468         PR binutils/24700
 469         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 470         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 471         EVEX_W_0F385B_P_2.
 472         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 473         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 474         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 475         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 476         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 477         EVEX_LEN_0F385B_P_2_W_1.
 478         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 479         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 480         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 481         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 482         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 483         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 484         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 485         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 486         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 487         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 488
 489 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 490
 491         PR binutils/24691
 492         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 493         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 494         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 495         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 496         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 497         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 498         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 499         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 500         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 501         EVEX_LEN_0F3A43_P_2_W_1.
 502         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 503         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 504         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 505         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 506         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 507         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 508         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 509         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 510         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 511         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 512         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 513         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 514
 515 2019-06-14  Nick Clifton  <nickc@redhat.com>
 516
 517         * po/fr.po; Updated French translation.
 518
 519 2019-06-13  Stafford Horne  <shorne@gmail.com>
 520
 521         * or1k-asm.c: Regenerated.
 522         * or1k-desc.c: Regenerated.
 523         * or1k-desc.h: Regenerated.
 524         * or1k-dis.c: Regenerated.
 525         * or1k-ibld.c: Regenerated.
 526         * or1k-opc.c: Regenerated.
 527         * or1k-opc.h: Regenerated.
 528         * or1k-opinst.c: Regenerated.
 529
 530 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 531
 532         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 533
 534 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 535
 536         PR binutils/24633
 537         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 538         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 539         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 540         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 541         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 542         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 543         EVEX_LEN_0F3A1B_P_2_W_1.
 544         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 545         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 546         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 547         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 548         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 549         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 550         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 551         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 552
 553 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 554
 555         PR binutils/24626
 556         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 557         EVEX.vvvv when disassembling VEX and EVEX instructions.
 558         (OP_VEX): Set vex.register_specifier to 0 after readding
 559         vex.register_specifier.
 560         (OP_Vex_2src_1): Likewise.
 561         (OP_Vex_2src_2): Likewise.
 562         (OP_LWP_E): Likewise.
 563         (OP_EX_Vex): Don't check vex.register_specifier.
 564         (OP_XMM_Vex): Likewise.
 565
 566 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 567             Lili Cui  <lili.cui@intel.com>
 568
 569         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 570         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 571         instructions.
 572         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 573         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 574         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 575         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 576         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 577         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 578         * i386-init.h: Regenerated.
 579         * i386-tbl.h: Likewise.
 580
 581 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 582             Lili Cui  <lili.cui@intel.com>
 583
 584         * doc/c-i386.texi: Document enqcmd.
 585         * testsuite/gas/i386/enqcmd-intel.d: New file.
 586         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 587         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 588         * testsuite/gas/i386/enqcmd.d: Likewise.
 589         * testsuite/gas/i386/enqcmd.s: Likewise.
 590         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 591         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 592         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 593         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 594         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 595         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 596         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 597         and x86-64-enqcmd.
 598
 599 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 600
 601         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 602
 603 2019-06-03  Alan Modra  <amodra@gmail.com>
 604
 605         * ppc-dis.c (prefix_opcd_indices): Correct size.
 606
 607 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 608
 609         PR gas/24625
 610         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 611         Disp8ShiftVL.
 612         * i386-tbl.h: Regenerated.
 613
 614 2019-05-24  Alan Modra  <amodra@gmail.com>
 615
 616         * po/POTFILES.in: Regenerate.
 617
 618 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 619             Alan Modra  <amodra@gmail.com>
 620
 621         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 622         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 623         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 624         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 625         XTOP>): Define and add entries.
 626         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 627         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 628         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 629         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 630
 631 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 632             Alan Modra  <amodra@gmail.com>
 633
 634         * ppc-dis.c (ppc_opts): Add "future" entry.
 635         (PREFIX_OPCD_SEGS): Define.
 636         (prefix_opcd_indices): New array.
 637         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 638         (lookup_prefix): New function.
 639         (print_insn_powerpc): Handle 64-bit prefix instructions.
 640         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 641         (PMRR, POWERXX): Define.
 642         (prefix_opcodes): New instruction table.
 643         (prefix_num_opcodes): New constant.
 644
 645 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 646
 647         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 648         * configure: Regenerated.
 649         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 650         and cpu/bpf.opc.
 651         (HFILES): Add bpf-desc.h and bpf-opc.h.
 652         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 653         bpf-ibld.c and bpf-opc.c.
 654         (BPF_DEPS): Define.
 655         * Makefile.in: Regenerated.
 656         * disassemble.c (ARCH_bpf): Define.
 657         (disassembler): Add case for bfd_arch_bpf.
 658         (disassemble_init_for_target): Likewise.
 659         (enum epbf_isa_attr): Define.
 660         * disassemble.h: extern print_insn_bpf.
 661         * bpf-asm.c: Generated.
 662         * bpf-opc.h: Likewise.
 663         * bpf-opc.c: Likewise.
 664         * bpf-ibld.c: Likewise.
 665         * bpf-dis.c: Likewise.
 666         * bpf-desc.h: Likewise.
 667         * bpf-desc.c: Likewise.
 668
 669 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 670
 671         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 672         and VMSR with the new operands.
 673
 674 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 675
 676         * arm-dis.c (enum mve_instructions): New enum
 677         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 678         and cneg.
 679         (mve_opcodes): New instructions as above.
 680         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 681         csneg and csel.
 682         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 683
 684 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 685
 686         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 687         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 688         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 689         uqshl, urshrl and urshr.
 690         (is_mve_okay_in_it): Add new instructions to TRUE list.
 691         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 692         (print_insn_mve): Updated to accept new %j,
 693         %<bitfield>m and %<bitfield>n patterns.
 694
 695 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 696
 697         * mips-opc.c (mips_builtin_opcodes): Change source register
 698         constraint for DAUI.
 699
 700 2019-05-20  Nick Clifton  <nickc@redhat.com>
 701
 702         * po/fr.po: Updated French translation.
 703
 704 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 705             Michael Collison <michael.collison@arm.com>
 706
 707         * arm-dis.c (thumb32_opcodes): Add new instructions.
 708         (enum mve_instructions): Likewise.
 709         (enum mve_undefined): Add new reasons.
 710         (is_mve_encoding_conflict): Handle new instructions.
 711         (is_mve_undefined): Likewise.
 712         (is_mve_unpredictable): Likewise.
 713         (print_mve_undefined): Likewise.
 714         (print_mve_size): Likewise.
 715
 716 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 717             Michael Collison <michael.collison@arm.com>
 718
 719         * arm-dis.c (thumb32_opcodes): Add new instructions.
 720         (enum mve_instructions): Likewise.
 721         (is_mve_encoding_conflict): Handle new instructions.
 722         (is_mve_undefined): Likewise.
 723         (is_mve_unpredictable): Likewise.
 724         (print_mve_size): Likewise.
 725
 726 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 727             Michael Collison <michael.collison@arm.com>
 728
 729         * arm-dis.c (thumb32_opcodes): Add new instructions.
 730         (enum mve_instructions): Likewise.
 731         (is_mve_encoding_conflict): Likewise.
 732         (is_mve_unpredictable): Likewise.
 733         (print_mve_size): Likewise.
 734
 735 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 736             Michael Collison <michael.collison@arm.com>
 737
 738         * arm-dis.c (thumb32_opcodes): Add new instructions.
 739         (enum mve_instructions): Likewise.
 740         (is_mve_encoding_conflict): Handle new instructions.
 741         (is_mve_undefined): Likewise.
 742         (is_mve_unpredictable): Likewise.
 743         (print_mve_size): Likewise.
 744
 745 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 746             Michael Collison <michael.collison@arm.com>
 747
 748         * arm-dis.c (thumb32_opcodes): Add new instructions.
 749         (enum mve_instructions): Likewise.
 750         (is_mve_encoding_conflict): Handle new instructions.
 751         (is_mve_undefined): Likewise.
 752         (is_mve_unpredictable): Likewise.
 753         (print_mve_size): Likewise.
 754         (print_insn_mve): Likewise.
 755
 756 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 757             Michael Collison <michael.collison@arm.com>
 758
 759         * arm-dis.c (thumb32_opcodes): Add new instructions.
 760         (print_insn_thumb32): Handle new instructions.
 761
 762 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 763             Michael Collison <michael.collison@arm.com>
 764
 765         * arm-dis.c (enum mve_instructions): Add new instructions.
 766         (enum mve_undefined): Add new reasons.
 767         (is_mve_encoding_conflict): Handle new instructions.
 768         (is_mve_undefined): Likewise.
 769         (is_mve_unpredictable): Likewise.
 770         (print_mve_undefined): Likewise.
 771         (print_mve_size): Likewise.
 772         (print_mve_shift_n): Likewise.
 773         (print_insn_mve): Likewise.
 774
 775 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 776             Michael Collison <michael.collison@arm.com>
 777
 778         * arm-dis.c (enum mve_instructions): Add new instructions.
 779         (is_mve_encoding_conflict): Handle new instructions.
 780         (is_mve_unpredictable): Likewise.
 781         (print_mve_rotate): Likewise.
 782         (print_mve_size): Likewise.
 783         (print_insn_mve): Likewise.
 784
 785 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 786             Michael Collison <michael.collison@arm.com>
 787
 788         * arm-dis.c (enum mve_instructions): Add new instructions.
 789         (is_mve_encoding_conflict): Handle new instructions.
 790         (is_mve_unpredictable): Likewise.
 791         (print_mve_size): Likewise.
 792         (print_insn_mve): Likewise.
 793
 794 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 795             Michael Collison <michael.collison@arm.com>
 796
 797         * arm-dis.c (enum mve_instructions): Add new instructions.
 798         (enum mve_undefined): Add new reasons.
 799         (is_mve_encoding_conflict): Handle new instructions.
 800         (is_mve_undefined): Likewise.
 801         (is_mve_unpredictable): Likewise.
 802         (print_mve_undefined): Likewise.
 803         (print_mve_size): Likewise.
 804         (print_insn_mve): Likewise.
 805
 806 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 807             Michael Collison <michael.collison@arm.com>
 808
 809         * arm-dis.c (enum mve_instructions): Add new instructions.
 810         (is_mve_encoding_conflict): Handle new instructions.
 811         (is_mve_undefined): Likewise.
 812         (is_mve_unpredictable): Likewise.
 813         (print_mve_size): Likewise.
 814         (print_insn_mve): Likewise.
 815
 816 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 817             Michael Collison <michael.collison@arm.com>
 818
 819         * arm-dis.c (enum mve_instructions): Add new instructions.
 820         (enum mve_unpredictable): Add new reasons.
 821         (enum mve_undefined): Likewise.
 822         (is_mve_okay_in_it): Handle new isntructions.
 823         (is_mve_encoding_conflict): Likewise.
 824         (is_mve_undefined): Likewise.
 825         (is_mve_unpredictable): Likewise.
 826         (print_mve_vmov_index): Likewise.
 827         (print_simd_imm8): Likewise.
 828         (print_mve_undefined): Likewise.
 829         (print_mve_unpredictable): Likewise.
 830         (print_mve_size): Likewise.
 831         (print_insn_mve): Likewise.
 832
 833 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 834             Michael Collison <michael.collison@arm.com>
 835
 836         * arm-dis.c (enum mve_instructions): Add new instructions.
 837         (enum mve_unpredictable): Add new reasons.
 838         (enum mve_undefined): Likewise.
 839         (is_mve_encoding_conflict): Handle new instructions.
 840         (is_mve_undefined): Likewise.
 841         (is_mve_unpredictable): Likewise.
 842         (print_mve_undefined): Likewise.
 843         (print_mve_unpredictable): Likewise.
 844         (print_mve_rounding_mode): Likewise.
 845         (print_mve_vcvt_size): Likewise.
 846         (print_mve_size): Likewise.
 847         (print_insn_mve): Likewise.
 848
 849 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 850             Michael Collison <michael.collison@arm.com>
 851
 852         * arm-dis.c (enum mve_instructions): Add new instructions.
 853         (enum mve_unpredictable): Add new reasons.
 854         (enum mve_undefined): Likewise.
 855         (is_mve_undefined): Handle new instructions.
 856         (is_mve_unpredictable): Likewise.
 857         (print_mve_undefined): Likewise.
 858         (print_mve_unpredictable): Likewise.
 859         (print_mve_size): Likewise.
 860         (print_insn_mve): Likewise.
 861
 862 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 863             Michael Collison <michael.collison@arm.com>
 864
 865         * arm-dis.c (enum mve_instructions): Add new instructions.
 866         (enum mve_undefined): Add new reasons.
 867         (insns): Add new instructions.
 868         (is_mve_encoding_conflict):
 869         (print_mve_vld_str_addr): New print function.
 870         (is_mve_undefined): Handle new instructions.
 871         (is_mve_unpredictable): Likewise.
 872         (print_mve_undefined): Likewise.
 873         (print_mve_size): Likewise.
 874         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 875         (print_insn_mve):  Handle new operands.
 876
 877 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 878             Michael Collison <michael.collison@arm.com>
 879
 880         * arm-dis.c (enum mve_instructions): Add new instructions.
 881         (enum mve_unpredictable): Add new reasons.
 882         (is_mve_encoding_conflict): Handle new instructions.
 883         (is_mve_unpredictable): Likewise.
 884         (mve_opcodes): Add new instructions.
 885         (print_mve_unpredictable): Handle new reasons.
 886         (print_mve_register_blocks): New print function.
 887         (print_mve_size): Handle new instructions.
 888         (print_insn_mve): Likewise.
 889
 890 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 891             Michael Collison <michael.collison@arm.com>
 892
 893         * arm-dis.c (enum mve_instructions): Add new instructions.
 894         (enum mve_unpredictable): Add new reasons.
 895         (enum mve_undefined): Likewise.
 896         (is_mve_encoding_conflict): Handle new instructions.
 897         (is_mve_undefined): Likewise.
 898         (is_mve_unpredictable): Likewise.
 899         (coprocessor_opcodes): Move NEON VDUP from here...
 900         (neon_opcodes): ... to here.
 901         (mve_opcodes): Add new instructions.
 902         (print_mve_undefined):  Handle new reasons.
 903         (print_mve_unpredictable): Likewise.
 904         (print_mve_size): Handle new instructions.
 905         (print_insn_neon): Handle vdup.
 906         (print_insn_mve): Handle new operands.
 907
 908 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 909             Michael Collison <michael.collison@arm.com>
 910
 911         * arm-dis.c (enum mve_instructions): Add new instructions.
 912         (enum mve_unpredictable): Add new values.
 913         (mve_opcodes): Add new instructions.
 914         (vec_condnames): New array with vector conditions.
 915         (mve_predicatenames): New array with predicate suffixes.
 916         (mve_vec_sizename): New array with vector sizes.
 917         (enum vpt_pred_state): New enum with vector predication states.
 918         (struct vpt_block): New struct type for vpt blocks.
 919         (vpt_block_state): Global struct to keep track of state.
 920         (mve_extract_pred_mask): New helper function.
 921         (num_instructions_vpt_block): Likewise.
 922         (mark_outside_vpt_block): Likewise.
 923         (mark_inside_vpt_block): Likewise.
 924         (invert_next_predicate_state): Likewise.
 925         (update_next_predicate_state): Likewise.
 926         (update_vpt_block_state): Likewise.
 927         (is_vpt_instruction): Likewise.
 928         (is_mve_encoding_conflict): Add entries for new instructions.
 929         (is_mve_unpredictable): Likewise.
 930         (print_mve_unpredictable): Handle new cases.
 931         (print_instruction_predicate): Likewise.
 932         (print_mve_size): New function.
 933         (print_vec_condition): New function.
 934         (print_insn_mve): Handle vpt blocks and new print operands.
 935
 936 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 937
 938         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 939         8, 14 and 15 for Armv8.1-M Mainline.
 940
 941 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 942             Michael Collison <michael.collison@arm.com>
 943
 944         * arm-dis.c (enum mve_instructions): New enum.
 945         (enum mve_unpredictable): Likewise.
 946         (enum mve_undefined): Likewise.
 947         (struct mopcode32): New struct.
 948         (is_mve_okay_in_it): New function.
 949         (is_mve_architecture): Likewise.
 950         (arm_decode_field): Likewise.
 951         (arm_decode_field_multiple): Likewise.
 952         (is_mve_encoding_conflict): Likewise.
 953         (is_mve_undefined): Likewise.
 954         (is_mve_unpredictable): Likewise.
 955         (print_mve_undefined): Likewise.
 956         (print_mve_unpredictable): Likewise.
 957         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 958         (print_insn_mve): New function.
 959         (print_insn_thumb32): Handle MVE architecture.
 960         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 961
 962 2019-05-10  Nick Clifton  <nickc@redhat.com>
 963
 964         PR 24538
 965         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 966         end of the table prematurely.
 967
 968 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 969
 970         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 971         macros for R6.
 972
 973 2019-05-11  Alan Modra  <amodra@gmail.com>
 974
 975         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 976         when -Mraw is in effect.
 977
 978 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 979
 980         * aarch64-dis-2.c: Regenerate.
 981         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 982         (OP_SVE_BBB): New variant set.
 983         (OP_SVE_DDDD): New variant set.
 984         (OP_SVE_HHH): New variant set.
 985         (OP_SVE_HHHU): New variant set.
 986         (OP_SVE_SSS): New variant set.
 987         (OP_SVE_SSSU): New variant set.
 988         (OP_SVE_SHH): New variant set.
 989         (OP_SVE_SBBU): New variant set.
 990         (OP_SVE_DSS): New variant set.
 991         (OP_SVE_DHHU): New variant set.
 992         (OP_SVE_VMV_HSD_BHS): New variant set.
 993         (OP_SVE_VVU_HSD_BHS): New variant set.
 994         (OP_SVE_VVVU_SD_BH): New variant set.
 995         (OP_SVE_VVVU_BHSD): New variant set.
 996         (OP_SVE_VVV_QHD_DBS): New variant set.
 997         (OP_SVE_VVV_HSD_BHS): New variant set.
 998         (OP_SVE_VVV_HSD_BHS2): New variant set.
 999         (OP_SVE_VVV_BHS_HSD): New variant set.
1000         (OP_SVE_VV_BHS_HSD): New variant set.
1001         (OP_SVE_VVV_SD): New variant set.
1002         (OP_SVE_VVU_BHS_HSD): New variant set.
1003         (OP_SVE_VZVV_SD): New variant set.
1004         (OP_SVE_VZVV_BH): New variant set.
1005         (OP_SVE_VZV_SD): New variant set.
1006         (aarch64_opcode_table): Add sve2 instructions.
1007
1008 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1009
1010         * aarch64-asm-2.c: Regenerated.
1011         * aarch64-dis-2.c: Regenerated.
1012         * aarch64-opc-2.c: Regenerated.
1013         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1014         for SVE_SHLIMM_UNPRED_22.
1015         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1016         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1017         operand.
1018
1019 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1020
1021         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1022         sve_size_tsz_bhs iclass encode.
1023         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1024         sve_size_tsz_bhs iclass decode.
1025
1026 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1027
1028         * aarch64-asm-2.c: Regenerated.
1029         * aarch64-dis-2.c: Regenerated.
1030         * aarch64-opc-2.c: Regenerated.
1031         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1032         for SVE_Zm4_11_INDEX.
1033         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1034         (fields): Handle SVE_i2h field.
1035         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1036         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1037
1038 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1039
1040         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1041         sve_shift_tsz_bhsd iclass encode.
1042         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1043         sve_shift_tsz_bhsd iclass decode.
1044
1045 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1046
1047         * aarch64-asm-2.c: Regenerated.
1048         * aarch64-dis-2.c: Regenerated.
1049         * aarch64-opc-2.c: Regenerated.
1050         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1051         (aarch64_encode_variant_using_iclass): Handle
1052         sve_shift_tsz_hsd iclass encode.
1053         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1054         sve_shift_tsz_hsd iclass decode.
1055         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1056         for SVE_SHRIMM_UNPRED_22.
1057         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1058         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1059         operand.
1060
1061 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1062
1063         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1064         sve_size_013 iclass encode.
1065         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1066         sve_size_013 iclass decode.
1067
1068 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1069
1070         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1071         sve_size_bh iclass encode.
1072         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1073         sve_size_bh iclass decode.
1074
1075 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1076
1077         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1078         sve_size_sd2 iclass encode.
1079         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1080         sve_size_sd2 iclass decode.
1081         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1082         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1083
1084 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1085
1086         * aarch64-asm-2.c: Regenerated.
1087         * aarch64-dis-2.c: Regenerated.
1088         * aarch64-opc-2.c: Regenerated.
1089         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1090         for SVE_ADDR_ZX.
1091         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1092         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1093
1094 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1095
1096         * aarch64-asm-2.c: Regenerated.
1097         * aarch64-dis-2.c: Regenerated.
1098         * aarch64-opc-2.c: Regenerated.
1099         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1100         for SVE_Zm3_11_INDEX.
1101         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1102         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1103         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1104         fields.
1105         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1106
1107 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1108
1109         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1110         sve_size_hsd2 iclass encode.
1111         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1112         sve_size_hsd2 iclass decode.
1113         * aarch64-opc.c (fields): Handle SVE_size field.
1114         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1115
1116 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1117
1118         * aarch64-asm-2.c: Regenerated.
1119         * aarch64-dis-2.c: Regenerated.
1120         * aarch64-opc-2.c: Regenerated.
1121         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1122         for SVE_IMM_ROT3.
1123         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1124         (fields): Handle SVE_rot3 field.
1125         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1126         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1127
1128 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1129
1130         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1131         instructions.
1132
1133 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1134
1135         * aarch64-tbl.h
1136         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1137         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1138         aarch64_feature_sve2bitperm): New feature sets.
1139         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1140         for feature set addresses.
1141         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1142         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1143
1144 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1145             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1146
1147         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1148         argument and set ASE_EVA_R6 appropriately.
1149         (set_default_mips_dis_options): Pass ISA to above.
1150         (parse_mips_dis_option): Likewise.
1151         * mips-opc.c (EVAR6): New macro.
1152         (mips_builtin_opcodes): Add llwpe, scwpe.
1153
1154 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1155
1156         * aarch64-asm-2.c: Regenerated.
1157         * aarch64-dis-2.c: Regenerated.
1158         * aarch64-opc-2.c: Regenerated.
1159         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1160         AARCH64_OPND_TME_UIMM16.
1161         (aarch64_print_operand): Likewise.
1162         * aarch64-tbl.h (QL_IMM_NIL): New.
1163         (TME): New.
1164         (_TME_INSN): New.
1165         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1166
1167 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1168
1169         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1170
1171 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1172             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1173
1174         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1175
1176 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1177
1178         * s12z-opc.h: Add extern "C" bracketing to help
1179         users who wish to use this interface in c++ code.
1180
1181 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1182
1183         * s12z-opc.c (bm_decode): Handle bit map operations with the
1184         "reserved0" mode.
1185
1186 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1187
1188         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1189         specifier.  Add entries for VLDR and VSTR of system registers.
1190         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1191         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1192         of %J and %K format specifier.
1193
1194 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1195
1196         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1197         Add new entries for VSCCLRM instruction.
1198         (print_insn_coprocessor): Handle new %C format control code.
1199
1200 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1201
1202         * arm-dis.c (enum isa): New enum.
1203         (struct sopcode32): New structure.
1204         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1205         set isa field of all current entries to ANY.
1206         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1207         Only match an entry if its isa field allows the current mode.
1208
1209 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1210
1211         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1212         CLRM.
1213         (print_insn_thumb32): Add logic to print %n CLRM register list.
1214
1215 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1216
1217         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1218         and %Q patterns.
1219
1220 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1221
1222         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1223         (print_insn_thumb32): Edit the switch case for %Z.
1224
1225 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1226
1227         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1228
1229 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1230
1231         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1232
1233 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1234
1235         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1236
1237 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1238
1239         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1240         Arm register with r13 and r15 unpredictable.
1241         (thumb32_opcodes): New instructions for bfx and bflx.
1242
1243 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1244
1245         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1246
1247 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1248
1249         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1250
1251 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1252
1253         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1254
1255 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1256
1257         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1258
1259 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1260
1261         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1262         "optr". ("operator" is a reserved word in c++).
1263
1264 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1265
1266         * aarch64-opc.c (aarch64_print_operand): Add case for
1267         AARCH64_OPND_Rt_SP.
1268         (verify_constraints): Likewise.
1269         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1270         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1271         to accept Rt|SP as first operand.
1272         (AARCH64_OPERANDS): Add new Rt_SP.
1273         * aarch64-asm-2.c: Regenerated.
1274         * aarch64-dis-2.c: Regenerated.
1275         * aarch64-opc-2.c: Regenerated.
1276
1277 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1278
1279         * aarch64-asm-2.c: Regenerated.
1280         * aarch64-dis-2.c: Likewise.
1281         * aarch64-opc-2.c: Likewise.
1282         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1283
1284 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1285
1286         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1287
1288 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1289
1290         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1291         * i386-init.h: Regenerated.
1292
1293 2019-04-07  Alan Modra  <amodra@gmail.com>
1294
1295         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1296         op_separator to control printing of spaces, comma and parens
1297         rather than need_comma, need_paren and spaces vars.
1298
1299 2019-04-07  Alan Modra  <amodra@gmail.com>
1300
1301         PR 24421
1302         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1303         (print_insn_neon, print_insn_arm): Likewise.
1304
1305 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1306
1307         * i386-dis-evex.h (evex_table): Updated to support BF16
1308         instructions.
1309         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1310         and EVEX_W_0F3872_P_3.
1311         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1312         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1313         * i386-opc.h (enum): Add CpuAVX512_BF16.
1314         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1315         * i386-opc.tbl: Add AVX512 BF16 instructions.
1316         * i386-init.h: Regenerated.
1317         * i386-tbl.h: Likewise.
1318
1319 2019-04-05  Alan Modra  <amodra@gmail.com>
1320
1321         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1322         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1323         to favour printing of "-" branch hint when using the "y" bit.
1324         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1325
1326 2019-04-05  Alan Modra  <amodra@gmail.com>
1327
1328         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1329         opcode until first operand is output.
1330
1331 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1332
1333         PR gas/24349
1334         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1335         (valid_bo_post_v2): Add support for 'at' branch hints.
1336         (insert_bo): Only error on branch on ctr.
1337         (get_bo_hint_mask): New function.
1338         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1339         for inserting 'at' branch hints.
1340         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1341         for extracting 'at' branch hints.
1342         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1343         (BOE): Delete operand.
1344         (BOM, BOP): New operands.
1345         (RM): Update value.
1346         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1347         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1348         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1349         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1350         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1351         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1352         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1353         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1354         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1355         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1356         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1357         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1358         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1359         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1360         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1361         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1362         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1363         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1364         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1365         bttarl+>: New extended mnemonics.
1366
1367 2019-03-28  Alan Modra  <amodra@gmail.com>
1368
1369         PR 24390
1370         * ppc-opc.c (BTF): Define.
1371         (powerpc_opcodes): Use for mtfsb*.
1372         * ppc-dis.c (print_insn_powerpc): Print fields with both
1373         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1374
1375 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1376
1377         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1378         (mapping_symbol_for_insn): Implement new algorithm.
1379         (print_insn): Remove duplicate code.
1380
1381 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1382
1383         * aarch64-dis.c (print_insn_aarch64):
1384         Implement override.
1385
1386 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1387
1388         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1389         order.
1390
1391 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1392
1393         * aarch64-dis.c (last_stop_offset): New.
1394         (print_insn_aarch64): Use stop_offset.
1395
1396 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1397
1398         PR gas/24359
1399         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1400         CPU_ANY_AVX2_FLAGS.
1401         * i386-init.h: Regenerated.
1402
1403 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1404
1405         PR gas/24348
1406         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1407         vmovdqu16, vmovdqu32 and vmovdqu64.
1408         * i386-tbl.h: Regenerated.
1409
1410 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1411
1412         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1413         from vstrszb, vstrszh, and vstrszf.
1414
1415 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1416
1417         * s390-opc.txt: Add instruction descriptions.
1418
1419 2019-02-08  Jim Wilson  <jimw@sifive.com>
1420
1421         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1422         <bne>: Likewise.
1423
1424 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1425
1426         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1427
1428 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1429
1430         PR binutils/23212
1431         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1432         * aarch64-opc.c (verify_elem_sd): New.
1433         (fields): Add FLD_sz entr.
1434         * aarch64-tbl.h (_SIMD_INSN): New.
1435         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1436         fmulx scalar and vector by element isns.
1437
1438 2019-02-07  Nick Clifton  <nickc@redhat.com>
1439
1440         * po/sv.po: Updated Swedish translation.
1441
1442 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1443
1444         * s390-mkopc.c (main): Accept arch13 as cpu string.
1445         * s390-opc.c: Add new instruction formats and instruction opcode
1446         masks.
1447         * s390-opc.txt: Add new arch13 instructions.
1448
1449 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1450
1451         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1452         (aarch64_opcode): Change encoding for stg, stzg
1453         st2g and st2zg.
1454         * aarch64-asm-2.c: Regenerated.
1455         * aarch64-dis-2.c: Regenerated.
1456         * aarch64-opc-2.c: Regenerated.
1457
1458 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1459
1460         * aarch64-asm-2.c: Regenerated.
1461         * aarch64-dis-2.c: Likewise.
1462         * aarch64-opc-2.c: Likewise.
1463         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1464
1465 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1466             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1467
1468         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1469         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1470         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1471         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1472         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1473         case for ldstgv_indexed.
1474         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1475         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1476         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1477         * aarch64-asm-2.c: Regenerated.
1478         * aarch64-dis-2.c: Regenerated.
1479         * aarch64-opc-2.c: Regenerated.
1480
1481 2019-01-23  Nick Clifton  <nickc@redhat.com>
1482
1483         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1484
1485 2019-01-21  Nick Clifton  <nickc@redhat.com>
1486
1487         * po/de.po: Updated German translation.
1488         * po/uk.po: Updated Ukranian translation.
1489
1490 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1491         * mips-dis.c (mips_arch_choices): Fix typo in
1492         gs464, gs464e and gs264e descriptors.
1493
1494 2019-01-19  Nick Clifton  <nickc@redhat.com>
1495
1496         * configure: Regenerate.
1497         * po/opcodes.pot: Regenerate.
1498
1499 2018-06-24  Nick Clifton  <nickc@redhat.com>
1500
1501         2.32 branch created.
1502
1503 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1504
1505         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1506         if it is null.
1507         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1508         zero.
1509
1510 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1511
1512         * configure: Regenerate.
1513
1514 2019-01-07  Alan Modra  <amodra@gmail.com>
1515
1516         * configure: Regenerate.
1517         * po/POTFILES.in: Regenerate.
1518
1519 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1520
1521         * s12z-opc.c: New file.
1522         * s12z-opc.h: New file.
1523         * s12z-dis.c: Removed all code not directly related to display
1524         of instructions.  Used the interface provided by the new files
1525         instead.
1526         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1527         * Makefile.in: Regenerate.
1528         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1529         * configure: Regenerate.
1530
1531 2019-01-01  Alan Modra  <amodra@gmail.com>
1532
1533         Update year range in copyright notice of all files.
1534
1535 For older changes see ChangeLog-2018
1536 \f
1537 Copyright (C) 2019 Free Software Foundation, Inc.
1538
1539 Copying and distribution of this file, with or without modification,
1540 are permitted in any medium without royalty provided the copyright
1541 notice and this notice are preserved.
1542
1543 Local Variables:
1544 mode: change-log
1545 left-margin: 8
1546 fill-column: 74
1547 version-control: never
1548 End: