opcodes/ChangeLog

   1 2020-07-08  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (XMVexScalarI4): Define.
   4         (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
   5         VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
   6         VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
   7         (vex_len_table): Move scalar FMA4 entries ...
   8         (prefix_table): ... here.
   9         (OP_REG_VexI4): Handle scalar_mode.
  10         * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
  11         * i386-tbl.h: Re-generate.
  12
  13 2020-07-08  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
  16         Vex_2src_2): Delete.
  17         (OP_VexW, VexW): New.
  18         (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
  19         for shifts and rotates by register.
  20
  21 2020-07-08  Jan Beulich  <jbeulich@suse.com>
  22
  23         * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
  24         VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
  25         OP_EX_VexReg): Delete.
  26         (OP_VexI4, VexI4): New.
  27         (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
  28         (prefix_table): ... here.
  29         (print_insn): Drop setting of vex_w_done.
  30
  31 2020-07-08  Jan Beulich  <jbeulich@suse.com>
  32
  33         * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
  34         (prefix_table, vex_len_table): Replace operands for FMA4 insns.
  35         (xop_table): Replace operands of 4-operand insns.
  36         (OP_REG_VexI4): Move VEX.W based operand swaping here.
  37
  38 2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
  39
  40         * arc-opc.c (insert_rbd): New function.
  41         (RBD): Define.
  42         (RBDdup): Likewise.
  43         * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
  44         instructions.
  45
  46 2020-07-07  Jan Beulich  <jbeulich@suse.com>
  47
  48         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
  49         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
  50         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
  51         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
  52         Delete.
  53         (putop): Handle "BW".
  54         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
  55         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
  56         and 0F3A3F ...
  57         * i386-dis-evex-prefix.h: ... here.
  58
  59 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
  62         (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
  63         VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
  64         VEX_W_0FXOP_09_83): New enumerators.
  65         (xop_table): Reference the above.
  66         (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
  67         (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
  68         VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
  69         (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
  70
  71 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-dis.c (EVEX_W_0F3838_P_1,
  74         EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
  75         EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
  76         EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
  77         EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
  78         EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
  79         (putop): Centralize management of last[]. Delete SAVE_LAST.
  80         * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
  81         0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
  82         0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
  83         * i386-dis-evex-prefix.h: here.
  84
  85 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
  88         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
  89         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
  90         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
  91         enumerators.
  92         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
  93         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
  94         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
  95         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
  96         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
  97         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
  98         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
  99         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
 100         these, respectively.
 101         * i386-dis-evex-len.h: Adjust comments.
 102         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
 103         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
 104         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
 105         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
 106         MOD_EVEX_0F385B_P_2_W_1 table entries.
 107         * i386-dis-evex-w.h: Reference mod_table[] for
 108         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
 109         EVEX_W_0F385B_P_2.
 110
 111 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 112
 113         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
 114         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
 115         EXymm.
 116         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
 117         Likewise. Mark 256-bit entries invalid.
 118
 119 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 120
 121         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
 122         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
 123         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
 124         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
 125         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
 126         PREFIX_EVEX_0F382B): Delete.
 127         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
 128         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
 129         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
 130         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
 131         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
 132         to ...
 133         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
 134         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
 135         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
 136         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
 137         respectively.
 138         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
 139         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
 140         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
 141         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
 142         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
 143         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
 144         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
 145         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
 146         PREFIX_EVEX_0F382B): Remove table entries.
 147         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
 148         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
 149         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
 150
 151 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
 154         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
 155         enumerators.
 156         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
 157         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
 158         EVEX_LEN_0F3A01_P_2_W_1 table entries.
 159         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
 160         entries.
 161
 162 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
 165         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
 166         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
 167         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
 168         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
 169         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
 170         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
 171         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
 172         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
 173         entries.
 174
 175 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 176
 177         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
 178         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
 179         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
 180         respectively.
 181         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
 182         entries.
 183         * i386-dis-evex.h (evex_table): Reference VEX table entry for
 184         opcode 0F3A1D.
 185         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
 186         entry.
 187         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
 188
 189 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
 192         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 193         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
 194         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
 195         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 196         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
 197         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
 198         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
 199         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 200         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
 201         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
 202         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
 203         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
 204         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
 205         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
 206         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
 207         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
 208         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
 209         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 210         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 211         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 212         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 213         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 214         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 215         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 216         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 217         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
 218         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
 219         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
 220         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
 221         (prefix_table): Add EXxEVexR to FMA table entries.
 222         (OP_Rounding): Move abort() invocation.
 223         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
 224         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
 225         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
 226         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
 227         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
 228         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
 229         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
 230         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
 231         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
 232         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
 233         0F3ACE, 0F3ACF.
 234         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
 235         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 236         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
 237         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
 238         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 239         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
 240         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
 241         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
 242         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 243         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
 244         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
 245         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
 246         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
 247         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
 248         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
 249         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
 250         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
 251         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
 252         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 253         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 254         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 255         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 256         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 257         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 258         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 259         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 260         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
 261         Delete table entries.
 262         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
 263         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
 264         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
 265         Likewise.
 266
 267 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 268
 269         * i386-dis.c (EXqScalarS): Delete.
 270         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
 271         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
 272
 273 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 274
 275         * i386-dis.c (safe-ctype.h): Include.
 276         (EXdScalar, EXqScalar): Delete.
 277         (d_scalar_mode, q_scalar_mode): Delete.
 278         (prefix_table, vex_len_table): Use EXxmm_md in place of
 279         EXdScalar and EXxmm_mq in place of EXqScalar.
 280         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
 281         d_scalar_mode and q_scalar_mode.
 282         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
 283         (vmovsd): Use EXxmm_mq.
 284
 285 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
 286
 287         PR 26204
 288         * arc-dis.c: Fix spelling mistake.
 289         * po/opcodes.pot: Regenerate.
 290
 291 2020-07-06  Nick Clifton  <nickc@redhat.com>
 292
 293         * po/pt_BR.po: Updated Brazilian Portugugese translation.
 294         * po/uk.po: Updated Ukranian translation.
 295
 296 2020-07-04  Nick Clifton  <nickc@redhat.com>
 297
 298         * configure: Regenerate.
 299         * po/opcodes.pot: Regenerate.
 300
 301 2020-07-04  Nick Clifton  <nickc@redhat.com>
 302
 303         Binutils 2.35 branch created.
 304
 305 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
 306
 307         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
 308         * i386-opc.h (VexSwapSources): New.
 309         (i386_opcode_modifier): Add vexswapsources.
 310         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
 311         with two source operands swapped.
 312         * i386-tbl.h: Regenerated.
 313
 314 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
 315
 316         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
 317         unprivileged CSR can also be initialized.
 318
 319 2020-06-29  Alan Modra  <amodra@gmail.com>
 320
 321         * arm-dis.c: Use C style comments.
 322         * cr16-opc.c: Likewise.
 323         * ft32-dis.c: Likewise.
 324         * moxie-opc.c: Likewise.
 325         * tic54x-dis.c: Likewise.
 326         * s12z-opc.c: Remove useless comment.
 327         * xgate-dis.c: Likewise.
 328
 329 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 330
 331         * i386-opc.tbl: Add a blank line.
 332
 333 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 334
 335         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
 336         (VecSIB128): Renamed to ...
 337         (VECSIB128): This.
 338         (VecSIB256): Renamed to ...
 339         (VECSIB256): This.
 340         (VecSIB512): Renamed to ...
 341         (VECSIB512): This.
 342         (VecSIB): Renamed to ...
 343         (SIB): This.
 344         (i386_opcode_modifier): Replace vecsib with sib.
 345         * i386-opc.tbl (VecSIB128): New.
 346         (VecSIB256): Likewise.
 347         (VecSIB512): Likewise.
 348         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
 349         and VecSIB512, respectively.
 350
 351 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 352
 353         * i386-dis.c: Adjust description of I macro.
 354         (x86_64_table): Drop use of I.
 355         (float_mem): Replace use of I.
 356         (putop): Remove handling of I. Adjust setting/clearing of "alt".
 357
 358 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 359
 360         * i386-dis.c: (print_insn): Avoid straight assignment to
 361         priv.orig_sizeflag when processing -M sub-options.
 362
 363 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-dis.c: Adjust description of J macro.
 366         (dis386, x86_64_table, mod_table): Replace J.
 367         (putop): Remove handling of J.
 368
 369 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 370
 371         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
 372
 373 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 374
 375         * i386-dis.c: Adjust description of "LQ" macro.
 376         (dis386_twobyte): Use LQ for sysret.
 377         (putop): Adjust handling of LQ.
 378
 379 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
 380
 381         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
 382         * riscv-dis.c: Include elfxx-riscv.h.
 383
 384 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 385
 386         * i386-dis.c (prefix_table): Revert the last vmgexit change.
 387
 388 2020-06-17  Lili Cui  <lili.cui@intel.com>
 389
 390         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 391
 392 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 393
 394         PR gas/26115
 395         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 396         * i386-opc.tbl: Likewise.
 397         * i386-tbl.h: Regenerated.
 398
 399 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 400
 401         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 402
 403 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 404
 405         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 406         (SR_CORE): Likewise.
 407         (SR_FEAT): Likewise.
 408         (SR_RNG): Likewise.
 409         (SR_V8_1): Likewise.
 410         (SR_V8_2): Likewise.
 411         (SR_V8_3): Likewise.
 412         (SR_V8_4): Likewise.
 413         (SR_PAN): Likewise.
 414         (SR_RAS): Likewise.
 415         (SR_SSBS): Likewise.
 416         (SR_SVE): Likewise.
 417         (SR_ID_PFR2): Likewise.
 418         (SR_PROFILE): Likewise.
 419         (SR_MEMTAG): Likewise.
 420         (SR_SCXTNUM): Likewise.
 421         (aarch64_sys_regs): Refactor to store feature information in the table.
 422         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 423         that now describe their own features.
 424         (aarch64_pstatefield_supported_p): Likewise.
 425
 426 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 427
 428         * i386-dis.c (prefix_table): Fix a typo in comments.
 429
 430 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 431
 432         * i386-dis.c (rex_ignored): Delete.
 433         (ckprefix): Drop rex_ignored initialization.
 434         (get_valid_dis386): Drop setting of rex_ignored.
 435         (print_insn): Drop checking of rex_ignored. Don't record data
 436         size prefix as used with VEX-and-alike encodings.
 437
 438 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 439
 440         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 441         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 442         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 443         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 444         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 445         VEX_0F12, and VEX_0F16.
 446         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 447         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 448         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 449         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 450         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 451         MOD_VEX_0F16_PREFIX_2 entries.
 452
 453 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 456         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 457         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 458         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 459         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 460         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 461         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 462         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 463         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 464         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 465         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 466         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 467         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 468         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 469         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 470         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 471         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 472         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 473         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 474         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 475         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 476         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 477         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 478         EVEX_W_0FC6_P_2): Delete.
 479         (print_insn): Add EVEX.W vs embedded prefix consistency check
 480         to prefix validation.
 481         * i386-dis-evex.h (evex_table): Don't further descend for
 482         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 483         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 484         and 0F2B.
 485         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 486         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 487         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 488         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 489         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 490         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 491         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 492         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 493         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 494         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 495         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 496         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 497         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 498         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 499         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 500         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 501         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 502         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 503         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 504         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 505         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 506         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 507         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 508         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 509         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 510         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 511         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 512
 513 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 514
 515         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 516         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 517         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 518         vmovmskpX.
 519         (print_insn): Drop pointless check against bad_opcode. Split
 520         prefix validation into legacy and VEX-and-alike parts.
 521         (putop): Re-work 'X' macro handling.
 522
 523 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 524
 525         * i386-dis.c (MOD_0F51): Rename to ...
 526         (MOD_0F50): ... this.
 527
 528 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 529
 530         * arm-dis.c (arm_opcodes): Add dfb.
 531         (thumb32_opcodes): Add dfb.
 532
 533 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 534
 535         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 536
 537 2020-06-06  Alan Modra  <amodra@gmail.com>
 538
 539         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 540
 541 2020-06-05  Alan Modra  <amodra@gmail.com>
 542
 543         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 544         size is large enough.
 545
 546 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 547
 548         * disassemble.c (disassemble_init_for_target): Set endian_code for
 549         bpf targets.
 550         * bpf-desc.c: Regenerate.
 551         * bpf-opc.c: Likewise.
 552         * bpf-dis.c: Likewise.
 553
 554 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 555
 556         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 557         (cgen_put_insn_value): Likewise.
 558         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 559         * cgen-dis.in (print_insn): Likewise.
 560         * cgen-ibld.in (insert_1): Likewise.
 561         (insert_1): Likewise.
 562         (insert_insn_normal): Likewise.
 563         (extract_1): Likewise.
 564         * bpf-dis.c: Regenerate.
 565         * bpf-ibld.c: Likewise.
 566         * bpf-ibld.c: Likewise.
 567         * cgen-dis.in: Likewise.
 568         * cgen-ibld.in: Likewise.
 569         * cgen-opc.c: Likewise.
 570         * epiphany-dis.c: Likewise.
 571         * epiphany-ibld.c: Likewise.
 572         * fr30-dis.c: Likewise.
 573         * fr30-ibld.c: Likewise.
 574         * frv-dis.c: Likewise.
 575         * frv-ibld.c: Likewise.
 576         * ip2k-dis.c: Likewise.
 577         * ip2k-ibld.c: Likewise.
 578         * iq2000-dis.c: Likewise.
 579         * iq2000-ibld.c: Likewise.
 580         * lm32-dis.c: Likewise.
 581         * lm32-ibld.c: Likewise.
 582         * m32c-dis.c: Likewise.
 583         * m32c-ibld.c: Likewise.
 584         * m32r-dis.c: Likewise.
 585         * m32r-ibld.c: Likewise.
 586         * mep-dis.c: Likewise.
 587         * mep-ibld.c: Likewise.
 588         * mt-dis.c: Likewise.
 589         * mt-ibld.c: Likewise.
 590         * or1k-dis.c: Likewise.
 591         * or1k-ibld.c: Likewise.
 592         * xc16x-dis.c: Likewise.
 593         * xc16x-ibld.c: Likewise.
 594         * xstormy16-dis.c: Likewise.
 595         * xstormy16-ibld.c: Likewise.
 596
 597 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 598
 599         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 600         (print_insn_): Handle instruction endian.
 601         * bpf-dis.c: Regenerate.
 602         * bpf-desc.c: Regenerate.
 603         * epiphany-dis.c: Likewise.
 604         * epiphany-desc.c: Likewise.
 605         * fr30-dis.c: Likewise.
 606         * fr30-desc.c: Likewise.
 607         * frv-dis.c: Likewise.
 608         * frv-desc.c: Likewise.
 609         * ip2k-dis.c: Likewise.
 610         * ip2k-desc.c: Likewise.
 611         * iq2000-dis.c: Likewise.
 612         * iq2000-desc.c: Likewise.
 613         * lm32-dis.c: Likewise.
 614         * lm32-desc.c: Likewise.
 615         * m32c-dis.c: Likewise.
 616         * m32c-desc.c: Likewise.
 617         * m32r-dis.c: Likewise.
 618         * m32r-desc.c: Likewise.
 619         * mep-dis.c: Likewise.
 620         * mep-desc.c: Likewise.
 621         * mt-dis.c: Likewise.
 622         * mt-desc.c: Likewise.
 623         * or1k-dis.c: Likewise.
 624         * or1k-desc.c: Likewise.
 625         * xc16x-dis.c: Likewise.
 626         * xc16x-desc.c: Likewise.
 627         * xstormy16-dis.c: Likewise.
 628         * xstormy16-desc.c: Likewise.
 629
 630 2020-06-03  Nick Clifton  <nickc@redhat.com>
 631
 632         * po/sr.po: Updated Serbian translation.
 633
 634 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 635
 636         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 637         (riscv_get_priv_spec_class): Likewise.
 638
 639 2020-06-01  Alan Modra  <amodra@gmail.com>
 640
 641         * bpf-desc.c: Regenerate.
 642
 643 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 644             David Faust <david.faust@oracle.com>
 645
 646         * bpf-desc.c: Regenerate.
 647         * bpf-opc.h: Likewise.
 648         * bpf-opc.c: Likewise.
 649         * bpf-dis.c: Likewise.
 650
 651 2020-05-28  Alan Modra  <amodra@gmail.com>
 652
 653         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 654         values.
 655
 656 2020-05-28  Alan Modra  <amodra@gmail.com>
 657
 658         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 659         immediates.
 660         (print_insn_ns32k): Revert last change.
 661
 662 2020-05-28  Nick Clifton  <nickc@redhat.com>
 663
 664         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 665         static.
 666
 667 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 668
 669         Fix extraction of signed constants in nios2 disassembler (again).
 670
 671         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 672         extractions of signed fields.
 673
 674 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 675
 676         * s390-opc.txt: Relocate vector load/store instructions with
 677         additional alignment parameter and change architecture level
 678         constraint from z14 to z13.
 679
 680 2020-05-21  Alan Modra  <amodra@gmail.com>
 681
 682         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 683         * sparc-dis.c: Likewise.
 684         * tic4x-dis.c: Likewise.
 685         * xtensa-dis.c: Likewise.
 686         * bpf-desc.c: Regenerate.
 687         * epiphany-desc.c: Regenerate.
 688         * fr30-desc.c: Regenerate.
 689         * frv-desc.c: Regenerate.
 690         * ip2k-desc.c: Regenerate.
 691         * iq2000-desc.c: Regenerate.
 692         * lm32-desc.c: Regenerate.
 693         * m32c-desc.c: Regenerate.
 694         * m32r-desc.c: Regenerate.
 695         * mep-asm.c: Regenerate.
 696         * mep-desc.c: Regenerate.
 697         * mt-desc.c: Regenerate.
 698         * or1k-desc.c: Regenerate.
 699         * xc16x-desc.c: Regenerate.
 700         * xstormy16-desc.c: Regenerate.
 701
 702 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 703
 704         * riscv-opc.c (riscv_ext_version_table): The table used to store
 705         all information about the supported spec and the corresponding ISA
 706         versions.  Currently, only Zicsr is supported to verify the
 707         correctness of Z sub extension settings.  Others will be supported
 708         in the future patches.
 709         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 710         classes and the corresponding strings.
 711         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 712         spec class by giving a ISA spec string.
 713         * riscv-opc.c (struct priv_spec_t): New structure.
 714         (struct priv_spec_t priv_specs): List for all supported privilege spec
 715         classes and the corresponding strings.
 716         (riscv_get_priv_spec_class): New function.  Get the corresponding
 717         privilege spec class by giving a spec string.
 718         (riscv_get_priv_spec_name): New function.  Get the corresponding
 719         privilege spec string by giving a CSR version class.
 720         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 721         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 722         according to the chosen version.  Build a hash table riscv_csr_hash to
 723         store the valid CSR for the chosen pirv verison.  Dump the direct
 724         CSR address rather than it's name if it is invalid.
 725         (parse_riscv_dis_option_without_args): New function.  Parse the options
 726         without arguments.
 727         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 728         parse the options without arguments first, and then handle the options
 729         with arguments.  Add the new option -Mpriv-spec, which has argument.
 730         * riscv-dis.c (print_riscv_disassembler_options): Add description
 731         about the new OBJDUMP option.
 732
 733 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 734
 735         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 736         WC values on POWER10 sync, dcbf  and wait instructions.
 737         (insert_pl, extract_pl): New functions.
 738         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 739         (LS3): New , 3-bit L for sync.
 740         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 741         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 742         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 743         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 744         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 745         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 746         <wait>: Enable PL operand on POWER10.
 747         <dcbf>: Enable L3OPT operand on POWER10.
 748         <sync>: Enable SC2 operand on POWER10.
 749
 750 2020-05-19  Stafford Horne  <shorne@gmail.com>
 751
 752         PR 25184
 753         * or1k-asm.c: Regenerate.
 754         * or1k-desc.c: Regenerate.
 755         * or1k-desc.h: Regenerate.
 756         * or1k-dis.c: Regenerate.
 757         * or1k-ibld.c: Regenerate.
 758         * or1k-opc.c: Regenerate.
 759         * or1k-opc.h: Regenerate.
 760         * or1k-opinst.c: Regenerate.
 761
 762 2020-05-11  Alan Modra  <amodra@gmail.com>
 763
 764         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 765         xsmaxcqp, xsmincqp.
 766
 767 2020-05-11  Alan Modra  <amodra@gmail.com>
 768
 769         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 770         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 771
 772 2020-05-11  Alan Modra  <amodra@gmail.com>
 773
 774         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 775
 776 2020-05-11  Alan Modra  <amodra@gmail.com>
 777
 778         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 779         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 780
 781 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 782
 783         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 784         mnemonics.
 785
 786 2020-05-11  Alan Modra  <amodra@gmail.com>
 787
 788         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 789         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 790         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 791         (prefix_opcodes): Add xxeval.
 792
 793 2020-05-11  Alan Modra  <amodra@gmail.com>
 794
 795         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 796         xxgenpcvwm, xxgenpcvdm.
 797
 798 2020-05-11  Alan Modra  <amodra@gmail.com>
 799
 800         * ppc-opc.c (MP, VXVAM_MASK): Define.
 801         (VXVAPS_MASK): Use VXVA_MASK.
 802         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 803         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 804         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 805         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 806
 807 2020-05-11  Alan Modra  <amodra@gmail.com>
 808             Peter Bergner  <bergner@linux.ibm.com>
 809
 810         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 811         New functions.
 812         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 813         YMSK2, XA6a, XA6ap, XB6a entries.
 814         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 815         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 816         (PPCVSX4): Define.
 817         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 818         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 819         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 820         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 821         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 822         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 823         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 824         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 825         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 826         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 827         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 828         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 829         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 830         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 831
 832 2020-05-11  Alan Modra  <amodra@gmail.com>
 833
 834         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 835         (insert_xts, extract_xts): New functions.
 836         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 837         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 838         (VXRC_MASK, VXSH_MASK): Define.
 839         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 840         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 841         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 842         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 843         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 844         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 845         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 846
 847 2020-05-11  Alan Modra  <amodra@gmail.com>
 848
 849         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 850         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 851         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 852         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 853         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 854
 855 2020-05-11  Alan Modra  <amodra@gmail.com>
 856
 857         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 858         (XTP, DQXP, DQXP_MASK): Define.
 859         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 860         (prefix_opcodes): Add plxvp and pstxvp.
 861
 862 2020-05-11  Alan Modra  <amodra@gmail.com>
 863
 864         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 865         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 866         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 867
 868 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 869
 870         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 871
 872 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 873
 874         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 875         (L1OPT): Define.
 876         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 877
 878 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 879
 880         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 881
 882 2020-05-11  Alan Modra  <amodra@gmail.com>
 883
 884         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 885
 886 2020-05-11  Alan Modra  <amodra@gmail.com>
 887
 888         * ppc-dis.c (ppc_opts): Add "power10" entry.
 889         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 890         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 891
 892 2020-05-11  Nick Clifton  <nickc@redhat.com>
 893
 894         * po/fr.po: Updated French translation.
 895
 896 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 897
 898         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 899         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 900         (operand_general_constraint_met_p): validate
 901         AARCH64_OPND_UNDEFINED.
 902         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 903         for FLD_imm16_2.
 904         * aarch64-asm-2.c: Regenerated.
 905         * aarch64-dis-2.c: Regenerated.
 906         * aarch64-opc-2.c: Regenerated.
 907
 908 2020-04-29  Nick Clifton  <nickc@redhat.com>
 909
 910         PR 22699
 911         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 912         and SETRC insns.
 913
 914 2020-04-29  Nick Clifton  <nickc@redhat.com>
 915
 916         * po/sv.po: Updated Swedish translation.
 917
 918 2020-04-29  Nick Clifton  <nickc@redhat.com>
 919
 920         PR 22699
 921         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 922         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 923         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 924         IMM0_8U case.
 925
 926 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 927
 928         PR 25848
 929         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 930         cmpi only on m68020up and cpu32.
 931
 932 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 933
 934         * aarch64-asm.c (aarch64_ins_none): New.
 935         * aarch64-asm.h (ins_none): New declaration.
 936         * aarch64-dis.c (aarch64_ext_none): New.
 937         * aarch64-dis.h (ext_none): New declaration.
 938         * aarch64-opc.c (aarch64_print_operand): Update case for
 939         AARCH64_OPND_BARRIER_PSB.
 940         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 941         (AARCH64_OPERANDS): Update inserter/extracter for
 942         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 943         * aarch64-asm-2.c: Regenerated.
 944         * aarch64-dis-2.c: Regenerated.
 945         * aarch64-opc-2.c: Regenerated.
 946
 947 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 948
 949         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 950         (aarch64_feature_ras, RAS): Likewise.
 951         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 952         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 953         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 954         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 955         * aarch64-asm-2.c: Regenerated.
 956         * aarch64-dis-2.c: Regenerated.
 957         * aarch64-opc-2.c: Regenerated.
 958
 959 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 960
 961         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 962         (print_insn_neon): Support disassembly of conditional
 963         instructions.
 964
 965 2020-02-16  David Faust  <david.faust@oracle.com>
 966
 967         * bpf-desc.c: Regenerate.
 968         * bpf-desc.h: Likewise.
 969         * bpf-opc.c: Regenerate.
 970         * bpf-opc.h: Likewise.
 971
 972 2020-04-07  Lili Cui  <lili.cui@intel.com>
 973
 974         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 975         (prefix_table): New instructions (see prefixes above).
 976         (rm_table): Likewise
 977         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 978         CPU_ANY_TSXLDTRK_FLAGS.
 979         (cpu_flags): Add CpuTSXLDTRK.
 980         * i386-opc.h (enum): Add CpuTSXLDTRK.
 981         (i386_cpu_flags): Add cputsxldtrk.
 982         * i386-opc.tbl: Add XSUSPLDTRK insns.
 983         * i386-init.h: Regenerate.
 984         * i386-tbl.h: Likewise.
 985
 986 2020-04-02  Lili Cui  <lili.cui@intel.com>
 987
 988         * i386-dis.c (prefix_table): New instructions serialize.
 989         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 990         CPU_ANY_SERIALIZE_FLAGS.
 991         (cpu_flags): Add CpuSERIALIZE.
 992         * i386-opc.h (enum): Add CpuSERIALIZE.
 993         (i386_cpu_flags): Add cpuserialize.
 994         * i386-opc.tbl: Add SERIALIZE insns.
 995         * i386-init.h: Regenerate.
 996         * i386-tbl.h: Likewise.
 997
 998 2020-03-26  Alan Modra  <amodra@gmail.com>
 999
1000         * disassemble.h (opcodes_assert): Declare.
1001         (OPCODES_ASSERT): Define.
1002         * disassemble.c: Don't include assert.h.  Include opintl.h.
1003         (opcodes_assert): New function.
1004         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1005         (bfd_h8_disassemble): Reduce size of data array.  Correctly
1006         calculate maxlen.  Omit insn decoding when insn length exceeds
1007         maxlen.  Exit from nibble loop when looking for E, before
1008         accessing next data byte.  Move processing of E outside loop.
1009         Replace tests of maxlen in loop with assertions.
1010
1011 2020-03-26  Alan Modra  <amodra@gmail.com>
1012
1013         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
1014
1015 2020-03-25  Alan Modra  <amodra@gmail.com>
1016
1017         * z80-dis.c (suffix): Init mybuf.
1018
1019 2020-03-22  Alan Modra  <amodra@gmail.com>
1020
1021         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1022         successflly read from section.
1023
1024 2020-03-22  Alan Modra  <amodra@gmail.com>
1025
1026         * arc-dis.c (find_format): Use ISO C string concatenation rather
1027         than line continuation within a string.  Don't access needs_limm
1028         before testing opcode != NULL.
1029
1030 2020-03-22  Alan Modra  <amodra@gmail.com>
1031
1032         * ns32k-dis.c (print_insn_arg): Update comment.
1033         (print_insn_ns32k): Reduce size of index_offset array, and
1034         initialize, passing -1 to print_insn_arg for args that are not
1035         an index.  Don't exit arg loop early.  Abort on bad arg number.
1036
1037 2020-03-22  Alan Modra  <amodra@gmail.com>
1038
1039         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1040         * s12z-opc.c: Formatting.
1041         (operands_f): Return an int.
1042         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1043         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1044         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1045         (exg_sex_discrim): Likewise.
1046         (create_immediate_operand, create_bitfield_operand),
1047         (create_register_operand_with_size, create_register_all_operand),
1048         (create_register_all16_operand, create_simple_memory_operand),
1049         (create_memory_operand, create_memory_auto_operand): Don't
1050         segfault on malloc failure.
1051         (z_ext24_decode): Return an int status, negative on fail, zero
1052         on success.
1053         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1054         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1055         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1056         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1057         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1058         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1059         (loop_primitive_decode, shift_decode, psh_pul_decode),
1060         (bit_field_decode): Similarly.
1061         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
1062         to return value, update callers.
1063         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1064         Don't segfault on NULL operand.
1065         (decode_operation): Return OP_INVALID on first fail.
1066         (decode_s12z): Check all reads, returning -1 on fail.
1067
1068 2020-03-20  Alan Modra  <amodra@gmail.com>
1069
1070         * metag-dis.c (print_insn_metag): Don't ignore status from
1071         read_memory_func.
1072
1073 2020-03-20  Alan Modra  <amodra@gmail.com>
1074
1075         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1076         Initialize parts of buffer not written when handling a possible
1077         2-byte insn at end of section.  Don't attempt decoding of such
1078         an insn by the 4-byte machinery.
1079
1080 2020-03-20  Alan Modra  <amodra@gmail.com>
1081
1082         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1083         partially filled buffer.  Prevent lookup of 4-byte insns when
1084         only VLE 2-byte insns are possible due to section size.  Print
1085         ".word" rather than ".long" for 2-byte leftovers.
1086
1087 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
1088
1089         PR 25641
1090         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1091
1092 2020-03-13  Jan Beulich  <jbeulich@suse.com>
1093
1094         * i386-dis.c (X86_64_0D): Rename to ...
1095         (X86_64_0E): ... this.
1096
1097 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1098
1099         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1100         * Makefile.in: Regenerated.
1101
1102 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1103
1104         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1105         3-operand pseudos.
1106         * i386-tbl.h: Re-generate.
1107
1108 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1109
1110         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1111         vprot*, vpsha*, and vpshl*.
1112         * i386-tbl.h: Re-generate.
1113
1114 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1115
1116         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1117         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1118         * i386-tbl.h: Re-generate.
1119
1120 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1121
1122         * i386-gen.c (set_bitfield): Ignore zero-length field names.
1123         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1124         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1125         * i386-tbl.h: Re-generate.
1126
1127 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1128
1129         * i386-gen.c (struct template_arg, struct template_instance,
1130         struct template_param, struct template, templates,
1131         parse_template, expand_templates): New.
1132         (process_i386_opcodes): Various local variables moved to
1133         expand_templates. Call parse_template and expand_templates.
1134         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1135         * i386-tbl.h: Re-generate.
1136
1137 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1140         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1141         register and memory source templates. Replace VexW= by VexW*
1142         where applicable.
1143         * i386-tbl.h: Re-generate.
1144
1145 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1146
1147         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1148         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1149         * i386-tbl.h: Re-generate.
1150
1151 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1152
1153         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1154         * i386-tbl.h: Re-generate.
1155
1156 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1157
1158         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1159         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1160         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1161         VexW0 on SSE2AVX variants.
1162         (vmovq): Drop NoRex64 from XMM/XMM variants.
1163         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1164         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1165         applicable use VexW0.
1166         * i386-tbl.h: Re-generate.
1167
1168 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1169
1170         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1171         * i386-opc.h (Rex64): Delete.
1172         (struct i386_opcode_modifier): Remove rex64 field.
1173         * i386-opc.tbl (crc32): Drop Rex64.
1174         Replace Rex64 with Size64 everywhere else.
1175         * i386-tbl.h: Re-generate.
1176
1177 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1178
1179         * i386-dis.c (OP_E_memory): Exclude recording of used address
1180         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1181         addressed memory operands for MPX insns.
1182
1183 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1184
1185         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1186         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1187         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1188         (ptwrite): Split into non-64-bit and 64-bit forms.
1189         * i386-tbl.h: Re-generate.
1190
1191 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1192
1193         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1194         template.
1195         * i386-tbl.h: Re-generate.
1196
1197 2020-03-04  Jan Beulich  <jbeulich@suse.com>
1198
1199         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1200         (prefix_table): Move vmmcall here. Add vmgexit.
1201         (rm_table): Replace vmmcall entry by prefix_table[] escape.
1202         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1203         (cpu_flags): Add CpuSEV_ES entry.
1204         * i386-opc.h (CpuSEV_ES): New.
1205         (union i386_cpu_flags): Add cpusev_es field.
1206         * i386-opc.tbl (vmgexit): New.
1207         * i386-init.h, i386-tbl.h: Re-generate.
1208
1209 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1210
1211         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1212         with MnemonicSize.
1213         * i386-opc.h (IGNORESIZE): New.
1214         (DEFAULTSIZE): Likewise.
1215         (IgnoreSize): Removed.
1216         (DefaultSize): Likewise.
1217         (MnemonicSize): New.
1218         (i386_opcode_modifier): Replace ignoresize/defaultsize with
1219         mnemonicsize.
1220         * i386-opc.tbl (IgnoreSize): New.
1221         (DefaultSize): Likewise.
1222         * i386-tbl.h: Regenerated.
1223
1224 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1225
1226         PR 25627
1227         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1228         instructions.
1229
1230 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1231
1232         PR gas/25622
1233         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1234         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1235         * i386-tbl.h: Regenerated.
1236
1237 2020-02-26  Alan Modra  <amodra@gmail.com>
1238
1239         * aarch64-asm.c: Indent labels correctly.
1240         * aarch64-dis.c: Likewise.
1241         * aarch64-gen.c: Likewise.
1242         * aarch64-opc.c: Likewise.
1243         * alpha-dis.c: Likewise.
1244         * i386-dis.c: Likewise.
1245         * nds32-asm.c: Likewise.
1246         * nfp-dis.c: Likewise.
1247         * visium-dis.c: Likewise.
1248
1249 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
1250
1251         * arc-regs.h (int_vector_base): Make it available for all ARC
1252         CPUs.
1253
1254 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
1255
1256         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1257         changed.
1258
1259 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
1260
1261         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1262         c.mv/c.li if rs1 is zero.
1263
1264 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
1265
1266         * i386-gen.c (cpu_flag_init): Replace CpuABM with
1267         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
1268         CPU_POPCNT_FLAGS.
1269         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
1270         * i386-opc.h (CpuABM): Removed.
1271         (CpuPOPCNT): New.
1272         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
1273         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1274         popcnt.  Remove CpuABM from lzcnt.
1275         * i386-init.h: Regenerated.
1276         * i386-tbl.h: Likewise.
1277
1278 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1279
1280         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1281         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1282         VexW1 instead of open-coding them.
1283         * i386-tbl.h: Re-generate.
1284
1285 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1286
1287         * i386-opc.tbl (AddrPrefixOpReg): Define.
1288         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1289         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1290         templates. Drop NoRex64.
1291         * i386-tbl.h: Re-generate.
1292
1293 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1294
1295         PR gas/6518
1296         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1297         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1298         into Intel syntax instance (with Unpsecified) and AT&T one
1299         (without).
1300         (vcvtneps2bf16): Likewise, along with folding the two so far
1301         separate ones.
1302         * i386-tbl.h: Re-generate.
1303
1304 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1305
1306         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1307         CPU_ANY_SSE4A_FLAGS.
1308
1309 2020-02-17  Alan Modra  <amodra@gmail.com>
1310
1311         * i386-gen.c (cpu_flag_init): Correct last change.
1312
1313 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1314
1315         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1316         CPU_ANY_SSE4_FLAGS.
1317
1318 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1319
1320         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1321         (movzx): Likewise.
1322
1323 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1324
1325         PR gas/25438
1326         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1327         destination for Cpu64-only variant.
1328         (movzx): Fold patterns.
1329         * i386-tbl.h: Re-generate.
1330
1331 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1332
1333         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1334         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1335         CPU_ANY_SSE4_FLAGS entry.
1336         * i386-init.h: Re-generate.
1337
1338 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1339
1340         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1341         with Unspecified, making the present one AT&T syntax only.
1342         * i386-tbl.h: Re-generate.
1343
1344 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1345
1346         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1347         * i386-tbl.h: Re-generate.
1348
1349 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1350
1351         PR gas/24546
1352         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1353         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1354         Amd64 and Intel64 templates.
1355         (call, jmp): Likewise for far indirect variants. Dro
1356         Unspecified.
1357         * i386-tbl.h: Re-generate.
1358
1359 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1360
1361         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1362         * i386-opc.h (ShortForm): Delete.
1363         (struct i386_opcode_modifier): Remove shortform field.
1364         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1365         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1366         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1367         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1368         Drop ShortForm.
1369         * i386-tbl.h: Re-generate.
1370
1371 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1372
1373         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1374         fucompi): Drop ShortForm from operand-less templates.
1375         * i386-tbl.h: Re-generate.
1376
1377 2020-02-11  Alan Modra  <amodra@gmail.com>
1378
1379         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1380         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1381         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1382         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1383         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1384
1385 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1386
1387         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1388         (cde_opcodes): Add VCX* instructions.
1389
1390 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1391             Matthew Malcomson  <matthew.malcomson@arm.com>
1392
1393         * arm-dis.c (struct cdeopcode32): New.
1394         (CDE_OPCODE): New macro.
1395         (cde_opcodes): New disassembly table.
1396         (regnames): New option to table.
1397         (cde_coprocs): New global variable.
1398         (print_insn_cde): New
1399         (print_insn_thumb32): Use print_insn_cde.
1400         (parse_arm_disassembler_options): Parse coprocN args.
1401
1402 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1403
1404         PR gas/25516
1405         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1406         with ISA64.
1407         * i386-opc.h (AMD64): Removed.
1408         (Intel64): Likewose.
1409         (AMD64): New.
1410         (INTEL64): Likewise.
1411         (INTEL64ONLY): Likewise.
1412         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1413         * i386-opc.tbl (Amd64): New.
1414         (Intel64): Likewise.
1415         (Intel64Only): Likewise.
1416         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1417         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1418         * i386-tbl.h: Regenerated.
1419
1420 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1421
1422         PR 25469
1423         * z80-dis.c: Add support for GBZ80 opcodes.
1424
1425 2020-02-04  Alan Modra  <amodra@gmail.com>
1426
1427         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1428
1429 2020-02-03  Alan Modra  <amodra@gmail.com>
1430
1431         * m32c-ibld.c: Regenerate.
1432
1433 2020-02-01  Alan Modra  <amodra@gmail.com>
1434
1435         * frv-ibld.c: Regenerate.
1436
1437 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1438
1439         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1440         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1441         (OP_E_memory): Replace xmm_mdq_mode case label by
1442         vex_scalar_w_dq_mode one.
1443         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1444
1445 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1446
1447         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1448         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1449         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1450         (intel_operand_size): Drop vex_w_dq_mode case label.
1451
1452 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1453
1454         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1455         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1456
1457 2020-01-30  Alan Modra  <amodra@gmail.com>
1458
1459         * m32c-ibld.c: Regenerate.
1460
1461 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1462
1463         * bpf-opc.c: Regenerate.
1464
1465 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1466
1467         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1468         (dis386): Use them to replace C2/C3 table entries.
1469         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1470         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1471         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1472         * i386-tbl.h: Re-generate.
1473
1474 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1475
1476         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1477         forms.
1478         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1479         DefaultSize.
1480         * i386-tbl.h: Re-generate.
1481
1482 2020-01-30  Alan Modra  <amodra@gmail.com>
1483
1484         * tic4x-dis.c (tic4x_dp): Make unsigned.
1485
1486 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1487             Jan Beulich  <jbeulich@suse.com>
1488
1489         PR binutils/25445
1490         * i386-dis.c (MOVSXD_Fixup): New function.
1491         (movsxd_mode): New enum.
1492         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1493         (intel_operand_size): Handle movsxd_mode.
1494         (OP_E_register): Likewise.
1495         (OP_G): Likewise.
1496         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1497         register on movsxd.  Add movsxd with 16-bit destination register
1498         for AMD64 and Intel64 ISAs.
1499         * i386-tbl.h: Regenerated.
1500
1501 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1502
1503         PR 25403
1504         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1505         * aarch64-asm-2.c: Regenerate
1506         * aarch64-dis-2.c: Likewise.
1507         * aarch64-opc-2.c: Likewise.
1508
1509 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1510
1511         * i386-opc.tbl (sysret): Drop DefaultSize.
1512         * i386-tbl.h: Re-generate.
1513
1514 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1515
1516         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1517         Dword.
1518         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1519         * i386-tbl.h: Re-generate.
1520
1521 2020-01-20  Nick Clifton  <nickc@redhat.com>
1522
1523         * po/de.po: Updated German translation.
1524         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1525         * po/uk.po: Updated Ukranian translation.
1526
1527 2020-01-20  Alan Modra  <amodra@gmail.com>
1528
1529         * hppa-dis.c (fput_const): Remove useless cast.
1530
1531 2020-01-20  Alan Modra  <amodra@gmail.com>
1532
1533         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1534
1535 2020-01-18  Nick Clifton  <nickc@redhat.com>
1536
1537         * configure: Regenerate.
1538         * po/opcodes.pot: Regenerate.
1539
1540 2020-01-18  Nick Clifton  <nickc@redhat.com>
1541
1542         Binutils 2.34 branch created.
1543
1544 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1545
1546         * opintl.h: Fix spelling error (seperate).
1547
1548 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1549
1550         * i386-opc.tbl: Add {vex} pseudo prefix.
1551         * i386-tbl.h: Regenerated.
1552
1553 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1554
1555         PR 25376
1556         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1557         (neon_opcodes): Likewise.
1558         (select_arm_features): Make sure we enable MVE bits when selecting
1559         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1560         any architecture.
1561
1562 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1563
1564         * i386-opc.tbl: Drop stale comment from XOP section.
1565
1566 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1567
1568         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1569         (extractps): Add VexWIG to SSE2AVX forms.
1570         * i386-tbl.h: Re-generate.
1571
1572 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1573
1574         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1575         Size64 from and use VexW1 on SSE2AVX forms.
1576         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1577         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1578         * i386-tbl.h: Re-generate.
1579
1580 2020-01-15  Alan Modra  <amodra@gmail.com>
1581
1582         * tic4x-dis.c (tic4x_version): Make unsigned long.
1583         (optab, optab_special, registernames): New file scope vars.
1584         (tic4x_print_register): Set up registernames rather than
1585         malloc'd registertable.
1586         (tic4x_disassemble): Delete optable and optable_special.  Use
1587         optab and optab_special instead.  Throw away old optab,
1588         optab_special and registernames when info->mach changes.
1589
1590 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1591
1592         PR 25377
1593         * z80-dis.c (suffix): Use .db instruction to generate double
1594         prefix.
1595
1596 2020-01-14  Alan Modra  <amodra@gmail.com>
1597
1598         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1599         values to unsigned before shifting.
1600
1601 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1602
1603         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1604         flow instructions.
1605         (print_insn_thumb16, print_insn_thumb32): Likewise.
1606         (print_insn): Initialize the insn info.
1607         * i386-dis.c (print_insn): Initialize the insn info fields, and
1608         detect jumps.
1609
1610 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1611
1612         * arc-opc.c (C_NE): Make it required.
1613
1614 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1615
1616         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1617         reserved register name.
1618
1619 2020-01-13  Alan Modra  <amodra@gmail.com>
1620
1621         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1622         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1623
1624 2020-01-13  Alan Modra  <amodra@gmail.com>
1625
1626         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1627         result of wasm_read_leb128 in a uint64_t and check that bits
1628         are not lost when copying to other locals.  Use uint32_t for
1629         most locals.  Use PRId64 when printing int64_t.
1630
1631 2020-01-13  Alan Modra  <amodra@gmail.com>
1632
1633         * score-dis.c: Formatting.
1634         * score7-dis.c: Formatting.
1635
1636 2020-01-13  Alan Modra  <amodra@gmail.com>
1637
1638         * score-dis.c (print_insn_score48): Use unsigned variables for
1639         unsigned values.  Don't left shift negative values.
1640         (print_insn_score32): Likewise.
1641         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1642
1643 2020-01-13  Alan Modra  <amodra@gmail.com>
1644
1645         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1646
1647 2020-01-13  Alan Modra  <amodra@gmail.com>
1648
1649         * fr30-ibld.c: Regenerate.
1650
1651 2020-01-13  Alan Modra  <amodra@gmail.com>
1652
1653         * xgate-dis.c (print_insn): Don't left shift signed value.
1654         (ripBits): Formatting, use 1u.
1655
1656 2020-01-10  Alan Modra  <amodra@gmail.com>
1657
1658         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1659         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1660
1661 2020-01-10  Alan Modra  <amodra@gmail.com>
1662
1663         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1664         and XRREG value earlier to avoid a shift with negative exponent.
1665         * m10200-dis.c (disassemble): Similarly.
1666
1667 2020-01-09  Nick Clifton  <nickc@redhat.com>
1668
1669         PR 25224
1670         * z80-dis.c (ld_ii_ii): Use correct cast.
1671
1672 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1673
1674         PR 25224
1675         * z80-dis.c (ld_ii_ii): Use character constant when checking
1676         opcode byte value.
1677
1678 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1679
1680         * i386-dis.c (SEP_Fixup): New.
1681         (SEP): Define.
1682         (dis386_twobyte): Use it for sysenter/sysexit.
1683         (enum x86_64_isa): Change amd64 enumerator to value 1.
1684         (OP_J): Compare isa64 against intel64 instead of amd64.
1685         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1686         forms.
1687         * i386-tbl.h: Re-generate.
1688
1689 2020-01-08  Alan Modra  <amodra@gmail.com>
1690
1691         * z8k-dis.c: Include libiberty.h
1692         (instr_data_s): Make max_fetched unsigned.
1693         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1694         Don't exceed byte_info bounds.
1695         (output_instr): Make num_bytes unsigned.
1696         (unpack_instr): Likewise for nibl_count and loop.
1697         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1698         idx unsigned.
1699         * z8k-opc.h: Regenerate.
1700
1701 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1702
1703         * arc-tbl.h (llock): Use 'LLOCK' as class.
1704         (llockd): Likewise.
1705         (scond): Use 'SCOND' as class.
1706         (scondd): Likewise.
1707         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1708         (scondd): Likewise.
1709
1710 2020-01-06  Alan Modra  <amodra@gmail.com>
1711
1712         * m32c-ibld.c: Regenerate.
1713
1714 2020-01-06  Alan Modra  <amodra@gmail.com>
1715
1716         PR 25344
1717         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1718         Peek at next byte to prevent recursion on repeated prefix bytes.
1719         Ensure uninitialised "mybuf" is not accessed.
1720         (print_insn_z80): Don't zero n_fetch and n_used here,..
1721         (print_insn_z80_buf): ..do it here instead.
1722
1723 2020-01-04  Alan Modra  <amodra@gmail.com>
1724
1725         * m32r-ibld.c: Regenerate.
1726
1727 2020-01-04  Alan Modra  <amodra@gmail.com>
1728
1729         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1730
1731 2020-01-04  Alan Modra  <amodra@gmail.com>
1732
1733         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1734
1735 2020-01-04  Alan Modra  <amodra@gmail.com>
1736
1737         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1738
1739 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1740
1741         * aarch64-tbl.h (aarch64_opcode_table): Use
1742         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1743
1744 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1745
1746         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1747         forms of SUDOT and USDOT.
1748
1749 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1750
1751         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1752         uzip{1,2}.
1753         * opcodes/aarch64-dis-2.c: Re-generate.
1754
1755 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1756
1757         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1758         FMMLA encoding.
1759         * opcodes/aarch64-dis-2.c: Re-generate.
1760
1761 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1762
1763         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1764
1765 2020-01-01  Alan Modra  <amodra@gmail.com>
1766
1767         Update year range in copyright notice of all files.
1768
1769 For older changes see ChangeLog-2019
1770 \f
1771 Copyright (C) 2020 Free Software Foundation, Inc.
1772
1773 Copying and distribution of this file, with or without modification,
1774 are permitted in any medium without royalty provided the copyright
1775 notice and this notice are preserved.
1776
1777 Local Variables:
1778 mode: change-log
1779 left-margin: 8
1780 fill-column: 74
1781 version-control: never
1782 End: