opcodes/ChangeLog

   1 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
   4         compact jumps.
   5
   6 2016-12-13 Renlin Li <renlin.li@arm.com>
   7
   8         * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
   9         qualifier.
  10         (operand_general_constraint_met_p): Remove case for CP_REG.
  11         (aarch64_print_operand): Print CRn, CRm operand using imm field.
  12         * aarch64-tbl.h (QL_SYS): Use CR qualifier.
  13         (QL_SYSL): Likewise.
  14         (aarch64_opcode_table): Change CRn, CRm operand class and type.
  15         * aarch64-opc-2.c : Regenerate.
  16         * aarch64-asm-2.c : Likewise.
  17         * aarch64-dis-2.c : Likewise.
  18
  19 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  20
  21         * rx-dis.c: Include <setjmp.h>
  22         (struct private): New.
  23         (rx_get_byte): Check return value of read_memory_func, and
  24         call memory_error_func and OPCODES_SIGLONGJMP on error.
  25         (print_insn_rx): Call OPCODES_SIGSETJMP.
  26
  27 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  28
  29         * rl78-dis.c: Include <setjmp.h>.
  30         (struct private): New.
  31         (rl78_get_byte): Check return value of read_memory_func, and
  32         call memory_error_func and OPCODES_SIGLONGJMP on error.
  33         (print_insn_rl78_common): Call OPCODES_SIGJMP.
  34
  35 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  36
  37         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
  38
  39 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  40
  41         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
  42         than UINT.
  43
  44 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  45
  46         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
  47         to separate `extend' and its uninterpreted argument output.
  48         Separate hexadecimal halves of undecoded extended instructions
  49         output.
  50
  51 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  52
  53         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
  54         indentation space across.
  55
  56 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  57
  58         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
  59         adjustment for PC-relative operations following MIPS16e compact
  60         jumps or undefined RR/J(AL)R(C) encodings.
  61
  62 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  63
  64         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
  65         variable to `reglane_index'.
  66
  67 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
  68
  69         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
  70
  71 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  72
  73         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
  74
  75 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  76
  77         * mips16-opc.c (mips16_opcodes): Update comment naming structure
  78         members.
  79
  80 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  81
  82         * mips-dis.c (print_mips_disassembler_options): Reformat output.
  83
  84 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  85
  86         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
  87         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
  88
  89 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  90
  91         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
  92
  93 2016-12-01  Nick Clifton  <nickc@redhat.com>
  94
  95         PR binutils/20893
  96         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
  97         opcode designator.
  98
  99 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 100
 101         * arc-opc.c (insert_ra_chk): New function.
 102         (insert_rb_chk): Likewise.
 103         (insert_rad): Update text error message.
 104         (insert_rcd): Likewise.
 105         (insert_rhv2): Likewise.
 106         (insert_r0): Likewise.
 107         (insert_r1): Likewise.
 108         (insert_r2): Likewise.
 109         (insert_r3): Likewise.
 110         (insert_sp): Likewise.
 111         (insert_gp): Likewise.
 112         (insert_pcl): Likewise.
 113         (insert_blink): Likewise.
 114         (insert_ilink1): Likewise.
 115         (insert_ilink2): Likewise.
 116         (insert_ras): Likewise.
 117         (insert_rbs): Likewise.
 118         (insert_rcs): Likewise.
 119         (insert_simm3s): Likewise.
 120         (insert_rrange): Likewise.
 121         (insert_fpel): Likewise.
 122         (insert_blinkel): Likewise.
 123         (insert_pcel): Likewise.
 124         (insert_nps_3bit_dst): Likewise.
 125         (insert_nps_3bit_dst_short): Likewise.
 126         (insert_nps_3bit_src2_short): Likewise.
 127         (insert_nps_bitop_size_2b): Likewise.
 128         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 129         (RA_CHK): Define.
 130         (RB): Adjust.
 131         (RB_CHK): Define.
 132         (RC): Adjust.
 133         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 134         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 135         Change first insn argument to check for LP_COUNT usage.
 136         (rem): Likewise.
 137         (ld, ldd): All instructions are LOAD class.  Change first insn
 138         argument to check for LP_COUNT usage.
 139         (st, std): All instructions are STORE class.
 140         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 141         Change first insn argument to check for LP_COUNT usage.
 142         (mov): All instructions are MOVE class.  Change first insn
 143         argument to check for LP_COUNT usage.
 144
 145 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 146
 147         * arc-dis.c (is_compatible_p): Remove function.
 148         (skip_this_opcode): Don't add any decoding class to decode list.
 149         Remove warning.
 150         (find_format_from_table): Go through all opcodes, and warn if we
 151         use a guessed mnemonic.
 152
 153 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 154             Amit Pawar  <amit.pawar@amd.com>
 155
 156         PR binutils/20637
 157         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 158         instructions.
 159
 160 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 161
 162         * configure: Regenerate.
 163
 164 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 165
 166         * sparc-opc.c (HWS_V8): Definition moved from
 167         gas/config/tc-sparc.c.
 168         (HWS_V9): Likewise.
 169         (HWS_VA): Likewise.
 170         (HWS_VB): Likewise.
 171         (HWS_VC): Likewise.
 172         (HWS_VD): Likewise.
 173         (HWS_VE): Likewise.
 174         (HWS_VV): Likewise.
 175         (HWS_VM): Likewise.
 176         (HWS2_VM): Likewise.
 177         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 178         existing entries.
 179
 180 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 181
 182         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 183         instructions.
 184
 185 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 186
 187         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 188         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 189         (aarch64_opcode_table): Add fcmla and fcadd.
 190         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 191         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 192         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 193         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 194         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 195         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 196         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 197         (operand_general_constraint_met_p): Rotate and index range check.
 198         (aarch64_print_operand): Handle rotate operand.
 199         * aarch64-asm-2.c: Regenerate.
 200         * aarch64-dis-2.c: Likewise.
 201         * aarch64-opc-2.c: Likewise.
 202
 203 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 204
 205         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 206         * aarch64-asm-2.c: Regenerate.
 207         * aarch64-dis-2.c: Regenerate.
 208         * aarch64-opc-2.c: Regenerate.
 209
 210 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 211
 212         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 213         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 214         * aarch64-asm-2.c: Regenerate.
 215         * aarch64-dis-2.c: Regenerate.
 216         * aarch64-opc-2.c: Regenerate.
 217
 218 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 219
 220         * aarch64-tbl.h (QL_X1NIL): New.
 221         (arch64_opcode_table): Add ldraa, ldrab.
 222         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 223         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 224         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 225         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 226         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 227         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 228         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 229         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 230         (aarch64_print_operand): Likewise.
 231         * aarch64-asm-2.c: Regenerate.
 232         * aarch64-dis-2.c: Regenerate.
 233         * aarch64-opc-2.c: Regenerate.
 234
 235 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 236
 237         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 238         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 239         * aarch64-asm-2.c: Regenerate.
 240         * aarch64-dis-2.c: Regenerate.
 241         * aarch64-opc-2.c: Regenerate.
 242
 243 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 244
 245         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 246         (AARCH64_OPERANDS): Add Rm_SP.
 247         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 248         * aarch64-asm-2.c: Regenerate.
 249         * aarch64-dis-2.c: Regenerate.
 250         * aarch64-opc-2.c: Regenerate.
 251
 252 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 253
 254         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 255         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 256         autdzb, xpaci, xpacd.
 257         * aarch64-asm-2.c: Regenerate.
 258         * aarch64-dis-2.c: Regenerate.
 259         * aarch64-opc-2.c: Regenerate.
 260
 261 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 262
 263         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 264         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 265         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 266         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 267
 268 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 269
 270         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 271         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 272         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 273         autibsp.
 274         * aarch64-asm-2.c: Regenerate.
 275         * aarch64-dis-2.c: Regenerate.
 276
 277 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 278
 279         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 280
 281 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 282
 283         PR binutils/20799
 284         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 285         * i386-dis.c (EdqwS): Removed.
 286         (dqw_swap_mode): Likewise.
 287         (intel_operand_size): Don't check dqw_swap_mode.
 288         (OP_E_register): Likewise.
 289         (OP_E_memory): Likewise.
 290         (OP_G): Likewise.
 291         (OP_EX): Likewise.
 292         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 293         * i386-tbl.h: Regerated.
 294
 295 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 296
 297         * i386-opc.tbl: Merge AVX512F vmovq.
 298         * i386-tbl.h: Regerated.
 299
 300 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         PR binutils/20701
 303         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 304         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 305         (three_byte_table): Remove THREE_BYTE_0F7A.
 306
 307 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 308
 309         PR binutils/20775
 310         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 311         (FGRPd9_4): Replace 1 with 2.
 312         (FGRPd9_5): Replace 2 with 3.
 313         (FGRPd9_6): Replace 3 with 4.
 314         (FGRPd9_7): Replace 4 with 5.
 315         (FGRPda_5): Replace 5 with 6.
 316         (FGRPdb_4): Replace 6 with 7.
 317         (FGRPde_3): Replace 7 with 8.
 318         (FGRPdf_4): Replace 8 with 9.
 319         (fgrps): Add an entry for Bad_Opcode.
 320
 321 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 322
 323         * arc-opc.c (arc_flag_operands): Add F_DI14.
 324         (arc_flag_classes): Add C_DI14.
 325         * arc-nps400-tbl.h: Add new exc instructions.
 326
 327 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 328
 329         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 330         major opcode 0xa.
 331         * arc-nps-400-tbl.h: Add dcmac instruction.
 332         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 333         (insert_nps_rbdouble_64): Added.
 334         (extract_nps_rbdouble_64): Added.
 335         (insert_nps_proto_size): Added.
 336         (extract_nps_proto_size): Added.
 337
 338 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 339
 340         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 341         relating to long instruction processing, add new limm field.
 342         (OPCODE): Rename to...
 343         (OPCODE_32BIT_INSN): ...this.
 344         (OPCODE_AC): Delete.
 345         (skip_this_opcode): Handle different instruction lengths, update
 346         macro name.
 347         (special_flag_p): Update parameter type.
 348         (find_format_from_table): Update for more instruction lengths.
 349         (find_format_long_instructions): Delete.
 350         (find_format): Update for more instruction lengths.
 351         (arc_insn_length): Likewise.
 352         (extract_operand_value): Update for more instruction lengths.
 353         (operand_iterator_next): Remove code relating to long
 354         instructions.
 355         (arc_opcode_to_insn_type): New function.
 356         (print_insn_arc):Update for more instructions lengths.
 357         * arc-ext.c (extInstruction_t): Change argument type.
 358         * arc-ext.h (extInstruction_t): Change argument type.
 359         * arc-fxi.h: Change type unsigned to unsigned long long
 360         extensively throughout.
 361         * arc-nps400-tbl.h: Add long instructions taken from
 362         arc_long_opcodes table in arc-opc.c.
 363         * arc-opc.c: Update parameter types on insert/extract handlers.
 364         (arc_long_opcodes): Delete.
 365         (arc_num_long_opcodes): Delete.
 366         (arc_opcode_len): Update for more instruction lengths.
 367
 368 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 369
 370         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 371
 372 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 373
 374         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 375         with arc_opcode_len.
 376         (find_format_long_instructions): Likewise.
 377         * arc-opc.c (arc_opcode_len): New function.
 378
 379 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 380
 381         * arc-nps400-tbl.h: Fix some instruction masks.
 382
 383 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 384
 385         * i386-dis.c (REG_82): Removed.
 386         (X86_64_82_REG_0): Likewise.
 387         (X86_64_82_REG_1): Likewise.
 388         (X86_64_82_REG_2): Likewise.
 389         (X86_64_82_REG_3): Likewise.
 390         (X86_64_82_REG_4): Likewise.
 391         (X86_64_82_REG_5): Likewise.
 392         (X86_64_82_REG_6): Likewise.
 393         (X86_64_82_REG_7): Likewise.
 394         (X86_64_82): New.
 395         (dis386): Use X86_64_82 instead of REG_82.
 396         (reg_table): Remove REG_82.
 397         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 398         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 399         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 400         X86_64_82_REG_7.
 401
 402 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 403
 404         PR binutils/20754
 405         * i386-dis.c (REG_82): New.
 406         (X86_64_82_REG_0): Likewise.
 407         (X86_64_82_REG_1): Likewise.
 408         (X86_64_82_REG_2): Likewise.
 409         (X86_64_82_REG_3): Likewise.
 410         (X86_64_82_REG_4): Likewise.
 411         (X86_64_82_REG_5): Likewise.
 412         (X86_64_82_REG_6): Likewise.
 413         (X86_64_82_REG_7): Likewise.
 414         (dis386): Use REG_82.
 415         (reg_table): Add REG_82.
 416         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 417         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 418         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 419
 420 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 421
 422         * i386-dis.c (REG_82): Renamed to ...
 423         (REG_83): This.
 424         (dis386): Updated.
 425         (reg_table): Likewise.
 426
 427 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 428
 429         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 430         * i386-dis-evex.h (evex_table): Updated.
 431         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 432         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 433         (cpu_flags): Add CpuAVX512_4VNNIW.
 434         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 435         (i386_cpu_flags): Add cpuavx512_4vnniw.
 436         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 437         * i386-init.h: Regenerate.
 438         * i386-tbl.h: Ditto.
 439
 440 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 441
 442         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 443         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 444         * i386-dis-evex.h (evex_table): Updated.
 445         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 446         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 447         (cpu_flags): Add CpuAVX512_4FMAPS.
 448         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 449         * i386-opc.h (AVX512_4FMAP): New.
 450         (i386_cpu_flags): Add cpuavx512_4fmaps.
 451         (ImplicitQuadGroup): New.
 452         (i386_opcode_modifier): Add implicitquadgroup.
 453         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 454         * i386-init.h: Regenerate.
 455         * i386-tbl.h: Ditto.
 456
 457 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 458             Andrew Waterman <andrew@sifive.com>
 459
 460         Add support for RISC-V architecture.
 461         * configure.ac: Add entry for bfd_riscv_arch.
 462         * configure: Regenerate.
 463         * disassemble.c (disassembler): Add support for riscv.
 464         (disassembler_usage): Likewise.
 465         * riscv-dis.c: New file.
 466         * riscv-opc.c: New file.
 467
 468 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 469
 470         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 471         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 472         (rm_table): Update the RM_0FAE_REG_7 entry.
 473         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 474         (cpu_flags): Remove CpuPCOMMIT.
 475         * i386-opc.h (CpuPCOMMIT): Removed.
 476         (i386_cpu_flags): Remove cpupcommit.
 477         * i386-opc.tbl: Remove pcommit.
 478         * i386-init.h: Regenerated.
 479         * i386-tbl.h: Likewise.
 480
 481 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 482
 483         PR binutis/20705
 484         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 485         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 486         32-bit mode.  Don't check vex.register_specifier in 32-bit
 487         mode.
 488         (OP_VEX): Check for invalid mask registers.
 489
 490 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 491
 492         PR binutis/20699
 493         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 494         sizeflag.
 495
 496 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 497
 498         PR binutis/20704
 499         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 500
 501 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 502
 503         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 504         local variable to `index_regno'.
 505
 506 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 507
 508         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 509
 510 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 511
 512         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 513         usage on ISA basis.
 514
 515 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 516
 517         PR target/20666
 518         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 519
 520 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 521
 522         PR target/20667
 523         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 524         available.
 525
 526 2016-10-07  Alan Modra  <amodra@gmail.com>
 527
 528         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 529
 530 2016-10-06  Alan Modra  <amodra@gmail.com>
 531
 532         * aarch64-opc.c: Spell fall through comments consistently.
 533         * i386-dis.c: Likewise.
 534         * aarch64-dis.c: Add missing fall through comments.
 535         * aarch64-opc.c: Likewise.
 536         * arc-dis.c: Likewise.
 537         * arm-dis.c: Likewise.
 538         * i386-dis.c: Likewise.
 539         * m68k-dis.c: Likewise.
 540         * mep-asm.c: Likewise.
 541         * ns32k-dis.c: Likewise.
 542         * sh-dis.c: Likewise.
 543         * tic4x-dis.c: Likewise.
 544         * tic6x-dis.c: Likewise.
 545         * vax-dis.c: Likewise.
 546
 547 2016-10-06  Alan Modra  <amodra@gmail.com>
 548
 549         * arc-ext.c (create_map): Add missing break.
 550         * msp430-decode.opc (encode_as): Likewise.
 551         * msp430-decode.c: Regenerate.
 552
 553 2016-10-06  Alan Modra  <amodra@gmail.com>
 554
 555         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 556         * crx-dis.c (print_insn_crx): Likewise.
 557
 558 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 559
 560         PR binutils/20657
 561         * i386-dis.c (putop): Don't assign alt twice.
 562
 563 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 564
 565         PR target/20553
 566         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 567
 568 2016-09-29  Alan Modra  <amodra@gmail.com>
 569
 570         * ppc-opc.c (L): Make compulsory.
 571         (LOPT): New, optional form of L.
 572         (HTM_R): Define as LOPT.
 573         (L0, L1): Delete.
 574         (L32OPT): New, optional for 32-bit L.
 575         (L2OPT): New, 2-bit L for dcbf.
 576         (SVC_LEC): Update.
 577         (L2): Define.
 578         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 579         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 580         <dcbf>: Use L2OPT.
 581         <tlbiel, tlbie>: Use LOPT.
 582         <wclr, wclrall>: Use L2.
 583
 584 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 585
 586         * Makefile.in: Regenerate.
 587         * configure: Likewise.
 588
 589 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 590
 591         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 592         (EXTINSN2OP): Use EXTINSN2OPF.
 593         (bspeekm, bspop, modapp): New extension instructions.
 594         * arc-opc.c (F_DNZ_ND): Define.
 595         (F_DNZ_D): Likewise.
 596         (F_SIZEB1): Changed.
 597         (C_DNZ_D): Define.
 598         (C_HARD): Changed.
 599         * arc-tbl.h (dbnz): New instruction.
 600         (prealloc): Allow it for ARC EM.
 601         (xbfu): Likewise.
 602
 603 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 604
 605         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 606         after commas in addresses.
 607         (aarch64_print_operand): Likewise.
 608
 609 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 610
 611         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 612         rather than "should be" or "expected to be" in error messages.
 613
 614 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 615
 616         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 617         (print_mnemonic_name): ...here.
 618         (print_comment): New function.
 619         (print_aarch64_insn): Call it.
 620         * aarch64-opc.c (aarch64_conds): Add SVE names.
 621         (aarch64_print_operand): Print alternative condition names in
 622         a comment.
 623
 624 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 625
 626         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 627         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 628         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 629         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 630         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 631         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 632         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 633         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 634         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 635         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 636         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 637         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 638         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 639         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 640         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 641         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 642         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 643         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 644         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 645         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 646         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 647         (aarch64_feature_sve): New variable.
 648         (SVE): New macro.
 649         (_SVE_INSN): Likewise.
 650         (aarch64_opcode_table): Add SVE instructions.
 651         * aarch64-opc.h (extract_fields): Declare.
 652         * aarch64-opc-2.c: Regenerate.
 653         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 654         * aarch64-asm-2.c: Regenerate.
 655         * aarch64-dis.c (extract_fields): Make global.
 656         (do_misc_decoding): Handle the new SVE aarch64_ops.
 657         * aarch64-dis-2.c: Regenerate.
 658
 659 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 660
 661         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 662         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 663         aarch64_field_kinds.
 664         * aarch64-opc.c (fields): Add corresponding entries.
 665         * aarch64-asm.c (aarch64_get_variant): New function.
 666         (aarch64_encode_variant_using_iclass): Likewise.
 667         (aarch64_opcode_encode): Call it.
 668         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 669         (aarch64_opcode_decode): Call it.
 670
 671 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 672
 673         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 674         and FP register operands.
 675         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 676         (FLD_SVE_Vn): New aarch64_field_kinds.
 677         * aarch64-opc.c (fields): Add corresponding entries.
 678         (aarch64_print_operand): Handle the new SVE core and FP register
 679         operands.
 680         * aarch64-opc-2.c: Regenerate.
 681         * aarch64-asm-2.c: Likewise.
 682         * aarch64-dis-2.c: Likewise.
 683
 684 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 685
 686         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 687         immediate operands.
 688         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 689         * aarch64-opc.c (fields): Add corresponding entry.
 690         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 691         operands.
 692         (aarch64_print_operand): Likewise.
 693         * aarch64-opc-2.c: Regenerate.
 694         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 695         (ins_sve_float_zero_one): New inserters.
 696         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 697         (aarch64_ins_sve_float_half_two): Likewise.
 698         (aarch64_ins_sve_float_zero_one): Likewise.
 699         * aarch64-asm-2.c: Regenerate.
 700         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 701         (ext_sve_float_zero_one): New extractors.
 702         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 703         (aarch64_ext_sve_float_half_two): Likewise.
 704         (aarch64_ext_sve_float_zero_one): Likewise.
 705         * aarch64-dis-2.c: Regenerate.
 706
 707 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 708
 709         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 710         integer immediate operands.
 711         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 712         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 713         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 714         * aarch64-opc.c (fields): Add corresponding entries.
 715         (operand_general_constraint_met_p): Handle the new SVE integer
 716         immediate operands.
 717         (aarch64_print_operand): Likewise.
 718         (aarch64_sve_dupm_mov_immediate_p): New function.
 719         * aarch64-opc-2.c: Regenerate.
 720         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 721         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 722         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 723         (aarch64_ins_limm): ...here.
 724         (aarch64_ins_inv_limm): New function.
 725         (aarch64_ins_sve_aimm): Likewise.
 726         (aarch64_ins_sve_asimm): Likewise.
 727         (aarch64_ins_sve_limm_mov): Likewise.
 728         (aarch64_ins_sve_shlimm): Likewise.
 729         (aarch64_ins_sve_shrimm): Likewise.
 730         * aarch64-asm-2.c: Regenerate.
 731         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 732         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 733         * aarch64-dis.c (decode_limm): New function, split out from...
 734         (aarch64_ext_limm): ...here.
 735         (aarch64_ext_inv_limm): New function.
 736         (decode_sve_aimm): Likewise.
 737         (aarch64_ext_sve_aimm): Likewise.
 738         (aarch64_ext_sve_asimm): Likewise.
 739         (aarch64_ext_sve_limm_mov): Likewise.
 740         (aarch64_top_bit): Likewise.
 741         (aarch64_ext_sve_shlimm): Likewise.
 742         (aarch64_ext_sve_shrimm): Likewise.
 743         * aarch64-dis-2.c: Regenerate.
 744
 745 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 746
 747         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 748         operands.
 749         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 750         the AARCH64_MOD_MUL_VL entry.
 751         (value_aligned_p): Cope with non-power-of-two alignments.
 752         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 753         (print_immediate_offset_address): Likewise.
 754         (aarch64_print_operand): Likewise.
 755         * aarch64-opc-2.c: Regenerate.
 756         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 757         (ins_sve_addr_ri_s9xvl): New inserters.
 758         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 759         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 760         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 761         * aarch64-asm-2.c: Regenerate.
 762         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 763         (ext_sve_addr_ri_s9xvl): New extractors.
 764         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 765         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 766         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 767         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 768         * aarch64-dis-2.c: Regenerate.
 769
 770 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 771
 772         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 773         address operands.
 774         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 775         (FLD_SVE_xs_22): New aarch64_field_kinds.
 776         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 777         (get_operand_specific_data): New function.
 778         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 779         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 780         (operand_general_constraint_met_p): Handle the new SVE address
 781         operands.
 782         (sve_reg): New array.
 783         (get_addr_sve_reg_name): New function.
 784         (aarch64_print_operand): Handle the new SVE address operands.
 785         * aarch64-opc-2.c: Regenerate.
 786         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 787         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 788         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 789         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 790         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 791         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 792         (aarch64_ins_sve_addr_zi_u5): Likewise.
 793         (aarch64_ins_sve_addr_zz): Likewise.
 794         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 795         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 796         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 797         * aarch64-asm-2.c: Regenerate.
 798         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 799         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 800         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 801         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 802         (aarch64_ext_sve_addr_ri_u6): Likewise.
 803         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 804         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 805         (aarch64_ext_sve_addr_zi_u5): Likewise.
 806         (aarch64_ext_sve_addr_zz): Likewise.
 807         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 808         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 809         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 810         * aarch64-dis-2.c: Regenerate.
 811
 812 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 813
 814         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 815         AARCH64_OPND_SVE_PATTERN_SCALED.
 816         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 817         * aarch64-opc.c (fields): Add a corresponding entry.
 818         (set_multiplier_out_of_range_error): New function.
 819         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 820         (operand_general_constraint_met_p): Handle
 821         AARCH64_OPND_SVE_PATTERN_SCALED.
 822         (print_register_offset_address): Use PRIi64 to print the
 823         shift amount.
 824         (aarch64_print_operand): Likewise.  Handle
 825         AARCH64_OPND_SVE_PATTERN_SCALED.
 826         * aarch64-opc-2.c: Regenerate.
 827         * aarch64-asm.h (ins_sve_scale): New inserter.
 828         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 829         * aarch64-asm-2.c: Regenerate.
 830         * aarch64-dis.h (ext_sve_scale): New inserter.
 831         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 832         * aarch64-dis-2.c: Regenerate.
 833
 834 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 835
 836         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 837         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 838         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 839         (FLD_SVE_prfop): Likewise.
 840         * aarch64-opc.c: Include libiberty.h.
 841         (aarch64_sve_pattern_array): New variable.
 842         (aarch64_sve_prfop_array): Likewise.
 843         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 844         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 845         AARCH64_OPND_SVE_PRFOP.
 846         * aarch64-asm-2.c: Regenerate.
 847         * aarch64-dis-2.c: Likewise.
 848         * aarch64-opc-2.c: Likewise.
 849
 850 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 851
 852         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 853         AARCH64_OPND_QLF_P_[ZM].
 854         (aarch64_print_operand): Print /z and /m where appropriate.
 855
 856 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 857
 858         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 859         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 860         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 861         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 862         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 863         * aarch64-opc.c (fields): Add corresponding entries here.
 864         (operand_general_constraint_met_p): Check that SVE register lists
 865         have the correct length.  Check the ranges of SVE index registers.
 866         Check for cases where p8-p15 are used in 3-bit predicate fields.
 867         (aarch64_print_operand): Handle the new SVE operands.
 868         * aarch64-opc-2.c: Regenerate.
 869         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 870         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 871         (aarch64_ins_sve_reglist): Likewise.
 872         * aarch64-asm-2.c: Regenerate.
 873         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 874         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 875         (aarch64_ext_sve_reglist): Likewise.
 876         * aarch64-dis-2.c: Regenerate.
 877
 878 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 879
 880         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 881         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 882         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 883         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 884         tied operands.
 885
 886 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 887
 888         * aarch64-opc.c (get_offset_int_reg_name): New function.
 889         (print_immediate_offset_address): Likewise.
 890         (print_register_offset_address): Take the base and offset
 891         registers as parameters.
 892         (aarch64_print_operand): Update caller accordingly.  Use
 893         print_immediate_offset_address.
 894
 895 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 896
 897         * aarch64-opc.c (BANK): New macro.
 898         (R32, R64): Take a register number as argument
 899         (int_reg): Use BANK.
 900
 901 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 902
 903         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 904         (aarch64_print_operand): Update accordingly.
 905
 906 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 907
 908         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 909         for FPIMM.
 910         * aarch64-asm.h (ins_fpimm): New inserter.
 911         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 912         * aarch64-asm-2.c: Regenerate.
 913         * aarch64-dis.h (ext_fpimm): New extractor.
 914         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 915         (aarch64_ext_fpimm): New function.
 916         * aarch64-dis-2.c: Regenerate.
 917
 918 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 919
 920         * aarch64-asm.c: Include libiberty.h.
 921         (insert_fields): New function.
 922         (aarch64_ins_imm): Use it.
 923         * aarch64-dis.c (extract_fields): New function.
 924         (aarch64_ext_imm): Use it.
 925
 926 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 927
 928         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 929         with an esize parameter.
 930         (operand_general_constraint_met_p): Update accordingly.
 931         Fix misindented code.
 932         * aarch64-asm.c (aarch64_ins_limm): Update call to
 933         aarch64_logical_immediate_p.
 934
 935 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 936
 937         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 938
 939 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 940
 941         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 942
 943 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 944
 945         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 946
 947 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 948
 949         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 950         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 951         xor3>: Delete mnemonics.
 952         <cp_abort>: Rename mnemonic from ...
 953         <cpabort>: ...to this.
 954         <setb>: Change to a X form instruction.
 955         <sync>: Change to 1 operand form.
 956         <copy>: Delete mnemonic.
 957         <copy_first>: Rename mnemonic from ...
 958         <copy>: ...to this.
 959         <paste, paste.>: Delete mnemonics.
 960         <paste_last>: Rename mnemonic from ...
 961         <paste.>: ...to this.
 962
 963 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 964
 965         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 966
 967 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 968
 969         * s390-mkopc.c (main): Support alternate arch strings.
 970
 971 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 972
 973         * s390-opc.txt: Fix kmctr instruction type.
 974
 975 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 976
 977         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 978         * i386-init.h: Regenerated.
 979
 980 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 981
 982         * opcodes/arc-dis.c (print_insn_arc): Changed.
 983
 984 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 985
 986         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 987         camellia_fl.
 988
 989 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 990
 991         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 992         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 993         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 994
 995 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 996
 997         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 998         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 999         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1000         PREFIX_MOD_3_0FAE_REG_4.
1001         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1002         PREFIX_MOD_3_0FAE_REG_4.
1003         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1004         (cpu_flags): Add CpuPTWRITE.
1005         * i386-opc.h (CpuPTWRITE): New.
1006         (i386_cpu_flags): Add cpuptwrite.
1007         * i386-opc.tbl: Add ptwrite instruction.
1008         * i386-init.h: Regenerated.
1009         * i386-tbl.h: Likewise.
1010
1011 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1012
1013         * arc-dis.h: Wrap around in extern "C".
1014
1015 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1016
1017         * aarch64-tbl.h (V8_2_INSN): New macro.
1018         (aarch64_opcode_table): Use it.
1019
1020 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1021
1022         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1023         CORE_INSN, __FP_INSN and SIMD_INSN.
1024
1025 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1026
1027         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1028         (aarch64_opcode_table): Update uses accordingly.
1029
1030 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1031         Kwok Cheung Yeung  <kcy@codesourcery.com>
1032
1033         opcodes/
1034         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1035         'e_cmplwi' to 'e_cmpli' instead.
1036         (OPVUPRT, OPVUPRT_MASK): Define.
1037         (powerpc_opcodes): Add E200Z4 insns.
1038         (vle_opcodes): Add context save/restore insns.
1039
1040 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1041
1042         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1043         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1044         "j".
1045
1046 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1047
1048         * arc-nps400-tbl.h: Change block comments to GNU format.
1049         * arc-dis.c: Add new globals addrtypenames,
1050         addrtypenames_max, and addtypeunknown.
1051         (get_addrtype): New function.
1052         (print_insn_arc): Print colons and address types when
1053         required.
1054         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1055         define insert and extract functions for all address types.
1056         (arc_operands): Add operands for colon and all address
1057         types.
1058         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1059         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1060         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1061         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1062         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1063         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1064
1065 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1066
1067         * configure: Regenerated.
1068
1069 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1070
1071         * arc-dis.c (skipclass): New structure.
1072         (decodelist): New variable.
1073         (is_compatible_p): New function.
1074         (new_element): Likewise.
1075         (skip_class_p): Likewise.
1076         (find_format_from_table): Use skip_class_p function.
1077         (find_format): Decode first the extension instructions.
1078         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1079         e_flags.
1080         (parse_option): New function.
1081         (parse_disassembler_options): Likewise.
1082         (print_arc_disassembler_options): Likewise.
1083         (print_insn_arc): Use parse_disassembler_options function.  Proper
1084         select ARCv2 cpu variant.
1085         * disassemble.c (disassembler_usage): Add ARC disassembler
1086         options.
1087
1088 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1089
1090         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1091         annotation from the "nal" entry and reorder it beyond "bltzal".
1092
1093 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1094
1095         * sparc-opc.c (ldtxa): New macro.
1096         (sparc_opcodes): Use the macro defined above to add entries for
1097         the LDTXA instructions.
1098         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1099         instruction.
1100
1101 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1102
1103         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1104         and "jmpc".
1105
1106 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1107
1108         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1109         (movzb): Adjust to cover all permitted suffixes.
1110         (movzw): New.
1111         * i386-tbl.h: Re-generate.
1112
1113 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1114
1115         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1116         (lgdt): Remove Tbyte from non-64-bit variant.
1117         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1118         xsaves64, xsavec64): Remove Disp16.
1119         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1120         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1121         64-bit variants.
1122         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1123         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1124         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1125         64-bit variants.
1126         * i386-tbl.h: Re-generate.
1127
1128 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1129
1130         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1131         * i386-tbl.h: Re-generate.
1132
1133 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1134
1135         * arm-dis.c (print_insn): Fix typo in comment.
1136
1137 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1138
1139         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1140         range of ldst_elemlist operands.
1141         (print_register_list): Use PRIi64 to print the index.
1142         (aarch64_print_operand): Likewise.
1143
1144 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1145
1146         * mcore-opc.h: Remove sentinal.
1147         * mcore-dis.c (print_insn_mcore): Adjust.
1148
1149 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1150
1151         * arc-opc.c: Correct description of availability of NPS400
1152         features.
1153
1154 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1155
1156         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1157         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1158         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1159         xor3>: New mnemonics.
1160         <setb>: Change to a VX form instruction.
1161         (insert_sh6): Add support for rldixor.
1162         (extract_sh6): Likewise.
1163
1164 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1165
1166         * arc-ext.h: Wrap in extern C.
1167
1168 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1169
1170         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1171         Use same method for determining instruction length on ARC700 and
1172         NPS-400.
1173         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1174         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1175         with the NPS400 subclass.
1176         * arc-opc.c: Likewise.
1177
1178 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1179
1180         * sparc-opc.c (rdasr): New macro.
1181         (wrasr): Likewise.
1182         (rdpr): Likewise.
1183         (wrpr): Likewise.
1184         (rdhpr): Likewise.
1185         (wrhpr): Likewise.
1186         (sparc_opcodes): Use the macros above to fix and expand the
1187         definition of read/write instructions from/to
1188         asr/privileged/hyperprivileged instructions.
1189         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1190         %hva_mask_nz.  Prefer softint_set and softint_clear over
1191         set_softint and clear_softint.
1192         (print_insn_sparc): Support %ver in Rd.
1193
1194 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1195
1196         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1197         architecture according to the hardware capabilities they require.
1198
1199 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1200
1201         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1202         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1203         bfd_mach_sparc_v9{c,d,e,v,m}.
1204         * sparc-opc.c (MASK_V9C): Define.
1205         (MASK_V9D): Likewise.
1206         (MASK_V9E): Likewise.
1207         (MASK_V9V): Likewise.
1208         (MASK_V9M): Likewise.
1209         (v6): Add MASK_V9{C,D,E,V,M}.
1210         (v6notlet): Likewise.
1211         (v7): Likewise.
1212         (v8): Likewise.
1213         (v9): Likewise.
1214         (v9andleon): Likewise.
1215         (v9a): Likewise.
1216         (v9b): Likewise.
1217         (v9c): Define.
1218         (v9d): Likewise.
1219         (v9e): Likewise.
1220         (v9v): Likewise.
1221         (v9m): Likewise.
1222         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1223
1224 2016-06-15  Nick Clifton  <nickc@redhat.com>
1225
1226         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1227         constants to match expected behaviour.
1228         (nds32_parse_opcode): Likewise.  Also for whitespace.
1229
1230 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1231
1232         * arc-opc.c (extract_rhv1): Extract value from insn.
1233
1234 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1235
1236         * arc-nps400-tbl.h: Add ldbit instruction.
1237         * arc-opc.c: Add flag classes required for ldbit.
1238
1239 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1240
1241         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1242         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1243         support the above instructions.
1244
1245 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1246
1247         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1248         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1249         csma, cbba, zncv, and hofs.
1250         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1251         support the above instructions.
1252
1253 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1254
1255         * arc-nps400-tbl.h: Add andab and orab instructions.
1256
1257 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1258
1259         * arc-nps400-tbl.h: Add addl-like instructions.
1260
1261 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1262
1263         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1264
1265 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1266
1267         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1268         instructions.
1269
1270 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1271
1272         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1273         variable.
1274         (init_disasm): Handle new command line option "insnlength".
1275         (print_s390_disassembler_options): Mention new option in help
1276         output.
1277         (print_insn_s390): Use the encoded insn length when dumping
1278         unknown instructions.
1279
1280 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1281
1282         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1283          to the address and set as symbol address for LDS/ STS immediate operands.
1284
1285 2016-06-07  Alan Modra  <amodra@gmail.com>
1286
1287         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1288         cpu for "vle" to e500.
1289         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1290         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1291         (PPCNONE): Delete, substitute throughout.
1292         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1293         except for major opcode 4 and 31.
1294         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1295
1296 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1297
1298         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1299         ARM_EXT_RAS in relevant entries.
1300
1301 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1302
1303         PR binutils/20196
1304         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1305         opcodes for E6500.
1306
1307 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1308
1309         PR binutis/18386
1310         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1311         (indir_v_mode): New.
1312         Add comments for '&'.
1313         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1314         (putop): Handle '&'.
1315         (intel_operand_size): Handle indir_v_mode.
1316         (OP_E_register): Likewise.
1317         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1318         64-bit indirect call/jmp for AMD64.
1319         * i386-tbl.h: Regenerated
1320
1321 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1322
1323         * arc-dis.c (struct arc_operand_iterator): New structure.
1324         (find_format_from_table): All the old content from find_format,
1325         with some minor adjustments, and parameter renaming.
1326         (find_format_long_instructions): New function.
1327         (find_format): Rewritten.
1328         (arc_insn_length): Add LSB parameter.
1329         (extract_operand_value): New function.
1330         (operand_iterator_next): New function.
1331         (print_insn_arc): Use new functions to find opcode, and iterator
1332         over operands.
1333         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1334         (extract_nps_3bit_dst_short): New function.
1335         (insert_nps_3bit_src2_short): New function.
1336         (extract_nps_3bit_src2_short): New function.
1337         (insert_nps_bitop1_size): New function.
1338         (extract_nps_bitop1_size): New function.
1339         (insert_nps_bitop2_size): New function.
1340         (extract_nps_bitop2_size): New function.
1341         (insert_nps_bitop_mod4_msb): New function.
1342         (extract_nps_bitop_mod4_msb): New function.
1343         (insert_nps_bitop_mod4_lsb): New function.
1344         (extract_nps_bitop_mod4_lsb): New function.
1345         (insert_nps_bitop_dst_pos3_pos4): New function.
1346         (extract_nps_bitop_dst_pos3_pos4): New function.
1347         (insert_nps_bitop_ins_ext): New function.
1348         (extract_nps_bitop_ins_ext): New function.
1349         (arc_operands): Add new operands.
1350         (arc_long_opcodes): New global array.
1351         (arc_num_long_opcodes): New global.
1352         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1353
1354 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1355
1356         * nds32-asm.h: Add extern "C".
1357         * sh-opc.h: Likewise.
1358
1359 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1360
1361         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1362         0,b,limm to the rflt instruction.
1363
1364 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1365
1366         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1367         constant.
1368
1369 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1370
1371         PR gas/20145
1372         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1373         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1374         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1375         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1376         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1377         * i386-init.h: Regenerated.
1378
1379 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1380
1381         PR gas/20145
1382         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1383         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1384         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1385         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1386         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1387         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1388         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1389         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1390         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1391         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1392         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1393         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1394         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1395         CpuRegMask for AVX512.
1396         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1397         and CpuRegMask.
1398         (set_bitfield_from_cpu_flag_init): New function.
1399         (set_bitfield): Remove const on f.  Call
1400         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1401         * i386-opc.h (CpuRegMMX): New.
1402         (CpuRegXMM): Likewise.
1403         (CpuRegYMM): Likewise.
1404         (CpuRegZMM): Likewise.
1405         (CpuRegMask): Likewise.
1406         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1407         and cpuregmask.
1408         * i386-init.h: Regenerated.
1409         * i386-tbl.h: Likewise.
1410
1411 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1412
1413         PR gas/20154
1414         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1415         (opcode_modifiers): Add AMD64 and Intel64.
1416         (main): Properly verify CpuMax.
1417         * i386-opc.h (CpuAMD64): Removed.
1418         (CpuIntel64): Likewise.
1419         (CpuMax): Set to CpuNo64.
1420         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1421         (AMD64): New.
1422         (Intel64): Likewise.
1423         (i386_opcode_modifier): Add amd64 and intel64.
1424         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1425         on call and jmp.
1426         * i386-init.h: Regenerated.
1427         * i386-tbl.h: Likewise.
1428
1429 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1430
1431         PR gas/20154
1432         * i386-gen.c (main): Fail if CpuMax is incorrect.
1433         * i386-opc.h (CpuMax): Set to CpuIntel64.
1434         * i386-tbl.h: Regenerated.
1435
1436 2016-05-27  Nick Clifton  <nickc@redhat.com>
1437
1438         PR target/20150
1439         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1440         (msp430dis_opcode_unsigned): New function.
1441         (msp430dis_opcode_signed): New function.
1442         (msp430_singleoperand): Use the new opcode reading functions.
1443         Only disassenmble bytes if they were successfully read.
1444         (msp430_doubleoperand): Likewise.
1445         (msp430_branchinstr): Likewise.
1446         (msp430x_callx_instr): Likewise.
1447         (print_insn_msp430): Check that it is safe to read bytes before
1448         attempting disassembly.  Use the new opcode reading functions.
1449
1450 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1451
1452         * ppc-opc.c (CY): New define.  Document it.
1453         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1454
1455 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1456
1457         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1458         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1459         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1460         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1461         CPU_ANY_AVX_FLAGS.
1462         * i386-init.h: Regenerated.
1463
1464 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1465
1466         PR gas/20141
1467         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1468         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1469         * i386-init.h: Regenerated.
1470
1471 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1472
1473         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1474         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1475         * i386-init.h: Regenerated.
1476
1477 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1478
1479         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1480         information.
1481         (print_insn_arc): Set insn_type information.
1482         * arc-opc.c (C_CC): Add F_CLASS_COND.
1483         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1484         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1485         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1486         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1487         (brne, brne_s, jeq_s, jne_s): Likewise.
1488
1489 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1490
1491         * arc-tbl.h (neg): New instruction variant.
1492
1493 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1494
1495         * arc-dis.c (find_format, find_format, get_auxreg)
1496         (print_insn_arc): Changed.
1497         * arc-ext.h (INSERT_XOP): Likewise.
1498
1499 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1500
1501         * tic54x-dis.c (sprint_mmr): Adjust.
1502         * tic54x-opc.c: Likewise.
1503
1504 2016-05-19  Alan Modra  <amodra@gmail.com>
1505
1506         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1507
1508 2016-05-19  Alan Modra  <amodra@gmail.com>
1509
1510         * ppc-opc.c: Formatting.
1511         (NSISIGNOPT): Define.
1512         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1513
1514 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1515
1516         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1517         replacing references to `micromips_ase' throughout.
1518         (_print_insn_mips): Don't use file-level microMIPS annotation to
1519         determine the disassembly mode with the symbol table.
1520
1521 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1522
1523         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1524
1525 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1526
1527         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1528         mips64r6.
1529         * mips-opc.c (D34): New macro.
1530         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1531
1532 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1533
1534         * i386-dis.c (prefix_table): Add RDPID instruction.
1535         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1536         (cpu_flags): Add RDPID bitfield.
1537         * i386-opc.h (enum): Add RDPID element.
1538         (i386_cpu_flags): Add RDPID field.
1539         * i386-opc.tbl: Add RDPID instruction.
1540         * i386-init.h: Regenerate.
1541         * i386-tbl.h: Regenerate.
1542
1543 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1544
1545         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1546         branch type of a symbol.
1547         (print_insn): Likewise.
1548
1549 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1550
1551         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1552         Mainline Security Extensions instructions.
1553         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1554         Extensions instructions.
1555         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1556         instructions.
1557         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1558         special registers.
1559
1560 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1561
1562         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1563
1564 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1565
1566         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1567         (arcExtMap_genOpcode): Likewise.
1568         * arc-opc.c (arg_32bit_rc): Define new variable.
1569         (arg_32bit_u6): Likewise.
1570         (arg_32bit_limm): Likewise.
1571
1572 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1573
1574         * aarch64-gen.c (VERIFIER): Define.
1575         * aarch64-opc.c (VERIFIER): Define.
1576         (verify_ldpsw): Use static linkage.
1577         * aarch64-opc.h (verify_ldpsw): Remove.
1578         * aarch64-tbl.h: Use VERIFIER for verifiers.
1579
1580 2016-04-28  Nick Clifton  <nickc@redhat.com>
1581
1582         PR target/19722
1583         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1584         * aarch64-opc.c (verify_ldpsw): New function.
1585         * aarch64-opc.h (verify_ldpsw): New prototype.
1586         * aarch64-tbl.h: Add initialiser for verifier field.
1587         (LDPSW): Set verifier to verify_ldpsw.
1588
1589 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1590
1591         PR binutils/19983
1592         PR binutils/19984
1593         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1594         smaller than address size.
1595
1596 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1597
1598         * alpha-dis.c: Regenerate.
1599         * crx-dis.c: Likewise.
1600         * disassemble.c: Likewise.
1601         * epiphany-opc.c: Likewise.
1602         * fr30-opc.c: Likewise.
1603         * frv-opc.c: Likewise.
1604         * ip2k-opc.c: Likewise.
1605         * iq2000-opc.c: Likewise.
1606         * lm32-opc.c: Likewise.
1607         * lm32-opinst.c: Likewise.
1608         * m32c-opc.c: Likewise.
1609         * m32r-opc.c: Likewise.
1610         * m32r-opinst.c: Likewise.
1611         * mep-opc.c: Likewise.
1612         * mt-opc.c: Likewise.
1613         * or1k-opc.c: Likewise.
1614         * or1k-opinst.c: Likewise.
1615         * tic80-opc.c: Likewise.
1616         * xc16x-opc.c: Likewise.
1617         * xstormy16-opc.c: Likewise.
1618
1619 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1620
1621         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1622         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1623         calcsd, and calcxd instructions.
1624         * arc-opc.c (insert_nps_bitop_size): Delete.
1625         (extract_nps_bitop_size): Delete.
1626         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1627         (extract_nps_qcmp_m3): Define.
1628         (extract_nps_qcmp_m2): Define.
1629         (extract_nps_qcmp_m1): Define.
1630         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1631         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1632         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1633         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1634         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1635         NPS_QCMP_M3.
1636
1637 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1638
1639         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1640
1641 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1642
1643         * Makefile.in: Regenerated with automake 1.11.6.
1644         * aclocal.m4: Likewise.
1645
1646 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1647
1648         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1649         instructions.
1650         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1651         (extract_nps_cmem_uimm16): New function.
1652         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1653
1654 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1655
1656         * arc-dis.c (arc_insn_length): New function.
1657         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1658         (find_format): Change insnLen parameter to unsigned.
1659
1660 2016-04-13  Nick Clifton  <nickc@redhat.com>
1661
1662         PR target/19937
1663         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1664         the LD.B and LD.BU instructions.
1665
1666 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1667
1668         * arc-dis.c (find_format): Check for extension flags.
1669         (print_flags): New function.
1670         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1671         .extAuxRegister.
1672         * arc-ext.c (arcExtMap_coreRegName): Use
1673         LAST_EXTENSION_CORE_REGISTER.
1674         (arcExtMap_coreReadWrite): Likewise.
1675         (dump_ARC_extmap): Update printing.
1676         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1677         (arc_aux_regs): Add cpu field.
1678         * arc-regs.h: Add cpu field, lower case name aux registers.
1679
1680 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1681
1682         * arc-tbl.h: Add rtsc, sleep with no arguments.
1683
1684 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1685
1686         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1687         Initialize.
1688         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1689         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1690         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1691         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1692         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1693         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1694         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1695         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1696         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1697         (arc_opcode arc_opcodes): Null terminate the array.
1698         (arc_num_opcodes): Remove.
1699         * arc-ext.h (INSERT_XOP): Define.
1700         (extInstruction_t): Likewise.
1701         (arcExtMap_instName): Delete.
1702         (arcExtMap_insn): New function.
1703         (arcExtMap_genOpcode): Likewise.
1704         * arc-ext.c (ExtInstruction): Remove.
1705         (create_map): Zero initialize instruction fields.
1706         (arcExtMap_instName): Remove.
1707         (arcExtMap_insn): New function.
1708         (dump_ARC_extmap): More info while debuging.
1709         (arcExtMap_genOpcode): New function.
1710         * arc-dis.c (find_format): New function.
1711         (print_insn_arc): Use find_format.
1712         (arc_get_disassembler): Enable dump_ARC_extmap only when
1713         debugging.
1714
1715 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1716
1717         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1718         instruction bits out.
1719
1720 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1721
1722         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1723         * arc-opc.c (arc_flag_operands): Add new flags.
1724         (arc_flag_classes): Add new classes.
1725
1726 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1727
1728         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1729
1730 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1731
1732         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1733         encode1, rflt, crc16, and crc32 instructions.
1734         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1735         (arc_flag_classes): Add C_NPS_R.
1736         (insert_nps_bitop_size_2b): New function.
1737         (extract_nps_bitop_size_2b): Likewise.
1738         (insert_nps_bitop_uimm8): Likewise.
1739         (extract_nps_bitop_uimm8): Likewise.
1740         (arc_operands): Add new operand entries.
1741
1742 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1743
1744         * arc-regs.h: Add a new subclass field.  Add double assist
1745         accumulator register values.
1746         * arc-tbl.h: Use DPA subclass to mark the double assist
1747         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1748         * arc-opc.c (RSP): Define instead of SP.
1749         (arc_aux_regs): Add the subclass field.
1750
1751 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1752
1753         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1754
1755 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1756
1757         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1758         NPS_R_SRC1.
1759
1760 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1761
1762         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1763         issues.  No functional changes.
1764
1765 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1766
1767         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1768         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1769         (RTT): Remove duplicate.
1770         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1771         (PCT_CONFIG*): Remove.
1772         (D1L, D1H, D2H, D2L): Define.
1773
1774 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1775
1776         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1777
1778 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1779
1780         * arc-tbl.h (invld07): Remove.
1781         * arc-ext-tbl.h: New file.
1782         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1783         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1784
1785 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1786
1787         Fix -Wstack-usage warnings.
1788         * aarch64-dis.c (print_operands): Substitute size.
1789         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1790
1791 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1792
1793         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1794         to get a proper diagnostic when an invalid ASR register is used.
1795
1796 2016-03-22  Nick Clifton  <nickc@redhat.com>
1797
1798         * configure: Regenerate.
1799
1800 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1801
1802         * arc-nps400-tbl.h: New file.
1803         * arc-opc.c: Add top level comment.
1804         (insert_nps_3bit_dst): New function.
1805         (extract_nps_3bit_dst): New function.
1806         (insert_nps_3bit_src2): New function.
1807         (extract_nps_3bit_src2): New function.
1808         (insert_nps_bitop_size): New function.
1809         (extract_nps_bitop_size): New function.
1810         (arc_flag_operands): Add nps400 entries.
1811         (arc_flag_classes): Add nps400 entries.
1812         (arc_operands): Add nps400 entries.
1813         (arc_opcodes): Add nps400 include.
1814
1815 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1816
1817         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1818         the new class enum values.
1819
1820 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1821
1822         * arc-dis.c (print_insn_arc): Handle nps400.
1823
1824 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1825
1826         * arc-opc.c (BASE): Delete.
1827
1828 2016-03-18  Nick Clifton  <nickc@redhat.com>
1829
1830         PR target/19721
1831         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1832         of MOV insn that aliases an ORR insn.
1833
1834 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1835
1836         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1837
1838 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1839
1840         * mcore-opc.h: Add const qualifiers.
1841         * microblaze-opc.h (struct op_code_struct): Likewise.
1842         * sh-opc.h: Likewise.
1843         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1844         (tic4x_print_op): Likewise.
1845
1846 2016-03-02  Alan Modra  <amodra@gmail.com>
1847
1848         * or1k-desc.h: Regenerate.
1849         * fr30-ibld.c: Regenerate.
1850         * rl78-decode.c: Regenerate.
1851
1852 2016-03-01  Nick Clifton  <nickc@redhat.com>
1853
1854         PR target/19747
1855         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1856
1857 2016-02-24  Renlin Li  <renlin.li@arm.com>
1858
1859         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1860         (print_insn_coprocessor): Support fp16 instructions.
1861
1862 2016-02-24  Renlin Li  <renlin.li@arm.com>
1863
1864         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1865         vminnm, vrint(mpna).
1866
1867 2016-02-24  Renlin Li  <renlin.li@arm.com>
1868
1869         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1870         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1871
1872 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1873
1874         * i386-dis.c (print_insn): Parenthesize expression to prevent
1875         truncated addresses.
1876         (OP_J): Likewise.
1877
1878 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1879             Janek van Oirschot  <jvanoirs@synopsys.com>
1880
1881         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1882         variable.
1883
1884 2016-02-04  Nick Clifton  <nickc@redhat.com>
1885
1886         PR target/19561
1887         * msp430-dis.c (print_insn_msp430): Add a special case for
1888         decoding an RRC instruction with the ZC bit set in the extension
1889         word.
1890
1891 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1892
1893         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1894         * epiphany-ibld.c: Regenerate.
1895         * fr30-ibld.c: Regenerate.
1896         * frv-ibld.c: Regenerate.
1897         * ip2k-ibld.c: Regenerate.
1898         * iq2000-ibld.c: Regenerate.
1899         * lm32-ibld.c: Regenerate.
1900         * m32c-ibld.c: Regenerate.
1901         * m32r-ibld.c: Regenerate.
1902         * mep-ibld.c: Regenerate.
1903         * mt-ibld.c: Regenerate.
1904         * or1k-ibld.c: Regenerate.
1905         * xc16x-ibld.c: Regenerate.
1906         * xstormy16-ibld.c: Regenerate.
1907
1908 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1909
1910         * epiphany-dis.c: Regenerated from latest cpu files.
1911
1912 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1913
1914         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1915         test bit.
1916
1917 2016-01-25  Renlin Li  <renlin.li@arm.com>
1918
1919         * arm-dis.c (mapping_symbol_for_insn): New function.
1920         (find_ifthen_state): Call mapping_symbol_for_insn().
1921
1922 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1923
1924         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1925         of MSR UAO immediate operand.
1926
1927 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1928
1929         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1930         instruction support.
1931
1932 2016-01-17  Alan Modra  <amodra@gmail.com>
1933
1934         * configure: Regenerate.
1935
1936 2016-01-14  Nick Clifton  <nickc@redhat.com>
1937
1938         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1939         instructions that can support stack pointer operations.
1940         * rl78-decode.c: Regenerate.
1941         * rl78-dis.c: Fix display of stack pointer in MOVW based
1942         instructions.
1943
1944 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1945
1946         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1947         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1948         erxtatus_el1 and erxaddr_el1.
1949
1950 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1951
1952         * arm-dis.c (arm_opcodes): Add "esb".
1953         (thumb_opcodes): Likewise.
1954
1955 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1956
1957         * ppc-opc.c <xscmpnedp>: Delete.
1958         <xvcmpnedp>: Likewise.
1959         <xvcmpnedp.>: Likewise.
1960         <xvcmpnesp>: Likewise.
1961         <xvcmpnesp.>: Likewise.
1962
1963 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1964
1965         PR gas/13050
1966         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1967         addition to ISA_A.
1968
1969 2016-01-01  Alan Modra  <amodra@gmail.com>
1970
1971         Update year range in copyright notice of all files.
1972
1973 For older changes see ChangeLog-2015
1974 \f
1975 Copyright (C) 2016 Free Software Foundation, Inc.
1976
1977 Copying and distribution of this file, with or without modification,
1978 are permitted in any medium without royalty provided the copyright
1979 notice and this notice are preserved.
1980
1981 Local Variables:
1982 mode: change-log
1983 left-margin: 8
1984 fill-column: 74
1985 version-control: never
1986 End: