1 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
3 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
5 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
7 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
8 are used when extracting signed fields and converting them to
9 potentially 64-bit types.
11 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
13 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
14 * Makefile.in: Re-generate.
15 * aclocal.m4: Re-generate.
16 * configure: Re-generate.
17 * configure.ac: Remove check for -Wno-missing-field-initializers.
18 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
19 (csky_v2_opcodes): Likewise.
21 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
23 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
25 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
27 * nds32-asm.c (operand_fields): Remove the unused fields.
28 (nds32_opcodes): Remove the unused instructions.
29 * nds32-dis.c (nds32_ex9_info): Removed.
30 (nds32_parse_opcode): Updated.
31 (print_insn_nds32): Likewise.
32 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
33 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
34 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
35 build_opcode_hash_table): New functions.
36 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
37 nds32_opcode_table): New.
38 (hw_ktabs): Declare it to a pointer rather than an array.
39 (build_hash_table): Removed.
40 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
41 SYN_ROPT and upadte HW_GPR and HW_INT.
42 * nds32-dis.c (keywords): Remove const.
43 (match_field): New function.
44 (nds32_parse_opcode): Updated.
45 * disassemble.c (disassemble_init_for_target):
46 Add disassemble_init_nds32.
47 * nds32-dis.c (eum map_type): New.
48 (nds32_private_data): Likewise.
49 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
50 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
51 (print_insn_nds32): Updated.
52 * nds32-asm.c (parse_aext_reg): Add new parameter.
53 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
56 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
57 (operand_fields): Add new fields.
58 (nds32_opcodes): Add new instructions.
59 (keyword_aridxi_mx): New keyword.
60 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
62 (ALU2_1, ALU2_2, ALU2_3): New macros.
63 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
65 2018-09-17 Kito Cheng <kito@andestech.com>
67 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
69 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
72 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
73 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
74 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
75 (EVEX_LEN_0F7E_P_1): Likewise.
76 (EVEX_LEN_0F7E_P_2): Likewise.
77 (EVEX_LEN_0FD6_P_2): Likewise.
78 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
79 (EVEX_LEN_TABLE): Likewise.
80 (EVEX_LEN_0F6E_P_2): New enum.
81 (EVEX_LEN_0F7E_P_1): Likewise.
82 (EVEX_LEN_0F7E_P_2): Likewise.
83 (EVEX_LEN_0FD6_P_2): Likewise.
84 (evex_len_table): New.
85 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
86 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
87 * i386-tbl.h: Regenerated.
89 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
92 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
93 VEX_LEN_0F7E_P_2 entries.
94 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
95 * i386-tbl.h: Regenerated.
97 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
99 * i386-dis.c (VZERO_Fixup): Removed.
101 (VEX_LEN_0F10_P_1): Likewise.
102 (VEX_LEN_0F10_P_3): Likewise.
103 (VEX_LEN_0F11_P_1): Likewise.
104 (VEX_LEN_0F11_P_3): Likewise.
105 (VEX_LEN_0F2E_P_0): Likewise.
106 (VEX_LEN_0F2E_P_2): Likewise.
107 (VEX_LEN_0F2F_P_0): Likewise.
108 (VEX_LEN_0F2F_P_2): Likewise.
109 (VEX_LEN_0F51_P_1): Likewise.
110 (VEX_LEN_0F51_P_3): Likewise.
111 (VEX_LEN_0F52_P_1): Likewise.
112 (VEX_LEN_0F53_P_1): Likewise.
113 (VEX_LEN_0F58_P_1): Likewise.
114 (VEX_LEN_0F58_P_3): Likewise.
115 (VEX_LEN_0F59_P_1): Likewise.
116 (VEX_LEN_0F59_P_3): Likewise.
117 (VEX_LEN_0F5A_P_1): Likewise.
118 (VEX_LEN_0F5A_P_3): Likewise.
119 (VEX_LEN_0F5C_P_1): Likewise.
120 (VEX_LEN_0F5C_P_3): Likewise.
121 (VEX_LEN_0F5D_P_1): Likewise.
122 (VEX_LEN_0F5D_P_3): Likewise.
123 (VEX_LEN_0F5E_P_1): Likewise.
124 (VEX_LEN_0F5E_P_3): Likewise.
125 (VEX_LEN_0F5F_P_1): Likewise.
126 (VEX_LEN_0F5F_P_3): Likewise.
127 (VEX_LEN_0FC2_P_1): Likewise.
128 (VEX_LEN_0FC2_P_3): Likewise.
129 (VEX_LEN_0F3A0A_P_2): Likewise.
130 (VEX_LEN_0F3A0B_P_2): Likewise.
131 (VEX_W_0F10_P_0): Likewise.
132 (VEX_W_0F10_P_1): Likewise.
133 (VEX_W_0F10_P_2): Likewise.
134 (VEX_W_0F10_P_3): Likewise.
135 (VEX_W_0F11_P_0): Likewise.
136 (VEX_W_0F11_P_1): Likewise.
137 (VEX_W_0F11_P_2): Likewise.
138 (VEX_W_0F11_P_3): Likewise.
139 (VEX_W_0F12_P_0_M_0): Likewise.
140 (VEX_W_0F12_P_0_M_1): Likewise.
141 (VEX_W_0F12_P_1): Likewise.
142 (VEX_W_0F12_P_2): Likewise.
143 (VEX_W_0F12_P_3): Likewise.
144 (VEX_W_0F13_M_0): Likewise.
145 (VEX_W_0F14): Likewise.
146 (VEX_W_0F15): Likewise.
147 (VEX_W_0F16_P_0_M_0): Likewise.
148 (VEX_W_0F16_P_0_M_1): Likewise.
149 (VEX_W_0F16_P_1): Likewise.
150 (VEX_W_0F16_P_2): Likewise.
151 (VEX_W_0F17_M_0): Likewise.
152 (VEX_W_0F28): Likewise.
153 (VEX_W_0F29): Likewise.
154 (VEX_W_0F2B_M_0): Likewise.
155 (VEX_W_0F2E_P_0): Likewise.
156 (VEX_W_0F2E_P_2): Likewise.
157 (VEX_W_0F2F_P_0): Likewise.
158 (VEX_W_0F2F_P_2): Likewise.
159 (VEX_W_0F50_M_0): Likewise.
160 (VEX_W_0F51_P_0): Likewise.
161 (VEX_W_0F51_P_1): Likewise.
162 (VEX_W_0F51_P_2): Likewise.
163 (VEX_W_0F51_P_3): Likewise.
164 (VEX_W_0F52_P_0): Likewise.
165 (VEX_W_0F52_P_1): Likewise.
166 (VEX_W_0F53_P_0): Likewise.
167 (VEX_W_0F53_P_1): Likewise.
168 (VEX_W_0F58_P_0): Likewise.
169 (VEX_W_0F58_P_1): Likewise.
170 (VEX_W_0F58_P_2): Likewise.
171 (VEX_W_0F58_P_3): Likewise.
172 (VEX_W_0F59_P_0): Likewise.
173 (VEX_W_0F59_P_1): Likewise.
174 (VEX_W_0F59_P_2): Likewise.
175 (VEX_W_0F59_P_3): Likewise.
176 (VEX_W_0F5A_P_0): Likewise.
177 (VEX_W_0F5A_P_1): Likewise.
178 (VEX_W_0F5A_P_3): Likewise.
179 (VEX_W_0F5B_P_0): Likewise.
180 (VEX_W_0F5B_P_1): Likewise.
181 (VEX_W_0F5B_P_2): Likewise.
182 (VEX_W_0F5C_P_0): Likewise.
183 (VEX_W_0F5C_P_1): Likewise.
184 (VEX_W_0F5C_P_2): Likewise.
185 (VEX_W_0F5C_P_3): Likewise.
186 (VEX_W_0F5D_P_0): Likewise.
187 (VEX_W_0F5D_P_1): Likewise.
188 (VEX_W_0F5D_P_2): Likewise.
189 (VEX_W_0F5D_P_3): Likewise.
190 (VEX_W_0F5E_P_0): Likewise.
191 (VEX_W_0F5E_P_1): Likewise.
192 (VEX_W_0F5E_P_2): Likewise.
193 (VEX_W_0F5E_P_3): Likewise.
194 (VEX_W_0F5F_P_0): Likewise.
195 (VEX_W_0F5F_P_1): Likewise.
196 (VEX_W_0F5F_P_2): Likewise.
197 (VEX_W_0F5F_P_3): Likewise.
198 (VEX_W_0F60_P_2): Likewise.
199 (VEX_W_0F61_P_2): Likewise.
200 (VEX_W_0F62_P_2): Likewise.
201 (VEX_W_0F63_P_2): Likewise.
202 (VEX_W_0F64_P_2): Likewise.
203 (VEX_W_0F65_P_2): Likewise.
204 (VEX_W_0F66_P_2): Likewise.
205 (VEX_W_0F67_P_2): Likewise.
206 (VEX_W_0F68_P_2): Likewise.
207 (VEX_W_0F69_P_2): Likewise.
208 (VEX_W_0F6A_P_2): Likewise.
209 (VEX_W_0F6B_P_2): Likewise.
210 (VEX_W_0F6C_P_2): Likewise.
211 (VEX_W_0F6D_P_2): Likewise.
212 (VEX_W_0F6F_P_1): Likewise.
213 (VEX_W_0F6F_P_2): Likewise.
214 (VEX_W_0F70_P_1): Likewise.
215 (VEX_W_0F70_P_2): Likewise.
216 (VEX_W_0F70_P_3): Likewise.
217 (VEX_W_0F71_R_2_P_2): Likewise.
218 (VEX_W_0F71_R_4_P_2): Likewise.
219 (VEX_W_0F71_R_6_P_2): Likewise.
220 (VEX_W_0F72_R_2_P_2): Likewise.
221 (VEX_W_0F72_R_4_P_2): Likewise.
222 (VEX_W_0F72_R_6_P_2): Likewise.
223 (VEX_W_0F73_R_2_P_2): Likewise.
224 (VEX_W_0F73_R_3_P_2): Likewise.
225 (VEX_W_0F73_R_6_P_2): Likewise.
226 (VEX_W_0F73_R_7_P_2): Likewise.
227 (VEX_W_0F74_P_2): Likewise.
228 (VEX_W_0F75_P_2): Likewise.
229 (VEX_W_0F76_P_2): Likewise.
230 (VEX_W_0F77_P_0): Likewise.
231 (VEX_W_0F7C_P_2): Likewise.
232 (VEX_W_0F7C_P_3): Likewise.
233 (VEX_W_0F7D_P_2): Likewise.
234 (VEX_W_0F7D_P_3): Likewise.
235 (VEX_W_0F7E_P_1): Likewise.
236 (VEX_W_0F7F_P_1): Likewise.
237 (VEX_W_0F7F_P_2): Likewise.
238 (VEX_W_0FAE_R_2_M_0): Likewise.
239 (VEX_W_0FAE_R_3_M_0): Likewise.
240 (VEX_W_0FC2_P_0): Likewise.
241 (VEX_W_0FC2_P_1): Likewise.
242 (VEX_W_0FC2_P_2): Likewise.
243 (VEX_W_0FC2_P_3): Likewise.
244 (VEX_W_0FD0_P_2): Likewise.
245 (VEX_W_0FD0_P_3): Likewise.
246 (VEX_W_0FD1_P_2): Likewise.
247 (VEX_W_0FD2_P_2): Likewise.
248 (VEX_W_0FD3_P_2): Likewise.
249 (VEX_W_0FD4_P_2): Likewise.
250 (VEX_W_0FD5_P_2): Likewise.
251 (VEX_W_0FD6_P_2): Likewise.
252 (VEX_W_0FD7_P_2_M_1): Likewise.
253 (VEX_W_0FD8_P_2): Likewise.
254 (VEX_W_0FD9_P_2): Likewise.
255 (VEX_W_0FDA_P_2): Likewise.
256 (VEX_W_0FDB_P_2): Likewise.
257 (VEX_W_0FDC_P_2): Likewise.
258 (VEX_W_0FDD_P_2): Likewise.
259 (VEX_W_0FDE_P_2): Likewise.
260 (VEX_W_0FDF_P_2): Likewise.
261 (VEX_W_0FE0_P_2): Likewise.
262 (VEX_W_0FE1_P_2): Likewise.
263 (VEX_W_0FE2_P_2): Likewise.
264 (VEX_W_0FE3_P_2): Likewise.
265 (VEX_W_0FE4_P_2): Likewise.
266 (VEX_W_0FE5_P_2): Likewise.
267 (VEX_W_0FE6_P_1): Likewise.
268 (VEX_W_0FE6_P_2): Likewise.
269 (VEX_W_0FE6_P_3): Likewise.
270 (VEX_W_0FE7_P_2_M_0): Likewise.
271 (VEX_W_0FE8_P_2): Likewise.
272 (VEX_W_0FE9_P_2): Likewise.
273 (VEX_W_0FEA_P_2): Likewise.
274 (VEX_W_0FEB_P_2): Likewise.
275 (VEX_W_0FEC_P_2): Likewise.
276 (VEX_W_0FED_P_2): Likewise.
277 (VEX_W_0FEE_P_2): Likewise.
278 (VEX_W_0FEF_P_2): Likewise.
279 (VEX_W_0FF0_P_3_M_0): Likewise.
280 (VEX_W_0FF1_P_2): Likewise.
281 (VEX_W_0FF2_P_2): Likewise.
282 (VEX_W_0FF3_P_2): Likewise.
283 (VEX_W_0FF4_P_2): Likewise.
284 (VEX_W_0FF5_P_2): Likewise.
285 (VEX_W_0FF6_P_2): Likewise.
286 (VEX_W_0FF7_P_2): Likewise.
287 (VEX_W_0FF8_P_2): Likewise.
288 (VEX_W_0FF9_P_2): Likewise.
289 (VEX_W_0FFA_P_2): Likewise.
290 (VEX_W_0FFB_P_2): Likewise.
291 (VEX_W_0FFC_P_2): Likewise.
292 (VEX_W_0FFD_P_2): Likewise.
293 (VEX_W_0FFE_P_2): Likewise.
294 (VEX_W_0F3800_P_2): Likewise.
295 (VEX_W_0F3801_P_2): Likewise.
296 (VEX_W_0F3802_P_2): Likewise.
297 (VEX_W_0F3803_P_2): Likewise.
298 (VEX_W_0F3804_P_2): Likewise.
299 (VEX_W_0F3805_P_2): Likewise.
300 (VEX_W_0F3806_P_2): Likewise.
301 (VEX_W_0F3807_P_2): Likewise.
302 (VEX_W_0F3808_P_2): Likewise.
303 (VEX_W_0F3809_P_2): Likewise.
304 (VEX_W_0F380A_P_2): Likewise.
305 (VEX_W_0F380B_P_2): Likewise.
306 (VEX_W_0F3817_P_2): Likewise.
307 (VEX_W_0F381C_P_2): Likewise.
308 (VEX_W_0F381D_P_2): Likewise.
309 (VEX_W_0F381E_P_2): Likewise.
310 (VEX_W_0F3820_P_2): Likewise.
311 (VEX_W_0F3821_P_2): Likewise.
312 (VEX_W_0F3822_P_2): Likewise.
313 (VEX_W_0F3823_P_2): Likewise.
314 (VEX_W_0F3824_P_2): Likewise.
315 (VEX_W_0F3825_P_2): Likewise.
316 (VEX_W_0F3828_P_2): Likewise.
317 (VEX_W_0F3829_P_2): Likewise.
318 (VEX_W_0F382A_P_2_M_0): Likewise.
319 (VEX_W_0F382B_P_2): Likewise.
320 (VEX_W_0F3830_P_2): Likewise.
321 (VEX_W_0F3831_P_2): Likewise.
322 (VEX_W_0F3832_P_2): Likewise.
323 (VEX_W_0F3833_P_2): Likewise.
324 (VEX_W_0F3834_P_2): Likewise.
325 (VEX_W_0F3835_P_2): Likewise.
326 (VEX_W_0F3837_P_2): Likewise.
327 (VEX_W_0F3838_P_2): Likewise.
328 (VEX_W_0F3839_P_2): Likewise.
329 (VEX_W_0F383A_P_2): Likewise.
330 (VEX_W_0F383B_P_2): Likewise.
331 (VEX_W_0F383C_P_2): Likewise.
332 (VEX_W_0F383D_P_2): Likewise.
333 (VEX_W_0F383E_P_2): Likewise.
334 (VEX_W_0F383F_P_2): Likewise.
335 (VEX_W_0F3840_P_2): Likewise.
336 (VEX_W_0F3841_P_2): Likewise.
337 (VEX_W_0F38DB_P_2): Likewise.
338 (VEX_W_0F3A08_P_2): Likewise.
339 (VEX_W_0F3A09_P_2): Likewise.
340 (VEX_W_0F3A0A_P_2): Likewise.
341 (VEX_W_0F3A0B_P_2): Likewise.
342 (VEX_W_0F3A0C_P_2): Likewise.
343 (VEX_W_0F3A0D_P_2): Likewise.
344 (VEX_W_0F3A0E_P_2): Likewise.
345 (VEX_W_0F3A0F_P_2): Likewise.
346 (VEX_W_0F3A21_P_2): Likewise.
347 (VEX_W_0F3A40_P_2): Likewise.
348 (VEX_W_0F3A41_P_2): Likewise.
349 (VEX_W_0F3A42_P_2): Likewise.
350 (VEX_W_0F3A62_P_2): Likewise.
351 (VEX_W_0F3A63_P_2): Likewise.
352 (VEX_W_0F3ADF_P_2): Likewise.
353 (VEX_LEN_0F77_P_0): New.
354 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
355 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
356 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
357 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
358 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
359 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
360 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
361 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
362 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
363 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
364 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
365 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
366 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
367 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
368 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
369 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
370 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
371 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
372 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
373 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
374 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
375 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
376 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
377 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
378 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
379 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
380 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
381 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
382 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
383 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
384 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
385 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
386 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
387 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
388 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
389 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
390 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
391 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
392 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
393 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
394 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
395 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
396 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
397 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
398 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
399 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
400 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
401 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
402 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
403 (vex_table): Update VEX 0F28 and 0F29 entries.
404 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
405 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
406 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
407 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
408 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
409 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
410 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
411 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
412 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
413 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
414 VEX_LEN_0F3A0B_P_2 entries.
415 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
416 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
417 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
418 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
419 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
420 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
421 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
422 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
423 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
424 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
425 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
426 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
427 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
428 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
429 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
430 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
431 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
432 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
433 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
434 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
435 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
436 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
437 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
438 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
439 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
440 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
441 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
442 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
443 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
444 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
445 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
446 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
447 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
448 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
449 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
450 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
451 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
452 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
453 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
454 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
455 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
456 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
457 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
458 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
459 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
460 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
461 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
462 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
463 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
464 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
465 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
466 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
467 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
468 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
469 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
470 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
471 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
472 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
473 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
474 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
475 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
476 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
477 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
478 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
479 VEX_W_0F3ADF_P_2 entries.
480 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
481 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
482 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
484 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
486 * i386-opc.tbl (VexWIG): New.
487 Replace VexW=3 with VexWIG.
489 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
491 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
492 * i386-tbl.h: Regenerated.
494 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
497 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
498 VEX_LEN_0FD6_P_2 entries.
499 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
500 * i386-tbl.h: Regenerated.
502 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
505 * i386-opc.h (VEXWIG): New.
506 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
507 * i386-tbl.h: Regenerated.
509 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
512 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
513 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
514 * i386-dis.c (EXxEVexR64): New.
515 (evex_rounding_64_mode): Likewise.
516 (OP_Rounding): Handle evex_rounding_64_mode.
518 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
521 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
522 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
523 * i386-dis.c (Edqa): New.
524 (dqa_mode): Likewise.
525 (intel_operand_size): Handle dqa_mode as m_mode.
526 (OP_E_register): Handle dqa_mode as dq_mode.
527 (OP_E_memory): Set shift for dqa_mode based on address_mode.
529 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
531 * i386-dis.c (OP_E_memory): Reformat.
533 2018-09-14 Jan Beulich <jbeulich@suse.com>
535 * i386-opc.tbl (crc32): Fold byte and word forms.
536 * i386-tbl.h: Re-generate.
538 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
540 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
541 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
542 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
543 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
544 * i386-tbl.h: Regenerated.
546 2018-09-13 Jan Beulich <jbeulich@suse.com>
548 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
550 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
551 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
552 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
553 * i386-tbl.h: Re-generate.
555 2018-09-13 Jan Beulich <jbeulich@suse.com>
557 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
559 * i386-tbl.h: Re-generate.
561 2018-09-13 Jan Beulich <jbeulich@suse.com>
563 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
565 * i386-tbl.h: Re-generate.
567 2018-09-13 Jan Beulich <jbeulich@suse.com>
569 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
571 * i386-tbl.h: Re-generate.
573 2018-09-13 Jan Beulich <jbeulich@suse.com>
575 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
577 * i386-tbl.h: Re-generate.
579 2018-09-13 Jan Beulich <jbeulich@suse.com>
581 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
583 * i386-tbl.h: Re-generate.
585 2018-09-13 Jan Beulich <jbeulich@suse.com>
587 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
589 * i386-tbl.h: Re-generate.
591 2018-09-13 Jan Beulich <jbeulich@suse.com>
593 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
594 * i386-tbl.h: Re-generate.
596 2018-09-13 Jan Beulich <jbeulich@suse.com>
598 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
599 * i386-tbl.h: Re-generate.
601 2018-09-13 Jan Beulich <jbeulich@suse.com>
603 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
605 * i386-tbl.h: Re-generate.
607 2018-09-13 Jan Beulich <jbeulich@suse.com>
609 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
611 * i386-tbl.h: Re-generate.
613 2018-09-13 Jan Beulich <jbeulich@suse.com>
615 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
616 * i386-tbl.h: Re-generate.
618 2018-09-13 Jan Beulich <jbeulich@suse.com>
620 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
621 * i386-tbl.h: Re-generate.
623 2018-09-13 Jan Beulich <jbeulich@suse.com>
625 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
626 * i386-tbl.h: Re-generate.
628 2018-09-13 Jan Beulich <jbeulich@suse.com>
630 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
632 * i386-tbl.h: Re-generate.
634 2018-09-13 Jan Beulich <jbeulich@suse.com>
636 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
638 * i386-tbl.h: Re-generate.
640 2018-09-13 Jan Beulich <jbeulich@suse.com>
642 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
644 * i386-tbl.h: Re-generate.
646 2018-09-13 Jan Beulich <jbeulich@suse.com>
648 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
649 * i386-tbl.h: Re-generate.
651 2018-09-13 Jan Beulich <jbeulich@suse.com>
653 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
654 * i386-tbl.h: Re-generate.
656 2018-09-13 Jan Beulich <jbeulich@suse.com>
658 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
659 * i386-tbl.h: Re-generate.
661 2018-09-13 Jan Beulich <jbeulich@suse.com>
663 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
664 (vpbroadcastw, rdpid): Drop NoRex64.
665 * i386-tbl.h: Re-generate.
667 2018-09-13 Jan Beulich <jbeulich@suse.com>
669 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
670 store templates, adding D.
671 * i386-tbl.h: Re-generate.
673 2018-09-13 Jan Beulich <jbeulich@suse.com>
675 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
676 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
677 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
678 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
679 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
680 Fold load and store templates where possible, adding D. Drop
681 IgnoreSize where it was pointlessly present. Drop redundant
683 * i386-tbl.h: Re-generate.
685 2018-09-13 Jan Beulich <jbeulich@suse.com>
687 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
688 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
689 (intel_operand_size): Handle v_bndmk_mode.
690 (OP_E_memory): Likewise. Produce (bad) when also riprel.
692 2018-09-08 John Darrington <john@darrington.wattle.id.au>
694 * disassemble.c (ARCH_s12z): Define if ARCH_all.
696 2018-08-31 Kito Cheng <kito@andestech.com>
698 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
699 compressed floating point instructions.
701 2018-08-30 Kito Cheng <kito@andestech.com>
703 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
704 riscv_opcode.xlen_requirement.
705 * riscv-opc.c (riscv_opcodes): Update for struct change.
707 2018-08-29 Martin Aberg <maberg@gaisler.com>
709 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
710 psr (PWRPSR) instruction.
712 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
714 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
716 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
718 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
720 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
722 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
723 loongson3a as an alias of gs464 for compatibility.
724 * mips-opc.c (mips_opcodes): Change Comments.
726 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
728 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
730 (print_mips_disassembler_options): Document -M loongson-ext.
731 * mips-opc.c (LEXT2): New macro.
732 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
734 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
736 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
738 (parse_mips_ase_option): Handle -M loongson-ext option.
739 (print_mips_disassembler_options): Document -M loongson-ext.
740 * mips-opc.c (IL3A): Delete.
741 * mips-opc.c (LEXT): New macro.
742 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
745 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
747 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
749 (parse_mips_ase_option): Handle -M loongson-cam option.
750 (print_mips_disassembler_options): Document -M loongson-cam.
751 * mips-opc.c (LCAM): New macro.
752 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
755 2018-08-21 Alan Modra <amodra@gmail.com>
757 * ppc-dis.c (operand_value_powerpc): Init "invalid".
758 (skip_optional_operands): Count optional operands, and update
759 ppc_optional_operand_value call.
760 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
761 (extract_vlensi): Likewise.
762 (extract_fxm): Return default value for missing optional operand.
763 (extract_ls, extract_raq, extract_tbr): Likewise.
764 (insert_sxl, extract_sxl): New functions.
765 (insert_esync, extract_esync): Remove Power9 handling and simplify.
766 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
767 flag and extra entry.
768 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
771 2018-08-20 Alan Modra <amodra@gmail.com>
773 * sh-opc.h (MASK): Simplify.
775 2018-08-18 John Darrington <john@darrington.wattle.id.au>
777 * s12z-dis.c (bm_decode): Deal with cases where the mode is
778 BM_RESERVED0 or BM_RESERVED1
779 (bm_rel_decode, bm_n_bytes): Ditto.
781 2018-08-18 John Darrington <john@darrington.wattle.id.au>
785 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
787 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
788 address with the addr32 prefix and without base nor index
791 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
793 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
794 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
795 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
796 (cpu_flags): Add CpuCMOV and CpuFXSR.
797 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
798 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
799 * i386-init.h: Regenerated.
800 * i386-tbl.h: Likewise.
802 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
804 * arc-regs.h: Update auxiliary registers.
806 2018-08-06 Jan Beulich <jbeulich@suse.com>
808 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
809 (RegIP, RegIZ): Define.
810 * i386-reg.tbl: Adjust comments.
811 (rip): Use Qword instead of BaseIndex. Use RegIP.
812 (eip): Use Dword instead of BaseIndex. Use RegIP.
813 (riz): Add Qword. Use RegIZ.
814 (eiz): Add Dword. Use RegIZ.
815 * i386-tbl.h: Re-generate.
817 2018-08-03 Jan Beulich <jbeulich@suse.com>
819 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
820 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
821 vpmovzxdq, vpmovzxwd): Remove NoRex64.
822 * i386-tbl.h: Re-generate.
824 2018-08-03 Jan Beulich <jbeulich@suse.com>
826 * i386-gen.c (operand_types): Remove Mem field.
827 * i386-opc.h (union i386_operand_type): Remove mem field.
828 * i386-init.h, i386-tbl.h: Re-generate.
830 2018-08-01 Alan Modra <amodra@gmail.com>
832 * po/POTFILES.in: Regenerate.
834 2018-07-31 Nick Clifton <nickc@redhat.com>
836 * po/sv.po: Updated Swedish translation.
838 2018-07-31 Jan Beulich <jbeulich@suse.com>
840 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
841 * i386-init.h, i386-tbl.h: Re-generate.
843 2018-07-31 Jan Beulich <jbeulich@suse.com>
845 * i386-opc.h (ZEROING_MASKING) Rename to ...
846 (DYNAMIC_MASKING): ... this. Adjust comment.
847 * i386-opc.tbl (MaskingMorZ): Define.
848 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
849 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
850 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
851 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
852 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
853 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
854 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
855 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
856 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
858 2018-07-31 Jan Beulich <jbeulich@suse.com>
860 * i386-opc.tbl: Use element rather than vector size for AVX512*
861 scatter/gather insns.
862 * i386-tbl.h: Re-generate.
864 2018-07-31 Jan Beulich <jbeulich@suse.com>
866 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
867 (cpu_flags): Drop CpuVREX.
868 * i386-opc.h (CpuVREX): Delete.
869 (union i386_cpu_flags): Remove cpuvrex.
870 * i386-init.h, i386-tbl.h: Re-generate.
872 2018-07-30 Jim Wilson <jimw@sifive.com>
874 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
876 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
878 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
880 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
881 * Makefile.in: Regenerated.
882 * configure.ac: Add C-SKY.
883 * configure: Regenerated.
884 * csky-dis.c: New file.
885 * csky-opc.h: New file.
886 * disassemble.c (ARCH_csky): Define.
887 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
888 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
890 2018-07-27 Alan Modra <amodra@gmail.com>
892 * ppc-opc.c (insert_sprbat): Correct function parameter and
894 (extract_sprbat): Likewise, variable too.
896 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
897 Alan Modra <amodra@gmail.com>
899 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
900 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
901 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
902 support disjointed BAT.
903 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
904 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
905 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
907 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
908 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
910 * i386-gen.c (adjust_broadcast_modifier): New function.
911 (process_i386_opcode_modifier): Add an argument for operands.
912 Adjust the Broadcast value based on operands.
913 (output_i386_opcode): Pass operand_types to
914 process_i386_opcode_modifier.
915 (process_i386_opcodes): Pass NULL as operands to
916 process_i386_opcode_modifier.
917 * i386-opc.h (BYTE_BROADCAST): New.
918 (WORD_BROADCAST): Likewise.
919 (DWORD_BROADCAST): Likewise.
920 (QWORD_BROADCAST): Likewise.
921 (i386_opcode_modifier): Expand broadcast to 3 bits.
922 * i386-tbl.h: Regenerated.
924 2018-07-24 Alan Modra <amodra@gmail.com>
927 * or1k-desc.h: Regenerate.
929 2018-07-24 Jan Beulich <jbeulich@suse.com>
931 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
932 vcvtusi2ss, and vcvtusi2sd.
933 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
934 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
935 * i386-tbl.h: Re-generate.
937 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
939 * arc-opc.c (extract_w6): Fix extending the sign.
941 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
943 * arc-tbl.h (vewt): Allow it for ARC EM family.
945 2018-07-23 Alan Modra <amodra@gmail.com>
948 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
949 opcode variants for mtspr/mfspr encodings.
951 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
952 Maciej W. Rozycki <macro@mips.com>
954 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
955 loongson3a descriptors.
956 (parse_mips_ase_option): Handle -M loongson-mmi option.
957 (print_mips_disassembler_options): Document -M loongson-mmi.
958 * mips-opc.c (LMMI): New macro.
959 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
962 2018-07-19 Jan Beulich <jbeulich@suse.com>
964 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
965 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
966 IgnoreSize and [XYZ]MMword where applicable.
967 * i386-tbl.h: Re-generate.
969 2018-07-19 Jan Beulich <jbeulich@suse.com>
971 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
972 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
973 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
974 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
975 * i386-tbl.h: Re-generate.
977 2018-07-19 Jan Beulich <jbeulich@suse.com>
979 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
980 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
981 VPCLMULQDQ templates into their respective AVX512VL counterparts
982 where possible, using Disp8ShiftVL and CheckRegSize instead of
983 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
984 * i386-tbl.h: Re-generate.
986 2018-07-19 Jan Beulich <jbeulich@suse.com>
988 * i386-opc.tbl: Fold AVX512DQ templates into their respective
989 AVX512VL counterparts where possible, using Disp8ShiftVL and
990 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
991 IgnoreSize) as appropriate.
992 * i386-tbl.h: Re-generate.
994 2018-07-19 Jan Beulich <jbeulich@suse.com>
996 * i386-opc.tbl: Fold AVX512BW templates into their respective
997 AVX512VL counterparts where possible, using Disp8ShiftVL and
998 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
999 IgnoreSize) as appropriate.
1000 * i386-tbl.h: Re-generate.
1002 2018-07-19 Jan Beulich <jbeulich@suse.com>
1004 * i386-opc.tbl: Fold AVX512CD templates into their respective
1005 AVX512VL counterparts where possible, using Disp8ShiftVL and
1006 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1007 IgnoreSize) as appropriate.
1008 * i386-tbl.h: Re-generate.
1010 2018-07-19 Jan Beulich <jbeulich@suse.com>
1012 * i386-opc.h (DISP8_SHIFT_VL): New.
1013 * i386-opc.tbl (Disp8ShiftVL): Define.
1014 (various): Fold AVX512VL templates into their respective
1015 AVX512F counterparts where possible, using Disp8ShiftVL and
1016 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1017 IgnoreSize) as appropriate.
1018 * i386-tbl.h: Re-generate.
1020 2018-07-19 Jan Beulich <jbeulich@suse.com>
1022 * Makefile.am: Change dependencies and rule for
1023 $(srcdir)/i386-init.h.
1024 * Makefile.in: Re-generate.
1025 * i386-gen.c (process_i386_opcodes): New local variable
1026 "marker". Drop opening of input file. Recognize marker and line
1028 * i386-opc.tbl (OPCODE_I386_H): Define.
1029 (i386-opc.h): Include it.
1032 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1035 * i386-opc.h (Byte): Update comments.
1041 (Xmmword): Likewise.
1042 (Ymmword): Likewise.
1043 (Zmmword): Likewise.
1044 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1046 * i386-tbl.h: Regenerated.
1048 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1050 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1051 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1052 * aarch64-asm-2.c: Regenerate.
1053 * aarch64-dis-2.c: Regenerate.
1054 * aarch64-opc-2.c: Regenerate.
1056 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1059 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1060 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1061 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1062 sqdmulh, sqrdmulh): Use Em16.
1064 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1066 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1067 csdb together with them.
1068 (thumb32_opcodes): Likewise.
1070 2018-07-11 Jan Beulich <jbeulich@suse.com>
1072 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1073 requiring 32-bit registers as operands 2 and 3. Improve
1075 (mwait, mwaitx): Fold templates. Improve comments.
1076 OPERAND_TYPE_INOUTPORTREG.
1077 * i386-tbl.h: Re-generate.
1079 2018-07-11 Jan Beulich <jbeulich@suse.com>
1081 * i386-gen.c (operand_type_init): Remove
1082 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1083 OPERAND_TYPE_INOUTPORTREG.
1084 * i386-init.h: Re-generate.
1086 2018-07-11 Jan Beulich <jbeulich@suse.com>
1088 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1089 (wrssq, wrussq): Add Qword.
1090 * i386-tbl.h: Re-generate.
1092 2018-07-11 Jan Beulich <jbeulich@suse.com>
1094 * i386-opc.h: Rename OTMax to OTNum.
1095 (OTNumOfUints): Adjust calculation.
1096 (OTUnused): Directly alias to OTNum.
1098 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1100 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1102 (lea_reg_xys): Likewise.
1103 (print_insn_loop_primitive): Rename `reg' local variable to
1106 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1109 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1111 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1114 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1115 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1117 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1120 * mips-dis.c (mips_option_arg_t): New enumeration.
1121 (mips_options): New variable.
1122 (disassembler_options_mips): New function.
1123 (print_mips_disassembler_options): Reimplement in terms of
1124 `disassembler_options_mips'.
1125 * arm-dis.c (disassembler_options_arm): Adapt to using the
1126 `disasm_options_and_args_t' structure.
1127 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1128 * s390-dis.c (disassembler_options_s390): Likewise.
1130 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1132 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1134 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1135 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1136 * testsuite/ld-arm/tls-longplt.d: Likewise.
1138 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1141 * aarch64-asm-2.c: Regenerate.
1142 * aarch64-dis-2.c: Likewise.
1143 * aarch64-opc-2.c: Likewise.
1144 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1145 * aarch64-opc.c (operand_general_constraint_met_p,
1146 aarch64_print_operand): Likewise.
1147 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1148 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1150 (AARCH64_OPERANDS): Add Em2.
1152 2018-06-26 Nick Clifton <nickc@redhat.com>
1154 * po/uk.po: Updated Ukranian translation.
1155 * po/de.po: Updated German translation.
1156 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1158 2018-06-26 Nick Clifton <nickc@redhat.com>
1160 * nfp-dis.c: Fix spelling mistake.
1162 2018-06-24 Nick Clifton <nickc@redhat.com>
1164 * configure: Regenerate.
1165 * po/opcodes.pot: Regenerate.
1167 2018-06-24 Nick Clifton <nickc@redhat.com>
1169 2.31 branch created.
1171 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1173 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1174 * aarch64-asm-2.c: Regenerate.
1175 * aarch64-dis-2.c: Likewise.
1177 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1179 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1180 `-M ginv' option description.
1182 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1185 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1188 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1190 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1191 * configure.ac: Remove AC_PREREQ.
1192 * Makefile.in: Re-generate.
1193 * aclocal.m4: Re-generate.
1194 * configure: Re-generate.
1196 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1198 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1199 mips64r6 descriptors.
1200 (parse_mips_ase_option): Handle -Mginv option.
1201 (print_mips_disassembler_options): Document -Mginv.
1202 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1204 (mips_opcodes): Define ginvi and ginvt.
1206 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1207 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1209 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1210 * mips-opc.c (CRC, CRC64): New macros.
1211 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1212 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1215 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1218 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1219 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1221 2018-06-06 Alan Modra <amodra@gmail.com>
1223 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1224 setjmp. Move init for some other vars later too.
1226 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1228 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1229 (dis_private): Add new fields for property section tracking.
1230 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1231 (xtensa_instruction_fits): New functions.
1232 (fetch_data): Bump minimal fetch size to 4.
1233 (print_insn_xtensa): Make struct dis_private static.
1234 Load and prepare property table on section change.
1235 Don't disassemble literals. Don't disassemble instructions that
1236 cross property table boundaries.
1238 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1240 * configure: Regenerated.
1242 2018-06-01 Jan Beulich <jbeulich@suse.com>
1244 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1245 * i386-tbl.h: Re-generate.
1247 2018-06-01 Jan Beulich <jbeulich@suse.com>
1249 * i386-opc.tbl (sldt, str): Add NoRex64.
1250 * i386-tbl.h: Re-generate.
1252 2018-06-01 Jan Beulich <jbeulich@suse.com>
1254 * i386-opc.tbl (invpcid): Add Oword.
1255 * i386-tbl.h: Re-generate.
1257 2018-06-01 Alan Modra <amodra@gmail.com>
1259 * sysdep.h (_bfd_error_handler): Don't declare.
1260 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1261 * rl78-decode.opc: Likewise.
1262 * msp430-decode.c: Regenerate.
1263 * rl78-decode.c: Regenerate.
1265 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1267 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1268 * i386-init.h : Regenerated.
1270 2018-05-25 Alan Modra <amodra@gmail.com>
1272 * Makefile.in: Regenerate.
1273 * po/POTFILES.in: Regenerate.
1275 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1277 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1278 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1279 (insert_bab, extract_bab, insert_btab, extract_btab,
1280 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1281 (BAT, BBA VBA RBS XB6S): Delete macros.
1282 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1283 (BB, BD, RBX, XC6): Update for new macros.
1284 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1285 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1286 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1287 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1289 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1291 * Makefile.am: Add support for s12z architecture.
1292 * configure.ac: Likewise.
1293 * disassemble.c: Likewise.
1294 * disassemble.h: Likewise.
1295 * Makefile.in: Regenerate.
1296 * configure: Regenerate.
1297 * s12z-dis.c: New file.
1300 2018-05-18 Alan Modra <amodra@gmail.com>
1302 * nfp-dis.c: Don't #include libbfd.h.
1303 (init_nfp3200_priv): Use bfd_get_section_contents.
1304 (nit_nfp6000_mecsr_sec): Likewise.
1306 2018-05-17 Nick Clifton <nickc@redhat.com>
1308 * po/zh_CN.po: Updated simplified Chinese translation.
1310 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1313 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1314 * aarch64-dis-2.c: Regenerate.
1316 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1319 * aarch64-asm.c (opintl.h): Include.
1320 (aarch64_ins_sysreg): Enforce read/write constraints.
1321 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1322 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1323 (F_REG_READ, F_REG_WRITE): New.
1324 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1325 AARCH64_OPND_SYSREG.
1326 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1327 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1328 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1329 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1330 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1331 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1332 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1333 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1334 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1335 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1336 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1337 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1338 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1339 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1340 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1341 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1342 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1344 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1347 * aarch64-dis.c (no_notes: New.
1348 (parse_aarch64_dis_option): Support notes.
1349 (aarch64_decode_insn, print_operands): Likewise.
1350 (print_aarch64_disassembler_options): Document notes.
1351 * aarch64-opc.c (aarch64_print_operand): Support notes.
1353 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1356 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1357 and take error struct.
1358 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1359 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1360 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1361 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1362 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1363 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1364 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1365 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1366 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1367 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1368 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1369 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1370 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1371 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1372 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1373 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1374 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1375 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1376 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1377 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1378 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1379 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1380 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1381 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1382 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1383 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1384 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1385 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1386 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1387 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1388 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1389 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1390 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1391 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1392 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1393 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1394 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1395 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1396 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1397 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1398 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1399 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1400 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1401 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1402 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1403 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1404 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1405 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1406 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1407 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1408 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1409 (determine_disassembling_preference, aarch64_decode_insn,
1410 print_insn_aarch64_word, print_insn_data): Take errors struct.
1411 (print_insn_aarch64): Use errors.
1412 * aarch64-asm-2.c: Regenerate.
1413 * aarch64-dis-2.c: Regenerate.
1414 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1415 boolean in aarch64_insert_operan.
1416 (print_operand_extractor): Likewise.
1417 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1419 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1421 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1423 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1425 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1427 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1429 * cr16-opc.c (cr16_instruction): Comment typo fix.
1430 * hppa-dis.c (print_insn_hppa): Likewise.
1432 2018-05-08 Jim Wilson <jimw@sifive.com>
1434 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1435 (match_c_slli64, match_srxi_as_c_srxi): New.
1436 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1437 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1438 <c.slli, c.srli, c.srai>: Use match_s_slli.
1439 <c.slli64, c.srli64, c.srai64>: New.
1441 2018-05-08 Alan Modra <amodra@gmail.com>
1443 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1444 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1445 partition opcode space for index lookup.
1447 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1449 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1450 <insn_length>: ...with this. Update usage.
1451 Remove duplicate call to *info->memory_error_func.
1453 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1454 H.J. Lu <hongjiu.lu@intel.com>
1456 * i386-dis.c (Gva): New.
1457 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1458 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1459 (prefix_table): New instructions (see prefix above).
1460 (mod_table): New instructions (see prefix above).
1461 (OP_G): Handle va_mode.
1462 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1463 CPU_MOVDIR64B_FLAGS.
1464 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1465 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1466 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1467 * i386-opc.tbl: Add movidir{i,64b}.
1468 * i386-init.h: Regenerated.
1469 * i386-tbl.h: Likewise.
1471 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1473 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1475 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1476 (AddrPrefixOpReg): This.
1477 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1478 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1480 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1482 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1483 (vle_num_opcodes): Likewise.
1484 (spe2_num_opcodes): Likewise.
1485 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1486 initialization loop.
1487 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1488 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1491 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1493 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1495 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1497 Makefile.am: Added nfp-dis.c.
1498 configure.ac: Added bfd_nfp_arch.
1499 disassemble.h: Added print_insn_nfp prototype.
1500 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1501 nfp-dis.c: New, for NFP support.
1502 po/POTFILES.in: Added nfp-dis.c to the list.
1503 Makefile.in: Regenerate.
1504 configure: Regenerate.
1506 2018-04-26 Jan Beulich <jbeulich@suse.com>
1508 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1509 templates into their base ones.
1510 * i386-tlb.h: Re-generate.
1512 2018-04-26 Jan Beulich <jbeulich@suse.com>
1514 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1515 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1516 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1517 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1518 * i386-init.h: Re-generate.
1520 2018-04-26 Jan Beulich <jbeulich@suse.com>
1522 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1523 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1524 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1525 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1527 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1529 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1531 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1532 cpuregzmm, and cpuregmask.
1533 * i386-init.h: Re-generate.
1534 * i386-tbl.h: Re-generate.
1536 2018-04-26 Jan Beulich <jbeulich@suse.com>
1538 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1539 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1540 * i386-init.h: Re-generate.
1542 2018-04-26 Jan Beulich <jbeulich@suse.com>
1544 * i386-gen.c (VexImmExt): Delete.
1545 * i386-opc.h (VexImmExt, veximmext): Delete.
1546 * i386-opc.tbl: Drop all VexImmExt uses.
1547 * i386-tlb.h: Re-generate.
1549 2018-04-25 Jan Beulich <jbeulich@suse.com>
1551 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1552 register-only forms.
1553 * i386-tlb.h: Re-generate.
1555 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1557 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1559 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1561 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1563 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1564 (cpu_flags): Add CpuCLDEMOTE.
1565 * i386-init.h: Regenerate.
1566 * i386-opc.h (enum): Add CpuCLDEMOTE,
1567 (i386_cpu_flags): Add cpucldemote.
1568 * i386-opc.tbl: Add cldemote.
1569 * i386-tbl.h: Regenerate.
1571 2018-04-16 Alan Modra <amodra@gmail.com>
1573 * Makefile.am: Remove sh5 and sh64 support.
1574 * configure.ac: Likewise.
1575 * disassemble.c: Likewise.
1576 * disassemble.h: Likewise.
1577 * sh-dis.c: Likewise.
1578 * sh64-dis.c: Delete.
1579 * sh64-opc.c: Delete.
1580 * sh64-opc.h: Delete.
1581 * Makefile.in: Regenerate.
1582 * configure: Regenerate.
1583 * po/POTFILES.in: Regenerate.
1585 2018-04-16 Alan Modra <amodra@gmail.com>
1587 * Makefile.am: Remove w65 support.
1588 * configure.ac: Likewise.
1589 * disassemble.c: Likewise.
1590 * disassemble.h: Likewise.
1591 * w65-dis.c: Delete.
1592 * w65-opc.h: Delete.
1593 * Makefile.in: Regenerate.
1594 * configure: Regenerate.
1595 * po/POTFILES.in: Regenerate.
1597 2018-04-16 Alan Modra <amodra@gmail.com>
1599 * configure.ac: Remove we32k support.
1600 * configure: Regenerate.
1602 2018-04-16 Alan Modra <amodra@gmail.com>
1604 * Makefile.am: Remove m88k support.
1605 * configure.ac: Likewise.
1606 * disassemble.c: Likewise.
1607 * disassemble.h: Likewise.
1608 * m88k-dis.c: Delete.
1609 * Makefile.in: Regenerate.
1610 * configure: Regenerate.
1611 * po/POTFILES.in: Regenerate.
1613 2018-04-16 Alan Modra <amodra@gmail.com>
1615 * Makefile.am: Remove i370 support.
1616 * configure.ac: Likewise.
1617 * disassemble.c: Likewise.
1618 * disassemble.h: Likewise.
1619 * i370-dis.c: Delete.
1620 * i370-opc.c: Delete.
1621 * Makefile.in: Regenerate.
1622 * configure: Regenerate.
1623 * po/POTFILES.in: Regenerate.
1625 2018-04-16 Alan Modra <amodra@gmail.com>
1627 * Makefile.am: Remove h8500 support.
1628 * configure.ac: Likewise.
1629 * disassemble.c: Likewise.
1630 * disassemble.h: Likewise.
1631 * h8500-dis.c: Delete.
1632 * h8500-opc.h: Delete.
1633 * Makefile.in: Regenerate.
1634 * configure: Regenerate.
1635 * po/POTFILES.in: Regenerate.
1637 2018-04-16 Alan Modra <amodra@gmail.com>
1639 * configure.ac: Remove tahoe support.
1640 * configure: Regenerate.
1642 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1644 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1646 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1648 * i386-tbl.h: Regenerated.
1650 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1652 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1653 PREFIX_MOD_1_0FAE_REG_6.
1655 (OP_E_register): Use va_mode.
1656 * i386-dis-evex.h (prefix_table):
1657 New instructions (see prefixes above).
1658 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1659 (cpu_flags): Likewise.
1660 * i386-opc.h (enum): Likewise.
1661 (i386_cpu_flags): Likewise.
1662 * i386-opc.tbl: Add umonitor, umwait, tpause.
1663 * i386-init.h: Regenerate.
1664 * i386-tbl.h: Likewise.
1666 2018-04-11 Alan Modra <amodra@gmail.com>
1668 * opcodes/i860-dis.c: Delete.
1669 * opcodes/i960-dis.c: Delete.
1670 * Makefile.am: Remove i860 and i960 support.
1671 * configure.ac: Likewise.
1672 * disassemble.c: Likewise.
1673 * disassemble.h: Likewise.
1674 * Makefile.in: Regenerate.
1675 * configure: Regenerate.
1676 * po/POTFILES.in: Regenerate.
1678 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1681 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1683 (print_insn): Clear vex instead of vex.evex.
1685 2018-04-04 Nick Clifton <nickc@redhat.com>
1687 * po/es.po: Updated Spanish translation.
1689 2018-03-28 Jan Beulich <jbeulich@suse.com>
1691 * i386-gen.c (opcode_modifiers): Delete VecESize.
1692 * i386-opc.h (VecESize): Delete.
1693 (struct i386_opcode_modifier): Delete vecesize.
1694 * i386-opc.tbl: Drop VecESize.
1695 * i386-tlb.h: Re-generate.
1697 2018-03-28 Jan Beulich <jbeulich@suse.com>
1699 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1700 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1701 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1702 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1703 * i386-tlb.h: Re-generate.
1705 2018-03-28 Jan Beulich <jbeulich@suse.com>
1707 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1709 * i386-tlb.h: Re-generate.
1711 2018-03-28 Jan Beulich <jbeulich@suse.com>
1713 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1714 (vex_len_table): Drop Y for vcvt*2si.
1715 (putop): Replace plain 'Y' handling by abort().
1717 2018-03-28 Nick Clifton <nickc@redhat.com>
1720 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1721 instructions with only a base address register.
1722 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1723 handle AARHC64_OPND_SVE_ADDR_R.
1724 (aarch64_print_operand): Likewise.
1725 * aarch64-asm-2.c: Regenerate.
1726 * aarch64_dis-2.c: Regenerate.
1727 * aarch64-opc-2.c: Regenerate.
1729 2018-03-22 Jan Beulich <jbeulich@suse.com>
1731 * i386-opc.tbl: Drop VecESize from register only insn forms and
1732 memory forms not allowing broadcast.
1733 * i386-tlb.h: Re-generate.
1735 2018-03-22 Jan Beulich <jbeulich@suse.com>
1737 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1738 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1739 sha256*): Drop Disp<N>.
1741 2018-03-22 Jan Beulich <jbeulich@suse.com>
1743 * i386-dis.c (EbndS, bnd_swap_mode): New.
1744 (prefix_table): Use EbndS.
1745 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1746 * i386-opc.tbl (bndmov): Move misplaced Load.
1747 * i386-tlb.h: Re-generate.
1749 2018-03-22 Jan Beulich <jbeulich@suse.com>
1751 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1752 templates allowing memory operands and folded ones for register
1754 * i386-tlb.h: Re-generate.
1756 2018-03-22 Jan Beulich <jbeulich@suse.com>
1758 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1759 256-bit templates. Drop redundant leftover Disp<N>.
1760 * i386-tlb.h: Re-generate.
1762 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1764 * riscv-opc.c (riscv_insn_types): New.
1766 2018-03-13 Nick Clifton <nickc@redhat.com>
1768 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1770 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1772 * i386-opc.tbl: Add Optimize to clr.
1773 * i386-tbl.h: Regenerated.
1775 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1777 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1778 * i386-opc.h (OldGcc): Removed.
1779 (i386_opcode_modifier): Remove oldgcc.
1780 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1781 instructions for old (<= 2.8.1) versions of gcc.
1782 * i386-tbl.h: Regenerated.
1784 2018-03-08 Jan Beulich <jbeulich@suse.com>
1786 * i386-opc.h (EVEXDYN): New.
1787 * i386-opc.tbl: Fold various AVX512VL templates.
1788 * i386-tlb.h: Re-generate.
1790 2018-03-08 Jan Beulich <jbeulich@suse.com>
1792 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1793 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1794 vpexpandd, vpexpandq): Fold AFX512VF templates.
1795 * i386-tlb.h: Re-generate.
1797 2018-03-08 Jan Beulich <jbeulich@suse.com>
1799 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1800 Fold 128- and 256-bit VEX-encoded templates.
1801 * i386-tlb.h: Re-generate.
1803 2018-03-08 Jan Beulich <jbeulich@suse.com>
1805 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1806 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1807 vpexpandd, vpexpandq): Fold AVX512F templates.
1808 * i386-tlb.h: Re-generate.
1810 2018-03-08 Jan Beulich <jbeulich@suse.com>
1812 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1813 64-bit templates. Drop Disp<N>.
1814 * i386-tlb.h: Re-generate.
1816 2018-03-08 Jan Beulich <jbeulich@suse.com>
1818 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1819 and 256-bit templates.
1820 * i386-tlb.h: Re-generate.
1822 2018-03-08 Jan Beulich <jbeulich@suse.com>
1824 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1825 * i386-tlb.h: Re-generate.
1827 2018-03-08 Jan Beulich <jbeulich@suse.com>
1829 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1831 * i386-tlb.h: Re-generate.
1833 2018-03-08 Jan Beulich <jbeulich@suse.com>
1835 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1836 * i386-tlb.h: Re-generate.
1838 2018-03-08 Jan Beulich <jbeulich@suse.com>
1840 * i386-gen.c (opcode_modifiers): Delete FloatD.
1841 * i386-opc.h (FloatD): Delete.
1842 (struct i386_opcode_modifier): Delete floatd.
1843 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1845 * i386-tlb.h: Re-generate.
1847 2018-03-08 Jan Beulich <jbeulich@suse.com>
1849 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1851 2018-03-08 Jan Beulich <jbeulich@suse.com>
1853 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1854 * i386-tlb.h: Re-generate.
1856 2018-03-08 Jan Beulich <jbeulich@suse.com>
1858 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1860 * i386-tlb.h: Re-generate.
1862 2018-03-07 Alan Modra <amodra@gmail.com>
1864 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1866 * disassemble.h (print_insn_rs6000): Delete.
1867 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1868 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1869 (print_insn_rs6000): Delete.
1871 2018-03-03 Alan Modra <amodra@gmail.com>
1873 * sysdep.h (opcodes_error_handler): Define.
1874 (_bfd_error_handler): Declare.
1875 * Makefile.am: Remove stray #.
1876 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1878 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1879 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1880 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1881 opcodes_error_handler to print errors. Standardize error messages.
1882 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1883 and include opintl.h.
1884 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1885 * i386-gen.c: Standardize error messages.
1886 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1887 * Makefile.in: Regenerate.
1888 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1889 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1890 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1891 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1892 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1893 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1894 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1895 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1896 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1897 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1898 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1899 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1900 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1902 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1904 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1905 vpsub[bwdq] instructions.
1906 * i386-tbl.h: Regenerated.
1908 2018-03-01 Alan Modra <amodra@gmail.com>
1910 * configure.ac (ALL_LINGUAS): Sort.
1911 * configure: Regenerate.
1913 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1915 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1916 macro by assignements.
1918 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1921 * i386-gen.c (opcode_modifiers): Add Optimize.
1922 * i386-opc.h (Optimize): New enum.
1923 (i386_opcode_modifier): Add optimize.
1924 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1925 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1926 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1927 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1928 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1930 * i386-tbl.h: Regenerated.
1932 2018-02-26 Alan Modra <amodra@gmail.com>
1934 * crx-dis.c (getregliststring): Allocate a large enough buffer
1935 to silence false positive gcc8 warning.
1937 2018-02-22 Shea Levy <shea@shealevy.com>
1939 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1941 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1943 * i386-opc.tbl: Add {rex},
1944 * i386-tbl.h: Regenerated.
1946 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1948 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1949 (mips16_opcodes): Replace `M' with `m' for "restore".
1951 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1953 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1955 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1957 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1958 variable to `function_index'.
1960 2018-02-13 Nick Clifton <nickc@redhat.com>
1963 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1964 about truncation of printing.
1966 2018-02-12 Henry Wong <henry@stuffedcow.net>
1968 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1970 2018-02-05 Nick Clifton <nickc@redhat.com>
1972 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1974 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1976 * i386-dis.c (enum): Add pconfig.
1977 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1978 (cpu_flags): Add CpuPCONFIG.
1979 * i386-opc.h (enum): Add CpuPCONFIG.
1980 (i386_cpu_flags): Add cpupconfig.
1981 * i386-opc.tbl: Add PCONFIG instruction.
1982 * i386-init.h: Regenerate.
1983 * i386-tbl.h: Likewise.
1985 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1987 * i386-dis.c (enum): Add PREFIX_0F09.
1988 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1989 (cpu_flags): Add CpuWBNOINVD.
1990 * i386-opc.h (enum): Add CpuWBNOINVD.
1991 (i386_cpu_flags): Add cpuwbnoinvd.
1992 * i386-opc.tbl: Add WBNOINVD instruction.
1993 * i386-init.h: Regenerate.
1994 * i386-tbl.h: Likewise.
1996 2018-01-17 Jim Wilson <jimw@sifive.com>
1998 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2000 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2002 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2003 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2004 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2005 (cpu_flags): Add CpuIBT, CpuSHSTK.
2006 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2007 (i386_cpu_flags): Add cpuibt, cpushstk.
2008 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2009 * i386-init.h: Regenerate.
2010 * i386-tbl.h: Likewise.
2012 2018-01-16 Nick Clifton <nickc@redhat.com>
2014 * po/pt_BR.po: Updated Brazilian Portugese translation.
2015 * po/de.po: Updated German translation.
2017 2018-01-15 Jim Wilson <jimw@sifive.com>
2019 * riscv-opc.c (match_c_nop): New.
2020 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2022 2018-01-15 Nick Clifton <nickc@redhat.com>
2024 * po/uk.po: Updated Ukranian translation.
2026 2018-01-13 Nick Clifton <nickc@redhat.com>
2028 * po/opcodes.pot: Regenerated.
2030 2018-01-13 Nick Clifton <nickc@redhat.com>
2032 * configure: Regenerate.
2034 2018-01-13 Nick Clifton <nickc@redhat.com>
2036 2.30 branch created.
2038 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2040 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2041 * i386-tbl.h: Regenerate.
2043 2018-01-10 Jan Beulich <jbeulich@suse.com>
2045 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2046 * i386-tbl.h: Re-generate.
2048 2018-01-10 Jan Beulich <jbeulich@suse.com>
2050 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2051 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2052 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2053 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2054 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2055 Disp8MemShift of AVX512VL forms.
2056 * i386-tbl.h: Re-generate.
2058 2018-01-09 Jim Wilson <jimw@sifive.com>
2060 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2061 then the hi_addr value is zero.
2063 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2065 * arm-dis.c (arm_opcodes): Add csdb.
2066 (thumb32_opcodes): Add csdb.
2068 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2070 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2071 * aarch64-asm-2.c: Regenerate.
2072 * aarch64-dis-2.c: Regenerate.
2073 * aarch64-opc-2.c: Regenerate.
2075 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2078 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2079 Remove AVX512 vmovd with 64-bit operands.
2080 * i386-tbl.h: Regenerated.
2082 2018-01-05 Jim Wilson <jimw@sifive.com>
2084 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2087 2018-01-03 Alan Modra <amodra@gmail.com>
2089 Update year range in copyright notice of all files.
2091 2018-01-02 Jan Beulich <jbeulich@suse.com>
2093 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2094 and OPERAND_TYPE_REGZMM entries.
2096 For older changes see ChangeLog-2017
2098 Copyright (C) 2018 Free Software Foundation, Inc.
2100 Copying and distribution of this file, with or without modification,
2101 are permitted in any medium without royalty provided the copyright
2102 notice and this notice are preserved.
2108 version-control: never
projects / deliverable / binutils-gdb.git / blob