opcodes/ChangeLog

   1 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
   4         * i386-tbl.h: Re-generate.
   5
   6 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
   9         * i386-tbl.h: Re-generate.
  10
  11 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  12
  13         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
  14         meaningless.
  15         * i386-tbl.h: Re-generate.
  16
  17 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  18
  19         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
  20         meaningless.
  21         * i386-tbl.h: Re-generate.
  22
  23 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
  26         meaningless.
  27         * i386-tbl.h: Re-generate.
  28
  29 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  30
  31         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
  32         * i386-tbl.h: Re-generate.
  33
  34 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
  37         * i386-tbl.h: Re-generate.
  38
  39 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
  42         * i386-tbl.h: Re-generate.
  43
  44 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  45
  46         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
  47         (vpbroadcastw, rdpid): Drop NoRex64.
  48         * i386-tbl.h: Re-generate.
  49
  50 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  51
  52         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
  53         store templates, adding D.
  54         * i386-tbl.h: Re-generate.
  55
  56 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  57
  58         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
  59         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
  60         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
  61         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
  62         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
  63         Fold load and store templates where possible, adding D. Drop
  64         IgnoreSize where it was pointlessly present. Drop redundant
  65         *word.
  66         * i386-tbl.h: Re-generate.
  67
  68 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  69
  70         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
  71         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
  72         (intel_operand_size): Handle v_bndmk_mode.
  73         (OP_E_memory): Likewise. Produce (bad) when also riprel.
  74
  75 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
  76
  77         * disassemble.c (ARCH_s12z): Define if ARCH_all.
  78
  79 2018-08-31  Kito Cheng  <kito@andestech.com>
  80
  81         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
  82         compressed floating point instructions.
  83
  84 2018-08-30  Kito Cheng  <kito@andestech.com>
  85
  86         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
  87         riscv_opcode.xlen_requirement.
  88         * riscv-opc.c (riscv_opcodes): Update for struct change.
  89
  90 2018-08-29  Martin Aberg  <maberg@gaisler.com>
  91
  92         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
  93         psr (PWRPSR) instruction.
  94
  95 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  96
  97         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
  98
  99 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 100
 101         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 102
 103 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 104
 105         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 106         loongson3a as an alias of gs464 for compatibility.
 107         * mips-opc.c (mips_opcodes): Change Comments.
 108
 109 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 110
 111         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 112         option.
 113         (print_mips_disassembler_options): Document -M loongson-ext.
 114         * mips-opc.c (LEXT2): New macro.
 115         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 116
 117 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 118
 119          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 120          descriptors.
 121          (parse_mips_ase_option): Handle -M loongson-ext option.
 122          (print_mips_disassembler_options): Document -M loongson-ext.
 123          * mips-opc.c (IL3A): Delete.
 124          * mips-opc.c (LEXT): New macro.
 125          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 126          instructions.
 127
 128 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 129
 130         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 131         descriptors.
 132         (parse_mips_ase_option): Handle -M loongson-cam option.
 133         (print_mips_disassembler_options): Document -M loongson-cam.
 134         * mips-opc.c (LCAM): New macro.
 135         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 136         instructions.
 137
 138 2018-08-21  Alan Modra  <amodra@gmail.com>
 139
 140         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 141         (skip_optional_operands): Count optional operands, and update
 142         ppc_optional_operand_value call.
 143         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 144         (extract_vlensi): Likewise.
 145         (extract_fxm): Return default value for missing optional operand.
 146         (extract_ls, extract_raq, extract_tbr): Likewise.
 147         (insert_sxl, extract_sxl): New functions.
 148         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 149         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 150         flag and extra entry.
 151         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 152         extract_sxl.
 153
 154 2018-08-20  Alan Modra  <amodra@gmail.com>
 155
 156         * sh-opc.h (MASK): Simplify.
 157
 158 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 159
 160         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 161         BM_RESERVED0 or BM_RESERVED1
 162         (bm_rel_decode, bm_n_bytes): Ditto.
 163
 164 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 165
 166         * s12z.h: Delete.
 167
 168 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 169
 170         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 171         address with the addr32 prefix and without base nor index
 172         registers.
 173
 174 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 175
 176         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 177         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 178         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 179         (cpu_flags): Add CpuCMOV and CpuFXSR.
 180         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 181         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 182         * i386-init.h: Regenerated.
 183         * i386-tbl.h: Likewise.
 184
 185 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 186
 187         * arc-regs.h: Update auxiliary registers.
 188
 189 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 192         (RegIP, RegIZ): Define.
 193         * i386-reg.tbl: Adjust comments.
 194         (rip): Use Qword instead of BaseIndex. Use RegIP.
 195         (eip): Use Dword instead of BaseIndex. Use RegIP.
 196         (riz): Add Qword. Use RegIZ.
 197         (eiz): Add Dword. Use RegIZ.
 198         * i386-tbl.h: Re-generate.
 199
 200 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 201
 202         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 203         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 204         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 205         * i386-tbl.h: Re-generate.
 206
 207 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-gen.c (operand_types): Remove Mem field.
 210         * i386-opc.h (union i386_operand_type): Remove mem field.
 211         * i386-init.h, i386-tbl.h: Re-generate.
 212
 213 2018-08-01  Alan Modra  <amodra@gmail.com>
 214
 215         * po/POTFILES.in: Regenerate.
 216
 217 2018-07-31  Nick Clifton  <nickc@redhat.com>
 218
 219         * po/sv.po: Updated Swedish translation.
 220
 221 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 222
 223         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 224         * i386-init.h, i386-tbl.h: Re-generate.
 225
 226 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 227
 228         * i386-opc.h (ZEROING_MASKING) Rename to ...
 229         (DYNAMIC_MASKING): ... this. Adjust comment.
 230         * i386-opc.tbl (MaskingMorZ): Define.
 231         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 232         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 233         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 234         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 235         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 236         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 237         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 238         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 239         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 240
 241 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-opc.tbl: Use element rather than vector size for AVX512*
 244         scatter/gather insns.
 245         * i386-tbl.h: Re-generate.
 246
 247 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 250         (cpu_flags): Drop CpuVREX.
 251         * i386-opc.h (CpuVREX): Delete.
 252         (union i386_cpu_flags): Remove cpuvrex.
 253         * i386-init.h, i386-tbl.h: Re-generate.
 254
 255 2018-07-30  Jim Wilson  <jimw@sifive.com>
 256
 257         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 258         fields.
 259         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 260
 261 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 262
 263         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 264         * Makefile.in: Regenerated.
 265         * configure.ac: Add C-SKY.
 266         * configure: Regenerated.
 267         * csky-dis.c: New file.
 268         * csky-opc.h: New file.
 269         * disassemble.c (ARCH_csky): Define.
 270         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 271         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 272
 273 2018-07-27  Alan Modra  <amodra@gmail.com>
 274
 275         * ppc-opc.c (insert_sprbat): Correct function parameter and
 276         return type.
 277         (extract_sprbat): Likewise, variable too.
 278
 279 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 280             Alan Modra  <amodra@gmail.com>
 281
 282         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 283         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 284         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 285         support disjointed BAT.
 286         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 287         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 288         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 289
 290 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 291             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 292
 293         * i386-gen.c (adjust_broadcast_modifier): New function.
 294         (process_i386_opcode_modifier): Add an argument for operands.
 295         Adjust the Broadcast value based on operands.
 296         (output_i386_opcode): Pass operand_types to
 297         process_i386_opcode_modifier.
 298         (process_i386_opcodes): Pass NULL as operands to
 299         process_i386_opcode_modifier.
 300         * i386-opc.h (BYTE_BROADCAST): New.
 301         (WORD_BROADCAST): Likewise.
 302         (DWORD_BROADCAST): Likewise.
 303         (QWORD_BROADCAST): Likewise.
 304         (i386_opcode_modifier): Expand broadcast to 3 bits.
 305         * i386-tbl.h: Regenerated.
 306
 307 2018-07-24  Alan Modra  <amodra@gmail.com>
 308
 309         PR 23430
 310         * or1k-desc.h: Regenerate.
 311
 312 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 315         vcvtusi2ss, and vcvtusi2sd.
 316         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 317         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 318         * i386-tbl.h: Re-generate.
 319
 320 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 321
 322         * arc-opc.c (extract_w6): Fix extending the sign.
 323
 324 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 325
 326         * arc-tbl.h (vewt): Allow it for ARC EM family.
 327
 328 2018-07-23  Alan Modra  <amodra@gmail.com>
 329
 330         PR 23419
 331         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 332         opcode variants for mtspr/mfspr encodings.
 333
 334 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 335             Maciej W. Rozycki  <macro@mips.com>
 336
 337         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 338         loongson3a descriptors.
 339         (parse_mips_ase_option): Handle -M loongson-mmi option.
 340         (print_mips_disassembler_options): Document -M loongson-mmi.
 341         * mips-opc.c (LMMI): New macro.
 342         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 343         instructions.
 344
 345 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 346
 347         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 348         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 349         IgnoreSize and [XYZ]MMword where applicable.
 350         * i386-tbl.h: Re-generate.
 351
 352 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 353
 354         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 355         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 356         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 357         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 358         * i386-tbl.h: Re-generate.
 359
 360 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 361
 362         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 363         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 364         VPCLMULQDQ templates into their respective AVX512VL counterparts
 365         where possible, using Disp8ShiftVL and CheckRegSize instead of
 366         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 367         * i386-tbl.h: Re-generate.
 368
 369 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 370
 371         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 372         AVX512VL counterparts where possible, using Disp8ShiftVL and
 373         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 374         IgnoreSize) as appropriate.
 375         * i386-tbl.h: Re-generate.
 376
 377 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 378
 379         * i386-opc.tbl: Fold AVX512BW templates into their respective
 380         AVX512VL counterparts where possible, using Disp8ShiftVL and
 381         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 382         IgnoreSize) as appropriate.
 383         * i386-tbl.h: Re-generate.
 384
 385 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 386
 387         * i386-opc.tbl: Fold AVX512CD templates into their respective
 388         AVX512VL counterparts where possible, using Disp8ShiftVL and
 389         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 390         IgnoreSize) as appropriate.
 391         * i386-tbl.h: Re-generate.
 392
 393 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 394
 395         * i386-opc.h (DISP8_SHIFT_VL): New.
 396         * i386-opc.tbl (Disp8ShiftVL):  Define.
 397         (various): Fold AVX512VL templates into their respective
 398         AVX512F counterparts where possible, using Disp8ShiftVL and
 399         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 400         IgnoreSize) as appropriate.
 401         * i386-tbl.h: Re-generate.
 402
 403 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 404
 405         * Makefile.am: Change dependencies and rule for
 406         $(srcdir)/i386-init.h.
 407         * Makefile.in: Re-generate.
 408         * i386-gen.c (process_i386_opcodes): New local variable
 409         "marker". Drop opening of input file. Recognize marker and line
 410         number directives.
 411         * i386-opc.tbl (OPCODE_I386_H): Define.
 412         (i386-opc.h): Include it.
 413         (None): Undefine.
 414
 415 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 416
 417         PR gas/23418
 418         * i386-opc.h (Byte): Update comments.
 419         (Word): Likewise.
 420         (Dword): Likewise.
 421         (Fword): Likewise.
 422         (Qword): Likewise.
 423         (Tbyte): Likewise.
 424         (Xmmword): Likewise.
 425         (Ymmword): Likewise.
 426         (Zmmword): Likewise.
 427         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 428         vcvttps2uqq.
 429         * i386-tbl.h: Regenerated.
 430
 431 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 432
 433         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 434         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 435         * aarch64-asm-2.c: Regenerate.
 436         * aarch64-dis-2.c: Regenerate.
 437         * aarch64-opc-2.c: Regenerate.
 438
 439 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 440
 441         PR binutils/23192
 442         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 443         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 444         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 445         sqdmulh, sqrdmulh): Use Em16.
 446
 447 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 448
 449         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 450         csdb together with them.
 451         (thumb32_opcodes): Likewise.
 452
 453 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 456         requiring 32-bit registers as operands 2 and 3. Improve
 457         comments.
 458         (mwait, mwaitx): Fold templates. Improve comments.
 459         OPERAND_TYPE_INOUTPORTREG.
 460         * i386-tbl.h: Re-generate.
 461
 462 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 463
 464         * i386-gen.c (operand_type_init): Remove
 465         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 466         OPERAND_TYPE_INOUTPORTREG.
 467         * i386-init.h: Re-generate.
 468
 469 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 470
 471         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 472         (wrssq, wrussq): Add Qword.
 473         * i386-tbl.h: Re-generate.
 474
 475 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 476
 477         * i386-opc.h: Rename OTMax to OTNum.
 478         (OTNumOfUints): Adjust calculation.
 479         (OTUnused): Directly alias to OTNum.
 480
 481 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 482
 483         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 484         `reg_xys'.
 485         (lea_reg_xys): Likewise.
 486         (print_insn_loop_primitive): Rename `reg' local variable to
 487         `reg_dxy'.
 488
 489 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 490
 491         PR binutils/23242
 492         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 493
 494 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 495
 496         PR binutils/23369
 497         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 498         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 499
 500 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 501
 502         PR tdep/8282
 503         * mips-dis.c (mips_option_arg_t): New enumeration.
 504         (mips_options): New variable.
 505         (disassembler_options_mips): New function.
 506         (print_mips_disassembler_options): Reimplement in terms of
 507         `disassembler_options_mips'.
 508         * arm-dis.c (disassembler_options_arm): Adapt to using the
 509         `disasm_options_and_args_t' structure.
 510         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 511         * s390-dis.c (disassembler_options_s390): Likewise.
 512
 513 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 514
 515         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 516         expected result.
 517         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 518         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 519         * testsuite/ld-arm/tls-longplt.d: Likewise.
 520
 521 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 522
 523         PR binutils/23192
 524         * aarch64-asm-2.c: Regenerate.
 525         * aarch64-dis-2.c: Likewise.
 526         * aarch64-opc-2.c: Likewise.
 527         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 528         * aarch64-opc.c (operand_general_constraint_met_p,
 529         aarch64_print_operand): Likewise.
 530         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 531         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 532         fmlal2, fmlsl2.
 533         (AARCH64_OPERANDS): Add Em2.
 534
 535 2018-06-26  Nick Clifton  <nickc@redhat.com>
 536
 537         * po/uk.po: Updated Ukranian translation.
 538         * po/de.po: Updated German translation.
 539         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 540
 541 2018-06-26  Nick Clifton  <nickc@redhat.com>
 542
 543         * nfp-dis.c: Fix spelling mistake.
 544
 545 2018-06-24  Nick Clifton  <nickc@redhat.com>
 546
 547         * configure: Regenerate.
 548         * po/opcodes.pot: Regenerate.
 549
 550 2018-06-24  Nick Clifton  <nickc@redhat.com>
 551
 552         2.31 branch created.
 553
 554 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 555
 556         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 557         * aarch64-asm-2.c: Regenerate.
 558         * aarch64-dis-2.c: Likewise.
 559
 560 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 561
 562         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 563         `-M ginv' option description.
 564
 565 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 566
 567         PR gas/23305
 568         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 569         la and lla.
 570
 571 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 572
 573         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 574         * configure.ac: Remove AC_PREREQ.
 575         * Makefile.in: Re-generate.
 576         * aclocal.m4: Re-generate.
 577         * configure: Re-generate.
 578
 579 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 580
 581         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 582         mips64r6 descriptors.
 583         (parse_mips_ase_option): Handle -Mginv option.
 584         (print_mips_disassembler_options): Document -Mginv.
 585         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 586         (GINV): New macro.
 587         (mips_opcodes): Define ginvi and ginvt.
 588
 589 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 590             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 591
 592         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 593         * mips-opc.c (CRC, CRC64): New macros.
 594         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 595         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 596         crc32cd for CRC64.
 597
 598 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 599
 600         PR 20319
 601         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 602         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 603
 604 2018-06-06  Alan Modra  <amodra@gmail.com>
 605
 606         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 607         setjmp.  Move init for some other vars later too.
 608
 609 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 610
 611         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 612         (dis_private): Add new fields for property section tracking.
 613         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 614         (xtensa_instruction_fits): New functions.
 615         (fetch_data): Bump minimal fetch size to 4.
 616         (print_insn_xtensa): Make struct dis_private static.
 617         Load and prepare property table on section change.
 618         Don't disassemble literals. Don't disassemble instructions that
 619         cross property table boundaries.
 620
 621 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 622
 623         * configure: Regenerated.
 624
 625 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 626
 627         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 628         * i386-tbl.h: Re-generate.
 629
 630 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 631
 632         * i386-opc.tbl (sldt, str): Add NoRex64.
 633         * i386-tbl.h: Re-generate.
 634
 635 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 636
 637         * i386-opc.tbl (invpcid): Add Oword.
 638         * i386-tbl.h: Re-generate.
 639
 640 2018-06-01  Alan Modra  <amodra@gmail.com>
 641
 642         * sysdep.h (_bfd_error_handler): Don't declare.
 643         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 644         * rl78-decode.opc: Likewise.
 645         * msp430-decode.c: Regenerate.
 646         * rl78-decode.c: Regenerate.
 647
 648 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 649
 650         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 651         * i386-init.h : Regenerated.
 652
 653 2018-05-25  Alan Modra  <amodra@gmail.com>
 654
 655         * Makefile.in: Regenerate.
 656         * po/POTFILES.in: Regenerate.
 657
 658 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 659
 660         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 661         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 662         (insert_bab, extract_bab, insert_btab, extract_btab,
 663         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 664         (BAT, BBA VBA RBS XB6S): Delete macros.
 665         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 666         (BB, BD, RBX, XC6): Update for new macros.
 667         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 668         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 669         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 670         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 671
 672 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 673
 674         * Makefile.am: Add support for s12z architecture.
 675         * configure.ac: Likewise.
 676         * disassemble.c: Likewise.
 677         * disassemble.h: Likewise.
 678         * Makefile.in: Regenerate.
 679         * configure: Regenerate.
 680         * s12z-dis.c: New file.
 681         * s12z.h: New file.
 682
 683 2018-05-18  Alan Modra  <amodra@gmail.com>
 684
 685         * nfp-dis.c: Don't #include libbfd.h.
 686         (init_nfp3200_priv): Use bfd_get_section_contents.
 687         (nit_nfp6000_mecsr_sec): Likewise.
 688
 689 2018-05-17  Nick Clifton  <nickc@redhat.com>
 690
 691         * po/zh_CN.po: Updated simplified Chinese translation.
 692
 693 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 694
 695         PR binutils/23109
 696         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 697         * aarch64-dis-2.c: Regenerate.
 698
 699 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 700
 701         PR binutils/21446
 702         * aarch64-asm.c (opintl.h): Include.
 703         (aarch64_ins_sysreg): Enforce read/write constraints.
 704         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 705         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 706         (F_REG_READ, F_REG_WRITE): New.
 707         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 708         AARCH64_OPND_SYSREG.
 709         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 710         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 711         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 712         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 713         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 714         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 715         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 716         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 717         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 718         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 719         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 720         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 721         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 722         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 723         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 724         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 725         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 726
 727 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 728
 729         PR binutils/21446
 730         * aarch64-dis.c (no_notes: New.
 731         (parse_aarch64_dis_option): Support notes.
 732         (aarch64_decode_insn, print_operands): Likewise.
 733         (print_aarch64_disassembler_options): Document notes.
 734         * aarch64-opc.c (aarch64_print_operand): Support notes.
 735
 736 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 737
 738         PR binutils/21446
 739         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 740         and take error struct.
 741         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 742         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 743         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 744         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 745         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 746         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 747         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 748         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 749         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 750         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 751         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 752         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 753         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 754         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 755         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 756         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 757         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 758         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 759         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 760         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 761         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 762         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 763         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 764         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 765         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 766         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 767         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 768         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 769         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 770         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 771         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 772         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 773         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 774         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 775         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 776         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 777         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 778         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 779         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 780         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 781         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 782         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 783         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 784         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 785         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 786         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 787         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 788         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 789         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 790         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 791         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 792         (determine_disassembling_preference, aarch64_decode_insn,
 793         print_insn_aarch64_word, print_insn_data): Take errors struct.
 794         (print_insn_aarch64): Use errors.
 795         * aarch64-asm-2.c: Regenerate.
 796         * aarch64-dis-2.c: Regenerate.
 797         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 798         boolean in aarch64_insert_operan.
 799         (print_operand_extractor): Likewise.
 800         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 801
 802 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 803
 804         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 805
 806 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 807
 808         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 809
 810 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 811
 812         * cr16-opc.c (cr16_instruction): Comment typo fix.
 813         * hppa-dis.c (print_insn_hppa): Likewise.
 814
 815 2018-05-08  Jim Wilson  <jimw@sifive.com>
 816
 817         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 818         (match_c_slli64, match_srxi_as_c_srxi): New.
 819         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 820         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 821         <c.slli, c.srli, c.srai>: Use match_s_slli.
 822         <c.slli64, c.srli64, c.srai64>: New.
 823
 824 2018-05-08  Alan Modra  <amodra@gmail.com>
 825
 826         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 827         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 828         partition opcode space for index lookup.
 829
 830 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 831
 832         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 833         <insn_length>: ...with this.  Update usage.
 834         Remove duplicate call to *info->memory_error_func.
 835
 836 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 837             H.J. Lu  <hongjiu.lu@intel.com>
 838
 839         * i386-dis.c (Gva): New.
 840         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 841         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 842         (prefix_table): New instructions (see prefix above).
 843         (mod_table): New instructions (see prefix above).
 844         (OP_G): Handle va_mode.
 845         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 846         CPU_MOVDIR64B_FLAGS.
 847         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 848         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 849         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 850         * i386-opc.tbl: Add movidir{i,64b}.
 851         * i386-init.h: Regenerated.
 852         * i386-tbl.h: Likewise.
 853
 854 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 855
 856         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 857         AddrPrefixOpReg.
 858         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 859         (AddrPrefixOpReg): This.
 860         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 861         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 862
 863 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 864
 865         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 866         (vle_num_opcodes): Likewise.
 867         (spe2_num_opcodes): Likewise.
 868         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 869         initialization loop.
 870         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 871         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 872         only once.
 873
 874 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 875
 876         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 877
 878 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 879
 880         Makefile.am: Added nfp-dis.c.
 881         configure.ac: Added bfd_nfp_arch.
 882         disassemble.h: Added print_insn_nfp prototype.
 883         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 884         nfp-dis.c: New, for NFP support.
 885         po/POTFILES.in: Added nfp-dis.c to the list.
 886         Makefile.in: Regenerate.
 887         configure: Regenerate.
 888
 889 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 890
 891         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 892         templates into their base ones.
 893         * i386-tlb.h: Re-generate.
 894
 895 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 896
 897         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 898         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 899         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 900         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 901         * i386-init.h: Re-generate.
 902
 903 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 904
 905         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 906         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 907         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 908         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 909         comment.
 910         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 911         and CpuRegMask.
 912         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 913         CpuRegMask: Delete.
 914         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 915         cpuregzmm, and cpuregmask.
 916         * i386-init.h: Re-generate.
 917         * i386-tbl.h: Re-generate.
 918
 919 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 920
 921         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 922         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 923         * i386-init.h: Re-generate.
 924
 925 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 926
 927         * i386-gen.c (VexImmExt): Delete.
 928         * i386-opc.h (VexImmExt, veximmext): Delete.
 929         * i386-opc.tbl: Drop all VexImmExt uses.
 930         * i386-tlb.h: Re-generate.
 931
 932 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 933
 934         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 935         register-only forms.
 936         * i386-tlb.h: Re-generate.
 937
 938 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 939
 940         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 941
 942 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 943
 944         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 945         PREFIX_0F1C.
 946         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 947         (cpu_flags): Add CpuCLDEMOTE.
 948         * i386-init.h: Regenerate.
 949         * i386-opc.h (enum): Add CpuCLDEMOTE,
 950         (i386_cpu_flags): Add cpucldemote.
 951         * i386-opc.tbl: Add cldemote.
 952         * i386-tbl.h: Regenerate.
 953
 954 2018-04-16  Alan Modra  <amodra@gmail.com>
 955
 956         * Makefile.am: Remove sh5 and sh64 support.
 957         * configure.ac: Likewise.
 958         * disassemble.c: Likewise.
 959         * disassemble.h: Likewise.
 960         * sh-dis.c: Likewise.
 961         * sh64-dis.c: Delete.
 962         * sh64-opc.c: Delete.
 963         * sh64-opc.h: Delete.
 964         * Makefile.in: Regenerate.
 965         * configure: Regenerate.
 966         * po/POTFILES.in: Regenerate.
 967
 968 2018-04-16  Alan Modra  <amodra@gmail.com>
 969
 970         * Makefile.am: Remove w65 support.
 971         * configure.ac: Likewise.
 972         * disassemble.c: Likewise.
 973         * disassemble.h: Likewise.
 974         * w65-dis.c: Delete.
 975         * w65-opc.h: Delete.
 976         * Makefile.in: Regenerate.
 977         * configure: Regenerate.
 978         * po/POTFILES.in: Regenerate.
 979
 980 2018-04-16  Alan Modra  <amodra@gmail.com>
 981
 982         * configure.ac: Remove we32k support.
 983         * configure: Regenerate.
 984
 985 2018-04-16  Alan Modra  <amodra@gmail.com>
 986
 987         * Makefile.am: Remove m88k support.
 988         * configure.ac: Likewise.
 989         * disassemble.c: Likewise.
 990         * disassemble.h: Likewise.
 991         * m88k-dis.c: Delete.
 992         * Makefile.in: Regenerate.
 993         * configure: Regenerate.
 994         * po/POTFILES.in: Regenerate.
 995
 996 2018-04-16  Alan Modra  <amodra@gmail.com>
 997
 998         * Makefile.am: Remove i370 support.
 999         * configure.ac: Likewise.
1000         * disassemble.c: Likewise.
1001         * disassemble.h: Likewise.
1002         * i370-dis.c: Delete.
1003         * i370-opc.c: Delete.
1004         * Makefile.in: Regenerate.
1005         * configure: Regenerate.
1006         * po/POTFILES.in: Regenerate.
1007
1008 2018-04-16  Alan Modra  <amodra@gmail.com>
1009
1010         * Makefile.am: Remove h8500 support.
1011         * configure.ac: Likewise.
1012         * disassemble.c: Likewise.
1013         * disassemble.h: Likewise.
1014         * h8500-dis.c: Delete.
1015         * h8500-opc.h: Delete.
1016         * Makefile.in: Regenerate.
1017         * configure: Regenerate.
1018         * po/POTFILES.in: Regenerate.
1019
1020 2018-04-16  Alan Modra  <amodra@gmail.com>
1021
1022         * configure.ac: Remove tahoe support.
1023         * configure: Regenerate.
1024
1025 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1026
1027         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1028         umwait.
1029         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1030         64-bit mode.
1031         * i386-tbl.h: Regenerated.
1032
1033 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1034
1035         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1036         PREFIX_MOD_1_0FAE_REG_6.
1037         (va_mode): New.
1038         (OP_E_register): Use va_mode.
1039         * i386-dis-evex.h (prefix_table):
1040         New instructions (see prefixes above).
1041         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1042         (cpu_flags): Likewise.
1043         * i386-opc.h (enum): Likewise.
1044         (i386_cpu_flags): Likewise.
1045         * i386-opc.tbl: Add umonitor, umwait, tpause.
1046         * i386-init.h: Regenerate.
1047         * i386-tbl.h: Likewise.
1048
1049 2018-04-11  Alan Modra  <amodra@gmail.com>
1050
1051         * opcodes/i860-dis.c: Delete.
1052         * opcodes/i960-dis.c: Delete.
1053         * Makefile.am: Remove i860 and i960 support.
1054         * configure.ac: Likewise.
1055         * disassemble.c: Likewise.
1056         * disassemble.h: Likewise.
1057         * Makefile.in: Regenerate.
1058         * configure: Regenerate.
1059         * po/POTFILES.in: Regenerate.
1060
1061 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1062
1063         PR binutils/23025
1064         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1065         to 0.
1066         (print_insn): Clear vex instead of vex.evex.
1067
1068 2018-04-04  Nick Clifton  <nickc@redhat.com>
1069
1070         * po/es.po: Updated Spanish translation.
1071
1072 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-gen.c (opcode_modifiers): Delete VecESize.
1075         * i386-opc.h (VecESize): Delete.
1076         (struct i386_opcode_modifier): Delete vecesize.
1077         * i386-opc.tbl: Drop VecESize.
1078         * i386-tlb.h: Re-generate.
1079
1080 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1081
1082         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1083         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1084         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1085         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1086         * i386-tlb.h: Re-generate.
1087
1088 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1089
1090         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1091         Fold AVX512 forms
1092         * i386-tlb.h: Re-generate.
1093
1094 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1095
1096         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1097         (vex_len_table): Drop Y for vcvt*2si.
1098         (putop): Replace plain 'Y' handling by abort().
1099
1100 2018-03-28  Nick Clifton  <nickc@redhat.com>
1101
1102         PR 22988
1103         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1104         instructions with only a base address register.
1105         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1106         handle AARHC64_OPND_SVE_ADDR_R.
1107         (aarch64_print_operand): Likewise.
1108         * aarch64-asm-2.c: Regenerate.
1109         * aarch64_dis-2.c: Regenerate.
1110         * aarch64-opc-2.c: Regenerate.
1111
1112 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1113
1114         * i386-opc.tbl: Drop VecESize from register only insn forms and
1115         memory forms not allowing broadcast.
1116         * i386-tlb.h: Re-generate.
1117
1118 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1119
1120         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1121         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1122         sha256*): Drop Disp<N>.
1123
1124 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1125
1126         * i386-dis.c (EbndS, bnd_swap_mode): New.
1127         (prefix_table): Use EbndS.
1128         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1129         * i386-opc.tbl (bndmov): Move misplaced Load.
1130         * i386-tlb.h: Re-generate.
1131
1132 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1133
1134         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1135         templates allowing memory operands and folded ones for register
1136         only flavors.
1137         * i386-tlb.h: Re-generate.
1138
1139 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1140
1141         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1142         256-bit templates. Drop redundant leftover Disp<N>.
1143         * i386-tlb.h: Re-generate.
1144
1145 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1146
1147         * riscv-opc.c (riscv_insn_types): New.
1148
1149 2018-03-13  Nick Clifton  <nickc@redhat.com>
1150
1151         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1152
1153 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1154
1155         * i386-opc.tbl: Add Optimize to clr.
1156         * i386-tbl.h: Regenerated.
1157
1158 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1159
1160         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1161         * i386-opc.h (OldGcc): Removed.
1162         (i386_opcode_modifier): Remove oldgcc.
1163         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1164         instructions for old (<= 2.8.1) versions of gcc.
1165         * i386-tbl.h: Regenerated.
1166
1167 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1168
1169         * i386-opc.h (EVEXDYN): New.
1170         * i386-opc.tbl: Fold various AVX512VL templates.
1171         * i386-tlb.h: Re-generate.
1172
1173 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1174
1175         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1176         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1177         vpexpandd, vpexpandq): Fold AFX512VF templates.
1178         * i386-tlb.h: Re-generate.
1179
1180 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1181
1182         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1183         Fold 128- and 256-bit VEX-encoded templates.
1184         * i386-tlb.h: Re-generate.
1185
1186 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1187
1188         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1189         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1190         vpexpandd, vpexpandq): Fold AVX512F templates.
1191         * i386-tlb.h: Re-generate.
1192
1193 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1194
1195         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1196         64-bit templates. Drop Disp<N>.
1197         * i386-tlb.h: Re-generate.
1198
1199 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1200
1201         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1202         and 256-bit templates.
1203         * i386-tlb.h: Re-generate.
1204
1205 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1206
1207         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1208         * i386-tlb.h: Re-generate.
1209
1210 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1211
1212         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1213         Drop NoAVX.
1214         * i386-tlb.h: Re-generate.
1215
1216 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1217
1218         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1219         * i386-tlb.h: Re-generate.
1220
1221 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1222
1223         * i386-gen.c (opcode_modifiers): Delete FloatD.
1224         * i386-opc.h (FloatD): Delete.
1225         (struct i386_opcode_modifier): Delete floatd.
1226         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1227         FloatD by D.
1228         * i386-tlb.h: Re-generate.
1229
1230 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1231
1232         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1233
1234 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1235
1236         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1237         * i386-tlb.h: Re-generate.
1238
1239 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1240
1241         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1242         forms.
1243         * i386-tlb.h: Re-generate.
1244
1245 2018-03-07  Alan Modra  <amodra@gmail.com>
1246
1247         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1248         bfd_arch_rs6000.
1249         * disassemble.h (print_insn_rs6000): Delete.
1250         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1251         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1252         (print_insn_rs6000): Delete.
1253
1254 2018-03-03  Alan Modra  <amodra@gmail.com>
1255
1256         * sysdep.h (opcodes_error_handler): Define.
1257         (_bfd_error_handler): Declare.
1258         * Makefile.am: Remove stray #.
1259         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1260         EDIT" comment.
1261         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1262         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1263         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1264         opcodes_error_handler to print errors.  Standardize error messages.
1265         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1266         and include opintl.h.
1267         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1268         * i386-gen.c: Standardize error messages.
1269         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1270         * Makefile.in: Regenerate.
1271         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1272         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1273         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1274         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1275         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1276         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1277         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1278         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1279         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1280         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1281         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1282         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1283         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1284
1285 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1286
1287         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1288         vpsub[bwdq] instructions.
1289         * i386-tbl.h: Regenerated.
1290
1291 2018-03-01  Alan Modra  <amodra@gmail.com>
1292
1293         * configure.ac (ALL_LINGUAS): Sort.
1294         * configure: Regenerate.
1295
1296 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1297
1298         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1299         macro by assignements.
1300
1301 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1302
1303         PR gas/22871
1304         * i386-gen.c (opcode_modifiers): Add Optimize.
1305         * i386-opc.h (Optimize): New enum.
1306         (i386_opcode_modifier): Add optimize.
1307         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1308         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1309         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1310         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1311         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1312         vpxord and vpxorq.
1313         * i386-tbl.h: Regenerated.
1314
1315 2018-02-26  Alan Modra  <amodra@gmail.com>
1316
1317         * crx-dis.c (getregliststring): Allocate a large enough buffer
1318         to silence false positive gcc8 warning.
1319
1320 2018-02-22  Shea Levy <shea@shealevy.com>
1321
1322         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1323
1324 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1325
1326         * i386-opc.tbl: Add {rex},
1327         * i386-tbl.h: Regenerated.
1328
1329 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1330
1331         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1332         (mips16_opcodes): Replace `M' with `m' for "restore".
1333
1334 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1335
1336         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1337
1338 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1339
1340         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1341         variable to `function_index'.
1342
1343 2018-02-13  Nick Clifton  <nickc@redhat.com>
1344
1345         PR 22823
1346         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1347         about truncation of printing.
1348
1349 2018-02-12  Henry Wong <henry@stuffedcow.net>
1350
1351         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1352
1353 2018-02-05  Nick Clifton  <nickc@redhat.com>
1354
1355         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1356
1357 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1358
1359         * i386-dis.c (enum): Add pconfig.
1360         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1361         (cpu_flags): Add CpuPCONFIG.
1362         * i386-opc.h (enum): Add CpuPCONFIG.
1363         (i386_cpu_flags): Add cpupconfig.
1364         * i386-opc.tbl: Add PCONFIG instruction.
1365         * i386-init.h: Regenerate.
1366         * i386-tbl.h: Likewise.
1367
1368 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1369
1370         * i386-dis.c (enum): Add PREFIX_0F09.
1371         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1372         (cpu_flags): Add CpuWBNOINVD.
1373         * i386-opc.h (enum): Add CpuWBNOINVD.
1374         (i386_cpu_flags): Add cpuwbnoinvd.
1375         * i386-opc.tbl: Add WBNOINVD instruction.
1376         * i386-init.h: Regenerate.
1377         * i386-tbl.h: Likewise.
1378
1379 2018-01-17  Jim Wilson  <jimw@sifive.com>
1380
1381         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1382
1383 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1384
1385         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1386         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1387         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1388         (cpu_flags): Add CpuIBT, CpuSHSTK.
1389         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1390         (i386_cpu_flags): Add cpuibt, cpushstk.
1391         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1392         * i386-init.h: Regenerate.
1393         * i386-tbl.h: Likewise.
1394
1395 2018-01-16  Nick Clifton  <nickc@redhat.com>
1396
1397         * po/pt_BR.po: Updated Brazilian Portugese translation.
1398         * po/de.po: Updated German translation.
1399
1400 2018-01-15  Jim Wilson  <jimw@sifive.com>
1401
1402         * riscv-opc.c (match_c_nop): New.
1403         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1404
1405 2018-01-15  Nick Clifton  <nickc@redhat.com>
1406
1407         * po/uk.po: Updated Ukranian translation.
1408
1409 2018-01-13  Nick Clifton  <nickc@redhat.com>
1410
1411         * po/opcodes.pot: Regenerated.
1412
1413 2018-01-13  Nick Clifton  <nickc@redhat.com>
1414
1415         * configure: Regenerate.
1416
1417 2018-01-13  Nick Clifton  <nickc@redhat.com>
1418
1419         2.30 branch created.
1420
1421 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1422
1423         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1424         * i386-tbl.h: Regenerate.
1425
1426 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1427
1428         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1429         * i386-tbl.h: Re-generate.
1430
1431 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1432
1433         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1434         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1435         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1436         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1437         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1438         Disp8MemShift of AVX512VL forms.
1439         * i386-tbl.h: Re-generate.
1440
1441 2018-01-09  Jim Wilson  <jimw@sifive.com>
1442
1443         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1444         then the hi_addr value is zero.
1445
1446 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1447
1448         * arm-dis.c (arm_opcodes): Add csdb.
1449         (thumb32_opcodes): Add csdb.
1450
1451 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1452
1453         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1454         * aarch64-asm-2.c: Regenerate.
1455         * aarch64-dis-2.c: Regenerate.
1456         * aarch64-opc-2.c: Regenerate.
1457
1458 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1459
1460         PR gas/22681
1461         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1462         Remove AVX512 vmovd with 64-bit operands.
1463         * i386-tbl.h: Regenerated.
1464
1465 2018-01-05  Jim Wilson  <jimw@sifive.com>
1466
1467         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1468         jalr.
1469
1470 2018-01-03  Alan Modra  <amodra@gmail.com>
1471
1472         Update year range in copyright notice of all files.
1473
1474 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1475
1476         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1477         and OPERAND_TYPE_REGZMM entries.
1478
1479 For older changes see ChangeLog-2017
1480 \f
1481 Copyright (C) 2018 Free Software Foundation, Inc.
1482
1483 Copying and distribution of this file, with or without modification,
1484 are permitted in any medium without royalty provided the copyright
1485 notice and this notice are preserved.
1486
1487 Local Variables:
1488 mode: change-log
1489 left-margin: 8
1490 fill-column: 74
1491 version-control: never
1492 End: