opcodes/ChangeLog

   1 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * mips-dis.c (print_mips_disassembler_options): Reformat output.
   4
   5 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
   6
   7         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
   8         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
   9
  10 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  11
  12         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
  13
  14 2016-12-01  Nick Clifton  <nickc@redhat.com>
  15
  16         PR binutils/20893
  17         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
  18         opcode designator.
  19
  20 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  21
  22         * arc-opc.c (insert_ra_chk): New function.
  23         (insert_rb_chk): Likewise.
  24         (insert_rad): Update text error message.
  25         (insert_rcd): Likewise.
  26         (insert_rhv2): Likewise.
  27         (insert_r0): Likewise.
  28         (insert_r1): Likewise.
  29         (insert_r2): Likewise.
  30         (insert_r3): Likewise.
  31         (insert_sp): Likewise.
  32         (insert_gp): Likewise.
  33         (insert_pcl): Likewise.
  34         (insert_blink): Likewise.
  35         (insert_ilink1): Likewise.
  36         (insert_ilink2): Likewise.
  37         (insert_ras): Likewise.
  38         (insert_rbs): Likewise.
  39         (insert_rcs): Likewise.
  40         (insert_simm3s): Likewise.
  41         (insert_rrange): Likewise.
  42         (insert_fpel): Likewise.
  43         (insert_blinkel): Likewise.
  44         (insert_pcel): Likewise.
  45         (insert_nps_3bit_dst): Likewise.
  46         (insert_nps_3bit_dst_short): Likewise.
  47         (insert_nps_3bit_src2_short): Likewise.
  48         (insert_nps_bitop_size_2b): Likewise.
  49         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
  50         (RA_CHK): Define.
  51         (RB): Adjust.
  52         (RB_CHK): Define.
  53         (RC): Adjust.
  54         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
  55         * arc-tbl.h (div, divu): All instructions are DIVREM class.
  56         Change first insn argument to check for LP_COUNT usage.
  57         (rem): Likewise.
  58         (ld, ldd): All instructions are LOAD class.  Change first insn
  59         argument to check for LP_COUNT usage.
  60         (st, std): All instructions are STORE class.
  61         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
  62         Change first insn argument to check for LP_COUNT usage.
  63         (mov): All instructions are MOVE class.  Change first insn
  64         argument to check for LP_COUNT usage.
  65
  66 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  67
  68         * arc-dis.c (is_compatible_p): Remove function.
  69         (skip_this_opcode): Don't add any decoding class to decode list.
  70         Remove warning.
  71         (find_format_from_table): Go through all opcodes, and warn if we
  72         use a guessed mnemonic.
  73
  74 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
  75             Amit Pawar  <amit.pawar@amd.com>
  76
  77         PR binutils/20637
  78         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
  79         instructions.
  80
  81 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
  82
  83         * configure: Regenerate.
  84
  85 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
  86
  87         * sparc-opc.c (HWS_V8): Definition moved from
  88         gas/config/tc-sparc.c.
  89         (HWS_V9): Likewise.
  90         (HWS_VA): Likewise.
  91         (HWS_VB): Likewise.
  92         (HWS_VC): Likewise.
  93         (HWS_VD): Likewise.
  94         (HWS_VE): Likewise.
  95         (HWS_VV): Likewise.
  96         (HWS_VM): Likewise.
  97         (HWS2_VM): Likewise.
  98         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
  99         existing entries.
 100
 101 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 102
 103         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 104         instructions.
 105
 106 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 107
 108         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 109         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 110         (aarch64_opcode_table): Add fcmla and fcadd.
 111         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 112         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 113         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 114         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 115         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 116         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 117         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 118         (operand_general_constraint_met_p): Rotate and index range check.
 119         (aarch64_print_operand): Handle rotate operand.
 120         * aarch64-asm-2.c: Regenerate.
 121         * aarch64-dis-2.c: Likewise.
 122         * aarch64-opc-2.c: Likewise.
 123
 124 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 125
 126         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 127         * aarch64-asm-2.c: Regenerate.
 128         * aarch64-dis-2.c: Regenerate.
 129         * aarch64-opc-2.c: Regenerate.
 130
 131 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 132
 133         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 134         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 135         * aarch64-asm-2.c: Regenerate.
 136         * aarch64-dis-2.c: Regenerate.
 137         * aarch64-opc-2.c: Regenerate.
 138
 139 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 140
 141         * aarch64-tbl.h (QL_X1NIL): New.
 142         (arch64_opcode_table): Add ldraa, ldrab.
 143         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 144         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 145         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 146         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 147         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 148         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 149         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 150         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 151         (aarch64_print_operand): Likewise.
 152         * aarch64-asm-2.c: Regenerate.
 153         * aarch64-dis-2.c: Regenerate.
 154         * aarch64-opc-2.c: Regenerate.
 155
 156 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 157
 158         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 159         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 160         * aarch64-asm-2.c: Regenerate.
 161         * aarch64-dis-2.c: Regenerate.
 162         * aarch64-opc-2.c: Regenerate.
 163
 164 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 165
 166         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 167         (AARCH64_OPERANDS): Add Rm_SP.
 168         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 169         * aarch64-asm-2.c: Regenerate.
 170         * aarch64-dis-2.c: Regenerate.
 171         * aarch64-opc-2.c: Regenerate.
 172
 173 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 174
 175         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 176         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 177         autdzb, xpaci, xpacd.
 178         * aarch64-asm-2.c: Regenerate.
 179         * aarch64-dis-2.c: Regenerate.
 180         * aarch64-opc-2.c: Regenerate.
 181
 182 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 183
 184         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 185         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 186         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 187         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 188
 189 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 190
 191         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 192         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 193         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 194         autibsp.
 195         * aarch64-asm-2.c: Regenerate.
 196         * aarch64-dis-2.c: Regenerate.
 197
 198 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 199
 200         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 201
 202 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 203
 204         PR binutils/20799
 205         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 206         * i386-dis.c (EdqwS): Removed.
 207         (dqw_swap_mode): Likewise.
 208         (intel_operand_size): Don't check dqw_swap_mode.
 209         (OP_E_register): Likewise.
 210         (OP_E_memory): Likewise.
 211         (OP_G): Likewise.
 212         (OP_EX): Likewise.
 213         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 214         * i386-tbl.h: Regerated.
 215
 216 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 217
 218         * i386-opc.tbl: Merge AVX512F vmovq.
 219         * i386-tbl.h: Regerated.
 220
 221 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 222
 223         PR binutils/20701
 224         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 225         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 226         (three_byte_table): Remove THREE_BYTE_0F7A.
 227
 228 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 229
 230         PR binutils/20775
 231         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 232         (FGRPd9_4): Replace 1 with 2.
 233         (FGRPd9_5): Replace 2 with 3.
 234         (FGRPd9_6): Replace 3 with 4.
 235         (FGRPd9_7): Replace 4 with 5.
 236         (FGRPda_5): Replace 5 with 6.
 237         (FGRPdb_4): Replace 6 with 7.
 238         (FGRPde_3): Replace 7 with 8.
 239         (FGRPdf_4): Replace 8 with 9.
 240         (fgrps): Add an entry for Bad_Opcode.
 241
 242 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 243
 244         * arc-opc.c (arc_flag_operands): Add F_DI14.
 245         (arc_flag_classes): Add C_DI14.
 246         * arc-nps400-tbl.h: Add new exc instructions.
 247
 248 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 249
 250         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 251         major opcode 0xa.
 252         * arc-nps-400-tbl.h: Add dcmac instruction.
 253         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 254         (insert_nps_rbdouble_64): Added.
 255         (extract_nps_rbdouble_64): Added.
 256         (insert_nps_proto_size): Added.
 257         (extract_nps_proto_size): Added.
 258
 259 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 260
 261         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 262         relating to long instruction processing, add new limm field.
 263         (OPCODE): Rename to...
 264         (OPCODE_32BIT_INSN): ...this.
 265         (OPCODE_AC): Delete.
 266         (skip_this_opcode): Handle different instruction lengths, update
 267         macro name.
 268         (special_flag_p): Update parameter type.
 269         (find_format_from_table): Update for more instruction lengths.
 270         (find_format_long_instructions): Delete.
 271         (find_format): Update for more instruction lengths.
 272         (arc_insn_length): Likewise.
 273         (extract_operand_value): Update for more instruction lengths.
 274         (operand_iterator_next): Remove code relating to long
 275         instructions.
 276         (arc_opcode_to_insn_type): New function.
 277         (print_insn_arc):Update for more instructions lengths.
 278         * arc-ext.c (extInstruction_t): Change argument type.
 279         * arc-ext.h (extInstruction_t): Change argument type.
 280         * arc-fxi.h: Change type unsigned to unsigned long long
 281         extensively throughout.
 282         * arc-nps400-tbl.h: Add long instructions taken from
 283         arc_long_opcodes table in arc-opc.c.
 284         * arc-opc.c: Update parameter types on insert/extract handlers.
 285         (arc_long_opcodes): Delete.
 286         (arc_num_long_opcodes): Delete.
 287         (arc_opcode_len): Update for more instruction lengths.
 288
 289 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 290
 291         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 292
 293 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 294
 295         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 296         with arc_opcode_len.
 297         (find_format_long_instructions): Likewise.
 298         * arc-opc.c (arc_opcode_len): New function.
 299
 300 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 301
 302         * arc-nps400-tbl.h: Fix some instruction masks.
 303
 304 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 305
 306         * i386-dis.c (REG_82): Removed.
 307         (X86_64_82_REG_0): Likewise.
 308         (X86_64_82_REG_1): Likewise.
 309         (X86_64_82_REG_2): Likewise.
 310         (X86_64_82_REG_3): Likewise.
 311         (X86_64_82_REG_4): Likewise.
 312         (X86_64_82_REG_5): Likewise.
 313         (X86_64_82_REG_6): Likewise.
 314         (X86_64_82_REG_7): Likewise.
 315         (X86_64_82): New.
 316         (dis386): Use X86_64_82 instead of REG_82.
 317         (reg_table): Remove REG_82.
 318         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 319         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 320         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 321         X86_64_82_REG_7.
 322
 323 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 324
 325         PR binutils/20754
 326         * i386-dis.c (REG_82): New.
 327         (X86_64_82_REG_0): Likewise.
 328         (X86_64_82_REG_1): Likewise.
 329         (X86_64_82_REG_2): Likewise.
 330         (X86_64_82_REG_3): Likewise.
 331         (X86_64_82_REG_4): Likewise.
 332         (X86_64_82_REG_5): Likewise.
 333         (X86_64_82_REG_6): Likewise.
 334         (X86_64_82_REG_7): Likewise.
 335         (dis386): Use REG_82.
 336         (reg_table): Add REG_82.
 337         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 338         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 339         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 340
 341 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 342
 343         * i386-dis.c (REG_82): Renamed to ...
 344         (REG_83): This.
 345         (dis386): Updated.
 346         (reg_table): Likewise.
 347
 348 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 349
 350         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 351         * i386-dis-evex.h (evex_table): Updated.
 352         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 353         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 354         (cpu_flags): Add CpuAVX512_4VNNIW.
 355         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 356         (i386_cpu_flags): Add cpuavx512_4vnniw.
 357         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 358         * i386-init.h: Regenerate.
 359         * i386-tbl.h: Ditto.
 360
 361 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 362
 363         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 364         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 365         * i386-dis-evex.h (evex_table): Updated.
 366         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 367         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 368         (cpu_flags): Add CpuAVX512_4FMAPS.
 369         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 370         * i386-opc.h (AVX512_4FMAP): New.
 371         (i386_cpu_flags): Add cpuavx512_4fmaps.
 372         (ImplicitQuadGroup): New.
 373         (i386_opcode_modifier): Add implicitquadgroup.
 374         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 375         * i386-init.h: Regenerate.
 376         * i386-tbl.h: Ditto.
 377
 378 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 379             Andrew Waterman <andrew@sifive.com>
 380
 381         Add support for RISC-V architecture.
 382         * configure.ac: Add entry for bfd_riscv_arch.
 383         * configure: Regenerate.
 384         * disassemble.c (disassembler): Add support for riscv.
 385         (disassembler_usage): Likewise.
 386         * riscv-dis.c: New file.
 387         * riscv-opc.c: New file.
 388
 389 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 390
 391         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 392         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 393         (rm_table): Update the RM_0FAE_REG_7 entry.
 394         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 395         (cpu_flags): Remove CpuPCOMMIT.
 396         * i386-opc.h (CpuPCOMMIT): Removed.
 397         (i386_cpu_flags): Remove cpupcommit.
 398         * i386-opc.tbl: Remove pcommit.
 399         * i386-init.h: Regenerated.
 400         * i386-tbl.h: Likewise.
 401
 402 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 403
 404         PR binutis/20705
 405         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 406         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 407         32-bit mode.  Don't check vex.register_specifier in 32-bit
 408         mode.
 409         (OP_VEX): Check for invalid mask registers.
 410
 411 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 412
 413         PR binutis/20699
 414         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 415         sizeflag.
 416
 417 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 418
 419         PR binutis/20704
 420         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 421
 422 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 423
 424         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 425         local variable to `index_regno'.
 426
 427 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 428
 429         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 430
 431 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 432
 433         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 434         usage on ISA basis.
 435
 436 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 437
 438         PR target/20666
 439         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 440
 441 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 442
 443         PR target/20667
 444         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 445         available.
 446
 447 2016-10-07  Alan Modra  <amodra@gmail.com>
 448
 449         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 450
 451 2016-10-06  Alan Modra  <amodra@gmail.com>
 452
 453         * aarch64-opc.c: Spell fall through comments consistently.
 454         * i386-dis.c: Likewise.
 455         * aarch64-dis.c: Add missing fall through comments.
 456         * aarch64-opc.c: Likewise.
 457         * arc-dis.c: Likewise.
 458         * arm-dis.c: Likewise.
 459         * i386-dis.c: Likewise.
 460         * m68k-dis.c: Likewise.
 461         * mep-asm.c: Likewise.
 462         * ns32k-dis.c: Likewise.
 463         * sh-dis.c: Likewise.
 464         * tic4x-dis.c: Likewise.
 465         * tic6x-dis.c: Likewise.
 466         * vax-dis.c: Likewise.
 467
 468 2016-10-06  Alan Modra  <amodra@gmail.com>
 469
 470         * arc-ext.c (create_map): Add missing break.
 471         * msp430-decode.opc (encode_as): Likewise.
 472         * msp430-decode.c: Regenerate.
 473
 474 2016-10-06  Alan Modra  <amodra@gmail.com>
 475
 476         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 477         * crx-dis.c (print_insn_crx): Likewise.
 478
 479 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 480
 481         PR binutils/20657
 482         * i386-dis.c (putop): Don't assign alt twice.
 483
 484 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 485
 486         PR target/20553
 487         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 488
 489 2016-09-29  Alan Modra  <amodra@gmail.com>
 490
 491         * ppc-opc.c (L): Make compulsory.
 492         (LOPT): New, optional form of L.
 493         (HTM_R): Define as LOPT.
 494         (L0, L1): Delete.
 495         (L32OPT): New, optional for 32-bit L.
 496         (L2OPT): New, 2-bit L for dcbf.
 497         (SVC_LEC): Update.
 498         (L2): Define.
 499         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 500         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 501         <dcbf>: Use L2OPT.
 502         <tlbiel, tlbie>: Use LOPT.
 503         <wclr, wclrall>: Use L2.
 504
 505 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 506
 507         * Makefile.in: Regenerate.
 508         * configure: Likewise.
 509
 510 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 511
 512         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 513         (EXTINSN2OP): Use EXTINSN2OPF.
 514         (bspeekm, bspop, modapp): New extension instructions.
 515         * arc-opc.c (F_DNZ_ND): Define.
 516         (F_DNZ_D): Likewise.
 517         (F_SIZEB1): Changed.
 518         (C_DNZ_D): Define.
 519         (C_HARD): Changed.
 520         * arc-tbl.h (dbnz): New instruction.
 521         (prealloc): Allow it for ARC EM.
 522         (xbfu): Likewise.
 523
 524 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 525
 526         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 527         after commas in addresses.
 528         (aarch64_print_operand): Likewise.
 529
 530 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 531
 532         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 533         rather than "should be" or "expected to be" in error messages.
 534
 535 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 536
 537         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 538         (print_mnemonic_name): ...here.
 539         (print_comment): New function.
 540         (print_aarch64_insn): Call it.
 541         * aarch64-opc.c (aarch64_conds): Add SVE names.
 542         (aarch64_print_operand): Print alternative condition names in
 543         a comment.
 544
 545 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 546
 547         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 548         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 549         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 550         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 551         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 552         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 553         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 554         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 555         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 556         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 557         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 558         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 559         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 560         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 561         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 562         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 563         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 564         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 565         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 566         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 567         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 568         (aarch64_feature_sve): New variable.
 569         (SVE): New macro.
 570         (_SVE_INSN): Likewise.
 571         (aarch64_opcode_table): Add SVE instructions.
 572         * aarch64-opc.h (extract_fields): Declare.
 573         * aarch64-opc-2.c: Regenerate.
 574         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 575         * aarch64-asm-2.c: Regenerate.
 576         * aarch64-dis.c (extract_fields): Make global.
 577         (do_misc_decoding): Handle the new SVE aarch64_ops.
 578         * aarch64-dis-2.c: Regenerate.
 579
 580 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 581
 582         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 583         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 584         aarch64_field_kinds.
 585         * aarch64-opc.c (fields): Add corresponding entries.
 586         * aarch64-asm.c (aarch64_get_variant): New function.
 587         (aarch64_encode_variant_using_iclass): Likewise.
 588         (aarch64_opcode_encode): Call it.
 589         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 590         (aarch64_opcode_decode): Call it.
 591
 592 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 593
 594         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 595         and FP register operands.
 596         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 597         (FLD_SVE_Vn): New aarch64_field_kinds.
 598         * aarch64-opc.c (fields): Add corresponding entries.
 599         (aarch64_print_operand): Handle the new SVE core and FP register
 600         operands.
 601         * aarch64-opc-2.c: Regenerate.
 602         * aarch64-asm-2.c: Likewise.
 603         * aarch64-dis-2.c: Likewise.
 604
 605 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 606
 607         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 608         immediate operands.
 609         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 610         * aarch64-opc.c (fields): Add corresponding entry.
 611         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 612         operands.
 613         (aarch64_print_operand): Likewise.
 614         * aarch64-opc-2.c: Regenerate.
 615         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 616         (ins_sve_float_zero_one): New inserters.
 617         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 618         (aarch64_ins_sve_float_half_two): Likewise.
 619         (aarch64_ins_sve_float_zero_one): Likewise.
 620         * aarch64-asm-2.c: Regenerate.
 621         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 622         (ext_sve_float_zero_one): New extractors.
 623         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 624         (aarch64_ext_sve_float_half_two): Likewise.
 625         (aarch64_ext_sve_float_zero_one): Likewise.
 626         * aarch64-dis-2.c: Regenerate.
 627
 628 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 629
 630         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 631         integer immediate operands.
 632         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 633         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 634         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 635         * aarch64-opc.c (fields): Add corresponding entries.
 636         (operand_general_constraint_met_p): Handle the new SVE integer
 637         immediate operands.
 638         (aarch64_print_operand): Likewise.
 639         (aarch64_sve_dupm_mov_immediate_p): New function.
 640         * aarch64-opc-2.c: Regenerate.
 641         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 642         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 643         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 644         (aarch64_ins_limm): ...here.
 645         (aarch64_ins_inv_limm): New function.
 646         (aarch64_ins_sve_aimm): Likewise.
 647         (aarch64_ins_sve_asimm): Likewise.
 648         (aarch64_ins_sve_limm_mov): Likewise.
 649         (aarch64_ins_sve_shlimm): Likewise.
 650         (aarch64_ins_sve_shrimm): Likewise.
 651         * aarch64-asm-2.c: Regenerate.
 652         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 653         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 654         * aarch64-dis.c (decode_limm): New function, split out from...
 655         (aarch64_ext_limm): ...here.
 656         (aarch64_ext_inv_limm): New function.
 657         (decode_sve_aimm): Likewise.
 658         (aarch64_ext_sve_aimm): Likewise.
 659         (aarch64_ext_sve_asimm): Likewise.
 660         (aarch64_ext_sve_limm_mov): Likewise.
 661         (aarch64_top_bit): Likewise.
 662         (aarch64_ext_sve_shlimm): Likewise.
 663         (aarch64_ext_sve_shrimm): Likewise.
 664         * aarch64-dis-2.c: Regenerate.
 665
 666 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 667
 668         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 669         operands.
 670         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 671         the AARCH64_MOD_MUL_VL entry.
 672         (value_aligned_p): Cope with non-power-of-two alignments.
 673         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 674         (print_immediate_offset_address): Likewise.
 675         (aarch64_print_operand): Likewise.
 676         * aarch64-opc-2.c: Regenerate.
 677         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 678         (ins_sve_addr_ri_s9xvl): New inserters.
 679         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 680         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 681         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 682         * aarch64-asm-2.c: Regenerate.
 683         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 684         (ext_sve_addr_ri_s9xvl): New extractors.
 685         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 686         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 687         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 688         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 689         * aarch64-dis-2.c: Regenerate.
 690
 691 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 692
 693         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 694         address operands.
 695         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 696         (FLD_SVE_xs_22): New aarch64_field_kinds.
 697         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 698         (get_operand_specific_data): New function.
 699         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 700         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 701         (operand_general_constraint_met_p): Handle the new SVE address
 702         operands.
 703         (sve_reg): New array.
 704         (get_addr_sve_reg_name): New function.
 705         (aarch64_print_operand): Handle the new SVE address operands.
 706         * aarch64-opc-2.c: Regenerate.
 707         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 708         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 709         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 710         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 711         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 712         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 713         (aarch64_ins_sve_addr_zi_u5): Likewise.
 714         (aarch64_ins_sve_addr_zz): Likewise.
 715         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 716         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 717         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 718         * aarch64-asm-2.c: Regenerate.
 719         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 720         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 721         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 722         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 723         (aarch64_ext_sve_addr_ri_u6): Likewise.
 724         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 725         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 726         (aarch64_ext_sve_addr_zi_u5): Likewise.
 727         (aarch64_ext_sve_addr_zz): Likewise.
 728         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 729         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 730         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 731         * aarch64-dis-2.c: Regenerate.
 732
 733 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 734
 735         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 736         AARCH64_OPND_SVE_PATTERN_SCALED.
 737         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 738         * aarch64-opc.c (fields): Add a corresponding entry.
 739         (set_multiplier_out_of_range_error): New function.
 740         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 741         (operand_general_constraint_met_p): Handle
 742         AARCH64_OPND_SVE_PATTERN_SCALED.
 743         (print_register_offset_address): Use PRIi64 to print the
 744         shift amount.
 745         (aarch64_print_operand): Likewise.  Handle
 746         AARCH64_OPND_SVE_PATTERN_SCALED.
 747         * aarch64-opc-2.c: Regenerate.
 748         * aarch64-asm.h (ins_sve_scale): New inserter.
 749         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 750         * aarch64-asm-2.c: Regenerate.
 751         * aarch64-dis.h (ext_sve_scale): New inserter.
 752         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 753         * aarch64-dis-2.c: Regenerate.
 754
 755 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 756
 757         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 758         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 759         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 760         (FLD_SVE_prfop): Likewise.
 761         * aarch64-opc.c: Include libiberty.h.
 762         (aarch64_sve_pattern_array): New variable.
 763         (aarch64_sve_prfop_array): Likewise.
 764         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 765         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 766         AARCH64_OPND_SVE_PRFOP.
 767         * aarch64-asm-2.c: Regenerate.
 768         * aarch64-dis-2.c: Likewise.
 769         * aarch64-opc-2.c: Likewise.
 770
 771 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 772
 773         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 774         AARCH64_OPND_QLF_P_[ZM].
 775         (aarch64_print_operand): Print /z and /m where appropriate.
 776
 777 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 778
 779         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 780         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 781         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 782         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 783         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 784         * aarch64-opc.c (fields): Add corresponding entries here.
 785         (operand_general_constraint_met_p): Check that SVE register lists
 786         have the correct length.  Check the ranges of SVE index registers.
 787         Check for cases where p8-p15 are used in 3-bit predicate fields.
 788         (aarch64_print_operand): Handle the new SVE operands.
 789         * aarch64-opc-2.c: Regenerate.
 790         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 791         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 792         (aarch64_ins_sve_reglist): Likewise.
 793         * aarch64-asm-2.c: Regenerate.
 794         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 795         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 796         (aarch64_ext_sve_reglist): Likewise.
 797         * aarch64-dis-2.c: Regenerate.
 798
 799 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 800
 801         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 802         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 803         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 804         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 805         tied operands.
 806
 807 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 808
 809         * aarch64-opc.c (get_offset_int_reg_name): New function.
 810         (print_immediate_offset_address): Likewise.
 811         (print_register_offset_address): Take the base and offset
 812         registers as parameters.
 813         (aarch64_print_operand): Update caller accordingly.  Use
 814         print_immediate_offset_address.
 815
 816 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 817
 818         * aarch64-opc.c (BANK): New macro.
 819         (R32, R64): Take a register number as argument
 820         (int_reg): Use BANK.
 821
 822 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 823
 824         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 825         (aarch64_print_operand): Update accordingly.
 826
 827 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 828
 829         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 830         for FPIMM.
 831         * aarch64-asm.h (ins_fpimm): New inserter.
 832         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 833         * aarch64-asm-2.c: Regenerate.
 834         * aarch64-dis.h (ext_fpimm): New extractor.
 835         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 836         (aarch64_ext_fpimm): New function.
 837         * aarch64-dis-2.c: Regenerate.
 838
 839 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 840
 841         * aarch64-asm.c: Include libiberty.h.
 842         (insert_fields): New function.
 843         (aarch64_ins_imm): Use it.
 844         * aarch64-dis.c (extract_fields): New function.
 845         (aarch64_ext_imm): Use it.
 846
 847 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 848
 849         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 850         with an esize parameter.
 851         (operand_general_constraint_met_p): Update accordingly.
 852         Fix misindented code.
 853         * aarch64-asm.c (aarch64_ins_limm): Update call to
 854         aarch64_logical_immediate_p.
 855
 856 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 857
 858         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 859
 860 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 861
 862         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 863
 864 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 865
 866         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 867
 868 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 869
 870         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 871         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 872         xor3>: Delete mnemonics.
 873         <cp_abort>: Rename mnemonic from ...
 874         <cpabort>: ...to this.
 875         <setb>: Change to a X form instruction.
 876         <sync>: Change to 1 operand form.
 877         <copy>: Delete mnemonic.
 878         <copy_first>: Rename mnemonic from ...
 879         <copy>: ...to this.
 880         <paste, paste.>: Delete mnemonics.
 881         <paste_last>: Rename mnemonic from ...
 882         <paste.>: ...to this.
 883
 884 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 885
 886         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 887
 888 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 889
 890         * s390-mkopc.c (main): Support alternate arch strings.
 891
 892 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 893
 894         * s390-opc.txt: Fix kmctr instruction type.
 895
 896 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 897
 898         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 899         * i386-init.h: Regenerated.
 900
 901 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 902
 903         * opcodes/arc-dis.c (print_insn_arc): Changed.
 904
 905 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 906
 907         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 908         camellia_fl.
 909
 910 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 911
 912         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 913         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 914         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 915
 916 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 917
 918         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 919         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 920         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 921         PREFIX_MOD_3_0FAE_REG_4.
 922         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 923         PREFIX_MOD_3_0FAE_REG_4.
 924         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 925         (cpu_flags): Add CpuPTWRITE.
 926         * i386-opc.h (CpuPTWRITE): New.
 927         (i386_cpu_flags): Add cpuptwrite.
 928         * i386-opc.tbl: Add ptwrite instruction.
 929         * i386-init.h: Regenerated.
 930         * i386-tbl.h: Likewise.
 931
 932 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 933
 934         * arc-dis.h: Wrap around in extern "C".
 935
 936 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 937
 938         * aarch64-tbl.h (V8_2_INSN): New macro.
 939         (aarch64_opcode_table): Use it.
 940
 941 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 942
 943         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 944         CORE_INSN, __FP_INSN and SIMD_INSN.
 945
 946 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 947
 948         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 949         (aarch64_opcode_table): Update uses accordingly.
 950
 951 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 952         Kwok Cheung Yeung  <kcy@codesourcery.com>
 953
 954         opcodes/
 955         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 956         'e_cmplwi' to 'e_cmpli' instead.
 957         (OPVUPRT, OPVUPRT_MASK): Define.
 958         (powerpc_opcodes): Add E200Z4 insns.
 959         (vle_opcodes): Add context save/restore insns.
 960
 961 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 962
 963         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 964         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 965         "j".
 966
 967 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 968
 969         * arc-nps400-tbl.h: Change block comments to GNU format.
 970         * arc-dis.c: Add new globals addrtypenames,
 971         addrtypenames_max, and addtypeunknown.
 972         (get_addrtype): New function.
 973         (print_insn_arc): Print colons and address types when
 974         required.
 975         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 976         define insert and extract functions for all address types.
 977         (arc_operands): Add operands for colon and all address
 978         types.
 979         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 980         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 981         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 982         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 983         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 984         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 985
 986 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 987
 988         * configure: Regenerated.
 989
 990 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 991
 992         * arc-dis.c (skipclass): New structure.
 993         (decodelist): New variable.
 994         (is_compatible_p): New function.
 995         (new_element): Likewise.
 996         (skip_class_p): Likewise.
 997         (find_format_from_table): Use skip_class_p function.
 998         (find_format): Decode first the extension instructions.
 999         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1000         e_flags.
1001         (parse_option): New function.
1002         (parse_disassembler_options): Likewise.
1003         (print_arc_disassembler_options): Likewise.
1004         (print_insn_arc): Use parse_disassembler_options function.  Proper
1005         select ARCv2 cpu variant.
1006         * disassemble.c (disassembler_usage): Add ARC disassembler
1007         options.
1008
1009 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1010
1011         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1012         annotation from the "nal" entry and reorder it beyond "bltzal".
1013
1014 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1015
1016         * sparc-opc.c (ldtxa): New macro.
1017         (sparc_opcodes): Use the macro defined above to add entries for
1018         the LDTXA instructions.
1019         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1020         instruction.
1021
1022 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1023
1024         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1025         and "jmpc".
1026
1027 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1030         (movzb): Adjust to cover all permitted suffixes.
1031         (movzw): New.
1032         * i386-tbl.h: Re-generate.
1033
1034 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1035
1036         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1037         (lgdt): Remove Tbyte from non-64-bit variant.
1038         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1039         xsaves64, xsavec64): Remove Disp16.
1040         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1041         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1042         64-bit variants.
1043         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1044         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1045         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1046         64-bit variants.
1047         * i386-tbl.h: Re-generate.
1048
1049 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1050
1051         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1052         * i386-tbl.h: Re-generate.
1053
1054 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1055
1056         * arm-dis.c (print_insn): Fix typo in comment.
1057
1058 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1059
1060         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1061         range of ldst_elemlist operands.
1062         (print_register_list): Use PRIi64 to print the index.
1063         (aarch64_print_operand): Likewise.
1064
1065 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1066
1067         * mcore-opc.h: Remove sentinal.
1068         * mcore-dis.c (print_insn_mcore): Adjust.
1069
1070 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1071
1072         * arc-opc.c: Correct description of availability of NPS400
1073         features.
1074
1075 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1076
1077         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1078         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1079         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1080         xor3>: New mnemonics.
1081         <setb>: Change to a VX form instruction.
1082         (insert_sh6): Add support for rldixor.
1083         (extract_sh6): Likewise.
1084
1085 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1086
1087         * arc-ext.h: Wrap in extern C.
1088
1089 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1090
1091         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1092         Use same method for determining instruction length on ARC700 and
1093         NPS-400.
1094         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1095         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1096         with the NPS400 subclass.
1097         * arc-opc.c: Likewise.
1098
1099 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1100
1101         * sparc-opc.c (rdasr): New macro.
1102         (wrasr): Likewise.
1103         (rdpr): Likewise.
1104         (wrpr): Likewise.
1105         (rdhpr): Likewise.
1106         (wrhpr): Likewise.
1107         (sparc_opcodes): Use the macros above to fix and expand the
1108         definition of read/write instructions from/to
1109         asr/privileged/hyperprivileged instructions.
1110         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1111         %hva_mask_nz.  Prefer softint_set and softint_clear over
1112         set_softint and clear_softint.
1113         (print_insn_sparc): Support %ver in Rd.
1114
1115 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1116
1117         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1118         architecture according to the hardware capabilities they require.
1119
1120 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1121
1122         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1123         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1124         bfd_mach_sparc_v9{c,d,e,v,m}.
1125         * sparc-opc.c (MASK_V9C): Define.
1126         (MASK_V9D): Likewise.
1127         (MASK_V9E): Likewise.
1128         (MASK_V9V): Likewise.
1129         (MASK_V9M): Likewise.
1130         (v6): Add MASK_V9{C,D,E,V,M}.
1131         (v6notlet): Likewise.
1132         (v7): Likewise.
1133         (v8): Likewise.
1134         (v9): Likewise.
1135         (v9andleon): Likewise.
1136         (v9a): Likewise.
1137         (v9b): Likewise.
1138         (v9c): Define.
1139         (v9d): Likewise.
1140         (v9e): Likewise.
1141         (v9v): Likewise.
1142         (v9m): Likewise.
1143         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1144
1145 2016-06-15  Nick Clifton  <nickc@redhat.com>
1146
1147         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1148         constants to match expected behaviour.
1149         (nds32_parse_opcode): Likewise.  Also for whitespace.
1150
1151 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1152
1153         * arc-opc.c (extract_rhv1): Extract value from insn.
1154
1155 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1156
1157         * arc-nps400-tbl.h: Add ldbit instruction.
1158         * arc-opc.c: Add flag classes required for ldbit.
1159
1160 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1161
1162         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1163         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1164         support the above instructions.
1165
1166 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1167
1168         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1169         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1170         csma, cbba, zncv, and hofs.
1171         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1172         support the above instructions.
1173
1174 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1175
1176         * arc-nps400-tbl.h: Add andab and orab instructions.
1177
1178 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1179
1180         * arc-nps400-tbl.h: Add addl-like instructions.
1181
1182 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1183
1184         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1185
1186 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1187
1188         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1189         instructions.
1190
1191 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1192
1193         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1194         variable.
1195         (init_disasm): Handle new command line option "insnlength".
1196         (print_s390_disassembler_options): Mention new option in help
1197         output.
1198         (print_insn_s390): Use the encoded insn length when dumping
1199         unknown instructions.
1200
1201 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1202
1203         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1204          to the address and set as symbol address for LDS/ STS immediate operands.
1205
1206 2016-06-07  Alan Modra  <amodra@gmail.com>
1207
1208         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1209         cpu for "vle" to e500.
1210         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1211         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1212         (PPCNONE): Delete, substitute throughout.
1213         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1214         except for major opcode 4 and 31.
1215         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1216
1217 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1218
1219         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1220         ARM_EXT_RAS in relevant entries.
1221
1222 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1223
1224         PR binutils/20196
1225         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1226         opcodes for E6500.
1227
1228 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1229
1230         PR binutis/18386
1231         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1232         (indir_v_mode): New.
1233         Add comments for '&'.
1234         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1235         (putop): Handle '&'.
1236         (intel_operand_size): Handle indir_v_mode.
1237         (OP_E_register): Likewise.
1238         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1239         64-bit indirect call/jmp for AMD64.
1240         * i386-tbl.h: Regenerated
1241
1242 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1243
1244         * arc-dis.c (struct arc_operand_iterator): New structure.
1245         (find_format_from_table): All the old content from find_format,
1246         with some minor adjustments, and parameter renaming.
1247         (find_format_long_instructions): New function.
1248         (find_format): Rewritten.
1249         (arc_insn_length): Add LSB parameter.
1250         (extract_operand_value): New function.
1251         (operand_iterator_next): New function.
1252         (print_insn_arc): Use new functions to find opcode, and iterator
1253         over operands.
1254         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1255         (extract_nps_3bit_dst_short): New function.
1256         (insert_nps_3bit_src2_short): New function.
1257         (extract_nps_3bit_src2_short): New function.
1258         (insert_nps_bitop1_size): New function.
1259         (extract_nps_bitop1_size): New function.
1260         (insert_nps_bitop2_size): New function.
1261         (extract_nps_bitop2_size): New function.
1262         (insert_nps_bitop_mod4_msb): New function.
1263         (extract_nps_bitop_mod4_msb): New function.
1264         (insert_nps_bitop_mod4_lsb): New function.
1265         (extract_nps_bitop_mod4_lsb): New function.
1266         (insert_nps_bitop_dst_pos3_pos4): New function.
1267         (extract_nps_bitop_dst_pos3_pos4): New function.
1268         (insert_nps_bitop_ins_ext): New function.
1269         (extract_nps_bitop_ins_ext): New function.
1270         (arc_operands): Add new operands.
1271         (arc_long_opcodes): New global array.
1272         (arc_num_long_opcodes): New global.
1273         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1274
1275 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1276
1277         * nds32-asm.h: Add extern "C".
1278         * sh-opc.h: Likewise.
1279
1280 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1281
1282         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1283         0,b,limm to the rflt instruction.
1284
1285 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1286
1287         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1288         constant.
1289
1290 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1291
1292         PR gas/20145
1293         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1294         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1295         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1296         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1297         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1298         * i386-init.h: Regenerated.
1299
1300 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1301
1302         PR gas/20145
1303         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1304         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1305         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1306         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1307         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1308         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1309         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1310         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1311         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1312         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1313         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1314         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1315         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1316         CpuRegMask for AVX512.
1317         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1318         and CpuRegMask.
1319         (set_bitfield_from_cpu_flag_init): New function.
1320         (set_bitfield): Remove const on f.  Call
1321         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1322         * i386-opc.h (CpuRegMMX): New.
1323         (CpuRegXMM): Likewise.
1324         (CpuRegYMM): Likewise.
1325         (CpuRegZMM): Likewise.
1326         (CpuRegMask): Likewise.
1327         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1328         and cpuregmask.
1329         * i386-init.h: Regenerated.
1330         * i386-tbl.h: Likewise.
1331
1332 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1333
1334         PR gas/20154
1335         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1336         (opcode_modifiers): Add AMD64 and Intel64.
1337         (main): Properly verify CpuMax.
1338         * i386-opc.h (CpuAMD64): Removed.
1339         (CpuIntel64): Likewise.
1340         (CpuMax): Set to CpuNo64.
1341         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1342         (AMD64): New.
1343         (Intel64): Likewise.
1344         (i386_opcode_modifier): Add amd64 and intel64.
1345         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1346         on call and jmp.
1347         * i386-init.h: Regenerated.
1348         * i386-tbl.h: Likewise.
1349
1350 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1351
1352         PR gas/20154
1353         * i386-gen.c (main): Fail if CpuMax is incorrect.
1354         * i386-opc.h (CpuMax): Set to CpuIntel64.
1355         * i386-tbl.h: Regenerated.
1356
1357 2016-05-27  Nick Clifton  <nickc@redhat.com>
1358
1359         PR target/20150
1360         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1361         (msp430dis_opcode_unsigned): New function.
1362         (msp430dis_opcode_signed): New function.
1363         (msp430_singleoperand): Use the new opcode reading functions.
1364         Only disassenmble bytes if they were successfully read.
1365         (msp430_doubleoperand): Likewise.
1366         (msp430_branchinstr): Likewise.
1367         (msp430x_callx_instr): Likewise.
1368         (print_insn_msp430): Check that it is safe to read bytes before
1369         attempting disassembly.  Use the new opcode reading functions.
1370
1371 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1372
1373         * ppc-opc.c (CY): New define.  Document it.
1374         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1375
1376 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1377
1378         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1379         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1380         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1381         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1382         CPU_ANY_AVX_FLAGS.
1383         * i386-init.h: Regenerated.
1384
1385 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1386
1387         PR gas/20141
1388         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1389         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1390         * i386-init.h: Regenerated.
1391
1392 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1393
1394         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1395         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1396         * i386-init.h: Regenerated.
1397
1398 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1399
1400         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1401         information.
1402         (print_insn_arc): Set insn_type information.
1403         * arc-opc.c (C_CC): Add F_CLASS_COND.
1404         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1405         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1406         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1407         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1408         (brne, brne_s, jeq_s, jne_s): Likewise.
1409
1410 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1411
1412         * arc-tbl.h (neg): New instruction variant.
1413
1414 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1415
1416         * arc-dis.c (find_format, find_format, get_auxreg)
1417         (print_insn_arc): Changed.
1418         * arc-ext.h (INSERT_XOP): Likewise.
1419
1420 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1421
1422         * tic54x-dis.c (sprint_mmr): Adjust.
1423         * tic54x-opc.c: Likewise.
1424
1425 2016-05-19  Alan Modra  <amodra@gmail.com>
1426
1427         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1428
1429 2016-05-19  Alan Modra  <amodra@gmail.com>
1430
1431         * ppc-opc.c: Formatting.
1432         (NSISIGNOPT): Define.
1433         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1434
1435 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1436
1437         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1438         replacing references to `micromips_ase' throughout.
1439         (_print_insn_mips): Don't use file-level microMIPS annotation to
1440         determine the disassembly mode with the symbol table.
1441
1442 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1443
1444         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1445
1446 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1447
1448         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1449         mips64r6.
1450         * mips-opc.c (D34): New macro.
1451         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1452
1453 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1454
1455         * i386-dis.c (prefix_table): Add RDPID instruction.
1456         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1457         (cpu_flags): Add RDPID bitfield.
1458         * i386-opc.h (enum): Add RDPID element.
1459         (i386_cpu_flags): Add RDPID field.
1460         * i386-opc.tbl: Add RDPID instruction.
1461         * i386-init.h: Regenerate.
1462         * i386-tbl.h: Regenerate.
1463
1464 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1465
1466         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1467         branch type of a symbol.
1468         (print_insn): Likewise.
1469
1470 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1471
1472         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1473         Mainline Security Extensions instructions.
1474         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1475         Extensions instructions.
1476         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1477         instructions.
1478         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1479         special registers.
1480
1481 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1482
1483         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1484
1485 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1486
1487         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1488         (arcExtMap_genOpcode): Likewise.
1489         * arc-opc.c (arg_32bit_rc): Define new variable.
1490         (arg_32bit_u6): Likewise.
1491         (arg_32bit_limm): Likewise.
1492
1493 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1494
1495         * aarch64-gen.c (VERIFIER): Define.
1496         * aarch64-opc.c (VERIFIER): Define.
1497         (verify_ldpsw): Use static linkage.
1498         * aarch64-opc.h (verify_ldpsw): Remove.
1499         * aarch64-tbl.h: Use VERIFIER for verifiers.
1500
1501 2016-04-28  Nick Clifton  <nickc@redhat.com>
1502
1503         PR target/19722
1504         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1505         * aarch64-opc.c (verify_ldpsw): New function.
1506         * aarch64-opc.h (verify_ldpsw): New prototype.
1507         * aarch64-tbl.h: Add initialiser for verifier field.
1508         (LDPSW): Set verifier to verify_ldpsw.
1509
1510 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1511
1512         PR binutils/19983
1513         PR binutils/19984
1514         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1515         smaller than address size.
1516
1517 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1518
1519         * alpha-dis.c: Regenerate.
1520         * crx-dis.c: Likewise.
1521         * disassemble.c: Likewise.
1522         * epiphany-opc.c: Likewise.
1523         * fr30-opc.c: Likewise.
1524         * frv-opc.c: Likewise.
1525         * ip2k-opc.c: Likewise.
1526         * iq2000-opc.c: Likewise.
1527         * lm32-opc.c: Likewise.
1528         * lm32-opinst.c: Likewise.
1529         * m32c-opc.c: Likewise.
1530         * m32r-opc.c: Likewise.
1531         * m32r-opinst.c: Likewise.
1532         * mep-opc.c: Likewise.
1533         * mt-opc.c: Likewise.
1534         * or1k-opc.c: Likewise.
1535         * or1k-opinst.c: Likewise.
1536         * tic80-opc.c: Likewise.
1537         * xc16x-opc.c: Likewise.
1538         * xstormy16-opc.c: Likewise.
1539
1540 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1541
1542         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1543         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1544         calcsd, and calcxd instructions.
1545         * arc-opc.c (insert_nps_bitop_size): Delete.
1546         (extract_nps_bitop_size): Delete.
1547         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1548         (extract_nps_qcmp_m3): Define.
1549         (extract_nps_qcmp_m2): Define.
1550         (extract_nps_qcmp_m1): Define.
1551         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1552         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1553         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1554         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1555         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1556         NPS_QCMP_M3.
1557
1558 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1559
1560         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1561
1562 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1563
1564         * Makefile.in: Regenerated with automake 1.11.6.
1565         * aclocal.m4: Likewise.
1566
1567 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1568
1569         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1570         instructions.
1571         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1572         (extract_nps_cmem_uimm16): New function.
1573         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1574
1575 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1576
1577         * arc-dis.c (arc_insn_length): New function.
1578         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1579         (find_format): Change insnLen parameter to unsigned.
1580
1581 2016-04-13  Nick Clifton  <nickc@redhat.com>
1582
1583         PR target/19937
1584         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1585         the LD.B and LD.BU instructions.
1586
1587 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1588
1589         * arc-dis.c (find_format): Check for extension flags.
1590         (print_flags): New function.
1591         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1592         .extAuxRegister.
1593         * arc-ext.c (arcExtMap_coreRegName): Use
1594         LAST_EXTENSION_CORE_REGISTER.
1595         (arcExtMap_coreReadWrite): Likewise.
1596         (dump_ARC_extmap): Update printing.
1597         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1598         (arc_aux_regs): Add cpu field.
1599         * arc-regs.h: Add cpu field, lower case name aux registers.
1600
1601 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1602
1603         * arc-tbl.h: Add rtsc, sleep with no arguments.
1604
1605 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1606
1607         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1608         Initialize.
1609         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1610         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1611         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1612         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1613         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1614         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1615         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1616         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1617         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1618         (arc_opcode arc_opcodes): Null terminate the array.
1619         (arc_num_opcodes): Remove.
1620         * arc-ext.h (INSERT_XOP): Define.
1621         (extInstruction_t): Likewise.
1622         (arcExtMap_instName): Delete.
1623         (arcExtMap_insn): New function.
1624         (arcExtMap_genOpcode): Likewise.
1625         * arc-ext.c (ExtInstruction): Remove.
1626         (create_map): Zero initialize instruction fields.
1627         (arcExtMap_instName): Remove.
1628         (arcExtMap_insn): New function.
1629         (dump_ARC_extmap): More info while debuging.
1630         (arcExtMap_genOpcode): New function.
1631         * arc-dis.c (find_format): New function.
1632         (print_insn_arc): Use find_format.
1633         (arc_get_disassembler): Enable dump_ARC_extmap only when
1634         debugging.
1635
1636 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1637
1638         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1639         instruction bits out.
1640
1641 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1642
1643         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1644         * arc-opc.c (arc_flag_operands): Add new flags.
1645         (arc_flag_classes): Add new classes.
1646
1647 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1648
1649         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1650
1651 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1652
1653         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1654         encode1, rflt, crc16, and crc32 instructions.
1655         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1656         (arc_flag_classes): Add C_NPS_R.
1657         (insert_nps_bitop_size_2b): New function.
1658         (extract_nps_bitop_size_2b): Likewise.
1659         (insert_nps_bitop_uimm8): Likewise.
1660         (extract_nps_bitop_uimm8): Likewise.
1661         (arc_operands): Add new operand entries.
1662
1663 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1664
1665         * arc-regs.h: Add a new subclass field.  Add double assist
1666         accumulator register values.
1667         * arc-tbl.h: Use DPA subclass to mark the double assist
1668         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1669         * arc-opc.c (RSP): Define instead of SP.
1670         (arc_aux_regs): Add the subclass field.
1671
1672 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1673
1674         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1675
1676 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1677
1678         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1679         NPS_R_SRC1.
1680
1681 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1682
1683         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1684         issues.  No functional changes.
1685
1686 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1687
1688         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1689         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1690         (RTT): Remove duplicate.
1691         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1692         (PCT_CONFIG*): Remove.
1693         (D1L, D1H, D2H, D2L): Define.
1694
1695 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1696
1697         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1698
1699 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1700
1701         * arc-tbl.h (invld07): Remove.
1702         * arc-ext-tbl.h: New file.
1703         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1704         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1705
1706 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1707
1708         Fix -Wstack-usage warnings.
1709         * aarch64-dis.c (print_operands): Substitute size.
1710         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1711
1712 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1713
1714         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1715         to get a proper diagnostic when an invalid ASR register is used.
1716
1717 2016-03-22  Nick Clifton  <nickc@redhat.com>
1718
1719         * configure: Regenerate.
1720
1721 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1722
1723         * arc-nps400-tbl.h: New file.
1724         * arc-opc.c: Add top level comment.
1725         (insert_nps_3bit_dst): New function.
1726         (extract_nps_3bit_dst): New function.
1727         (insert_nps_3bit_src2): New function.
1728         (extract_nps_3bit_src2): New function.
1729         (insert_nps_bitop_size): New function.
1730         (extract_nps_bitop_size): New function.
1731         (arc_flag_operands): Add nps400 entries.
1732         (arc_flag_classes): Add nps400 entries.
1733         (arc_operands): Add nps400 entries.
1734         (arc_opcodes): Add nps400 include.
1735
1736 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1737
1738         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1739         the new class enum values.
1740
1741 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1742
1743         * arc-dis.c (print_insn_arc): Handle nps400.
1744
1745 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1746
1747         * arc-opc.c (BASE): Delete.
1748
1749 2016-03-18  Nick Clifton  <nickc@redhat.com>
1750
1751         PR target/19721
1752         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1753         of MOV insn that aliases an ORR insn.
1754
1755 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1756
1757         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1758
1759 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1760
1761         * mcore-opc.h: Add const qualifiers.
1762         * microblaze-opc.h (struct op_code_struct): Likewise.
1763         * sh-opc.h: Likewise.
1764         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1765         (tic4x_print_op): Likewise.
1766
1767 2016-03-02  Alan Modra  <amodra@gmail.com>
1768
1769         * or1k-desc.h: Regenerate.
1770         * fr30-ibld.c: Regenerate.
1771         * rl78-decode.c: Regenerate.
1772
1773 2016-03-01  Nick Clifton  <nickc@redhat.com>
1774
1775         PR target/19747
1776         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1777
1778 2016-02-24  Renlin Li  <renlin.li@arm.com>
1779
1780         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1781         (print_insn_coprocessor): Support fp16 instructions.
1782
1783 2016-02-24  Renlin Li  <renlin.li@arm.com>
1784
1785         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1786         vminnm, vrint(mpna).
1787
1788 2016-02-24  Renlin Li  <renlin.li@arm.com>
1789
1790         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1791         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1792
1793 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1794
1795         * i386-dis.c (print_insn): Parenthesize expression to prevent
1796         truncated addresses.
1797         (OP_J): Likewise.
1798
1799 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1800             Janek van Oirschot  <jvanoirs@synopsys.com>
1801
1802         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1803         variable.
1804
1805 2016-02-04  Nick Clifton  <nickc@redhat.com>
1806
1807         PR target/19561
1808         * msp430-dis.c (print_insn_msp430): Add a special case for
1809         decoding an RRC instruction with the ZC bit set in the extension
1810         word.
1811
1812 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1813
1814         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1815         * epiphany-ibld.c: Regenerate.
1816         * fr30-ibld.c: Regenerate.
1817         * frv-ibld.c: Regenerate.
1818         * ip2k-ibld.c: Regenerate.
1819         * iq2000-ibld.c: Regenerate.
1820         * lm32-ibld.c: Regenerate.
1821         * m32c-ibld.c: Regenerate.
1822         * m32r-ibld.c: Regenerate.
1823         * mep-ibld.c: Regenerate.
1824         * mt-ibld.c: Regenerate.
1825         * or1k-ibld.c: Regenerate.
1826         * xc16x-ibld.c: Regenerate.
1827         * xstormy16-ibld.c: Regenerate.
1828
1829 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1830
1831         * epiphany-dis.c: Regenerated from latest cpu files.
1832
1833 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1834
1835         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1836         test bit.
1837
1838 2016-01-25  Renlin Li  <renlin.li@arm.com>
1839
1840         * arm-dis.c (mapping_symbol_for_insn): New function.
1841         (find_ifthen_state): Call mapping_symbol_for_insn().
1842
1843 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1844
1845         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1846         of MSR UAO immediate operand.
1847
1848 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1849
1850         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1851         instruction support.
1852
1853 2016-01-17  Alan Modra  <amodra@gmail.com>
1854
1855         * configure: Regenerate.
1856
1857 2016-01-14  Nick Clifton  <nickc@redhat.com>
1858
1859         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1860         instructions that can support stack pointer operations.
1861         * rl78-decode.c: Regenerate.
1862         * rl78-dis.c: Fix display of stack pointer in MOVW based
1863         instructions.
1864
1865 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1866
1867         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1868         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1869         erxtatus_el1 and erxaddr_el1.
1870
1871 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1872
1873         * arm-dis.c (arm_opcodes): Add "esb".
1874         (thumb_opcodes): Likewise.
1875
1876 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1877
1878         * ppc-opc.c <xscmpnedp>: Delete.
1879         <xvcmpnedp>: Likewise.
1880         <xvcmpnedp.>: Likewise.
1881         <xvcmpnesp>: Likewise.
1882         <xvcmpnesp.>: Likewise.
1883
1884 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1885
1886         PR gas/13050
1887         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1888         addition to ISA_A.
1889
1890 2016-01-01  Alan Modra  <amodra@gmail.com>
1891
1892         Update year range in copyright notice of all files.
1893
1894 For older changes see ChangeLog-2015
1895 \f
1896 Copyright (C) 2016 Free Software Foundation, Inc.
1897
1898 Copying and distribution of this file, with or without modification,
1899 are permitted in any medium without royalty provided the copyright
1900 notice and this notice are preserved.
1901
1902 Local Variables:
1903 mode: change-log
1904 left-margin: 8
1905 fill-column: 74
1906 version-control: never
1907 End: