opcodes/ChangeLog

   1 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
   2
   3         * sparc-opc.c (HWS_V8): Definition moved from
   4         gas/config/tc-sparc.c.
   5         (HWS_V9): Likewise.
   6         (HWS_VA): Likewise.
   7         (HWS_VB): Likewise.
   8         (HWS_VC): Likewise.
   9         (HWS_VD): Likewise.
  10         (HWS_VE): Likewise.
  11         (HWS_VV): Likewise.
  12         (HWS_VM): Likewise.
  13         (HWS2_VM): Likewise.
  14         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
  15         existing entries.
  16
  17 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
  18
  19         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
  20         instructions.
  21
  22 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  23
  24         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
  25         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
  26         (aarch64_opcode_table): Add fcmla and fcadd.
  27         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
  28         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
  29         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
  30         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
  31         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
  32         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
  33         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
  34         (operand_general_constraint_met_p): Rotate and index range check.
  35         (aarch64_print_operand): Handle rotate operand.
  36         * aarch64-asm-2.c: Regenerate.
  37         * aarch64-dis-2.c: Likewise.
  38         * aarch64-opc-2.c: Likewise.
  39
  40 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  41
  42         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
  43         * aarch64-asm-2.c: Regenerate.
  44         * aarch64-dis-2.c: Regenerate.
  45         * aarch64-opc-2.c: Regenerate.
  46
  47 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  48
  49         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
  50         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
  51         * aarch64-asm-2.c: Regenerate.
  52         * aarch64-dis-2.c: Regenerate.
  53         * aarch64-opc-2.c: Regenerate.
  54
  55 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  56
  57         * aarch64-tbl.h (QL_X1NIL): New.
  58         (arch64_opcode_table): Add ldraa, ldrab.
  59         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
  60         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
  61         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
  62         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
  63         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
  64         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
  65         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
  66         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
  67         (aarch64_print_operand): Likewise.
  68         * aarch64-asm-2.c: Regenerate.
  69         * aarch64-dis-2.c: Regenerate.
  70         * aarch64-opc-2.c: Regenerate.
  71
  72 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  73
  74         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
  75         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
  76         * aarch64-asm-2.c: Regenerate.
  77         * aarch64-dis-2.c: Regenerate.
  78         * aarch64-opc-2.c: Regenerate.
  79
  80 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  81
  82         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
  83         (AARCH64_OPERANDS): Add Rm_SP.
  84         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
  85         * aarch64-asm-2.c: Regenerate.
  86         * aarch64-dis-2.c: Regenerate.
  87         * aarch64-opc-2.c: Regenerate.
  88
  89 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  90
  91         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
  92         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
  93         autdzb, xpaci, xpacd.
  94         * aarch64-asm-2.c: Regenerate.
  95         * aarch64-dis-2.c: Regenerate.
  96         * aarch64-opc-2.c: Regenerate.
  97
  98 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  99
 100         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 101         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 102         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 103         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 104
 105 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 106
 107         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 108         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 109         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 110         autibsp.
 111         * aarch64-asm-2.c: Regenerate.
 112         * aarch64-dis-2.c: Regenerate.
 113
 114 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 115
 116         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 117
 118 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 119
 120         PR binutils/20799
 121         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 122         * i386-dis.c (EdqwS): Removed.
 123         (dqw_swap_mode): Likewise.
 124         (intel_operand_size): Don't check dqw_swap_mode.
 125         (OP_E_register): Likewise.
 126         (OP_E_memory): Likewise.
 127         (OP_G): Likewise.
 128         (OP_EX): Likewise.
 129         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 130         * i386-tbl.h: Regerated.
 131
 132 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 133
 134         * i386-opc.tbl: Merge AVX512F vmovq.
 135         * i386-tbl.h: Regerated.
 136
 137 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         PR binutils/20701
 140         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 141         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 142         (three_byte_table): Remove THREE_BYTE_0F7A.
 143
 144 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 145
 146         PR binutils/20775
 147         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 148         (FGRPd9_4): Replace 1 with 2.
 149         (FGRPd9_5): Replace 2 with 3.
 150         (FGRPd9_6): Replace 3 with 4.
 151         (FGRPd9_7): Replace 4 with 5.
 152         (FGRPda_5): Replace 5 with 6.
 153         (FGRPdb_4): Replace 6 with 7.
 154         (FGRPde_3): Replace 7 with 8.
 155         (FGRPdf_4): Replace 8 with 9.
 156         (fgrps): Add an entry for Bad_Opcode.
 157
 158 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 159
 160         * arc-opc.c (arc_flag_operands): Add F_DI14.
 161         (arc_flag_classes): Add C_DI14.
 162         * arc-nps400-tbl.h: Add new exc instructions.
 163
 164 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 165
 166         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 167         major opcode 0xa.
 168         * arc-nps-400-tbl.h: Add dcmac instruction.
 169         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 170         (insert_nps_rbdouble_64): Added.
 171         (extract_nps_rbdouble_64): Added.
 172         (insert_nps_proto_size): Added.
 173         (extract_nps_proto_size): Added.
 174
 175 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 176
 177         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 178         relating to long instruction processing, add new limm field.
 179         (OPCODE): Rename to...
 180         (OPCODE_32BIT_INSN): ...this.
 181         (OPCODE_AC): Delete.
 182         (skip_this_opcode): Handle different instruction lengths, update
 183         macro name.
 184         (special_flag_p): Update parameter type.
 185         (find_format_from_table): Update for more instruction lengths.
 186         (find_format_long_instructions): Delete.
 187         (find_format): Update for more instruction lengths.
 188         (arc_insn_length): Likewise.
 189         (extract_operand_value): Update for more instruction lengths.
 190         (operand_iterator_next): Remove code relating to long
 191         instructions.
 192         (arc_opcode_to_insn_type): New function.
 193         (print_insn_arc):Update for more instructions lengths.
 194         * arc-ext.c (extInstruction_t): Change argument type.
 195         * arc-ext.h (extInstruction_t): Change argument type.
 196         * arc-fxi.h: Change type unsigned to unsigned long long
 197         extensively throughout.
 198         * arc-nps400-tbl.h: Add long instructions taken from
 199         arc_long_opcodes table in arc-opc.c.
 200         * arc-opc.c: Update parameter types on insert/extract handlers.
 201         (arc_long_opcodes): Delete.
 202         (arc_num_long_opcodes): Delete.
 203         (arc_opcode_len): Update for more instruction lengths.
 204
 205 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 206
 207         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 208
 209 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 210
 211         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 212         with arc_opcode_len.
 213         (find_format_long_instructions): Likewise.
 214         * arc-opc.c (arc_opcode_len): New function.
 215
 216 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 217
 218         * arc-nps400-tbl.h: Fix some instruction masks.
 219
 220 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 221
 222         * i386-dis.c (REG_82): Removed.
 223         (X86_64_82_REG_0): Likewise.
 224         (X86_64_82_REG_1): Likewise.
 225         (X86_64_82_REG_2): Likewise.
 226         (X86_64_82_REG_3): Likewise.
 227         (X86_64_82_REG_4): Likewise.
 228         (X86_64_82_REG_5): Likewise.
 229         (X86_64_82_REG_6): Likewise.
 230         (X86_64_82_REG_7): Likewise.
 231         (X86_64_82): New.
 232         (dis386): Use X86_64_82 instead of REG_82.
 233         (reg_table): Remove REG_82.
 234         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 235         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 236         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 237         X86_64_82_REG_7.
 238
 239 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 240
 241         PR binutils/20754
 242         * i386-dis.c (REG_82): New.
 243         (X86_64_82_REG_0): Likewise.
 244         (X86_64_82_REG_1): Likewise.
 245         (X86_64_82_REG_2): Likewise.
 246         (X86_64_82_REG_3): Likewise.
 247         (X86_64_82_REG_4): Likewise.
 248         (X86_64_82_REG_5): Likewise.
 249         (X86_64_82_REG_6): Likewise.
 250         (X86_64_82_REG_7): Likewise.
 251         (dis386): Use REG_82.
 252         (reg_table): Add REG_82.
 253         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 254         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 255         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 256
 257 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 258
 259         * i386-dis.c (REG_82): Renamed to ...
 260         (REG_83): This.
 261         (dis386): Updated.
 262         (reg_table): Likewise.
 263
 264 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 265
 266         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 267         * i386-dis-evex.h (evex_table): Updated.
 268         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 269         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 270         (cpu_flags): Add CpuAVX512_4VNNIW.
 271         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 272         (i386_cpu_flags): Add cpuavx512_4vnniw.
 273         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 274         * i386-init.h: Regenerate.
 275         * i386-tbl.h: Ditto.
 276
 277 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 278
 279         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 280         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 281         * i386-dis-evex.h (evex_table): Updated.
 282         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 283         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 284         (cpu_flags): Add CpuAVX512_4FMAPS.
 285         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 286         * i386-opc.h (AVX512_4FMAP): New.
 287         (i386_cpu_flags): Add cpuavx512_4fmaps.
 288         (ImplicitQuadGroup): New.
 289         (i386_opcode_modifier): Add implicitquadgroup.
 290         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 291         * i386-init.h: Regenerate.
 292         * i386-tbl.h: Ditto.
 293
 294 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 295             Andrew Waterman <andrew@sifive.com>
 296
 297         Add support for RISC-V architecture.
 298         * configure.ac: Add entry for bfd_riscv_arch.
 299         * configure: Regenerate.
 300         * disassemble.c (disassembler): Add support for riscv.
 301         (disassembler_usage): Likewise.
 302         * riscv-dis.c: New file.
 303         * riscv-opc.c: New file.
 304
 305 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 306
 307         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 308         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 309         (rm_table): Update the RM_0FAE_REG_7 entry.
 310         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 311         (cpu_flags): Remove CpuPCOMMIT.
 312         * i386-opc.h (CpuPCOMMIT): Removed.
 313         (i386_cpu_flags): Remove cpupcommit.
 314         * i386-opc.tbl: Remove pcommit.
 315         * i386-init.h: Regenerated.
 316         * i386-tbl.h: Likewise.
 317
 318 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         PR binutis/20705
 321         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 322         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 323         32-bit mode.  Don't check vex.register_specifier in 32-bit
 324         mode.
 325         (OP_VEX): Check for invalid mask registers.
 326
 327 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 328
 329         PR binutis/20699
 330         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 331         sizeflag.
 332
 333 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 334
 335         PR binutis/20704
 336         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 337
 338 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 339
 340         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 341         local variable to `index_regno'.
 342
 343 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 344
 345         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 346
 347 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 348
 349         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 350         usage on ISA basis.
 351
 352 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 353
 354         PR target/20666
 355         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 356
 357 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 358
 359         PR target/20667
 360         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 361         available.
 362
 363 2016-10-07  Alan Modra  <amodra@gmail.com>
 364
 365         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 366
 367 2016-10-06  Alan Modra  <amodra@gmail.com>
 368
 369         * aarch64-opc.c: Spell fall through comments consistently.
 370         * i386-dis.c: Likewise.
 371         * aarch64-dis.c: Add missing fall through comments.
 372         * aarch64-opc.c: Likewise.
 373         * arc-dis.c: Likewise.
 374         * arm-dis.c: Likewise.
 375         * i386-dis.c: Likewise.
 376         * m68k-dis.c: Likewise.
 377         * mep-asm.c: Likewise.
 378         * ns32k-dis.c: Likewise.
 379         * sh-dis.c: Likewise.
 380         * tic4x-dis.c: Likewise.
 381         * tic6x-dis.c: Likewise.
 382         * vax-dis.c: Likewise.
 383
 384 2016-10-06  Alan Modra  <amodra@gmail.com>
 385
 386         * arc-ext.c (create_map): Add missing break.
 387         * msp430-decode.opc (encode_as): Likewise.
 388         * msp430-decode.c: Regenerate.
 389
 390 2016-10-06  Alan Modra  <amodra@gmail.com>
 391
 392         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 393         * crx-dis.c (print_insn_crx): Likewise.
 394
 395 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 396
 397         PR binutils/20657
 398         * i386-dis.c (putop): Don't assign alt twice.
 399
 400 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 401
 402         PR target/20553
 403         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 404
 405 2016-09-29  Alan Modra  <amodra@gmail.com>
 406
 407         * ppc-opc.c (L): Make compulsory.
 408         (LOPT): New, optional form of L.
 409         (HTM_R): Define as LOPT.
 410         (L0, L1): Delete.
 411         (L32OPT): New, optional for 32-bit L.
 412         (L2OPT): New, 2-bit L for dcbf.
 413         (SVC_LEC): Update.
 414         (L2): Define.
 415         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 416         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 417         <dcbf>: Use L2OPT.
 418         <tlbiel, tlbie>: Use LOPT.
 419         <wclr, wclrall>: Use L2.
 420
 421 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 422
 423         * Makefile.in: Regenerate.
 424         * configure: Likewise.
 425
 426 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 427
 428         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 429         (EXTINSN2OP): Use EXTINSN2OPF.
 430         (bspeekm, bspop, modapp): New extension instructions.
 431         * arc-opc.c (F_DNZ_ND): Define.
 432         (F_DNZ_D): Likewise.
 433         (F_SIZEB1): Changed.
 434         (C_DNZ_D): Define.
 435         (C_HARD): Changed.
 436         * arc-tbl.h (dbnz): New instruction.
 437         (prealloc): Allow it for ARC EM.
 438         (xbfu): Likewise.
 439
 440 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 441
 442         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 443         after commas in addresses.
 444         (aarch64_print_operand): Likewise.
 445
 446 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 447
 448         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 449         rather than "should be" or "expected to be" in error messages.
 450
 451 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 452
 453         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 454         (print_mnemonic_name): ...here.
 455         (print_comment): New function.
 456         (print_aarch64_insn): Call it.
 457         * aarch64-opc.c (aarch64_conds): Add SVE names.
 458         (aarch64_print_operand): Print alternative condition names in
 459         a comment.
 460
 461 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 462
 463         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 464         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 465         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 466         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 467         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 468         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 469         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 470         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 471         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 472         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 473         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 474         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 475         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 476         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 477         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 478         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 479         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 480         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 481         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 482         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 483         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 484         (aarch64_feature_sve): New variable.
 485         (SVE): New macro.
 486         (_SVE_INSN): Likewise.
 487         (aarch64_opcode_table): Add SVE instructions.
 488         * aarch64-opc.h (extract_fields): Declare.
 489         * aarch64-opc-2.c: Regenerate.
 490         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 491         * aarch64-asm-2.c: Regenerate.
 492         * aarch64-dis.c (extract_fields): Make global.
 493         (do_misc_decoding): Handle the new SVE aarch64_ops.
 494         * aarch64-dis-2.c: Regenerate.
 495
 496 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 497
 498         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 499         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 500         aarch64_field_kinds.
 501         * aarch64-opc.c (fields): Add corresponding entries.
 502         * aarch64-asm.c (aarch64_get_variant): New function.
 503         (aarch64_encode_variant_using_iclass): Likewise.
 504         (aarch64_opcode_encode): Call it.
 505         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 506         (aarch64_opcode_decode): Call it.
 507
 508 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 509
 510         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 511         and FP register operands.
 512         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 513         (FLD_SVE_Vn): New aarch64_field_kinds.
 514         * aarch64-opc.c (fields): Add corresponding entries.
 515         (aarch64_print_operand): Handle the new SVE core and FP register
 516         operands.
 517         * aarch64-opc-2.c: Regenerate.
 518         * aarch64-asm-2.c: Likewise.
 519         * aarch64-dis-2.c: Likewise.
 520
 521 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 522
 523         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 524         immediate operands.
 525         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 526         * aarch64-opc.c (fields): Add corresponding entry.
 527         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 528         operands.
 529         (aarch64_print_operand): Likewise.
 530         * aarch64-opc-2.c: Regenerate.
 531         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 532         (ins_sve_float_zero_one): New inserters.
 533         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 534         (aarch64_ins_sve_float_half_two): Likewise.
 535         (aarch64_ins_sve_float_zero_one): Likewise.
 536         * aarch64-asm-2.c: Regenerate.
 537         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 538         (ext_sve_float_zero_one): New extractors.
 539         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 540         (aarch64_ext_sve_float_half_two): Likewise.
 541         (aarch64_ext_sve_float_zero_one): Likewise.
 542         * aarch64-dis-2.c: Regenerate.
 543
 544 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 545
 546         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 547         integer immediate operands.
 548         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 549         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 550         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 551         * aarch64-opc.c (fields): Add corresponding entries.
 552         (operand_general_constraint_met_p): Handle the new SVE integer
 553         immediate operands.
 554         (aarch64_print_operand): Likewise.
 555         (aarch64_sve_dupm_mov_immediate_p): New function.
 556         * aarch64-opc-2.c: Regenerate.
 557         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 558         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 559         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 560         (aarch64_ins_limm): ...here.
 561         (aarch64_ins_inv_limm): New function.
 562         (aarch64_ins_sve_aimm): Likewise.
 563         (aarch64_ins_sve_asimm): Likewise.
 564         (aarch64_ins_sve_limm_mov): Likewise.
 565         (aarch64_ins_sve_shlimm): Likewise.
 566         (aarch64_ins_sve_shrimm): Likewise.
 567         * aarch64-asm-2.c: Regenerate.
 568         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 569         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 570         * aarch64-dis.c (decode_limm): New function, split out from...
 571         (aarch64_ext_limm): ...here.
 572         (aarch64_ext_inv_limm): New function.
 573         (decode_sve_aimm): Likewise.
 574         (aarch64_ext_sve_aimm): Likewise.
 575         (aarch64_ext_sve_asimm): Likewise.
 576         (aarch64_ext_sve_limm_mov): Likewise.
 577         (aarch64_top_bit): Likewise.
 578         (aarch64_ext_sve_shlimm): Likewise.
 579         (aarch64_ext_sve_shrimm): Likewise.
 580         * aarch64-dis-2.c: Regenerate.
 581
 582 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 583
 584         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 585         operands.
 586         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 587         the AARCH64_MOD_MUL_VL entry.
 588         (value_aligned_p): Cope with non-power-of-two alignments.
 589         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 590         (print_immediate_offset_address): Likewise.
 591         (aarch64_print_operand): Likewise.
 592         * aarch64-opc-2.c: Regenerate.
 593         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 594         (ins_sve_addr_ri_s9xvl): New inserters.
 595         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 596         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 597         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 598         * aarch64-asm-2.c: Regenerate.
 599         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 600         (ext_sve_addr_ri_s9xvl): New extractors.
 601         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 602         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 603         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 604         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 605         * aarch64-dis-2.c: Regenerate.
 606
 607 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 608
 609         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 610         address operands.
 611         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 612         (FLD_SVE_xs_22): New aarch64_field_kinds.
 613         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 614         (get_operand_specific_data): New function.
 615         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 616         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 617         (operand_general_constraint_met_p): Handle the new SVE address
 618         operands.
 619         (sve_reg): New array.
 620         (get_addr_sve_reg_name): New function.
 621         (aarch64_print_operand): Handle the new SVE address operands.
 622         * aarch64-opc-2.c: Regenerate.
 623         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 624         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 625         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 626         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 627         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 628         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 629         (aarch64_ins_sve_addr_zi_u5): Likewise.
 630         (aarch64_ins_sve_addr_zz): Likewise.
 631         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 632         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 633         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 634         * aarch64-asm-2.c: Regenerate.
 635         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 636         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 637         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 638         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 639         (aarch64_ext_sve_addr_ri_u6): Likewise.
 640         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 641         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 642         (aarch64_ext_sve_addr_zi_u5): Likewise.
 643         (aarch64_ext_sve_addr_zz): Likewise.
 644         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 645         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 646         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 647         * aarch64-dis-2.c: Regenerate.
 648
 649 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 650
 651         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 652         AARCH64_OPND_SVE_PATTERN_SCALED.
 653         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 654         * aarch64-opc.c (fields): Add a corresponding entry.
 655         (set_multiplier_out_of_range_error): New function.
 656         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 657         (operand_general_constraint_met_p): Handle
 658         AARCH64_OPND_SVE_PATTERN_SCALED.
 659         (print_register_offset_address): Use PRIi64 to print the
 660         shift amount.
 661         (aarch64_print_operand): Likewise.  Handle
 662         AARCH64_OPND_SVE_PATTERN_SCALED.
 663         * aarch64-opc-2.c: Regenerate.
 664         * aarch64-asm.h (ins_sve_scale): New inserter.
 665         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 666         * aarch64-asm-2.c: Regenerate.
 667         * aarch64-dis.h (ext_sve_scale): New inserter.
 668         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 669         * aarch64-dis-2.c: Regenerate.
 670
 671 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 672
 673         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 674         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 675         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 676         (FLD_SVE_prfop): Likewise.
 677         * aarch64-opc.c: Include libiberty.h.
 678         (aarch64_sve_pattern_array): New variable.
 679         (aarch64_sve_prfop_array): Likewise.
 680         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 681         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 682         AARCH64_OPND_SVE_PRFOP.
 683         * aarch64-asm-2.c: Regenerate.
 684         * aarch64-dis-2.c: Likewise.
 685         * aarch64-opc-2.c: Likewise.
 686
 687 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 688
 689         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 690         AARCH64_OPND_QLF_P_[ZM].
 691         (aarch64_print_operand): Print /z and /m where appropriate.
 692
 693 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 694
 695         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 696         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 697         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 698         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 699         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 700         * aarch64-opc.c (fields): Add corresponding entries here.
 701         (operand_general_constraint_met_p): Check that SVE register lists
 702         have the correct length.  Check the ranges of SVE index registers.
 703         Check for cases where p8-p15 are used in 3-bit predicate fields.
 704         (aarch64_print_operand): Handle the new SVE operands.
 705         * aarch64-opc-2.c: Regenerate.
 706         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 707         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 708         (aarch64_ins_sve_reglist): Likewise.
 709         * aarch64-asm-2.c: Regenerate.
 710         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 711         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 712         (aarch64_ext_sve_reglist): Likewise.
 713         * aarch64-dis-2.c: Regenerate.
 714
 715 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 716
 717         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 718         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 719         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 720         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 721         tied operands.
 722
 723 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 724
 725         * aarch64-opc.c (get_offset_int_reg_name): New function.
 726         (print_immediate_offset_address): Likewise.
 727         (print_register_offset_address): Take the base and offset
 728         registers as parameters.
 729         (aarch64_print_operand): Update caller accordingly.  Use
 730         print_immediate_offset_address.
 731
 732 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 733
 734         * aarch64-opc.c (BANK): New macro.
 735         (R32, R64): Take a register number as argument
 736         (int_reg): Use BANK.
 737
 738 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 739
 740         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 741         (aarch64_print_operand): Update accordingly.
 742
 743 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 744
 745         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 746         for FPIMM.
 747         * aarch64-asm.h (ins_fpimm): New inserter.
 748         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 749         * aarch64-asm-2.c: Regenerate.
 750         * aarch64-dis.h (ext_fpimm): New extractor.
 751         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 752         (aarch64_ext_fpimm): New function.
 753         * aarch64-dis-2.c: Regenerate.
 754
 755 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 756
 757         * aarch64-asm.c: Include libiberty.h.
 758         (insert_fields): New function.
 759         (aarch64_ins_imm): Use it.
 760         * aarch64-dis.c (extract_fields): New function.
 761         (aarch64_ext_imm): Use it.
 762
 763 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 764
 765         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 766         with an esize parameter.
 767         (operand_general_constraint_met_p): Update accordingly.
 768         Fix misindented code.
 769         * aarch64-asm.c (aarch64_ins_limm): Update call to
 770         aarch64_logical_immediate_p.
 771
 772 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 773
 774         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 775
 776 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 777
 778         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 779
 780 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 781
 782         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 783
 784 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 785
 786         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 787         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 788         xor3>: Delete mnemonics.
 789         <cp_abort>: Rename mnemonic from ...
 790         <cpabort>: ...to this.
 791         <setb>: Change to a X form instruction.
 792         <sync>: Change to 1 operand form.
 793         <copy>: Delete mnemonic.
 794         <copy_first>: Rename mnemonic from ...
 795         <copy>: ...to this.
 796         <paste, paste.>: Delete mnemonics.
 797         <paste_last>: Rename mnemonic from ...
 798         <paste.>: ...to this.
 799
 800 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 801
 802         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 803
 804 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 805
 806         * s390-mkopc.c (main): Support alternate arch strings.
 807
 808 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 809
 810         * s390-opc.txt: Fix kmctr instruction type.
 811
 812 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 813
 814         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 815         * i386-init.h: Regenerated.
 816
 817 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 818
 819         * opcodes/arc-dis.c (print_insn_arc): Changed.
 820
 821 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 822
 823         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 824         camellia_fl.
 825
 826 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 827
 828         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 829         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 830         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 831
 832 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 833
 834         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 835         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 836         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 837         PREFIX_MOD_3_0FAE_REG_4.
 838         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 839         PREFIX_MOD_3_0FAE_REG_4.
 840         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 841         (cpu_flags): Add CpuPTWRITE.
 842         * i386-opc.h (CpuPTWRITE): New.
 843         (i386_cpu_flags): Add cpuptwrite.
 844         * i386-opc.tbl: Add ptwrite instruction.
 845         * i386-init.h: Regenerated.
 846         * i386-tbl.h: Likewise.
 847
 848 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 849
 850         * arc-dis.h: Wrap around in extern "C".
 851
 852 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 853
 854         * aarch64-tbl.h (V8_2_INSN): New macro.
 855         (aarch64_opcode_table): Use it.
 856
 857 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 858
 859         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 860         CORE_INSN, __FP_INSN and SIMD_INSN.
 861
 862 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 863
 864         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 865         (aarch64_opcode_table): Update uses accordingly.
 866
 867 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 868         Kwok Cheung Yeung  <kcy@codesourcery.com>
 869
 870         opcodes/
 871         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 872         'e_cmplwi' to 'e_cmpli' instead.
 873         (OPVUPRT, OPVUPRT_MASK): Define.
 874         (powerpc_opcodes): Add E200Z4 insns.
 875         (vle_opcodes): Add context save/restore insns.
 876
 877 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 878
 879         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 880         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 881         "j".
 882
 883 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 884
 885         * arc-nps400-tbl.h: Change block comments to GNU format.
 886         * arc-dis.c: Add new globals addrtypenames,
 887         addrtypenames_max, and addtypeunknown.
 888         (get_addrtype): New function.
 889         (print_insn_arc): Print colons and address types when
 890         required.
 891         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 892         define insert and extract functions for all address types.
 893         (arc_operands): Add operands for colon and all address
 894         types.
 895         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 896         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 897         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 898         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 899         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 900         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 901
 902 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 903
 904         * configure: Regenerated.
 905
 906 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 907
 908         * arc-dis.c (skipclass): New structure.
 909         (decodelist): New variable.
 910         (is_compatible_p): New function.
 911         (new_element): Likewise.
 912         (skip_class_p): Likewise.
 913         (find_format_from_table): Use skip_class_p function.
 914         (find_format): Decode first the extension instructions.
 915         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 916         e_flags.
 917         (parse_option): New function.
 918         (parse_disassembler_options): Likewise.
 919         (print_arc_disassembler_options): Likewise.
 920         (print_insn_arc): Use parse_disassembler_options function.  Proper
 921         select ARCv2 cpu variant.
 922         * disassemble.c (disassembler_usage): Add ARC disassembler
 923         options.
 924
 925 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 926
 927         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 928         annotation from the "nal" entry and reorder it beyond "bltzal".
 929
 930 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 931
 932         * sparc-opc.c (ldtxa): New macro.
 933         (sparc_opcodes): Use the macro defined above to add entries for
 934         the LDTXA instructions.
 935         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 936         instruction.
 937
 938 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 939
 940         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 941         and "jmpc".
 942
 943 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 944
 945         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 946         (movzb): Adjust to cover all permitted suffixes.
 947         (movzw): New.
 948         * i386-tbl.h: Re-generate.
 949
 950 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 951
 952         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 953         (lgdt): Remove Tbyte from non-64-bit variant.
 954         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 955         xsaves64, xsavec64): Remove Disp16.
 956         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 957         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 958         64-bit variants.
 959         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 960         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 961         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 962         64-bit variants.
 963         * i386-tbl.h: Re-generate.
 964
 965 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 966
 967         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 968         * i386-tbl.h: Re-generate.
 969
 970 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 971
 972         * arm-dis.c (print_insn): Fix typo in comment.
 973
 974 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 975
 976         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 977         range of ldst_elemlist operands.
 978         (print_register_list): Use PRIi64 to print the index.
 979         (aarch64_print_operand): Likewise.
 980
 981 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 982
 983         * mcore-opc.h: Remove sentinal.
 984         * mcore-dis.c (print_insn_mcore): Adjust.
 985
 986 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 987
 988         * arc-opc.c: Correct description of availability of NPS400
 989         features.
 990
 991 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 992
 993         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 994         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 995         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 996         xor3>: New mnemonics.
 997         <setb>: Change to a VX form instruction.
 998         (insert_sh6): Add support for rldixor.
 999         (extract_sh6): Likewise.
1000
1001 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1002
1003         * arc-ext.h: Wrap in extern C.
1004
1005 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1006
1007         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1008         Use same method for determining instruction length on ARC700 and
1009         NPS-400.
1010         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1011         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1012         with the NPS400 subclass.
1013         * arc-opc.c: Likewise.
1014
1015 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1016
1017         * sparc-opc.c (rdasr): New macro.
1018         (wrasr): Likewise.
1019         (rdpr): Likewise.
1020         (wrpr): Likewise.
1021         (rdhpr): Likewise.
1022         (wrhpr): Likewise.
1023         (sparc_opcodes): Use the macros above to fix and expand the
1024         definition of read/write instructions from/to
1025         asr/privileged/hyperprivileged instructions.
1026         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1027         %hva_mask_nz.  Prefer softint_set and softint_clear over
1028         set_softint and clear_softint.
1029         (print_insn_sparc): Support %ver in Rd.
1030
1031 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1032
1033         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1034         architecture according to the hardware capabilities they require.
1035
1036 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1037
1038         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1039         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1040         bfd_mach_sparc_v9{c,d,e,v,m}.
1041         * sparc-opc.c (MASK_V9C): Define.
1042         (MASK_V9D): Likewise.
1043         (MASK_V9E): Likewise.
1044         (MASK_V9V): Likewise.
1045         (MASK_V9M): Likewise.
1046         (v6): Add MASK_V9{C,D,E,V,M}.
1047         (v6notlet): Likewise.
1048         (v7): Likewise.
1049         (v8): Likewise.
1050         (v9): Likewise.
1051         (v9andleon): Likewise.
1052         (v9a): Likewise.
1053         (v9b): Likewise.
1054         (v9c): Define.
1055         (v9d): Likewise.
1056         (v9e): Likewise.
1057         (v9v): Likewise.
1058         (v9m): Likewise.
1059         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1060
1061 2016-06-15  Nick Clifton  <nickc@redhat.com>
1062
1063         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1064         constants to match expected behaviour.
1065         (nds32_parse_opcode): Likewise.  Also for whitespace.
1066
1067 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1068
1069         * arc-opc.c (extract_rhv1): Extract value from insn.
1070
1071 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1072
1073         * arc-nps400-tbl.h: Add ldbit instruction.
1074         * arc-opc.c: Add flag classes required for ldbit.
1075
1076 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1077
1078         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1079         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1080         support the above instructions.
1081
1082 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1083
1084         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1085         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1086         csma, cbba, zncv, and hofs.
1087         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1088         support the above instructions.
1089
1090 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1091
1092         * arc-nps400-tbl.h: Add andab and orab instructions.
1093
1094 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1095
1096         * arc-nps400-tbl.h: Add addl-like instructions.
1097
1098 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1099
1100         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1101
1102 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1103
1104         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1105         instructions.
1106
1107 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1108
1109         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1110         variable.
1111         (init_disasm): Handle new command line option "insnlength".
1112         (print_s390_disassembler_options): Mention new option in help
1113         output.
1114         (print_insn_s390): Use the encoded insn length when dumping
1115         unknown instructions.
1116
1117 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1118
1119         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1120          to the address and set as symbol address for LDS/ STS immediate operands.
1121
1122 2016-06-07  Alan Modra  <amodra@gmail.com>
1123
1124         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1125         cpu for "vle" to e500.
1126         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1127         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1128         (PPCNONE): Delete, substitute throughout.
1129         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1130         except for major opcode 4 and 31.
1131         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1132
1133 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1134
1135         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1136         ARM_EXT_RAS in relevant entries.
1137
1138 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1139
1140         PR binutils/20196
1141         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1142         opcodes for E6500.
1143
1144 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1145
1146         PR binutis/18386
1147         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1148         (indir_v_mode): New.
1149         Add comments for '&'.
1150         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1151         (putop): Handle '&'.
1152         (intel_operand_size): Handle indir_v_mode.
1153         (OP_E_register): Likewise.
1154         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1155         64-bit indirect call/jmp for AMD64.
1156         * i386-tbl.h: Regenerated
1157
1158 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1159
1160         * arc-dis.c (struct arc_operand_iterator): New structure.
1161         (find_format_from_table): All the old content from find_format,
1162         with some minor adjustments, and parameter renaming.
1163         (find_format_long_instructions): New function.
1164         (find_format): Rewritten.
1165         (arc_insn_length): Add LSB parameter.
1166         (extract_operand_value): New function.
1167         (operand_iterator_next): New function.
1168         (print_insn_arc): Use new functions to find opcode, and iterator
1169         over operands.
1170         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1171         (extract_nps_3bit_dst_short): New function.
1172         (insert_nps_3bit_src2_short): New function.
1173         (extract_nps_3bit_src2_short): New function.
1174         (insert_nps_bitop1_size): New function.
1175         (extract_nps_bitop1_size): New function.
1176         (insert_nps_bitop2_size): New function.
1177         (extract_nps_bitop2_size): New function.
1178         (insert_nps_bitop_mod4_msb): New function.
1179         (extract_nps_bitop_mod4_msb): New function.
1180         (insert_nps_bitop_mod4_lsb): New function.
1181         (extract_nps_bitop_mod4_lsb): New function.
1182         (insert_nps_bitop_dst_pos3_pos4): New function.
1183         (extract_nps_bitop_dst_pos3_pos4): New function.
1184         (insert_nps_bitop_ins_ext): New function.
1185         (extract_nps_bitop_ins_ext): New function.
1186         (arc_operands): Add new operands.
1187         (arc_long_opcodes): New global array.
1188         (arc_num_long_opcodes): New global.
1189         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1190
1191 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1192
1193         * nds32-asm.h: Add extern "C".
1194         * sh-opc.h: Likewise.
1195
1196 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1197
1198         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1199         0,b,limm to the rflt instruction.
1200
1201 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1202
1203         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1204         constant.
1205
1206 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1207
1208         PR gas/20145
1209         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1210         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1211         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1212         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1213         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1214         * i386-init.h: Regenerated.
1215
1216 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1217
1218         PR gas/20145
1219         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1220         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1221         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1222         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1223         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1224         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1225         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1226         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1227         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1228         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1229         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1230         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1231         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1232         CpuRegMask for AVX512.
1233         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1234         and CpuRegMask.
1235         (set_bitfield_from_cpu_flag_init): New function.
1236         (set_bitfield): Remove const on f.  Call
1237         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1238         * i386-opc.h (CpuRegMMX): New.
1239         (CpuRegXMM): Likewise.
1240         (CpuRegYMM): Likewise.
1241         (CpuRegZMM): Likewise.
1242         (CpuRegMask): Likewise.
1243         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1244         and cpuregmask.
1245         * i386-init.h: Regenerated.
1246         * i386-tbl.h: Likewise.
1247
1248 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1249
1250         PR gas/20154
1251         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1252         (opcode_modifiers): Add AMD64 and Intel64.
1253         (main): Properly verify CpuMax.
1254         * i386-opc.h (CpuAMD64): Removed.
1255         (CpuIntel64): Likewise.
1256         (CpuMax): Set to CpuNo64.
1257         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1258         (AMD64): New.
1259         (Intel64): Likewise.
1260         (i386_opcode_modifier): Add amd64 and intel64.
1261         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1262         on call and jmp.
1263         * i386-init.h: Regenerated.
1264         * i386-tbl.h: Likewise.
1265
1266 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1267
1268         PR gas/20154
1269         * i386-gen.c (main): Fail if CpuMax is incorrect.
1270         * i386-opc.h (CpuMax): Set to CpuIntel64.
1271         * i386-tbl.h: Regenerated.
1272
1273 2016-05-27  Nick Clifton  <nickc@redhat.com>
1274
1275         PR target/20150
1276         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1277         (msp430dis_opcode_unsigned): New function.
1278         (msp430dis_opcode_signed): New function.
1279         (msp430_singleoperand): Use the new opcode reading functions.
1280         Only disassenmble bytes if they were successfully read.
1281         (msp430_doubleoperand): Likewise.
1282         (msp430_branchinstr): Likewise.
1283         (msp430x_callx_instr): Likewise.
1284         (print_insn_msp430): Check that it is safe to read bytes before
1285         attempting disassembly.  Use the new opcode reading functions.
1286
1287 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1288
1289         * ppc-opc.c (CY): New define.  Document it.
1290         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1291
1292 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1293
1294         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1295         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1296         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1297         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1298         CPU_ANY_AVX_FLAGS.
1299         * i386-init.h: Regenerated.
1300
1301 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1302
1303         PR gas/20141
1304         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1305         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1306         * i386-init.h: Regenerated.
1307
1308 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1309
1310         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1311         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1312         * i386-init.h: Regenerated.
1313
1314 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1315
1316         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1317         information.
1318         (print_insn_arc): Set insn_type information.
1319         * arc-opc.c (C_CC): Add F_CLASS_COND.
1320         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1321         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1322         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1323         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1324         (brne, brne_s, jeq_s, jne_s): Likewise.
1325
1326 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1327
1328         * arc-tbl.h (neg): New instruction variant.
1329
1330 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1331
1332         * arc-dis.c (find_format, find_format, get_auxreg)
1333         (print_insn_arc): Changed.
1334         * arc-ext.h (INSERT_XOP): Likewise.
1335
1336 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1337
1338         * tic54x-dis.c (sprint_mmr): Adjust.
1339         * tic54x-opc.c: Likewise.
1340
1341 2016-05-19  Alan Modra  <amodra@gmail.com>
1342
1343         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1344
1345 2016-05-19  Alan Modra  <amodra@gmail.com>
1346
1347         * ppc-opc.c: Formatting.
1348         (NSISIGNOPT): Define.
1349         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1350
1351 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1352
1353         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1354         replacing references to `micromips_ase' throughout.
1355         (_print_insn_mips): Don't use file-level microMIPS annotation to
1356         determine the disassembly mode with the symbol table.
1357
1358 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1359
1360         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1361
1362 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1363
1364         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1365         mips64r6.
1366         * mips-opc.c (D34): New macro.
1367         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1368
1369 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1370
1371         * i386-dis.c (prefix_table): Add RDPID instruction.
1372         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1373         (cpu_flags): Add RDPID bitfield.
1374         * i386-opc.h (enum): Add RDPID element.
1375         (i386_cpu_flags): Add RDPID field.
1376         * i386-opc.tbl: Add RDPID instruction.
1377         * i386-init.h: Regenerate.
1378         * i386-tbl.h: Regenerate.
1379
1380 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1381
1382         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1383         branch type of a symbol.
1384         (print_insn): Likewise.
1385
1386 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1387
1388         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1389         Mainline Security Extensions instructions.
1390         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1391         Extensions instructions.
1392         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1393         instructions.
1394         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1395         special registers.
1396
1397 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1398
1399         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1400
1401 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1402
1403         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1404         (arcExtMap_genOpcode): Likewise.
1405         * arc-opc.c (arg_32bit_rc): Define new variable.
1406         (arg_32bit_u6): Likewise.
1407         (arg_32bit_limm): Likewise.
1408
1409 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1410
1411         * aarch64-gen.c (VERIFIER): Define.
1412         * aarch64-opc.c (VERIFIER): Define.
1413         (verify_ldpsw): Use static linkage.
1414         * aarch64-opc.h (verify_ldpsw): Remove.
1415         * aarch64-tbl.h: Use VERIFIER for verifiers.
1416
1417 2016-04-28  Nick Clifton  <nickc@redhat.com>
1418
1419         PR target/19722
1420         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1421         * aarch64-opc.c (verify_ldpsw): New function.
1422         * aarch64-opc.h (verify_ldpsw): New prototype.
1423         * aarch64-tbl.h: Add initialiser for verifier field.
1424         (LDPSW): Set verifier to verify_ldpsw.
1425
1426 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1427
1428         PR binutils/19983
1429         PR binutils/19984
1430         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1431         smaller than address size.
1432
1433 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1434
1435         * alpha-dis.c: Regenerate.
1436         * crx-dis.c: Likewise.
1437         * disassemble.c: Likewise.
1438         * epiphany-opc.c: Likewise.
1439         * fr30-opc.c: Likewise.
1440         * frv-opc.c: Likewise.
1441         * ip2k-opc.c: Likewise.
1442         * iq2000-opc.c: Likewise.
1443         * lm32-opc.c: Likewise.
1444         * lm32-opinst.c: Likewise.
1445         * m32c-opc.c: Likewise.
1446         * m32r-opc.c: Likewise.
1447         * m32r-opinst.c: Likewise.
1448         * mep-opc.c: Likewise.
1449         * mt-opc.c: Likewise.
1450         * or1k-opc.c: Likewise.
1451         * or1k-opinst.c: Likewise.
1452         * tic80-opc.c: Likewise.
1453         * xc16x-opc.c: Likewise.
1454         * xstormy16-opc.c: Likewise.
1455
1456 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1457
1458         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1459         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1460         calcsd, and calcxd instructions.
1461         * arc-opc.c (insert_nps_bitop_size): Delete.
1462         (extract_nps_bitop_size): Delete.
1463         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1464         (extract_nps_qcmp_m3): Define.
1465         (extract_nps_qcmp_m2): Define.
1466         (extract_nps_qcmp_m1): Define.
1467         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1468         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1469         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1470         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1471         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1472         NPS_QCMP_M3.
1473
1474 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1475
1476         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1477
1478 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1479
1480         * Makefile.in: Regenerated with automake 1.11.6.
1481         * aclocal.m4: Likewise.
1482
1483 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1484
1485         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1486         instructions.
1487         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1488         (extract_nps_cmem_uimm16): New function.
1489         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1490
1491 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1492
1493         * arc-dis.c (arc_insn_length): New function.
1494         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1495         (find_format): Change insnLen parameter to unsigned.
1496
1497 2016-04-13  Nick Clifton  <nickc@redhat.com>
1498
1499         PR target/19937
1500         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1501         the LD.B and LD.BU instructions.
1502
1503 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1504
1505         * arc-dis.c (find_format): Check for extension flags.
1506         (print_flags): New function.
1507         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1508         .extAuxRegister.
1509         * arc-ext.c (arcExtMap_coreRegName): Use
1510         LAST_EXTENSION_CORE_REGISTER.
1511         (arcExtMap_coreReadWrite): Likewise.
1512         (dump_ARC_extmap): Update printing.
1513         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1514         (arc_aux_regs): Add cpu field.
1515         * arc-regs.h: Add cpu field, lower case name aux registers.
1516
1517 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1518
1519         * arc-tbl.h: Add rtsc, sleep with no arguments.
1520
1521 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1522
1523         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1524         Initialize.
1525         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1526         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1527         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1528         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1529         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1530         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1531         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1532         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1533         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1534         (arc_opcode arc_opcodes): Null terminate the array.
1535         (arc_num_opcodes): Remove.
1536         * arc-ext.h (INSERT_XOP): Define.
1537         (extInstruction_t): Likewise.
1538         (arcExtMap_instName): Delete.
1539         (arcExtMap_insn): New function.
1540         (arcExtMap_genOpcode): Likewise.
1541         * arc-ext.c (ExtInstruction): Remove.
1542         (create_map): Zero initialize instruction fields.
1543         (arcExtMap_instName): Remove.
1544         (arcExtMap_insn): New function.
1545         (dump_ARC_extmap): More info while debuging.
1546         (arcExtMap_genOpcode): New function.
1547         * arc-dis.c (find_format): New function.
1548         (print_insn_arc): Use find_format.
1549         (arc_get_disassembler): Enable dump_ARC_extmap only when
1550         debugging.
1551
1552 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1553
1554         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1555         instruction bits out.
1556
1557 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1558
1559         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1560         * arc-opc.c (arc_flag_operands): Add new flags.
1561         (arc_flag_classes): Add new classes.
1562
1563 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1564
1565         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1566
1567 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1568
1569         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1570         encode1, rflt, crc16, and crc32 instructions.
1571         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1572         (arc_flag_classes): Add C_NPS_R.
1573         (insert_nps_bitop_size_2b): New function.
1574         (extract_nps_bitop_size_2b): Likewise.
1575         (insert_nps_bitop_uimm8): Likewise.
1576         (extract_nps_bitop_uimm8): Likewise.
1577         (arc_operands): Add new operand entries.
1578
1579 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1580
1581         * arc-regs.h: Add a new subclass field.  Add double assist
1582         accumulator register values.
1583         * arc-tbl.h: Use DPA subclass to mark the double assist
1584         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1585         * arc-opc.c (RSP): Define instead of SP.
1586         (arc_aux_regs): Add the subclass field.
1587
1588 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1589
1590         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1591
1592 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1593
1594         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1595         NPS_R_SRC1.
1596
1597 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1598
1599         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1600         issues.  No functional changes.
1601
1602 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1603
1604         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1605         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1606         (RTT): Remove duplicate.
1607         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1608         (PCT_CONFIG*): Remove.
1609         (D1L, D1H, D2H, D2L): Define.
1610
1611 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1612
1613         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1614
1615 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1616
1617         * arc-tbl.h (invld07): Remove.
1618         * arc-ext-tbl.h: New file.
1619         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1620         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1621
1622 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1623
1624         Fix -Wstack-usage warnings.
1625         * aarch64-dis.c (print_operands): Substitute size.
1626         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1627
1628 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1629
1630         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1631         to get a proper diagnostic when an invalid ASR register is used.
1632
1633 2016-03-22  Nick Clifton  <nickc@redhat.com>
1634
1635         * configure: Regenerate.
1636
1637 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1638
1639         * arc-nps400-tbl.h: New file.
1640         * arc-opc.c: Add top level comment.
1641         (insert_nps_3bit_dst): New function.
1642         (extract_nps_3bit_dst): New function.
1643         (insert_nps_3bit_src2): New function.
1644         (extract_nps_3bit_src2): New function.
1645         (insert_nps_bitop_size): New function.
1646         (extract_nps_bitop_size): New function.
1647         (arc_flag_operands): Add nps400 entries.
1648         (arc_flag_classes): Add nps400 entries.
1649         (arc_operands): Add nps400 entries.
1650         (arc_opcodes): Add nps400 include.
1651
1652 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1653
1654         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1655         the new class enum values.
1656
1657 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1658
1659         * arc-dis.c (print_insn_arc): Handle nps400.
1660
1661 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1662
1663         * arc-opc.c (BASE): Delete.
1664
1665 2016-03-18  Nick Clifton  <nickc@redhat.com>
1666
1667         PR target/19721
1668         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1669         of MOV insn that aliases an ORR insn.
1670
1671 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1672
1673         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1674
1675 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1676
1677         * mcore-opc.h: Add const qualifiers.
1678         * microblaze-opc.h (struct op_code_struct): Likewise.
1679         * sh-opc.h: Likewise.
1680         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1681         (tic4x_print_op): Likewise.
1682
1683 2016-03-02  Alan Modra  <amodra@gmail.com>
1684
1685         * or1k-desc.h: Regenerate.
1686         * fr30-ibld.c: Regenerate.
1687         * rl78-decode.c: Regenerate.
1688
1689 2016-03-01  Nick Clifton  <nickc@redhat.com>
1690
1691         PR target/19747
1692         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1693
1694 2016-02-24  Renlin Li  <renlin.li@arm.com>
1695
1696         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1697         (print_insn_coprocessor): Support fp16 instructions.
1698
1699 2016-02-24  Renlin Li  <renlin.li@arm.com>
1700
1701         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1702         vminnm, vrint(mpna).
1703
1704 2016-02-24  Renlin Li  <renlin.li@arm.com>
1705
1706         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1707         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1708
1709 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1710
1711         * i386-dis.c (print_insn): Parenthesize expression to prevent
1712         truncated addresses.
1713         (OP_J): Likewise.
1714
1715 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1716             Janek van Oirschot  <jvanoirs@synopsys.com>
1717
1718         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1719         variable.
1720
1721 2016-02-04  Nick Clifton  <nickc@redhat.com>
1722
1723         PR target/19561
1724         * msp430-dis.c (print_insn_msp430): Add a special case for
1725         decoding an RRC instruction with the ZC bit set in the extension
1726         word.
1727
1728 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1729
1730         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1731         * epiphany-ibld.c: Regenerate.
1732         * fr30-ibld.c: Regenerate.
1733         * frv-ibld.c: Regenerate.
1734         * ip2k-ibld.c: Regenerate.
1735         * iq2000-ibld.c: Regenerate.
1736         * lm32-ibld.c: Regenerate.
1737         * m32c-ibld.c: Regenerate.
1738         * m32r-ibld.c: Regenerate.
1739         * mep-ibld.c: Regenerate.
1740         * mt-ibld.c: Regenerate.
1741         * or1k-ibld.c: Regenerate.
1742         * xc16x-ibld.c: Regenerate.
1743         * xstormy16-ibld.c: Regenerate.
1744
1745 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1746
1747         * epiphany-dis.c: Regenerated from latest cpu files.
1748
1749 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1750
1751         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1752         test bit.
1753
1754 2016-01-25  Renlin Li  <renlin.li@arm.com>
1755
1756         * arm-dis.c (mapping_symbol_for_insn): New function.
1757         (find_ifthen_state): Call mapping_symbol_for_insn().
1758
1759 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1760
1761         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1762         of MSR UAO immediate operand.
1763
1764 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1765
1766         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1767         instruction support.
1768
1769 2016-01-17  Alan Modra  <amodra@gmail.com>
1770
1771         * configure: Regenerate.
1772
1773 2016-01-14  Nick Clifton  <nickc@redhat.com>
1774
1775         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1776         instructions that can support stack pointer operations.
1777         * rl78-decode.c: Regenerate.
1778         * rl78-dis.c: Fix display of stack pointer in MOVW based
1779         instructions.
1780
1781 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1782
1783         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1784         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1785         erxtatus_el1 and erxaddr_el1.
1786
1787 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1788
1789         * arm-dis.c (arm_opcodes): Add "esb".
1790         (thumb_opcodes): Likewise.
1791
1792 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1793
1794         * ppc-opc.c <xscmpnedp>: Delete.
1795         <xvcmpnedp>: Likewise.
1796         <xvcmpnedp.>: Likewise.
1797         <xvcmpnesp>: Likewise.
1798         <xvcmpnesp.>: Likewise.
1799
1800 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1801
1802         PR gas/13050
1803         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1804         addition to ISA_A.
1805
1806 2016-01-01  Alan Modra  <amodra@gmail.com>
1807
1808         Update year range in copyright notice of all files.
1809
1810 For older changes see ChangeLog-2015
1811 \f
1812 Copyright (C) 2016 Free Software Foundation, Inc.
1813
1814 Copying and distribution of this file, with or without modification,
1815 are permitted in any medium without royalty provided the copyright
1816 notice and this notice are preserved.
1817
1818 Local Variables:
1819 mode: change-log
1820 left-margin: 8
1821 fill-column: 74
1822 version-control: never
1823 End: