opcodes/ChangeLog

   1 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * aarch64-tbl.h (aarch64_feature_sb): New.
   4         (SB, SB_INSN): New.
   5         (aarch64_opcode_table): Add entry for sb.
   6         * aarch64-asm-2.c: Regenerate.
   7         * aarch64-dis-2.c: Regenerate.
   8         * aarch64-opc-2.c: Regenerate.
   9
  10 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  11
  12         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
  13         (aarch64_feature_frintts): New.
  14         (FLAGMANIP, FRINTTS): New.
  15         (aarch64_opcode_table): Add entries for xaflag, axflag
  16         and frint[32,64][x,z] instructions.
  17         * aarch64-asm-2.c: Regenerate.
  18         * aarch64-dis-2.c: Regenerate.
  19         * aarch64-opc-2.c: Regenerate.
  20
  21 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  22
  23         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
  24         (ARMV8_5, V8_5_INSN): New.
  25
  26 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
  27
  28         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
  29
  30 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
  31
  32         * i386-dis.c (rm_table): Add enclv.
  33         * i386-opc.tbl: Add enclv.
  34         * i386-tbl.h: Regenerated.
  35
  36 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
  37
  38         * arm-dis.c (arm_opcodes): Add sb.
  39         (thumb32_opcodes): Likewise.
  40
  41 2018-10-05  Richard Henderson  <rth@twiddle.net>
  42             Stafford Horne  <shorne@gmail.com>
  43
  44         * or1k-desc.c: Regenerate.
  45         * or1k-desc.h: Regenerate.
  46         * or1k-opc.c: Regenerate.
  47         * or1k-opc.h: Regenerate.
  48         * or1k-opinst.c: Regenerate.
  49
  50 2018-10-05  Richard Henderson  <rth@twiddle.net>
  51
  52         * or1k-asm.c: Regenerated.
  53         * or1k-desc.c: Regenerated.
  54         * or1k-desc.h: Regenerated.
  55         * or1k-dis.c: Regenerated.
  56         * or1k-ibld.c: Regenerated.
  57         * or1k-opc.c: Regenerated.
  58         * or1k-opc.h: Regenerated.
  59         * or1k-opinst.c: Regenerated.
  60
  61 2018-10-05  Richard Henderson  <rth@twiddle.net>
  62
  63         * or1k-asm.c: Regenerate.
  64
  65 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  66
  67         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
  68         * aarch64-dis.c (print_operands): Refactor to take notes.
  69         (print_verifier_notes): New.
  70         (print_aarch64_insn): Apply constraint verifier.
  71         (print_insn_aarch64_word): Update call to print_aarch64_insn.
  72         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
  73
  74 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  75
  76         * aarch64-opc.c (init_insn_block): New.
  77         (verify_constraints, aarch64_is_destructive_by_operands): New.
  78         * aarch64-opc.h (verify_constraints): New.
  79
  80 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  81
  82         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
  83         * aarch64-opc.c (verify_ldpsw): Update arguments.
  84
  85 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  86
  87         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
  88         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
  89
  90 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  91
  92         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
  93         * aarch64-dis.c (insn_sequence): New.
  94
  95 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  96
  97         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
  98         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
  99         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 100         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 101         constraints.
 102         (_SVE_INSNC): New.
 103         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 104         constraints.
 105         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 106         F_SCAN flags.
 107         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 108         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 109         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 110         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 111         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 112         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 113         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 114
 115 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 116
 117         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 118
 119 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 120
 121         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 122         are used when extracting signed fields and converting them to
 123         potentially 64-bit types.
 124
 125 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 126
 127         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 128         * Makefile.in: Re-generate.
 129         * aclocal.m4: Re-generate.
 130         * configure: Re-generate.
 131         * configure.ac: Remove check for -Wno-missing-field-initializers.
 132         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 133         (csky_v2_opcodes): Likewise.
 134
 135 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 136
 137         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 138
 139 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 140
 141         * nds32-asm.c (operand_fields): Remove the unused fields.
 142         (nds32_opcodes): Remove the unused instructions.
 143         * nds32-dis.c (nds32_ex9_info): Removed.
 144         (nds32_parse_opcode): Updated.
 145         (print_insn_nds32): Likewise.
 146         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 147         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 148         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 149         build_opcode_hash_table): New functions.
 150         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 151         nds32_opcode_table): New.
 152         (hw_ktabs): Declare it to a pointer rather than an array.
 153         (build_hash_table): Removed.
 154         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 155         SYN_ROPT and upadte HW_GPR and HW_INT.
 156         * nds32-dis.c (keywords): Remove const.
 157         (match_field): New function.
 158         (nds32_parse_opcode): Updated.
 159         * disassemble.c (disassemble_init_for_target):
 160         Add disassemble_init_nds32.
 161         * nds32-dis.c (eum map_type): New.
 162         (nds32_private_data): Likewise.
 163         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 164         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 165         (print_insn_nds32): Updated.
 166         * nds32-asm.c (parse_aext_reg): Add new parameter.
 167         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 168         are allowed to use.
 169         All callers changed.
 170         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 171         (operand_fields): Add new fields.
 172         (nds32_opcodes): Add new instructions.
 173         (keyword_aridxi_mx): New keyword.
 174         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 175         and NASM_ATTR_ZOL.
 176         (ALU2_1, ALU2_2, ALU2_3): New macros.
 177         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 178
 179 2018-09-17  Kito Cheng  <kito@andestech.com>
 180
 181         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 182
 183 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 184
 185         PR gas/23670
 186         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 187         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 188         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 189         (EVEX_LEN_0F7E_P_1): Likewise.
 190         (EVEX_LEN_0F7E_P_2): Likewise.
 191         (EVEX_LEN_0FD6_P_2): Likewise.
 192         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 193         (EVEX_LEN_TABLE): Likewise.
 194         (EVEX_LEN_0F6E_P_2): New enum.
 195         (EVEX_LEN_0F7E_P_1): Likewise.
 196         (EVEX_LEN_0F7E_P_2): Likewise.
 197         (EVEX_LEN_0FD6_P_2): Likewise.
 198         (evex_len_table): New.
 199         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 200         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 201         * i386-tbl.h: Regenerated.
 202
 203 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 204
 205         PR gas/23665
 206         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 207         VEX_LEN_0F7E_P_2 entries.
 208         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 209         * i386-tbl.h: Regenerated.
 210
 211 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 212
 213         * i386-dis.c (VZERO_Fixup): Removed.
 214         (VZERO): Likewise.
 215         (VEX_LEN_0F10_P_1): Likewise.
 216         (VEX_LEN_0F10_P_3): Likewise.
 217         (VEX_LEN_0F11_P_1): Likewise.
 218         (VEX_LEN_0F11_P_3): Likewise.
 219         (VEX_LEN_0F2E_P_0): Likewise.
 220         (VEX_LEN_0F2E_P_2): Likewise.
 221         (VEX_LEN_0F2F_P_0): Likewise.
 222         (VEX_LEN_0F2F_P_2): Likewise.
 223         (VEX_LEN_0F51_P_1): Likewise.
 224         (VEX_LEN_0F51_P_3): Likewise.
 225         (VEX_LEN_0F52_P_1): Likewise.
 226         (VEX_LEN_0F53_P_1): Likewise.
 227         (VEX_LEN_0F58_P_1): Likewise.
 228         (VEX_LEN_0F58_P_3): Likewise.
 229         (VEX_LEN_0F59_P_1): Likewise.
 230         (VEX_LEN_0F59_P_3): Likewise.
 231         (VEX_LEN_0F5A_P_1): Likewise.
 232         (VEX_LEN_0F5A_P_3): Likewise.
 233         (VEX_LEN_0F5C_P_1): Likewise.
 234         (VEX_LEN_0F5C_P_3): Likewise.
 235         (VEX_LEN_0F5D_P_1): Likewise.
 236         (VEX_LEN_0F5D_P_3): Likewise.
 237         (VEX_LEN_0F5E_P_1): Likewise.
 238         (VEX_LEN_0F5E_P_3): Likewise.
 239         (VEX_LEN_0F5F_P_1): Likewise.
 240         (VEX_LEN_0F5F_P_3): Likewise.
 241         (VEX_LEN_0FC2_P_1): Likewise.
 242         (VEX_LEN_0FC2_P_3): Likewise.
 243         (VEX_LEN_0F3A0A_P_2): Likewise.
 244         (VEX_LEN_0F3A0B_P_2): Likewise.
 245         (VEX_W_0F10_P_0): Likewise.
 246         (VEX_W_0F10_P_1): Likewise.
 247         (VEX_W_0F10_P_2): Likewise.
 248         (VEX_W_0F10_P_3): Likewise.
 249         (VEX_W_0F11_P_0): Likewise.
 250         (VEX_W_0F11_P_1): Likewise.
 251         (VEX_W_0F11_P_2): Likewise.
 252         (VEX_W_0F11_P_3): Likewise.
 253         (VEX_W_0F12_P_0_M_0): Likewise.
 254         (VEX_W_0F12_P_0_M_1): Likewise.
 255         (VEX_W_0F12_P_1): Likewise.
 256         (VEX_W_0F12_P_2): Likewise.
 257         (VEX_W_0F12_P_3): Likewise.
 258         (VEX_W_0F13_M_0): Likewise.
 259         (VEX_W_0F14): Likewise.
 260         (VEX_W_0F15): Likewise.
 261         (VEX_W_0F16_P_0_M_0): Likewise.
 262         (VEX_W_0F16_P_0_M_1): Likewise.
 263         (VEX_W_0F16_P_1): Likewise.
 264         (VEX_W_0F16_P_2): Likewise.
 265         (VEX_W_0F17_M_0): Likewise.
 266         (VEX_W_0F28): Likewise.
 267         (VEX_W_0F29): Likewise.
 268         (VEX_W_0F2B_M_0): Likewise.
 269         (VEX_W_0F2E_P_0): Likewise.
 270         (VEX_W_0F2E_P_2): Likewise.
 271         (VEX_W_0F2F_P_0): Likewise.
 272         (VEX_W_0F2F_P_2): Likewise.
 273         (VEX_W_0F50_M_0): Likewise.
 274         (VEX_W_0F51_P_0): Likewise.
 275         (VEX_W_0F51_P_1): Likewise.
 276         (VEX_W_0F51_P_2): Likewise.
 277         (VEX_W_0F51_P_3): Likewise.
 278         (VEX_W_0F52_P_0): Likewise.
 279         (VEX_W_0F52_P_1): Likewise.
 280         (VEX_W_0F53_P_0): Likewise.
 281         (VEX_W_0F53_P_1): Likewise.
 282         (VEX_W_0F58_P_0): Likewise.
 283         (VEX_W_0F58_P_1): Likewise.
 284         (VEX_W_0F58_P_2): Likewise.
 285         (VEX_W_0F58_P_3): Likewise.
 286         (VEX_W_0F59_P_0): Likewise.
 287         (VEX_W_0F59_P_1): Likewise.
 288         (VEX_W_0F59_P_2): Likewise.
 289         (VEX_W_0F59_P_3): Likewise.
 290         (VEX_W_0F5A_P_0): Likewise.
 291         (VEX_W_0F5A_P_1): Likewise.
 292         (VEX_W_0F5A_P_3): Likewise.
 293         (VEX_W_0F5B_P_0): Likewise.
 294         (VEX_W_0F5B_P_1): Likewise.
 295         (VEX_W_0F5B_P_2): Likewise.
 296         (VEX_W_0F5C_P_0): Likewise.
 297         (VEX_W_0F5C_P_1): Likewise.
 298         (VEX_W_0F5C_P_2): Likewise.
 299         (VEX_W_0F5C_P_3): Likewise.
 300         (VEX_W_0F5D_P_0): Likewise.
 301         (VEX_W_0F5D_P_1): Likewise.
 302         (VEX_W_0F5D_P_2): Likewise.
 303         (VEX_W_0F5D_P_3): Likewise.
 304         (VEX_W_0F5E_P_0): Likewise.
 305         (VEX_W_0F5E_P_1): Likewise.
 306         (VEX_W_0F5E_P_2): Likewise.
 307         (VEX_W_0F5E_P_3): Likewise.
 308         (VEX_W_0F5F_P_0): Likewise.
 309         (VEX_W_0F5F_P_1): Likewise.
 310         (VEX_W_0F5F_P_2): Likewise.
 311         (VEX_W_0F5F_P_3): Likewise.
 312         (VEX_W_0F60_P_2): Likewise.
 313         (VEX_W_0F61_P_2): Likewise.
 314         (VEX_W_0F62_P_2): Likewise.
 315         (VEX_W_0F63_P_2): Likewise.
 316         (VEX_W_0F64_P_2): Likewise.
 317         (VEX_W_0F65_P_2): Likewise.
 318         (VEX_W_0F66_P_2): Likewise.
 319         (VEX_W_0F67_P_2): Likewise.
 320         (VEX_W_0F68_P_2): Likewise.
 321         (VEX_W_0F69_P_2): Likewise.
 322         (VEX_W_0F6A_P_2): Likewise.
 323         (VEX_W_0F6B_P_2): Likewise.
 324         (VEX_W_0F6C_P_2): Likewise.
 325         (VEX_W_0F6D_P_2): Likewise.
 326         (VEX_W_0F6F_P_1): Likewise.
 327         (VEX_W_0F6F_P_2): Likewise.
 328         (VEX_W_0F70_P_1): Likewise.
 329         (VEX_W_0F70_P_2): Likewise.
 330         (VEX_W_0F70_P_3): Likewise.
 331         (VEX_W_0F71_R_2_P_2): Likewise.
 332         (VEX_W_0F71_R_4_P_2): Likewise.
 333         (VEX_W_0F71_R_6_P_2): Likewise.
 334         (VEX_W_0F72_R_2_P_2): Likewise.
 335         (VEX_W_0F72_R_4_P_2): Likewise.
 336         (VEX_W_0F72_R_6_P_2): Likewise.
 337         (VEX_W_0F73_R_2_P_2): Likewise.
 338         (VEX_W_0F73_R_3_P_2): Likewise.
 339         (VEX_W_0F73_R_6_P_2): Likewise.
 340         (VEX_W_0F73_R_7_P_2): Likewise.
 341         (VEX_W_0F74_P_2): Likewise.
 342         (VEX_W_0F75_P_2): Likewise.
 343         (VEX_W_0F76_P_2): Likewise.
 344         (VEX_W_0F77_P_0): Likewise.
 345         (VEX_W_0F7C_P_2): Likewise.
 346         (VEX_W_0F7C_P_3): Likewise.
 347         (VEX_W_0F7D_P_2): Likewise.
 348         (VEX_W_0F7D_P_3): Likewise.
 349         (VEX_W_0F7E_P_1): Likewise.
 350         (VEX_W_0F7F_P_1): Likewise.
 351         (VEX_W_0F7F_P_2): Likewise.
 352         (VEX_W_0FAE_R_2_M_0): Likewise.
 353         (VEX_W_0FAE_R_3_M_0): Likewise.
 354         (VEX_W_0FC2_P_0): Likewise.
 355         (VEX_W_0FC2_P_1): Likewise.
 356         (VEX_W_0FC2_P_2): Likewise.
 357         (VEX_W_0FC2_P_3): Likewise.
 358         (VEX_W_0FD0_P_2): Likewise.
 359         (VEX_W_0FD0_P_3): Likewise.
 360         (VEX_W_0FD1_P_2): Likewise.
 361         (VEX_W_0FD2_P_2): Likewise.
 362         (VEX_W_0FD3_P_2): Likewise.
 363         (VEX_W_0FD4_P_2): Likewise.
 364         (VEX_W_0FD5_P_2): Likewise.
 365         (VEX_W_0FD6_P_2): Likewise.
 366         (VEX_W_0FD7_P_2_M_1): Likewise.
 367         (VEX_W_0FD8_P_2): Likewise.
 368         (VEX_W_0FD9_P_2): Likewise.
 369         (VEX_W_0FDA_P_2): Likewise.
 370         (VEX_W_0FDB_P_2): Likewise.
 371         (VEX_W_0FDC_P_2): Likewise.
 372         (VEX_W_0FDD_P_2): Likewise.
 373         (VEX_W_0FDE_P_2): Likewise.
 374         (VEX_W_0FDF_P_2): Likewise.
 375         (VEX_W_0FE0_P_2): Likewise.
 376         (VEX_W_0FE1_P_2): Likewise.
 377         (VEX_W_0FE2_P_2): Likewise.
 378         (VEX_W_0FE3_P_2): Likewise.
 379         (VEX_W_0FE4_P_2): Likewise.
 380         (VEX_W_0FE5_P_2): Likewise.
 381         (VEX_W_0FE6_P_1): Likewise.
 382         (VEX_W_0FE6_P_2): Likewise.
 383         (VEX_W_0FE6_P_3): Likewise.
 384         (VEX_W_0FE7_P_2_M_0): Likewise.
 385         (VEX_W_0FE8_P_2): Likewise.
 386         (VEX_W_0FE9_P_2): Likewise.
 387         (VEX_W_0FEA_P_2): Likewise.
 388         (VEX_W_0FEB_P_2): Likewise.
 389         (VEX_W_0FEC_P_2): Likewise.
 390         (VEX_W_0FED_P_2): Likewise.
 391         (VEX_W_0FEE_P_2): Likewise.
 392         (VEX_W_0FEF_P_2): Likewise.
 393         (VEX_W_0FF0_P_3_M_0): Likewise.
 394         (VEX_W_0FF1_P_2): Likewise.
 395         (VEX_W_0FF2_P_2): Likewise.
 396         (VEX_W_0FF3_P_2): Likewise.
 397         (VEX_W_0FF4_P_2): Likewise.
 398         (VEX_W_0FF5_P_2): Likewise.
 399         (VEX_W_0FF6_P_2): Likewise.
 400         (VEX_W_0FF7_P_2): Likewise.
 401         (VEX_W_0FF8_P_2): Likewise.
 402         (VEX_W_0FF9_P_2): Likewise.
 403         (VEX_W_0FFA_P_2): Likewise.
 404         (VEX_W_0FFB_P_2): Likewise.
 405         (VEX_W_0FFC_P_2): Likewise.
 406         (VEX_W_0FFD_P_2): Likewise.
 407         (VEX_W_0FFE_P_2): Likewise.
 408         (VEX_W_0F3800_P_2): Likewise.
 409         (VEX_W_0F3801_P_2): Likewise.
 410         (VEX_W_0F3802_P_2): Likewise.
 411         (VEX_W_0F3803_P_2): Likewise.
 412         (VEX_W_0F3804_P_2): Likewise.
 413         (VEX_W_0F3805_P_2): Likewise.
 414         (VEX_W_0F3806_P_2): Likewise.
 415         (VEX_W_0F3807_P_2): Likewise.
 416         (VEX_W_0F3808_P_2): Likewise.
 417         (VEX_W_0F3809_P_2): Likewise.
 418         (VEX_W_0F380A_P_2): Likewise.
 419         (VEX_W_0F380B_P_2): Likewise.
 420         (VEX_W_0F3817_P_2): Likewise.
 421         (VEX_W_0F381C_P_2): Likewise.
 422         (VEX_W_0F381D_P_2): Likewise.
 423         (VEX_W_0F381E_P_2): Likewise.
 424         (VEX_W_0F3820_P_2): Likewise.
 425         (VEX_W_0F3821_P_2): Likewise.
 426         (VEX_W_0F3822_P_2): Likewise.
 427         (VEX_W_0F3823_P_2): Likewise.
 428         (VEX_W_0F3824_P_2): Likewise.
 429         (VEX_W_0F3825_P_2): Likewise.
 430         (VEX_W_0F3828_P_2): Likewise.
 431         (VEX_W_0F3829_P_2): Likewise.
 432         (VEX_W_0F382A_P_2_M_0): Likewise.
 433         (VEX_W_0F382B_P_2): Likewise.
 434         (VEX_W_0F3830_P_2): Likewise.
 435         (VEX_W_0F3831_P_2): Likewise.
 436         (VEX_W_0F3832_P_2): Likewise.
 437         (VEX_W_0F3833_P_2): Likewise.
 438         (VEX_W_0F3834_P_2): Likewise.
 439         (VEX_W_0F3835_P_2): Likewise.
 440         (VEX_W_0F3837_P_2): Likewise.
 441         (VEX_W_0F3838_P_2): Likewise.
 442         (VEX_W_0F3839_P_2): Likewise.
 443         (VEX_W_0F383A_P_2): Likewise.
 444         (VEX_W_0F383B_P_2): Likewise.
 445         (VEX_W_0F383C_P_2): Likewise.
 446         (VEX_W_0F383D_P_2): Likewise.
 447         (VEX_W_0F383E_P_2): Likewise.
 448         (VEX_W_0F383F_P_2): Likewise.
 449         (VEX_W_0F3840_P_2): Likewise.
 450         (VEX_W_0F3841_P_2): Likewise.
 451         (VEX_W_0F38DB_P_2): Likewise.
 452         (VEX_W_0F3A08_P_2): Likewise.
 453         (VEX_W_0F3A09_P_2): Likewise.
 454         (VEX_W_0F3A0A_P_2): Likewise.
 455         (VEX_W_0F3A0B_P_2): Likewise.
 456         (VEX_W_0F3A0C_P_2): Likewise.
 457         (VEX_W_0F3A0D_P_2): Likewise.
 458         (VEX_W_0F3A0E_P_2): Likewise.
 459         (VEX_W_0F3A0F_P_2): Likewise.
 460         (VEX_W_0F3A21_P_2): Likewise.
 461         (VEX_W_0F3A40_P_2): Likewise.
 462         (VEX_W_0F3A41_P_2): Likewise.
 463         (VEX_W_0F3A42_P_2): Likewise.
 464         (VEX_W_0F3A62_P_2): Likewise.
 465         (VEX_W_0F3A63_P_2): Likewise.
 466         (VEX_W_0F3ADF_P_2): Likewise.
 467         (VEX_LEN_0F77_P_0): New.
 468         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 469         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 470         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 471         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 472         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 473         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 474         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 475         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 476         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 477         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 478         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 479         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 480         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 481         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 482         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 483         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 484         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 485         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 486         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 487         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 488         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 489         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 490         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 491         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 492         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 493         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 494         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 495         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 496         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 497         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 498         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 499         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 500         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 501         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 502         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 503         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 504         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 505         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 506         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 507         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 508         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 509         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 510         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 511         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 512         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 513         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 514         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 515         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 516         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 517         (vex_table): Update VEX 0F28 and 0F29 entries.
 518         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 519         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 520         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 521         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 522         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 523         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 524         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 525         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 526         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 527         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 528         VEX_LEN_0F3A0B_P_2 entries.
 529         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 530         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 531         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 532         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 533         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 534         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 535         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 536         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 537         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 538         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 539         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 540         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 541         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 542         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 543         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 544         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 545         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 546         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 547         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 548         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 549         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 550         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 551         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 552         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 553         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 554         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 555         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 556         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 557         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 558         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 559         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 560         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 561         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 562         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 563         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 564         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 565         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 566         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 567         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 568         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 569         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 570         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 571         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 572         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 573         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 574         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 575         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 576         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 577         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 578         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 579         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 580         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 581         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 582         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 583         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 584         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 585         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 586         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 587         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 588         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 589         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 590         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 591         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 592         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 593         VEX_W_0F3ADF_P_2 entries.
 594         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 595         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 596         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 597
 598 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 599
 600         * i386-opc.tbl (VexWIG): New.
 601         Replace VexW=3 with VexWIG.
 602
 603 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 604
 605         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 606         * i386-tbl.h: Regenerated.
 607
 608 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 609
 610         PR gas/23665
 611         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 612         VEX_LEN_0FD6_P_2 entries.
 613         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 614         * i386-tbl.h: Regenerated.
 615
 616 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 617
 618         PR gas/23642
 619         * i386-opc.h (VEXWIG): New.
 620         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 621         * i386-tbl.h: Regenerated.
 622
 623 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         PR binutils/23655
 626         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 627         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 628         * i386-dis.c (EXxEVexR64): New.
 629         (evex_rounding_64_mode): Likewise.
 630         (OP_Rounding): Handle evex_rounding_64_mode.
 631
 632 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 633
 634         PR binutils/23655
 635         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 636         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 637         * i386-dis.c (Edqa): New.
 638         (dqa_mode): Likewise.
 639         (intel_operand_size): Handle dqa_mode as m_mode.
 640         (OP_E_register): Handle dqa_mode as dq_mode.
 641         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 642
 643 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 644
 645         * i386-dis.c (OP_E_memory): Reformat.
 646
 647 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 648
 649         * i386-opc.tbl (crc32): Fold byte and word forms.
 650         * i386-tbl.h: Re-generate.
 651
 652 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 653
 654         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 655         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 656         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 657         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 658         * i386-tbl.h: Regenerated.
 659
 660 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 661
 662         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 663         meaningless.
 664         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 665         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 666         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 667         * i386-tbl.h: Re-generate.
 668
 669 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 670
 671         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 672         AVX512_4VNNIW insns.
 673         * i386-tbl.h: Re-generate.
 674
 675 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 676
 677         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 678         meaningless.
 679         * i386-tbl.h: Re-generate.
 680
 681 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 682
 683         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 684         meaningless.
 685         * i386-tbl.h: Re-generate.
 686
 687 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 688
 689         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 690         meaningless.
 691         * i386-tbl.h: Re-generate.
 692
 693 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 694
 695         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 696         meaningless.
 697         * i386-tbl.h: Re-generate.
 698
 699 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 700
 701         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 702         meaningless.
 703         * i386-tbl.h: Re-generate.
 704
 705 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 708         * i386-tbl.h: Re-generate.
 709
 710 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 711
 712         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 713         * i386-tbl.h: Re-generate.
 714
 715 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 716
 717         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 718         meaningless.
 719         * i386-tbl.h: Re-generate.
 720
 721 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 722
 723         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 724         meaningless.
 725         * i386-tbl.h: Re-generate.
 726
 727 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 728
 729         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 730         * i386-tbl.h: Re-generate.
 731
 732 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 733
 734         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 735         * i386-tbl.h: Re-generate.
 736
 737 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 738
 739         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 740         * i386-tbl.h: Re-generate.
 741
 742 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 743
 744         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 745         meaningless.
 746         * i386-tbl.h: Re-generate.
 747
 748 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 749
 750         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 751         meaningless.
 752         * i386-tbl.h: Re-generate.
 753
 754 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 755
 756         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 757         meaningless.
 758         * i386-tbl.h: Re-generate.
 759
 760 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 761
 762         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 763         * i386-tbl.h: Re-generate.
 764
 765 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 766
 767         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 768         * i386-tbl.h: Re-generate.
 769
 770 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 771
 772         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 773         * i386-tbl.h: Re-generate.
 774
 775 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 776
 777         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 778         (vpbroadcastw, rdpid): Drop NoRex64.
 779         * i386-tbl.h: Re-generate.
 780
 781 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 782
 783         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 784         store templates, adding D.
 785         * i386-tbl.h: Re-generate.
 786
 787 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 788
 789         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 790         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 791         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 792         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 793         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 794         Fold load and store templates where possible, adding D. Drop
 795         IgnoreSize where it was pointlessly present. Drop redundant
 796         *word.
 797         * i386-tbl.h: Re-generate.
 798
 799 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 802         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 803         (intel_operand_size): Handle v_bndmk_mode.
 804         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 805
 806 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 807
 808         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 809
 810 2018-08-31  Kito Cheng  <kito@andestech.com>
 811
 812         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 813         compressed floating point instructions.
 814
 815 2018-08-30  Kito Cheng  <kito@andestech.com>
 816
 817         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 818         riscv_opcode.xlen_requirement.
 819         * riscv-opc.c (riscv_opcodes): Update for struct change.
 820
 821 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 822
 823         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 824         psr (PWRPSR) instruction.
 825
 826 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 827
 828         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 829
 830 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 831
 832         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 833
 834 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 835
 836         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 837         loongson3a as an alias of gs464 for compatibility.
 838         * mips-opc.c (mips_opcodes): Change Comments.
 839
 840 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 841
 842         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 843         option.
 844         (print_mips_disassembler_options): Document -M loongson-ext.
 845         * mips-opc.c (LEXT2): New macro.
 846         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 847
 848 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 849
 850          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 851          descriptors.
 852          (parse_mips_ase_option): Handle -M loongson-ext option.
 853          (print_mips_disassembler_options): Document -M loongson-ext.
 854          * mips-opc.c (IL3A): Delete.
 855          * mips-opc.c (LEXT): New macro.
 856          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 857          instructions.
 858
 859 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 860
 861         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 862         descriptors.
 863         (parse_mips_ase_option): Handle -M loongson-cam option.
 864         (print_mips_disassembler_options): Document -M loongson-cam.
 865         * mips-opc.c (LCAM): New macro.
 866         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 867         instructions.
 868
 869 2018-08-21  Alan Modra  <amodra@gmail.com>
 870
 871         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 872         (skip_optional_operands): Count optional operands, and update
 873         ppc_optional_operand_value call.
 874         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 875         (extract_vlensi): Likewise.
 876         (extract_fxm): Return default value for missing optional operand.
 877         (extract_ls, extract_raq, extract_tbr): Likewise.
 878         (insert_sxl, extract_sxl): New functions.
 879         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 880         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 881         flag and extra entry.
 882         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 883         extract_sxl.
 884
 885 2018-08-20  Alan Modra  <amodra@gmail.com>
 886
 887         * sh-opc.h (MASK): Simplify.
 888
 889 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 890
 891         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 892         BM_RESERVED0 or BM_RESERVED1
 893         (bm_rel_decode, bm_n_bytes): Ditto.
 894
 895 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 896
 897         * s12z.h: Delete.
 898
 899 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 900
 901         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 902         address with the addr32 prefix and without base nor index
 903         registers.
 904
 905 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 906
 907         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 908         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 909         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 910         (cpu_flags): Add CpuCMOV and CpuFXSR.
 911         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 912         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 913         * i386-init.h: Regenerated.
 914         * i386-tbl.h: Likewise.
 915
 916 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 917
 918         * arc-regs.h: Update auxiliary registers.
 919
 920 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 921
 922         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 923         (RegIP, RegIZ): Define.
 924         * i386-reg.tbl: Adjust comments.
 925         (rip): Use Qword instead of BaseIndex. Use RegIP.
 926         (eip): Use Dword instead of BaseIndex. Use RegIP.
 927         (riz): Add Qword. Use RegIZ.
 928         (eiz): Add Dword. Use RegIZ.
 929         * i386-tbl.h: Re-generate.
 930
 931 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 932
 933         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 934         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 935         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 936         * i386-tbl.h: Re-generate.
 937
 938 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 939
 940         * i386-gen.c (operand_types): Remove Mem field.
 941         * i386-opc.h (union i386_operand_type): Remove mem field.
 942         * i386-init.h, i386-tbl.h: Re-generate.
 943
 944 2018-08-01  Alan Modra  <amodra@gmail.com>
 945
 946         * po/POTFILES.in: Regenerate.
 947
 948 2018-07-31  Nick Clifton  <nickc@redhat.com>
 949
 950         * po/sv.po: Updated Swedish translation.
 951
 952 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 955         * i386-init.h, i386-tbl.h: Re-generate.
 956
 957 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 958
 959         * i386-opc.h (ZEROING_MASKING) Rename to ...
 960         (DYNAMIC_MASKING): ... this. Adjust comment.
 961         * i386-opc.tbl (MaskingMorZ): Define.
 962         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 963         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 964         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 965         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 966         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 967         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 968         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 969         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 970         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 971
 972 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 973
 974         * i386-opc.tbl: Use element rather than vector size for AVX512*
 975         scatter/gather insns.
 976         * i386-tbl.h: Re-generate.
 977
 978 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 979
 980         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 981         (cpu_flags): Drop CpuVREX.
 982         * i386-opc.h (CpuVREX): Delete.
 983         (union i386_cpu_flags): Remove cpuvrex.
 984         * i386-init.h, i386-tbl.h: Re-generate.
 985
 986 2018-07-30  Jim Wilson  <jimw@sifive.com>
 987
 988         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 989         fields.
 990         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 991
 992 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 993
 994         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 995         * Makefile.in: Regenerated.
 996         * configure.ac: Add C-SKY.
 997         * configure: Regenerated.
 998         * csky-dis.c: New file.
 999         * csky-opc.h: New file.
1000         * disassemble.c (ARCH_csky): Define.
1001         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1002         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1003
1004 2018-07-27  Alan Modra  <amodra@gmail.com>
1005
1006         * ppc-opc.c (insert_sprbat): Correct function parameter and
1007         return type.
1008         (extract_sprbat): Likewise, variable too.
1009
1010 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1011             Alan Modra  <amodra@gmail.com>
1012
1013         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1014         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1015         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1016         support disjointed BAT.
1017         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1018         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1019         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1020
1021 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1022             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1023
1024         * i386-gen.c (adjust_broadcast_modifier): New function.
1025         (process_i386_opcode_modifier): Add an argument for operands.
1026         Adjust the Broadcast value based on operands.
1027         (output_i386_opcode): Pass operand_types to
1028         process_i386_opcode_modifier.
1029         (process_i386_opcodes): Pass NULL as operands to
1030         process_i386_opcode_modifier.
1031         * i386-opc.h (BYTE_BROADCAST): New.
1032         (WORD_BROADCAST): Likewise.
1033         (DWORD_BROADCAST): Likewise.
1034         (QWORD_BROADCAST): Likewise.
1035         (i386_opcode_modifier): Expand broadcast to 3 bits.
1036         * i386-tbl.h: Regenerated.
1037
1038 2018-07-24  Alan Modra  <amodra@gmail.com>
1039
1040         PR 23430
1041         * or1k-desc.h: Regenerate.
1042
1043 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1044
1045         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1046         vcvtusi2ss, and vcvtusi2sd.
1047         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1048         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1049         * i386-tbl.h: Re-generate.
1050
1051 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1052
1053         * arc-opc.c (extract_w6): Fix extending the sign.
1054
1055 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1056
1057         * arc-tbl.h (vewt): Allow it for ARC EM family.
1058
1059 2018-07-23  Alan Modra  <amodra@gmail.com>
1060
1061         PR 23419
1062         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1063         opcode variants for mtspr/mfspr encodings.
1064
1065 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1066             Maciej W. Rozycki  <macro@mips.com>
1067
1068         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1069         loongson3a descriptors.
1070         (parse_mips_ase_option): Handle -M loongson-mmi option.
1071         (print_mips_disassembler_options): Document -M loongson-mmi.
1072         * mips-opc.c (LMMI): New macro.
1073         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1074         instructions.
1075
1076 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1077
1078         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1079         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1080         IgnoreSize and [XYZ]MMword where applicable.
1081         * i386-tbl.h: Re-generate.
1082
1083 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1084
1085         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1086         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1087         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1088         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1089         * i386-tbl.h: Re-generate.
1090
1091 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1092
1093         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1094         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1095         VPCLMULQDQ templates into their respective AVX512VL counterparts
1096         where possible, using Disp8ShiftVL and CheckRegSize instead of
1097         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1098         * i386-tbl.h: Re-generate.
1099
1100 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1101
1102         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1103         AVX512VL counterparts where possible, using Disp8ShiftVL and
1104         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1105         IgnoreSize) as appropriate.
1106         * i386-tbl.h: Re-generate.
1107
1108 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1109
1110         * i386-opc.tbl: Fold AVX512BW templates into their respective
1111         AVX512VL counterparts where possible, using Disp8ShiftVL and
1112         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1113         IgnoreSize) as appropriate.
1114         * i386-tbl.h: Re-generate.
1115
1116 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1117
1118         * i386-opc.tbl: Fold AVX512CD templates into their respective
1119         AVX512VL counterparts where possible, using Disp8ShiftVL and
1120         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1121         IgnoreSize) as appropriate.
1122         * i386-tbl.h: Re-generate.
1123
1124 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1125
1126         * i386-opc.h (DISP8_SHIFT_VL): New.
1127         * i386-opc.tbl (Disp8ShiftVL):  Define.
1128         (various): Fold AVX512VL templates into their respective
1129         AVX512F counterparts where possible, using Disp8ShiftVL and
1130         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1131         IgnoreSize) as appropriate.
1132         * i386-tbl.h: Re-generate.
1133
1134 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1135
1136         * Makefile.am: Change dependencies and rule for
1137         $(srcdir)/i386-init.h.
1138         * Makefile.in: Re-generate.
1139         * i386-gen.c (process_i386_opcodes): New local variable
1140         "marker". Drop opening of input file. Recognize marker and line
1141         number directives.
1142         * i386-opc.tbl (OPCODE_I386_H): Define.
1143         (i386-opc.h): Include it.
1144         (None): Undefine.
1145
1146 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1147
1148         PR gas/23418
1149         * i386-opc.h (Byte): Update comments.
1150         (Word): Likewise.
1151         (Dword): Likewise.
1152         (Fword): Likewise.
1153         (Qword): Likewise.
1154         (Tbyte): Likewise.
1155         (Xmmword): Likewise.
1156         (Ymmword): Likewise.
1157         (Zmmword): Likewise.
1158         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1159         vcvttps2uqq.
1160         * i386-tbl.h: Regenerated.
1161
1162 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1163
1164         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1165         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1166         * aarch64-asm-2.c: Regenerate.
1167         * aarch64-dis-2.c: Regenerate.
1168         * aarch64-opc-2.c: Regenerate.
1169
1170 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1171
1172         PR binutils/23192
1173         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1174         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1175         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1176         sqdmulh, sqrdmulh): Use Em16.
1177
1178 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1179
1180         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1181         csdb together with them.
1182         (thumb32_opcodes): Likewise.
1183
1184 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1185
1186         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1187         requiring 32-bit registers as operands 2 and 3. Improve
1188         comments.
1189         (mwait, mwaitx): Fold templates. Improve comments.
1190         OPERAND_TYPE_INOUTPORTREG.
1191         * i386-tbl.h: Re-generate.
1192
1193 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1194
1195         * i386-gen.c (operand_type_init): Remove
1196         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1197         OPERAND_TYPE_INOUTPORTREG.
1198         * i386-init.h: Re-generate.
1199
1200 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1201
1202         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1203         (wrssq, wrussq): Add Qword.
1204         * i386-tbl.h: Re-generate.
1205
1206 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1207
1208         * i386-opc.h: Rename OTMax to OTNum.
1209         (OTNumOfUints): Adjust calculation.
1210         (OTUnused): Directly alias to OTNum.
1211
1212 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1213
1214         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1215         `reg_xys'.
1216         (lea_reg_xys): Likewise.
1217         (print_insn_loop_primitive): Rename `reg' local variable to
1218         `reg_dxy'.
1219
1220 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1221
1222         PR binutils/23242
1223         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1224
1225 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1226
1227         PR binutils/23369
1228         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1229         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1230
1231 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1232
1233         PR tdep/8282
1234         * mips-dis.c (mips_option_arg_t): New enumeration.
1235         (mips_options): New variable.
1236         (disassembler_options_mips): New function.
1237         (print_mips_disassembler_options): Reimplement in terms of
1238         `disassembler_options_mips'.
1239         * arm-dis.c (disassembler_options_arm): Adapt to using the
1240         `disasm_options_and_args_t' structure.
1241         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1242         * s390-dis.c (disassembler_options_s390): Likewise.
1243
1244 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1245
1246         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1247         expected result.
1248         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1249         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1250         * testsuite/ld-arm/tls-longplt.d: Likewise.
1251
1252 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1253
1254         PR binutils/23192
1255         * aarch64-asm-2.c: Regenerate.
1256         * aarch64-dis-2.c: Likewise.
1257         * aarch64-opc-2.c: Likewise.
1258         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1259         * aarch64-opc.c (operand_general_constraint_met_p,
1260         aarch64_print_operand): Likewise.
1261         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1262         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1263         fmlal2, fmlsl2.
1264         (AARCH64_OPERANDS): Add Em2.
1265
1266 2018-06-26  Nick Clifton  <nickc@redhat.com>
1267
1268         * po/uk.po: Updated Ukranian translation.
1269         * po/de.po: Updated German translation.
1270         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1271
1272 2018-06-26  Nick Clifton  <nickc@redhat.com>
1273
1274         * nfp-dis.c: Fix spelling mistake.
1275
1276 2018-06-24  Nick Clifton  <nickc@redhat.com>
1277
1278         * configure: Regenerate.
1279         * po/opcodes.pot: Regenerate.
1280
1281 2018-06-24  Nick Clifton  <nickc@redhat.com>
1282
1283         2.31 branch created.
1284
1285 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1286
1287         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1288         * aarch64-asm-2.c: Regenerate.
1289         * aarch64-dis-2.c: Likewise.
1290
1291 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1292
1293         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1294         `-M ginv' option description.
1295
1296 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1297
1298         PR gas/23305
1299         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1300         la and lla.
1301
1302 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1303
1304         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1305         * configure.ac: Remove AC_PREREQ.
1306         * Makefile.in: Re-generate.
1307         * aclocal.m4: Re-generate.
1308         * configure: Re-generate.
1309
1310 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1311
1312         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1313         mips64r6 descriptors.
1314         (parse_mips_ase_option): Handle -Mginv option.
1315         (print_mips_disassembler_options): Document -Mginv.
1316         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1317         (GINV): New macro.
1318         (mips_opcodes): Define ginvi and ginvt.
1319
1320 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1321             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1322
1323         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1324         * mips-opc.c (CRC, CRC64): New macros.
1325         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1326         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1327         crc32cd for CRC64.
1328
1329 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1330
1331         PR 20319
1332         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1333         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1334
1335 2018-06-06  Alan Modra  <amodra@gmail.com>
1336
1337         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1338         setjmp.  Move init for some other vars later too.
1339
1340 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1341
1342         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1343         (dis_private): Add new fields for property section tracking.
1344         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1345         (xtensa_instruction_fits): New functions.
1346         (fetch_data): Bump minimal fetch size to 4.
1347         (print_insn_xtensa): Make struct dis_private static.
1348         Load and prepare property table on section change.
1349         Don't disassemble literals. Don't disassemble instructions that
1350         cross property table boundaries.
1351
1352 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1353
1354         * configure: Regenerated.
1355
1356 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1357
1358         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1359         * i386-tbl.h: Re-generate.
1360
1361 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1362
1363         * i386-opc.tbl (sldt, str): Add NoRex64.
1364         * i386-tbl.h: Re-generate.
1365
1366 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1367
1368         * i386-opc.tbl (invpcid): Add Oword.
1369         * i386-tbl.h: Re-generate.
1370
1371 2018-06-01  Alan Modra  <amodra@gmail.com>
1372
1373         * sysdep.h (_bfd_error_handler): Don't declare.
1374         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1375         * rl78-decode.opc: Likewise.
1376         * msp430-decode.c: Regenerate.
1377         * rl78-decode.c: Regenerate.
1378
1379 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1380
1381         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1382         * i386-init.h : Regenerated.
1383
1384 2018-05-25  Alan Modra  <amodra@gmail.com>
1385
1386         * Makefile.in: Regenerate.
1387         * po/POTFILES.in: Regenerate.
1388
1389 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1390
1391         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1392         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1393         (insert_bab, extract_bab, insert_btab, extract_btab,
1394         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1395         (BAT, BBA VBA RBS XB6S): Delete macros.
1396         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1397         (BB, BD, RBX, XC6): Update for new macros.
1398         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1399         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1400         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1401         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1402
1403 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1404
1405         * Makefile.am: Add support for s12z architecture.
1406         * configure.ac: Likewise.
1407         * disassemble.c: Likewise.
1408         * disassemble.h: Likewise.
1409         * Makefile.in: Regenerate.
1410         * configure: Regenerate.
1411         * s12z-dis.c: New file.
1412         * s12z.h: New file.
1413
1414 2018-05-18  Alan Modra  <amodra@gmail.com>
1415
1416         * nfp-dis.c: Don't #include libbfd.h.
1417         (init_nfp3200_priv): Use bfd_get_section_contents.
1418         (nit_nfp6000_mecsr_sec): Likewise.
1419
1420 2018-05-17  Nick Clifton  <nickc@redhat.com>
1421
1422         * po/zh_CN.po: Updated simplified Chinese translation.
1423
1424 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1425
1426         PR binutils/23109
1427         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1428         * aarch64-dis-2.c: Regenerate.
1429
1430 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1431
1432         PR binutils/21446
1433         * aarch64-asm.c (opintl.h): Include.
1434         (aarch64_ins_sysreg): Enforce read/write constraints.
1435         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1436         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1437         (F_REG_READ, F_REG_WRITE): New.
1438         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1439         AARCH64_OPND_SYSREG.
1440         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1441         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1442         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1443         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1444         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1445         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1446         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1447         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1448         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1449         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1450         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1451         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1452         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1453         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1454         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1455         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1456         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1457
1458 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1459
1460         PR binutils/21446
1461         * aarch64-dis.c (no_notes: New.
1462         (parse_aarch64_dis_option): Support notes.
1463         (aarch64_decode_insn, print_operands): Likewise.
1464         (print_aarch64_disassembler_options): Document notes.
1465         * aarch64-opc.c (aarch64_print_operand): Support notes.
1466
1467 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1468
1469         PR binutils/21446
1470         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1471         and take error struct.
1472         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1473         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1474         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1475         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1476         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1477         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1478         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1479         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1480         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1481         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1482         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1483         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1484         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1485         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1486         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1487         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1488         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1489         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1490         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1491         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1492         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1493         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1494         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1495         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1496         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1497         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1498         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1499         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1500         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1501         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1502         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1503         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1504         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1505         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1506         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1507         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1508         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1509         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1510         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1511         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1512         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1513         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1514         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1515         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1516         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1517         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1518         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1519         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1520         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1521         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1522         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1523         (determine_disassembling_preference, aarch64_decode_insn,
1524         print_insn_aarch64_word, print_insn_data): Take errors struct.
1525         (print_insn_aarch64): Use errors.
1526         * aarch64-asm-2.c: Regenerate.
1527         * aarch64-dis-2.c: Regenerate.
1528         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1529         boolean in aarch64_insert_operan.
1530         (print_operand_extractor): Likewise.
1531         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1532
1533 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1534
1535         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1536
1537 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1538
1539         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1540
1541 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1542
1543         * cr16-opc.c (cr16_instruction): Comment typo fix.
1544         * hppa-dis.c (print_insn_hppa): Likewise.
1545
1546 2018-05-08  Jim Wilson  <jimw@sifive.com>
1547
1548         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1549         (match_c_slli64, match_srxi_as_c_srxi): New.
1550         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1551         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1552         <c.slli, c.srli, c.srai>: Use match_s_slli.
1553         <c.slli64, c.srli64, c.srai64>: New.
1554
1555 2018-05-08  Alan Modra  <amodra@gmail.com>
1556
1557         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1558         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1559         partition opcode space for index lookup.
1560
1561 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1562
1563         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1564         <insn_length>: ...with this.  Update usage.
1565         Remove duplicate call to *info->memory_error_func.
1566
1567 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1568             H.J. Lu  <hongjiu.lu@intel.com>
1569
1570         * i386-dis.c (Gva): New.
1571         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1572         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1573         (prefix_table): New instructions (see prefix above).
1574         (mod_table): New instructions (see prefix above).
1575         (OP_G): Handle va_mode.
1576         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1577         CPU_MOVDIR64B_FLAGS.
1578         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1579         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1580         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1581         * i386-opc.tbl: Add movidir{i,64b}.
1582         * i386-init.h: Regenerated.
1583         * i386-tbl.h: Likewise.
1584
1585 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1586
1587         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1588         AddrPrefixOpReg.
1589         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1590         (AddrPrefixOpReg): This.
1591         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1592         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1593
1594 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1595
1596         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1597         (vle_num_opcodes): Likewise.
1598         (spe2_num_opcodes): Likewise.
1599         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1600         initialization loop.
1601         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1602         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1603         only once.
1604
1605 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1606
1607         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1608
1609 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1610
1611         Makefile.am: Added nfp-dis.c.
1612         configure.ac: Added bfd_nfp_arch.
1613         disassemble.h: Added print_insn_nfp prototype.
1614         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1615         nfp-dis.c: New, for NFP support.
1616         po/POTFILES.in: Added nfp-dis.c to the list.
1617         Makefile.in: Regenerate.
1618         configure: Regenerate.
1619
1620 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1621
1622         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1623         templates into their base ones.
1624         * i386-tlb.h: Re-generate.
1625
1626 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1627
1628         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1629         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1630         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1631         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1632         * i386-init.h: Re-generate.
1633
1634 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1635
1636         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1637         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1638         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1639         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1640         comment.
1641         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1642         and CpuRegMask.
1643         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1644         CpuRegMask: Delete.
1645         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1646         cpuregzmm, and cpuregmask.
1647         * i386-init.h: Re-generate.
1648         * i386-tbl.h: Re-generate.
1649
1650 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1651
1652         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1653         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1654         * i386-init.h: Re-generate.
1655
1656 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1657
1658         * i386-gen.c (VexImmExt): Delete.
1659         * i386-opc.h (VexImmExt, veximmext): Delete.
1660         * i386-opc.tbl: Drop all VexImmExt uses.
1661         * i386-tlb.h: Re-generate.
1662
1663 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1664
1665         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1666         register-only forms.
1667         * i386-tlb.h: Re-generate.
1668
1669 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1670
1671         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1672
1673 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1674
1675         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1676         PREFIX_0F1C.
1677         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1678         (cpu_flags): Add CpuCLDEMOTE.
1679         * i386-init.h: Regenerate.
1680         * i386-opc.h (enum): Add CpuCLDEMOTE,
1681         (i386_cpu_flags): Add cpucldemote.
1682         * i386-opc.tbl: Add cldemote.
1683         * i386-tbl.h: Regenerate.
1684
1685 2018-04-16  Alan Modra  <amodra@gmail.com>
1686
1687         * Makefile.am: Remove sh5 and sh64 support.
1688         * configure.ac: Likewise.
1689         * disassemble.c: Likewise.
1690         * disassemble.h: Likewise.
1691         * sh-dis.c: Likewise.
1692         * sh64-dis.c: Delete.
1693         * sh64-opc.c: Delete.
1694         * sh64-opc.h: Delete.
1695         * Makefile.in: Regenerate.
1696         * configure: Regenerate.
1697         * po/POTFILES.in: Regenerate.
1698
1699 2018-04-16  Alan Modra  <amodra@gmail.com>
1700
1701         * Makefile.am: Remove w65 support.
1702         * configure.ac: Likewise.
1703         * disassemble.c: Likewise.
1704         * disassemble.h: Likewise.
1705         * w65-dis.c: Delete.
1706         * w65-opc.h: Delete.
1707         * Makefile.in: Regenerate.
1708         * configure: Regenerate.
1709         * po/POTFILES.in: Regenerate.
1710
1711 2018-04-16  Alan Modra  <amodra@gmail.com>
1712
1713         * configure.ac: Remove we32k support.
1714         * configure: Regenerate.
1715
1716 2018-04-16  Alan Modra  <amodra@gmail.com>
1717
1718         * Makefile.am: Remove m88k support.
1719         * configure.ac: Likewise.
1720         * disassemble.c: Likewise.
1721         * disassemble.h: Likewise.
1722         * m88k-dis.c: Delete.
1723         * Makefile.in: Regenerate.
1724         * configure: Regenerate.
1725         * po/POTFILES.in: Regenerate.
1726
1727 2018-04-16  Alan Modra  <amodra@gmail.com>
1728
1729         * Makefile.am: Remove i370 support.
1730         * configure.ac: Likewise.
1731         * disassemble.c: Likewise.
1732         * disassemble.h: Likewise.
1733         * i370-dis.c: Delete.
1734         * i370-opc.c: Delete.
1735         * Makefile.in: Regenerate.
1736         * configure: Regenerate.
1737         * po/POTFILES.in: Regenerate.
1738
1739 2018-04-16  Alan Modra  <amodra@gmail.com>
1740
1741         * Makefile.am: Remove h8500 support.
1742         * configure.ac: Likewise.
1743         * disassemble.c: Likewise.
1744         * disassemble.h: Likewise.
1745         * h8500-dis.c: Delete.
1746         * h8500-opc.h: Delete.
1747         * Makefile.in: Regenerate.
1748         * configure: Regenerate.
1749         * po/POTFILES.in: Regenerate.
1750
1751 2018-04-16  Alan Modra  <amodra@gmail.com>
1752
1753         * configure.ac: Remove tahoe support.
1754         * configure: Regenerate.
1755
1756 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1757
1758         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1759         umwait.
1760         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1761         64-bit mode.
1762         * i386-tbl.h: Regenerated.
1763
1764 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1765
1766         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1767         PREFIX_MOD_1_0FAE_REG_6.
1768         (va_mode): New.
1769         (OP_E_register): Use va_mode.
1770         * i386-dis-evex.h (prefix_table):
1771         New instructions (see prefixes above).
1772         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1773         (cpu_flags): Likewise.
1774         * i386-opc.h (enum): Likewise.
1775         (i386_cpu_flags): Likewise.
1776         * i386-opc.tbl: Add umonitor, umwait, tpause.
1777         * i386-init.h: Regenerate.
1778         * i386-tbl.h: Likewise.
1779
1780 2018-04-11  Alan Modra  <amodra@gmail.com>
1781
1782         * opcodes/i860-dis.c: Delete.
1783         * opcodes/i960-dis.c: Delete.
1784         * Makefile.am: Remove i860 and i960 support.
1785         * configure.ac: Likewise.
1786         * disassemble.c: Likewise.
1787         * disassemble.h: Likewise.
1788         * Makefile.in: Regenerate.
1789         * configure: Regenerate.
1790         * po/POTFILES.in: Regenerate.
1791
1792 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1793
1794         PR binutils/23025
1795         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1796         to 0.
1797         (print_insn): Clear vex instead of vex.evex.
1798
1799 2018-04-04  Nick Clifton  <nickc@redhat.com>
1800
1801         * po/es.po: Updated Spanish translation.
1802
1803 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1804
1805         * i386-gen.c (opcode_modifiers): Delete VecESize.
1806         * i386-opc.h (VecESize): Delete.
1807         (struct i386_opcode_modifier): Delete vecesize.
1808         * i386-opc.tbl: Drop VecESize.
1809         * i386-tlb.h: Re-generate.
1810
1811 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1812
1813         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1814         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1815         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1816         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1817         * i386-tlb.h: Re-generate.
1818
1819 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1820
1821         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1822         Fold AVX512 forms
1823         * i386-tlb.h: Re-generate.
1824
1825 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1826
1827         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1828         (vex_len_table): Drop Y for vcvt*2si.
1829         (putop): Replace plain 'Y' handling by abort().
1830
1831 2018-03-28  Nick Clifton  <nickc@redhat.com>
1832
1833         PR 22988
1834         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1835         instructions with only a base address register.
1836         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1837         handle AARHC64_OPND_SVE_ADDR_R.
1838         (aarch64_print_operand): Likewise.
1839         * aarch64-asm-2.c: Regenerate.
1840         * aarch64_dis-2.c: Regenerate.
1841         * aarch64-opc-2.c: Regenerate.
1842
1843 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1844
1845         * i386-opc.tbl: Drop VecESize from register only insn forms and
1846         memory forms not allowing broadcast.
1847         * i386-tlb.h: Re-generate.
1848
1849 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1850
1851         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1852         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1853         sha256*): Drop Disp<N>.
1854
1855 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1856
1857         * i386-dis.c (EbndS, bnd_swap_mode): New.
1858         (prefix_table): Use EbndS.
1859         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1860         * i386-opc.tbl (bndmov): Move misplaced Load.
1861         * i386-tlb.h: Re-generate.
1862
1863 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1864
1865         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1866         templates allowing memory operands and folded ones for register
1867         only flavors.
1868         * i386-tlb.h: Re-generate.
1869
1870 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1871
1872         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1873         256-bit templates. Drop redundant leftover Disp<N>.
1874         * i386-tlb.h: Re-generate.
1875
1876 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1877
1878         * riscv-opc.c (riscv_insn_types): New.
1879
1880 2018-03-13  Nick Clifton  <nickc@redhat.com>
1881
1882         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1883
1884 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1885
1886         * i386-opc.tbl: Add Optimize to clr.
1887         * i386-tbl.h: Regenerated.
1888
1889 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1890
1891         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1892         * i386-opc.h (OldGcc): Removed.
1893         (i386_opcode_modifier): Remove oldgcc.
1894         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1895         instructions for old (<= 2.8.1) versions of gcc.
1896         * i386-tbl.h: Regenerated.
1897
1898 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1899
1900         * i386-opc.h (EVEXDYN): New.
1901         * i386-opc.tbl: Fold various AVX512VL templates.
1902         * i386-tlb.h: Re-generate.
1903
1904 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1905
1906         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1907         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1908         vpexpandd, vpexpandq): Fold AFX512VF templates.
1909         * i386-tlb.h: Re-generate.
1910
1911 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1912
1913         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1914         Fold 128- and 256-bit VEX-encoded templates.
1915         * i386-tlb.h: Re-generate.
1916
1917 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1918
1919         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1920         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1921         vpexpandd, vpexpandq): Fold AVX512F templates.
1922         * i386-tlb.h: Re-generate.
1923
1924 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1925
1926         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1927         64-bit templates. Drop Disp<N>.
1928         * i386-tlb.h: Re-generate.
1929
1930 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1931
1932         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1933         and 256-bit templates.
1934         * i386-tlb.h: Re-generate.
1935
1936 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1937
1938         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1939         * i386-tlb.h: Re-generate.
1940
1941 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1942
1943         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1944         Drop NoAVX.
1945         * i386-tlb.h: Re-generate.
1946
1947 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1948
1949         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1950         * i386-tlb.h: Re-generate.
1951
1952 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1953
1954         * i386-gen.c (opcode_modifiers): Delete FloatD.
1955         * i386-opc.h (FloatD): Delete.
1956         (struct i386_opcode_modifier): Delete floatd.
1957         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1958         FloatD by D.
1959         * i386-tlb.h: Re-generate.
1960
1961 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1962
1963         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1964
1965 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1966
1967         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1968         * i386-tlb.h: Re-generate.
1969
1970 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1971
1972         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1973         forms.
1974         * i386-tlb.h: Re-generate.
1975
1976 2018-03-07  Alan Modra  <amodra@gmail.com>
1977
1978         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1979         bfd_arch_rs6000.
1980         * disassemble.h (print_insn_rs6000): Delete.
1981         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1982         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1983         (print_insn_rs6000): Delete.
1984
1985 2018-03-03  Alan Modra  <amodra@gmail.com>
1986
1987         * sysdep.h (opcodes_error_handler): Define.
1988         (_bfd_error_handler): Declare.
1989         * Makefile.am: Remove stray #.
1990         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1991         EDIT" comment.
1992         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1993         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1994         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1995         opcodes_error_handler to print errors.  Standardize error messages.
1996         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1997         and include opintl.h.
1998         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1999         * i386-gen.c: Standardize error messages.
2000         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2001         * Makefile.in: Regenerate.
2002         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2003         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2004         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2005         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2006         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2007         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2008         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2009         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2010         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2011         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2012         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2013         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2014         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2015
2016 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2017
2018         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2019         vpsub[bwdq] instructions.
2020         * i386-tbl.h: Regenerated.
2021
2022 2018-03-01  Alan Modra  <amodra@gmail.com>
2023
2024         * configure.ac (ALL_LINGUAS): Sort.
2025         * configure: Regenerate.
2026
2027 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2028
2029         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2030         macro by assignements.
2031
2032 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2033
2034         PR gas/22871
2035         * i386-gen.c (opcode_modifiers): Add Optimize.
2036         * i386-opc.h (Optimize): New enum.
2037         (i386_opcode_modifier): Add optimize.
2038         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2039         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2040         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2041         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2042         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2043         vpxord and vpxorq.
2044         * i386-tbl.h: Regenerated.
2045
2046 2018-02-26  Alan Modra  <amodra@gmail.com>
2047
2048         * crx-dis.c (getregliststring): Allocate a large enough buffer
2049         to silence false positive gcc8 warning.
2050
2051 2018-02-22  Shea Levy <shea@shealevy.com>
2052
2053         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2054
2055 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2056
2057         * i386-opc.tbl: Add {rex},
2058         * i386-tbl.h: Regenerated.
2059
2060 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2061
2062         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2063         (mips16_opcodes): Replace `M' with `m' for "restore".
2064
2065 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2066
2067         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2068
2069 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2070
2071         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2072         variable to `function_index'.
2073
2074 2018-02-13  Nick Clifton  <nickc@redhat.com>
2075
2076         PR 22823
2077         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2078         about truncation of printing.
2079
2080 2018-02-12  Henry Wong <henry@stuffedcow.net>
2081
2082         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2083
2084 2018-02-05  Nick Clifton  <nickc@redhat.com>
2085
2086         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2087
2088 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2089
2090         * i386-dis.c (enum): Add pconfig.
2091         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2092         (cpu_flags): Add CpuPCONFIG.
2093         * i386-opc.h (enum): Add CpuPCONFIG.
2094         (i386_cpu_flags): Add cpupconfig.
2095         * i386-opc.tbl: Add PCONFIG instruction.
2096         * i386-init.h: Regenerate.
2097         * i386-tbl.h: Likewise.
2098
2099 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2100
2101         * i386-dis.c (enum): Add PREFIX_0F09.
2102         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2103         (cpu_flags): Add CpuWBNOINVD.
2104         * i386-opc.h (enum): Add CpuWBNOINVD.
2105         (i386_cpu_flags): Add cpuwbnoinvd.
2106         * i386-opc.tbl: Add WBNOINVD instruction.
2107         * i386-init.h: Regenerate.
2108         * i386-tbl.h: Likewise.
2109
2110 2018-01-17  Jim Wilson  <jimw@sifive.com>
2111
2112         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2113
2114 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2115
2116         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2117         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2118         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2119         (cpu_flags): Add CpuIBT, CpuSHSTK.
2120         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2121         (i386_cpu_flags): Add cpuibt, cpushstk.
2122         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2123         * i386-init.h: Regenerate.
2124         * i386-tbl.h: Likewise.
2125
2126 2018-01-16  Nick Clifton  <nickc@redhat.com>
2127
2128         * po/pt_BR.po: Updated Brazilian Portugese translation.
2129         * po/de.po: Updated German translation.
2130
2131 2018-01-15  Jim Wilson  <jimw@sifive.com>
2132
2133         * riscv-opc.c (match_c_nop): New.
2134         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2135
2136 2018-01-15  Nick Clifton  <nickc@redhat.com>
2137
2138         * po/uk.po: Updated Ukranian translation.
2139
2140 2018-01-13  Nick Clifton  <nickc@redhat.com>
2141
2142         * po/opcodes.pot: Regenerated.
2143
2144 2018-01-13  Nick Clifton  <nickc@redhat.com>
2145
2146         * configure: Regenerate.
2147
2148 2018-01-13  Nick Clifton  <nickc@redhat.com>
2149
2150         2.30 branch created.
2151
2152 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2153
2154         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2155         * i386-tbl.h: Regenerate.
2156
2157 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2158
2159         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2160         * i386-tbl.h: Re-generate.
2161
2162 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2163
2164         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2165         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2166         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2167         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2168         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2169         Disp8MemShift of AVX512VL forms.
2170         * i386-tbl.h: Re-generate.
2171
2172 2018-01-09  Jim Wilson  <jimw@sifive.com>
2173
2174         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2175         then the hi_addr value is zero.
2176
2177 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2178
2179         * arm-dis.c (arm_opcodes): Add csdb.
2180         (thumb32_opcodes): Add csdb.
2181
2182 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2183
2184         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2185         * aarch64-asm-2.c: Regenerate.
2186         * aarch64-dis-2.c: Regenerate.
2187         * aarch64-opc-2.c: Regenerate.
2188
2189 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2190
2191         PR gas/22681
2192         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2193         Remove AVX512 vmovd with 64-bit operands.
2194         * i386-tbl.h: Regenerated.
2195
2196 2018-01-05  Jim Wilson  <jimw@sifive.com>
2197
2198         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2199         jalr.
2200
2201 2018-01-03  Alan Modra  <amodra@gmail.com>
2202
2203         Update year range in copyright notice of all files.
2204
2205 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2206
2207         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2208         and OPERAND_TYPE_REGZMM entries.
2209
2210 For older changes see ChangeLog-2017
2211 \f
2212 Copyright (C) 2018 Free Software Foundation, Inc.
2213
2214 Copying and distribution of this file, with or without modification,
2215 are permitted in any medium without royalty provided the copyright
2216 notice and this notice are preserved.
2217
2218 Local Variables:
2219 mode: change-log
2220 left-margin: 8
2221 fill-column: 74
2222 version-control: never
2223 End: