opcodes/ChangeLog

   1 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
   4         meaningless.
   5         * i386-tbl.h: Re-generate.
   6
   7 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
  10         * i386-tbl.h: Re-generate.
  11
  12 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  13
  14         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
  15         * i386-tbl.h: Re-generate.
  16
  17 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  18
  19         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
  20         meaningless.
  21         * i386-tbl.h: Re-generate.
  22
  23 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
  26         meaningless.
  27         * i386-tbl.h: Re-generate.
  28
  29 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  30
  31         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
  32         * i386-tbl.h: Re-generate.
  33
  34 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
  37         * i386-tbl.h: Re-generate.
  38
  39 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
  42         * i386-tbl.h: Re-generate.
  43
  44 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  45
  46         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
  47         meaningless.
  48         * i386-tbl.h: Re-generate.
  49
  50 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  51
  52         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
  53         meaningless.
  54         * i386-tbl.h: Re-generate.
  55
  56 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  57
  58         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
  59         meaningless.
  60         * i386-tbl.h: Re-generate.
  61
  62 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  63
  64         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
  65         * i386-tbl.h: Re-generate.
  66
  67 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
  70         * i386-tbl.h: Re-generate.
  71
  72 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
  75         * i386-tbl.h: Re-generate.
  76
  77 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  78
  79         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
  80         (vpbroadcastw, rdpid): Drop NoRex64.
  81         * i386-tbl.h: Re-generate.
  82
  83 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  84
  85         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
  86         store templates, adding D.
  87         * i386-tbl.h: Re-generate.
  88
  89 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
  92         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
  93         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
  94         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
  95         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
  96         Fold load and store templates where possible, adding D. Drop
  97         IgnoreSize where it was pointlessly present. Drop redundant
  98         *word.
  99         * i386-tbl.h: Re-generate.
 100
 101 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 102
 103         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 104         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 105         (intel_operand_size): Handle v_bndmk_mode.
 106         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 107
 108 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 109
 110         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 111
 112 2018-08-31  Kito Cheng  <kito@andestech.com>
 113
 114         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 115         compressed floating point instructions.
 116
 117 2018-08-30  Kito Cheng  <kito@andestech.com>
 118
 119         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 120         riscv_opcode.xlen_requirement.
 121         * riscv-opc.c (riscv_opcodes): Update for struct change.
 122
 123 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 124
 125         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 126         psr (PWRPSR) instruction.
 127
 128 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 129
 130         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 131
 132 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 133
 134         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 135
 136 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 137
 138         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 139         loongson3a as an alias of gs464 for compatibility.
 140         * mips-opc.c (mips_opcodes): Change Comments.
 141
 142 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 143
 144         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 145         option.
 146         (print_mips_disassembler_options): Document -M loongson-ext.
 147         * mips-opc.c (LEXT2): New macro.
 148         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 149
 150 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 151
 152          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 153          descriptors.
 154          (parse_mips_ase_option): Handle -M loongson-ext option.
 155          (print_mips_disassembler_options): Document -M loongson-ext.
 156          * mips-opc.c (IL3A): Delete.
 157          * mips-opc.c (LEXT): New macro.
 158          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 159          instructions.
 160
 161 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 162
 163         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 164         descriptors.
 165         (parse_mips_ase_option): Handle -M loongson-cam option.
 166         (print_mips_disassembler_options): Document -M loongson-cam.
 167         * mips-opc.c (LCAM): New macro.
 168         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 169         instructions.
 170
 171 2018-08-21  Alan Modra  <amodra@gmail.com>
 172
 173         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 174         (skip_optional_operands): Count optional operands, and update
 175         ppc_optional_operand_value call.
 176         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 177         (extract_vlensi): Likewise.
 178         (extract_fxm): Return default value for missing optional operand.
 179         (extract_ls, extract_raq, extract_tbr): Likewise.
 180         (insert_sxl, extract_sxl): New functions.
 181         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 182         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 183         flag and extra entry.
 184         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 185         extract_sxl.
 186
 187 2018-08-20  Alan Modra  <amodra@gmail.com>
 188
 189         * sh-opc.h (MASK): Simplify.
 190
 191 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 192
 193         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 194         BM_RESERVED0 or BM_RESERVED1
 195         (bm_rel_decode, bm_n_bytes): Ditto.
 196
 197 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 198
 199         * s12z.h: Delete.
 200
 201 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 202
 203         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 204         address with the addr32 prefix and without base nor index
 205         registers.
 206
 207 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 208
 209         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 210         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 211         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 212         (cpu_flags): Add CpuCMOV and CpuFXSR.
 213         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 214         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 215         * i386-init.h: Regenerated.
 216         * i386-tbl.h: Likewise.
 217
 218 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 219
 220         * arc-regs.h: Update auxiliary registers.
 221
 222 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 223
 224         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 225         (RegIP, RegIZ): Define.
 226         * i386-reg.tbl: Adjust comments.
 227         (rip): Use Qword instead of BaseIndex. Use RegIP.
 228         (eip): Use Dword instead of BaseIndex. Use RegIP.
 229         (riz): Add Qword. Use RegIZ.
 230         (eiz): Add Dword. Use RegIZ.
 231         * i386-tbl.h: Re-generate.
 232
 233 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 236         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 237         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 238         * i386-tbl.h: Re-generate.
 239
 240 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 241
 242         * i386-gen.c (operand_types): Remove Mem field.
 243         * i386-opc.h (union i386_operand_type): Remove mem field.
 244         * i386-init.h, i386-tbl.h: Re-generate.
 245
 246 2018-08-01  Alan Modra  <amodra@gmail.com>
 247
 248         * po/POTFILES.in: Regenerate.
 249
 250 2018-07-31  Nick Clifton  <nickc@redhat.com>
 251
 252         * po/sv.po: Updated Swedish translation.
 253
 254 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 255
 256         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 257         * i386-init.h, i386-tbl.h: Re-generate.
 258
 259 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 260
 261         * i386-opc.h (ZEROING_MASKING) Rename to ...
 262         (DYNAMIC_MASKING): ... this. Adjust comment.
 263         * i386-opc.tbl (MaskingMorZ): Define.
 264         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 265         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 266         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 267         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 268         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 269         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 270         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 271         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 272         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 273
 274 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 275
 276         * i386-opc.tbl: Use element rather than vector size for AVX512*
 277         scatter/gather insns.
 278         * i386-tbl.h: Re-generate.
 279
 280 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 283         (cpu_flags): Drop CpuVREX.
 284         * i386-opc.h (CpuVREX): Delete.
 285         (union i386_cpu_flags): Remove cpuvrex.
 286         * i386-init.h, i386-tbl.h: Re-generate.
 287
 288 2018-07-30  Jim Wilson  <jimw@sifive.com>
 289
 290         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 291         fields.
 292         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 293
 294 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 295
 296         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 297         * Makefile.in: Regenerated.
 298         * configure.ac: Add C-SKY.
 299         * configure: Regenerated.
 300         * csky-dis.c: New file.
 301         * csky-opc.h: New file.
 302         * disassemble.c (ARCH_csky): Define.
 303         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 304         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 305
 306 2018-07-27  Alan Modra  <amodra@gmail.com>
 307
 308         * ppc-opc.c (insert_sprbat): Correct function parameter and
 309         return type.
 310         (extract_sprbat): Likewise, variable too.
 311
 312 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 313             Alan Modra  <amodra@gmail.com>
 314
 315         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 316         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 317         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 318         support disjointed BAT.
 319         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 320         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 321         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 322
 323 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 324             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 325
 326         * i386-gen.c (adjust_broadcast_modifier): New function.
 327         (process_i386_opcode_modifier): Add an argument for operands.
 328         Adjust the Broadcast value based on operands.
 329         (output_i386_opcode): Pass operand_types to
 330         process_i386_opcode_modifier.
 331         (process_i386_opcodes): Pass NULL as operands to
 332         process_i386_opcode_modifier.
 333         * i386-opc.h (BYTE_BROADCAST): New.
 334         (WORD_BROADCAST): Likewise.
 335         (DWORD_BROADCAST): Likewise.
 336         (QWORD_BROADCAST): Likewise.
 337         (i386_opcode_modifier): Expand broadcast to 3 bits.
 338         * i386-tbl.h: Regenerated.
 339
 340 2018-07-24  Alan Modra  <amodra@gmail.com>
 341
 342         PR 23430
 343         * or1k-desc.h: Regenerate.
 344
 345 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 346
 347         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 348         vcvtusi2ss, and vcvtusi2sd.
 349         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 350         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 351         * i386-tbl.h: Re-generate.
 352
 353 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 354
 355         * arc-opc.c (extract_w6): Fix extending the sign.
 356
 357 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 358
 359         * arc-tbl.h (vewt): Allow it for ARC EM family.
 360
 361 2018-07-23  Alan Modra  <amodra@gmail.com>
 362
 363         PR 23419
 364         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 365         opcode variants for mtspr/mfspr encodings.
 366
 367 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 368             Maciej W. Rozycki  <macro@mips.com>
 369
 370         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 371         loongson3a descriptors.
 372         (parse_mips_ase_option): Handle -M loongson-mmi option.
 373         (print_mips_disassembler_options): Document -M loongson-mmi.
 374         * mips-opc.c (LMMI): New macro.
 375         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 376         instructions.
 377
 378 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 379
 380         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 381         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 382         IgnoreSize and [XYZ]MMword where applicable.
 383         * i386-tbl.h: Re-generate.
 384
 385 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 386
 387         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 388         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 389         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 390         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 391         * i386-tbl.h: Re-generate.
 392
 393 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 394
 395         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 396         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 397         VPCLMULQDQ templates into their respective AVX512VL counterparts
 398         where possible, using Disp8ShiftVL and CheckRegSize instead of
 399         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 400         * i386-tbl.h: Re-generate.
 401
 402 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 403
 404         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 405         AVX512VL counterparts where possible, using Disp8ShiftVL and
 406         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 407         IgnoreSize) as appropriate.
 408         * i386-tbl.h: Re-generate.
 409
 410 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 411
 412         * i386-opc.tbl: Fold AVX512BW templates into their respective
 413         AVX512VL counterparts where possible, using Disp8ShiftVL and
 414         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 415         IgnoreSize) as appropriate.
 416         * i386-tbl.h: Re-generate.
 417
 418 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 419
 420         * i386-opc.tbl: Fold AVX512CD templates into their respective
 421         AVX512VL counterparts where possible, using Disp8ShiftVL and
 422         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 423         IgnoreSize) as appropriate.
 424         * i386-tbl.h: Re-generate.
 425
 426 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 427
 428         * i386-opc.h (DISP8_SHIFT_VL): New.
 429         * i386-opc.tbl (Disp8ShiftVL):  Define.
 430         (various): Fold AVX512VL templates into their respective
 431         AVX512F counterparts where possible, using Disp8ShiftVL and
 432         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 433         IgnoreSize) as appropriate.
 434         * i386-tbl.h: Re-generate.
 435
 436 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 437
 438         * Makefile.am: Change dependencies and rule for
 439         $(srcdir)/i386-init.h.
 440         * Makefile.in: Re-generate.
 441         * i386-gen.c (process_i386_opcodes): New local variable
 442         "marker". Drop opening of input file. Recognize marker and line
 443         number directives.
 444         * i386-opc.tbl (OPCODE_I386_H): Define.
 445         (i386-opc.h): Include it.
 446         (None): Undefine.
 447
 448 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 449
 450         PR gas/23418
 451         * i386-opc.h (Byte): Update comments.
 452         (Word): Likewise.
 453         (Dword): Likewise.
 454         (Fword): Likewise.
 455         (Qword): Likewise.
 456         (Tbyte): Likewise.
 457         (Xmmword): Likewise.
 458         (Ymmword): Likewise.
 459         (Zmmword): Likewise.
 460         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 461         vcvttps2uqq.
 462         * i386-tbl.h: Regenerated.
 463
 464 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 465
 466         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 467         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 468         * aarch64-asm-2.c: Regenerate.
 469         * aarch64-dis-2.c: Regenerate.
 470         * aarch64-opc-2.c: Regenerate.
 471
 472 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 473
 474         PR binutils/23192
 475         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 476         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 477         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 478         sqdmulh, sqrdmulh): Use Em16.
 479
 480 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 481
 482         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 483         csdb together with them.
 484         (thumb32_opcodes): Likewise.
 485
 486 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 487
 488         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 489         requiring 32-bit registers as operands 2 and 3. Improve
 490         comments.
 491         (mwait, mwaitx): Fold templates. Improve comments.
 492         OPERAND_TYPE_INOUTPORTREG.
 493         * i386-tbl.h: Re-generate.
 494
 495 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-gen.c (operand_type_init): Remove
 498         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 499         OPERAND_TYPE_INOUTPORTREG.
 500         * i386-init.h: Re-generate.
 501
 502 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 503
 504         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 505         (wrssq, wrussq): Add Qword.
 506         * i386-tbl.h: Re-generate.
 507
 508 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 509
 510         * i386-opc.h: Rename OTMax to OTNum.
 511         (OTNumOfUints): Adjust calculation.
 512         (OTUnused): Directly alias to OTNum.
 513
 514 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 515
 516         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 517         `reg_xys'.
 518         (lea_reg_xys): Likewise.
 519         (print_insn_loop_primitive): Rename `reg' local variable to
 520         `reg_dxy'.
 521
 522 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 523
 524         PR binutils/23242
 525         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 526
 527 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 528
 529         PR binutils/23369
 530         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 531         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 532
 533 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 534
 535         PR tdep/8282
 536         * mips-dis.c (mips_option_arg_t): New enumeration.
 537         (mips_options): New variable.
 538         (disassembler_options_mips): New function.
 539         (print_mips_disassembler_options): Reimplement in terms of
 540         `disassembler_options_mips'.
 541         * arm-dis.c (disassembler_options_arm): Adapt to using the
 542         `disasm_options_and_args_t' structure.
 543         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 544         * s390-dis.c (disassembler_options_s390): Likewise.
 545
 546 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 547
 548         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 549         expected result.
 550         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 551         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 552         * testsuite/ld-arm/tls-longplt.d: Likewise.
 553
 554 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 555
 556         PR binutils/23192
 557         * aarch64-asm-2.c: Regenerate.
 558         * aarch64-dis-2.c: Likewise.
 559         * aarch64-opc-2.c: Likewise.
 560         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 561         * aarch64-opc.c (operand_general_constraint_met_p,
 562         aarch64_print_operand): Likewise.
 563         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 564         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 565         fmlal2, fmlsl2.
 566         (AARCH64_OPERANDS): Add Em2.
 567
 568 2018-06-26  Nick Clifton  <nickc@redhat.com>
 569
 570         * po/uk.po: Updated Ukranian translation.
 571         * po/de.po: Updated German translation.
 572         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 573
 574 2018-06-26  Nick Clifton  <nickc@redhat.com>
 575
 576         * nfp-dis.c: Fix spelling mistake.
 577
 578 2018-06-24  Nick Clifton  <nickc@redhat.com>
 579
 580         * configure: Regenerate.
 581         * po/opcodes.pot: Regenerate.
 582
 583 2018-06-24  Nick Clifton  <nickc@redhat.com>
 584
 585         2.31 branch created.
 586
 587 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 588
 589         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 590         * aarch64-asm-2.c: Regenerate.
 591         * aarch64-dis-2.c: Likewise.
 592
 593 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 594
 595         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 596         `-M ginv' option description.
 597
 598 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 599
 600         PR gas/23305
 601         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 602         la and lla.
 603
 604 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 605
 606         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 607         * configure.ac: Remove AC_PREREQ.
 608         * Makefile.in: Re-generate.
 609         * aclocal.m4: Re-generate.
 610         * configure: Re-generate.
 611
 612 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 613
 614         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 615         mips64r6 descriptors.
 616         (parse_mips_ase_option): Handle -Mginv option.
 617         (print_mips_disassembler_options): Document -Mginv.
 618         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 619         (GINV): New macro.
 620         (mips_opcodes): Define ginvi and ginvt.
 621
 622 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 623             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 624
 625         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 626         * mips-opc.c (CRC, CRC64): New macros.
 627         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 628         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 629         crc32cd for CRC64.
 630
 631 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 632
 633         PR 20319
 634         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 635         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 636
 637 2018-06-06  Alan Modra  <amodra@gmail.com>
 638
 639         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 640         setjmp.  Move init for some other vars later too.
 641
 642 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 643
 644         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 645         (dis_private): Add new fields for property section tracking.
 646         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 647         (xtensa_instruction_fits): New functions.
 648         (fetch_data): Bump minimal fetch size to 4.
 649         (print_insn_xtensa): Make struct dis_private static.
 650         Load and prepare property table on section change.
 651         Don't disassemble literals. Don't disassemble instructions that
 652         cross property table boundaries.
 653
 654 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 655
 656         * configure: Regenerated.
 657
 658 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 659
 660         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 661         * i386-tbl.h: Re-generate.
 662
 663 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 664
 665         * i386-opc.tbl (sldt, str): Add NoRex64.
 666         * i386-tbl.h: Re-generate.
 667
 668 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 669
 670         * i386-opc.tbl (invpcid): Add Oword.
 671         * i386-tbl.h: Re-generate.
 672
 673 2018-06-01  Alan Modra  <amodra@gmail.com>
 674
 675         * sysdep.h (_bfd_error_handler): Don't declare.
 676         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 677         * rl78-decode.opc: Likewise.
 678         * msp430-decode.c: Regenerate.
 679         * rl78-decode.c: Regenerate.
 680
 681 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 682
 683         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 684         * i386-init.h : Regenerated.
 685
 686 2018-05-25  Alan Modra  <amodra@gmail.com>
 687
 688         * Makefile.in: Regenerate.
 689         * po/POTFILES.in: Regenerate.
 690
 691 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 692
 693         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 694         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 695         (insert_bab, extract_bab, insert_btab, extract_btab,
 696         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 697         (BAT, BBA VBA RBS XB6S): Delete macros.
 698         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 699         (BB, BD, RBX, XC6): Update for new macros.
 700         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 701         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 702         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 703         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 704
 705 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 706
 707         * Makefile.am: Add support for s12z architecture.
 708         * configure.ac: Likewise.
 709         * disassemble.c: Likewise.
 710         * disassemble.h: Likewise.
 711         * Makefile.in: Regenerate.
 712         * configure: Regenerate.
 713         * s12z-dis.c: New file.
 714         * s12z.h: New file.
 715
 716 2018-05-18  Alan Modra  <amodra@gmail.com>
 717
 718         * nfp-dis.c: Don't #include libbfd.h.
 719         (init_nfp3200_priv): Use bfd_get_section_contents.
 720         (nit_nfp6000_mecsr_sec): Likewise.
 721
 722 2018-05-17  Nick Clifton  <nickc@redhat.com>
 723
 724         * po/zh_CN.po: Updated simplified Chinese translation.
 725
 726 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 727
 728         PR binutils/23109
 729         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 730         * aarch64-dis-2.c: Regenerate.
 731
 732 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 733
 734         PR binutils/21446
 735         * aarch64-asm.c (opintl.h): Include.
 736         (aarch64_ins_sysreg): Enforce read/write constraints.
 737         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 738         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 739         (F_REG_READ, F_REG_WRITE): New.
 740         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 741         AARCH64_OPND_SYSREG.
 742         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 743         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 744         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 745         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 746         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 747         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 748         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 749         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 750         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 751         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 752         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 753         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 754         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 755         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 756         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 757         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 758         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 759
 760 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 761
 762         PR binutils/21446
 763         * aarch64-dis.c (no_notes: New.
 764         (parse_aarch64_dis_option): Support notes.
 765         (aarch64_decode_insn, print_operands): Likewise.
 766         (print_aarch64_disassembler_options): Document notes.
 767         * aarch64-opc.c (aarch64_print_operand): Support notes.
 768
 769 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 770
 771         PR binutils/21446
 772         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 773         and take error struct.
 774         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 775         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 776         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 777         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 778         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 779         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 780         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 781         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 782         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 783         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 784         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 785         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 786         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 787         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 788         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 789         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 790         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 791         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 792         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 793         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 794         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 795         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 796         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 797         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 798         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 799         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 800         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 801         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 802         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 803         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 804         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 805         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 806         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 807         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 808         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 809         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 810         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 811         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 812         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 813         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 814         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 815         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 816         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 817         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 818         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 819         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 820         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 821         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 822         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 823         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 824         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 825         (determine_disassembling_preference, aarch64_decode_insn,
 826         print_insn_aarch64_word, print_insn_data): Take errors struct.
 827         (print_insn_aarch64): Use errors.
 828         * aarch64-asm-2.c: Regenerate.
 829         * aarch64-dis-2.c: Regenerate.
 830         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 831         boolean in aarch64_insert_operan.
 832         (print_operand_extractor): Likewise.
 833         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 834
 835 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 836
 837         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 838
 839 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 840
 841         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 842
 843 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 844
 845         * cr16-opc.c (cr16_instruction): Comment typo fix.
 846         * hppa-dis.c (print_insn_hppa): Likewise.
 847
 848 2018-05-08  Jim Wilson  <jimw@sifive.com>
 849
 850         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 851         (match_c_slli64, match_srxi_as_c_srxi): New.
 852         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 853         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 854         <c.slli, c.srli, c.srai>: Use match_s_slli.
 855         <c.slli64, c.srli64, c.srai64>: New.
 856
 857 2018-05-08  Alan Modra  <amodra@gmail.com>
 858
 859         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 860         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 861         partition opcode space for index lookup.
 862
 863 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 864
 865         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 866         <insn_length>: ...with this.  Update usage.
 867         Remove duplicate call to *info->memory_error_func.
 868
 869 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 870             H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         * i386-dis.c (Gva): New.
 873         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 874         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 875         (prefix_table): New instructions (see prefix above).
 876         (mod_table): New instructions (see prefix above).
 877         (OP_G): Handle va_mode.
 878         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 879         CPU_MOVDIR64B_FLAGS.
 880         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 881         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 882         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 883         * i386-opc.tbl: Add movidir{i,64b}.
 884         * i386-init.h: Regenerated.
 885         * i386-tbl.h: Likewise.
 886
 887 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 888
 889         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 890         AddrPrefixOpReg.
 891         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 892         (AddrPrefixOpReg): This.
 893         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 894         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 895
 896 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 897
 898         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 899         (vle_num_opcodes): Likewise.
 900         (spe2_num_opcodes): Likewise.
 901         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 902         initialization loop.
 903         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 904         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 905         only once.
 906
 907 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 908
 909         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 910
 911 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 912
 913         Makefile.am: Added nfp-dis.c.
 914         configure.ac: Added bfd_nfp_arch.
 915         disassemble.h: Added print_insn_nfp prototype.
 916         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 917         nfp-dis.c: New, for NFP support.
 918         po/POTFILES.in: Added nfp-dis.c to the list.
 919         Makefile.in: Regenerate.
 920         configure: Regenerate.
 921
 922 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 923
 924         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 925         templates into their base ones.
 926         * i386-tlb.h: Re-generate.
 927
 928 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 929
 930         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 931         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 932         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 933         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 934         * i386-init.h: Re-generate.
 935
 936 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 937
 938         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 939         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 940         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 941         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 942         comment.
 943         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 944         and CpuRegMask.
 945         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 946         CpuRegMask: Delete.
 947         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 948         cpuregzmm, and cpuregmask.
 949         * i386-init.h: Re-generate.
 950         * i386-tbl.h: Re-generate.
 951
 952 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 955         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 956         * i386-init.h: Re-generate.
 957
 958 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 959
 960         * i386-gen.c (VexImmExt): Delete.
 961         * i386-opc.h (VexImmExt, veximmext): Delete.
 962         * i386-opc.tbl: Drop all VexImmExt uses.
 963         * i386-tlb.h: Re-generate.
 964
 965 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 966
 967         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 968         register-only forms.
 969         * i386-tlb.h: Re-generate.
 970
 971 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 972
 973         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 974
 975 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 976
 977         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 978         PREFIX_0F1C.
 979         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 980         (cpu_flags): Add CpuCLDEMOTE.
 981         * i386-init.h: Regenerate.
 982         * i386-opc.h (enum): Add CpuCLDEMOTE,
 983         (i386_cpu_flags): Add cpucldemote.
 984         * i386-opc.tbl: Add cldemote.
 985         * i386-tbl.h: Regenerate.
 986
 987 2018-04-16  Alan Modra  <amodra@gmail.com>
 988
 989         * Makefile.am: Remove sh5 and sh64 support.
 990         * configure.ac: Likewise.
 991         * disassemble.c: Likewise.
 992         * disassemble.h: Likewise.
 993         * sh-dis.c: Likewise.
 994         * sh64-dis.c: Delete.
 995         * sh64-opc.c: Delete.
 996         * sh64-opc.h: Delete.
 997         * Makefile.in: Regenerate.
 998         * configure: Regenerate.
 999         * po/POTFILES.in: Regenerate.
1000
1001 2018-04-16  Alan Modra  <amodra@gmail.com>
1002
1003         * Makefile.am: Remove w65 support.
1004         * configure.ac: Likewise.
1005         * disassemble.c: Likewise.
1006         * disassemble.h: Likewise.
1007         * w65-dis.c: Delete.
1008         * w65-opc.h: Delete.
1009         * Makefile.in: Regenerate.
1010         * configure: Regenerate.
1011         * po/POTFILES.in: Regenerate.
1012
1013 2018-04-16  Alan Modra  <amodra@gmail.com>
1014
1015         * configure.ac: Remove we32k support.
1016         * configure: Regenerate.
1017
1018 2018-04-16  Alan Modra  <amodra@gmail.com>
1019
1020         * Makefile.am: Remove m88k support.
1021         * configure.ac: Likewise.
1022         * disassemble.c: Likewise.
1023         * disassemble.h: Likewise.
1024         * m88k-dis.c: Delete.
1025         * Makefile.in: Regenerate.
1026         * configure: Regenerate.
1027         * po/POTFILES.in: Regenerate.
1028
1029 2018-04-16  Alan Modra  <amodra@gmail.com>
1030
1031         * Makefile.am: Remove i370 support.
1032         * configure.ac: Likewise.
1033         * disassemble.c: Likewise.
1034         * disassemble.h: Likewise.
1035         * i370-dis.c: Delete.
1036         * i370-opc.c: Delete.
1037         * Makefile.in: Regenerate.
1038         * configure: Regenerate.
1039         * po/POTFILES.in: Regenerate.
1040
1041 2018-04-16  Alan Modra  <amodra@gmail.com>
1042
1043         * Makefile.am: Remove h8500 support.
1044         * configure.ac: Likewise.
1045         * disassemble.c: Likewise.
1046         * disassemble.h: Likewise.
1047         * h8500-dis.c: Delete.
1048         * h8500-opc.h: Delete.
1049         * Makefile.in: Regenerate.
1050         * configure: Regenerate.
1051         * po/POTFILES.in: Regenerate.
1052
1053 2018-04-16  Alan Modra  <amodra@gmail.com>
1054
1055         * configure.ac: Remove tahoe support.
1056         * configure: Regenerate.
1057
1058 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1059
1060         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1061         umwait.
1062         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1063         64-bit mode.
1064         * i386-tbl.h: Regenerated.
1065
1066 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1067
1068         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1069         PREFIX_MOD_1_0FAE_REG_6.
1070         (va_mode): New.
1071         (OP_E_register): Use va_mode.
1072         * i386-dis-evex.h (prefix_table):
1073         New instructions (see prefixes above).
1074         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1075         (cpu_flags): Likewise.
1076         * i386-opc.h (enum): Likewise.
1077         (i386_cpu_flags): Likewise.
1078         * i386-opc.tbl: Add umonitor, umwait, tpause.
1079         * i386-init.h: Regenerate.
1080         * i386-tbl.h: Likewise.
1081
1082 2018-04-11  Alan Modra  <amodra@gmail.com>
1083
1084         * opcodes/i860-dis.c: Delete.
1085         * opcodes/i960-dis.c: Delete.
1086         * Makefile.am: Remove i860 and i960 support.
1087         * configure.ac: Likewise.
1088         * disassemble.c: Likewise.
1089         * disassemble.h: Likewise.
1090         * Makefile.in: Regenerate.
1091         * configure: Regenerate.
1092         * po/POTFILES.in: Regenerate.
1093
1094 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1095
1096         PR binutils/23025
1097         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1098         to 0.
1099         (print_insn): Clear vex instead of vex.evex.
1100
1101 2018-04-04  Nick Clifton  <nickc@redhat.com>
1102
1103         * po/es.po: Updated Spanish translation.
1104
1105 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1106
1107         * i386-gen.c (opcode_modifiers): Delete VecESize.
1108         * i386-opc.h (VecESize): Delete.
1109         (struct i386_opcode_modifier): Delete vecesize.
1110         * i386-opc.tbl: Drop VecESize.
1111         * i386-tlb.h: Re-generate.
1112
1113 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1114
1115         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1116         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1117         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1118         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1119         * i386-tlb.h: Re-generate.
1120
1121 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1122
1123         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1124         Fold AVX512 forms
1125         * i386-tlb.h: Re-generate.
1126
1127 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1128
1129         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1130         (vex_len_table): Drop Y for vcvt*2si.
1131         (putop): Replace plain 'Y' handling by abort().
1132
1133 2018-03-28  Nick Clifton  <nickc@redhat.com>
1134
1135         PR 22988
1136         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1137         instructions with only a base address register.
1138         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1139         handle AARHC64_OPND_SVE_ADDR_R.
1140         (aarch64_print_operand): Likewise.
1141         * aarch64-asm-2.c: Regenerate.
1142         * aarch64_dis-2.c: Regenerate.
1143         * aarch64-opc-2.c: Regenerate.
1144
1145 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1146
1147         * i386-opc.tbl: Drop VecESize from register only insn forms and
1148         memory forms not allowing broadcast.
1149         * i386-tlb.h: Re-generate.
1150
1151 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1152
1153         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1154         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1155         sha256*): Drop Disp<N>.
1156
1157 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1158
1159         * i386-dis.c (EbndS, bnd_swap_mode): New.
1160         (prefix_table): Use EbndS.
1161         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1162         * i386-opc.tbl (bndmov): Move misplaced Load.
1163         * i386-tlb.h: Re-generate.
1164
1165 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1166
1167         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1168         templates allowing memory operands and folded ones for register
1169         only flavors.
1170         * i386-tlb.h: Re-generate.
1171
1172 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1173
1174         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1175         256-bit templates. Drop redundant leftover Disp<N>.
1176         * i386-tlb.h: Re-generate.
1177
1178 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1179
1180         * riscv-opc.c (riscv_insn_types): New.
1181
1182 2018-03-13  Nick Clifton  <nickc@redhat.com>
1183
1184         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1185
1186 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1187
1188         * i386-opc.tbl: Add Optimize to clr.
1189         * i386-tbl.h: Regenerated.
1190
1191 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1192
1193         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1194         * i386-opc.h (OldGcc): Removed.
1195         (i386_opcode_modifier): Remove oldgcc.
1196         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1197         instructions for old (<= 2.8.1) versions of gcc.
1198         * i386-tbl.h: Regenerated.
1199
1200 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1201
1202         * i386-opc.h (EVEXDYN): New.
1203         * i386-opc.tbl: Fold various AVX512VL templates.
1204         * i386-tlb.h: Re-generate.
1205
1206 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1207
1208         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1209         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1210         vpexpandd, vpexpandq): Fold AFX512VF templates.
1211         * i386-tlb.h: Re-generate.
1212
1213 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1214
1215         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1216         Fold 128- and 256-bit VEX-encoded templates.
1217         * i386-tlb.h: Re-generate.
1218
1219 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1220
1221         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1222         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1223         vpexpandd, vpexpandq): Fold AVX512F templates.
1224         * i386-tlb.h: Re-generate.
1225
1226 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1227
1228         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1229         64-bit templates. Drop Disp<N>.
1230         * i386-tlb.h: Re-generate.
1231
1232 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1233
1234         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1235         and 256-bit templates.
1236         * i386-tlb.h: Re-generate.
1237
1238 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1239
1240         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1241         * i386-tlb.h: Re-generate.
1242
1243 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1244
1245         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1246         Drop NoAVX.
1247         * i386-tlb.h: Re-generate.
1248
1249 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1250
1251         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1252         * i386-tlb.h: Re-generate.
1253
1254 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1255
1256         * i386-gen.c (opcode_modifiers): Delete FloatD.
1257         * i386-opc.h (FloatD): Delete.
1258         (struct i386_opcode_modifier): Delete floatd.
1259         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1260         FloatD by D.
1261         * i386-tlb.h: Re-generate.
1262
1263 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1264
1265         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1266
1267 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1268
1269         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1270         * i386-tlb.h: Re-generate.
1271
1272 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1273
1274         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1275         forms.
1276         * i386-tlb.h: Re-generate.
1277
1278 2018-03-07  Alan Modra  <amodra@gmail.com>
1279
1280         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1281         bfd_arch_rs6000.
1282         * disassemble.h (print_insn_rs6000): Delete.
1283         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1284         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1285         (print_insn_rs6000): Delete.
1286
1287 2018-03-03  Alan Modra  <amodra@gmail.com>
1288
1289         * sysdep.h (opcodes_error_handler): Define.
1290         (_bfd_error_handler): Declare.
1291         * Makefile.am: Remove stray #.
1292         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1293         EDIT" comment.
1294         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1295         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1296         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1297         opcodes_error_handler to print errors.  Standardize error messages.
1298         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1299         and include opintl.h.
1300         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1301         * i386-gen.c: Standardize error messages.
1302         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1303         * Makefile.in: Regenerate.
1304         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1305         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1306         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1307         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1308         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1309         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1310         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1311         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1312         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1313         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1314         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1315         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1316         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1317
1318 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1319
1320         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1321         vpsub[bwdq] instructions.
1322         * i386-tbl.h: Regenerated.
1323
1324 2018-03-01  Alan Modra  <amodra@gmail.com>
1325
1326         * configure.ac (ALL_LINGUAS): Sort.
1327         * configure: Regenerate.
1328
1329 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1330
1331         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1332         macro by assignements.
1333
1334 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1335
1336         PR gas/22871
1337         * i386-gen.c (opcode_modifiers): Add Optimize.
1338         * i386-opc.h (Optimize): New enum.
1339         (i386_opcode_modifier): Add optimize.
1340         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1341         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1342         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1343         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1344         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1345         vpxord and vpxorq.
1346         * i386-tbl.h: Regenerated.
1347
1348 2018-02-26  Alan Modra  <amodra@gmail.com>
1349
1350         * crx-dis.c (getregliststring): Allocate a large enough buffer
1351         to silence false positive gcc8 warning.
1352
1353 2018-02-22  Shea Levy <shea@shealevy.com>
1354
1355         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1356
1357 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1358
1359         * i386-opc.tbl: Add {rex},
1360         * i386-tbl.h: Regenerated.
1361
1362 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1363
1364         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1365         (mips16_opcodes): Replace `M' with `m' for "restore".
1366
1367 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1368
1369         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1370
1371 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1372
1373         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1374         variable to `function_index'.
1375
1376 2018-02-13  Nick Clifton  <nickc@redhat.com>
1377
1378         PR 22823
1379         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1380         about truncation of printing.
1381
1382 2018-02-12  Henry Wong <henry@stuffedcow.net>
1383
1384         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1385
1386 2018-02-05  Nick Clifton  <nickc@redhat.com>
1387
1388         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1389
1390 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1391
1392         * i386-dis.c (enum): Add pconfig.
1393         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1394         (cpu_flags): Add CpuPCONFIG.
1395         * i386-opc.h (enum): Add CpuPCONFIG.
1396         (i386_cpu_flags): Add cpupconfig.
1397         * i386-opc.tbl: Add PCONFIG instruction.
1398         * i386-init.h: Regenerate.
1399         * i386-tbl.h: Likewise.
1400
1401 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1402
1403         * i386-dis.c (enum): Add PREFIX_0F09.
1404         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1405         (cpu_flags): Add CpuWBNOINVD.
1406         * i386-opc.h (enum): Add CpuWBNOINVD.
1407         (i386_cpu_flags): Add cpuwbnoinvd.
1408         * i386-opc.tbl: Add WBNOINVD instruction.
1409         * i386-init.h: Regenerate.
1410         * i386-tbl.h: Likewise.
1411
1412 2018-01-17  Jim Wilson  <jimw@sifive.com>
1413
1414         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1415
1416 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1417
1418         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1419         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1420         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1421         (cpu_flags): Add CpuIBT, CpuSHSTK.
1422         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1423         (i386_cpu_flags): Add cpuibt, cpushstk.
1424         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1425         * i386-init.h: Regenerate.
1426         * i386-tbl.h: Likewise.
1427
1428 2018-01-16  Nick Clifton  <nickc@redhat.com>
1429
1430         * po/pt_BR.po: Updated Brazilian Portugese translation.
1431         * po/de.po: Updated German translation.
1432
1433 2018-01-15  Jim Wilson  <jimw@sifive.com>
1434
1435         * riscv-opc.c (match_c_nop): New.
1436         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1437
1438 2018-01-15  Nick Clifton  <nickc@redhat.com>
1439
1440         * po/uk.po: Updated Ukranian translation.
1441
1442 2018-01-13  Nick Clifton  <nickc@redhat.com>
1443
1444         * po/opcodes.pot: Regenerated.
1445
1446 2018-01-13  Nick Clifton  <nickc@redhat.com>
1447
1448         * configure: Regenerate.
1449
1450 2018-01-13  Nick Clifton  <nickc@redhat.com>
1451
1452         2.30 branch created.
1453
1454 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1455
1456         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1457         * i386-tbl.h: Regenerate.
1458
1459 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1460
1461         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1462         * i386-tbl.h: Re-generate.
1463
1464 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1465
1466         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1467         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1468         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1469         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1470         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1471         Disp8MemShift of AVX512VL forms.
1472         * i386-tbl.h: Re-generate.
1473
1474 2018-01-09  Jim Wilson  <jimw@sifive.com>
1475
1476         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1477         then the hi_addr value is zero.
1478
1479 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1480
1481         * arm-dis.c (arm_opcodes): Add csdb.
1482         (thumb32_opcodes): Add csdb.
1483
1484 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1485
1486         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1487         * aarch64-asm-2.c: Regenerate.
1488         * aarch64-dis-2.c: Regenerate.
1489         * aarch64-opc-2.c: Regenerate.
1490
1491 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1492
1493         PR gas/22681
1494         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1495         Remove AVX512 vmovd with 64-bit operands.
1496         * i386-tbl.h: Regenerated.
1497
1498 2018-01-05  Jim Wilson  <jimw@sifive.com>
1499
1500         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1501         jalr.
1502
1503 2018-01-03  Alan Modra  <amodra@gmail.com>
1504
1505         Update year range in copyright notice of all files.
1506
1507 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1508
1509         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1510         and OPERAND_TYPE_REGZMM entries.
1511
1512 For older changes see ChangeLog-2017
1513 \f
1514 Copyright (C) 2018 Free Software Foundation, Inc.
1515
1516 Copying and distribution of this file, with or without modification,
1517 are permitted in any medium without royalty provided the copyright
1518 notice and this notice are preserved.
1519
1520 Local Variables:
1521 mode: change-log
1522 left-margin: 8
1523 fill-column: 74
1524 version-control: never
1525 End: