opcodes/ChangeLog

   1 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-opc.tbl (VexWIG): New.
   4         Replace VexW=3 with VexWIG.
   5
   6 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
   9         * i386-tbl.h: Regenerated.
  10
  11 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
  12
  13         PR gas/23665
  14         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
  15         VEX_LEN_0FD6_P_2 entries.
  16         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
  17         * i386-tbl.h: Regenerated.
  18
  19 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  20
  21         PR gas/23642
  22         * i386-opc.h (VEXWIG): New.
  23         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
  24         * i386-tbl.h: Regenerated.
  25
  26 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  27
  28         PR binutils/23655
  29         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
  30         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
  31         * i386-dis.c (EXxEVexR64): New.
  32         (evex_rounding_64_mode): Likewise.
  33         (OP_Rounding): Handle evex_rounding_64_mode.
  34
  35 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  36
  37         PR binutils/23655
  38         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
  39         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
  40         * i386-dis.c (Edqa): New.
  41         (dqa_mode): Likewise.
  42         (intel_operand_size): Handle dqa_mode as m_mode.
  43         (OP_E_register): Handle dqa_mode as dq_mode.
  44         (OP_E_memory): Set shift for dqa_mode based on address_mode.
  45
  46 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  47
  48         * i386-dis.c (OP_E_memory): Reformat.
  49
  50 2018-09-14  Jan Beulich  <jbeulich@suse.com>
  51
  52         * i386-opc.tbl (crc32): Fold byte and word forms.
  53         * i386-tbl.h: Re-generate.
  54
  55 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
  56
  57         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
  58         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
  59         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
  60         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
  61         * i386-tbl.h: Regenerated.
  62
  63 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  64
  65         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
  66         meaningless.
  67         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
  68         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
  69         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
  70         * i386-tbl.h: Re-generate.
  71
  72 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
  75         AVX512_4VNNIW insns.
  76         * i386-tbl.h: Re-generate.
  77
  78 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  79
  80         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
  81         meaningless.
  82         * i386-tbl.h: Re-generate.
  83
  84 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
  87         meaningless.
  88         * i386-tbl.h: Re-generate.
  89
  90 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
  93         meaningless.
  94         * i386-tbl.h: Re-generate.
  95
  96 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
  99         meaningless.
 100         * i386-tbl.h: Re-generate.
 101
 102 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 105         meaningless.
 106         * i386-tbl.h: Re-generate.
 107
 108 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 111         * i386-tbl.h: Re-generate.
 112
 113 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 116         * i386-tbl.h: Re-generate.
 117
 118 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 119
 120         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 121         meaningless.
 122         * i386-tbl.h: Re-generate.
 123
 124 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 125
 126         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 127         meaningless.
 128         * i386-tbl.h: Re-generate.
 129
 130 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 133         * i386-tbl.h: Re-generate.
 134
 135 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 138         * i386-tbl.h: Re-generate.
 139
 140 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 143         * i386-tbl.h: Re-generate.
 144
 145 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 146
 147         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 148         meaningless.
 149         * i386-tbl.h: Re-generate.
 150
 151 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 154         meaningless.
 155         * i386-tbl.h: Re-generate.
 156
 157 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 158
 159         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 160         meaningless.
 161         * i386-tbl.h: Re-generate.
 162
 163 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 164
 165         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 166         * i386-tbl.h: Re-generate.
 167
 168 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 171         * i386-tbl.h: Re-generate.
 172
 173 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 174
 175         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 176         * i386-tbl.h: Re-generate.
 177
 178 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 179
 180         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 181         (vpbroadcastw, rdpid): Drop NoRex64.
 182         * i386-tbl.h: Re-generate.
 183
 184 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 187         store templates, adding D.
 188         * i386-tbl.h: Re-generate.
 189
 190 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 191
 192         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 193         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 194         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 195         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 196         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 197         Fold load and store templates where possible, adding D. Drop
 198         IgnoreSize where it was pointlessly present. Drop redundant
 199         *word.
 200         * i386-tbl.h: Re-generate.
 201
 202 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 203
 204         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 205         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 206         (intel_operand_size): Handle v_bndmk_mode.
 207         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 208
 209 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 210
 211         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 212
 213 2018-08-31  Kito Cheng  <kito@andestech.com>
 214
 215         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 216         compressed floating point instructions.
 217
 218 2018-08-30  Kito Cheng  <kito@andestech.com>
 219
 220         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 221         riscv_opcode.xlen_requirement.
 222         * riscv-opc.c (riscv_opcodes): Update for struct change.
 223
 224 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 225
 226         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 227         psr (PWRPSR) instruction.
 228
 229 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 230
 231         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 232
 233 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 234
 235         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 236
 237 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 238
 239         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 240         loongson3a as an alias of gs464 for compatibility.
 241         * mips-opc.c (mips_opcodes): Change Comments.
 242
 243 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 244
 245         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 246         option.
 247         (print_mips_disassembler_options): Document -M loongson-ext.
 248         * mips-opc.c (LEXT2): New macro.
 249         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 250
 251 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 252
 253          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 254          descriptors.
 255          (parse_mips_ase_option): Handle -M loongson-ext option.
 256          (print_mips_disassembler_options): Document -M loongson-ext.
 257          * mips-opc.c (IL3A): Delete.
 258          * mips-opc.c (LEXT): New macro.
 259          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 260          instructions.
 261
 262 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 263
 264         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 265         descriptors.
 266         (parse_mips_ase_option): Handle -M loongson-cam option.
 267         (print_mips_disassembler_options): Document -M loongson-cam.
 268         * mips-opc.c (LCAM): New macro.
 269         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 270         instructions.
 271
 272 2018-08-21  Alan Modra  <amodra@gmail.com>
 273
 274         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 275         (skip_optional_operands): Count optional operands, and update
 276         ppc_optional_operand_value call.
 277         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 278         (extract_vlensi): Likewise.
 279         (extract_fxm): Return default value for missing optional operand.
 280         (extract_ls, extract_raq, extract_tbr): Likewise.
 281         (insert_sxl, extract_sxl): New functions.
 282         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 283         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 284         flag and extra entry.
 285         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 286         extract_sxl.
 287
 288 2018-08-20  Alan Modra  <amodra@gmail.com>
 289
 290         * sh-opc.h (MASK): Simplify.
 291
 292 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 293
 294         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 295         BM_RESERVED0 or BM_RESERVED1
 296         (bm_rel_decode, bm_n_bytes): Ditto.
 297
 298 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 299
 300         * s12z.h: Delete.
 301
 302 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 303
 304         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 305         address with the addr32 prefix and without base nor index
 306         registers.
 307
 308 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 309
 310         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 311         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 312         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 313         (cpu_flags): Add CpuCMOV and CpuFXSR.
 314         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 315         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 316         * i386-init.h: Regenerated.
 317         * i386-tbl.h: Likewise.
 318
 319 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 320
 321         * arc-regs.h: Update auxiliary registers.
 322
 323 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 324
 325         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 326         (RegIP, RegIZ): Define.
 327         * i386-reg.tbl: Adjust comments.
 328         (rip): Use Qword instead of BaseIndex. Use RegIP.
 329         (eip): Use Dword instead of BaseIndex. Use RegIP.
 330         (riz): Add Qword. Use RegIZ.
 331         (eiz): Add Dword. Use RegIZ.
 332         * i386-tbl.h: Re-generate.
 333
 334 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 335
 336         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 337         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 338         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 339         * i386-tbl.h: Re-generate.
 340
 341 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 342
 343         * i386-gen.c (operand_types): Remove Mem field.
 344         * i386-opc.h (union i386_operand_type): Remove mem field.
 345         * i386-init.h, i386-tbl.h: Re-generate.
 346
 347 2018-08-01  Alan Modra  <amodra@gmail.com>
 348
 349         * po/POTFILES.in: Regenerate.
 350
 351 2018-07-31  Nick Clifton  <nickc@redhat.com>
 352
 353         * po/sv.po: Updated Swedish translation.
 354
 355 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 356
 357         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 358         * i386-init.h, i386-tbl.h: Re-generate.
 359
 360 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 361
 362         * i386-opc.h (ZEROING_MASKING) Rename to ...
 363         (DYNAMIC_MASKING): ... this. Adjust comment.
 364         * i386-opc.tbl (MaskingMorZ): Define.
 365         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 366         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 367         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 368         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 369         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 370         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 371         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 372         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 373         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 374
 375 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 376
 377         * i386-opc.tbl: Use element rather than vector size for AVX512*
 378         scatter/gather insns.
 379         * i386-tbl.h: Re-generate.
 380
 381 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 382
 383         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 384         (cpu_flags): Drop CpuVREX.
 385         * i386-opc.h (CpuVREX): Delete.
 386         (union i386_cpu_flags): Remove cpuvrex.
 387         * i386-init.h, i386-tbl.h: Re-generate.
 388
 389 2018-07-30  Jim Wilson  <jimw@sifive.com>
 390
 391         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 392         fields.
 393         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 394
 395 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 396
 397         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 398         * Makefile.in: Regenerated.
 399         * configure.ac: Add C-SKY.
 400         * configure: Regenerated.
 401         * csky-dis.c: New file.
 402         * csky-opc.h: New file.
 403         * disassemble.c (ARCH_csky): Define.
 404         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 405         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 406
 407 2018-07-27  Alan Modra  <amodra@gmail.com>
 408
 409         * ppc-opc.c (insert_sprbat): Correct function parameter and
 410         return type.
 411         (extract_sprbat): Likewise, variable too.
 412
 413 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 414             Alan Modra  <amodra@gmail.com>
 415
 416         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 417         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 418         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 419         support disjointed BAT.
 420         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 421         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 422         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 423
 424 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 425             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 426
 427         * i386-gen.c (adjust_broadcast_modifier): New function.
 428         (process_i386_opcode_modifier): Add an argument for operands.
 429         Adjust the Broadcast value based on operands.
 430         (output_i386_opcode): Pass operand_types to
 431         process_i386_opcode_modifier.
 432         (process_i386_opcodes): Pass NULL as operands to
 433         process_i386_opcode_modifier.
 434         * i386-opc.h (BYTE_BROADCAST): New.
 435         (WORD_BROADCAST): Likewise.
 436         (DWORD_BROADCAST): Likewise.
 437         (QWORD_BROADCAST): Likewise.
 438         (i386_opcode_modifier): Expand broadcast to 3 bits.
 439         * i386-tbl.h: Regenerated.
 440
 441 2018-07-24  Alan Modra  <amodra@gmail.com>
 442
 443         PR 23430
 444         * or1k-desc.h: Regenerate.
 445
 446 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 447
 448         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 449         vcvtusi2ss, and vcvtusi2sd.
 450         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 451         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 452         * i386-tbl.h: Re-generate.
 453
 454 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 455
 456         * arc-opc.c (extract_w6): Fix extending the sign.
 457
 458 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 459
 460         * arc-tbl.h (vewt): Allow it for ARC EM family.
 461
 462 2018-07-23  Alan Modra  <amodra@gmail.com>
 463
 464         PR 23419
 465         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 466         opcode variants for mtspr/mfspr encodings.
 467
 468 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 469             Maciej W. Rozycki  <macro@mips.com>
 470
 471         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 472         loongson3a descriptors.
 473         (parse_mips_ase_option): Handle -M loongson-mmi option.
 474         (print_mips_disassembler_options): Document -M loongson-mmi.
 475         * mips-opc.c (LMMI): New macro.
 476         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 477         instructions.
 478
 479 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 480
 481         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 482         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 483         IgnoreSize and [XYZ]MMword where applicable.
 484         * i386-tbl.h: Re-generate.
 485
 486 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 487
 488         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 489         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 490         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 491         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 492         * i386-tbl.h: Re-generate.
 493
 494 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 495
 496         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 497         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 498         VPCLMULQDQ templates into their respective AVX512VL counterparts
 499         where possible, using Disp8ShiftVL and CheckRegSize instead of
 500         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 501         * i386-tbl.h: Re-generate.
 502
 503 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 504
 505         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 506         AVX512VL counterparts where possible, using Disp8ShiftVL and
 507         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 508         IgnoreSize) as appropriate.
 509         * i386-tbl.h: Re-generate.
 510
 511 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 512
 513         * i386-opc.tbl: Fold AVX512BW templates into their respective
 514         AVX512VL counterparts where possible, using Disp8ShiftVL and
 515         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 516         IgnoreSize) as appropriate.
 517         * i386-tbl.h: Re-generate.
 518
 519 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 520
 521         * i386-opc.tbl: Fold AVX512CD templates into their respective
 522         AVX512VL counterparts where possible, using Disp8ShiftVL and
 523         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 524         IgnoreSize) as appropriate.
 525         * i386-tbl.h: Re-generate.
 526
 527 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 528
 529         * i386-opc.h (DISP8_SHIFT_VL): New.
 530         * i386-opc.tbl (Disp8ShiftVL):  Define.
 531         (various): Fold AVX512VL templates into their respective
 532         AVX512F counterparts where possible, using Disp8ShiftVL and
 533         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 534         IgnoreSize) as appropriate.
 535         * i386-tbl.h: Re-generate.
 536
 537 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 538
 539         * Makefile.am: Change dependencies and rule for
 540         $(srcdir)/i386-init.h.
 541         * Makefile.in: Re-generate.
 542         * i386-gen.c (process_i386_opcodes): New local variable
 543         "marker". Drop opening of input file. Recognize marker and line
 544         number directives.
 545         * i386-opc.tbl (OPCODE_I386_H): Define.
 546         (i386-opc.h): Include it.
 547         (None): Undefine.
 548
 549 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 550
 551         PR gas/23418
 552         * i386-opc.h (Byte): Update comments.
 553         (Word): Likewise.
 554         (Dword): Likewise.
 555         (Fword): Likewise.
 556         (Qword): Likewise.
 557         (Tbyte): Likewise.
 558         (Xmmword): Likewise.
 559         (Ymmword): Likewise.
 560         (Zmmword): Likewise.
 561         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 562         vcvttps2uqq.
 563         * i386-tbl.h: Regenerated.
 564
 565 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 566
 567         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 568         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 569         * aarch64-asm-2.c: Regenerate.
 570         * aarch64-dis-2.c: Regenerate.
 571         * aarch64-opc-2.c: Regenerate.
 572
 573 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 574
 575         PR binutils/23192
 576         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 577         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 578         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 579         sqdmulh, sqrdmulh): Use Em16.
 580
 581 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 582
 583         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 584         csdb together with them.
 585         (thumb32_opcodes): Likewise.
 586
 587 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 588
 589         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 590         requiring 32-bit registers as operands 2 and 3. Improve
 591         comments.
 592         (mwait, mwaitx): Fold templates. Improve comments.
 593         OPERAND_TYPE_INOUTPORTREG.
 594         * i386-tbl.h: Re-generate.
 595
 596 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 597
 598         * i386-gen.c (operand_type_init): Remove
 599         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 600         OPERAND_TYPE_INOUTPORTREG.
 601         * i386-init.h: Re-generate.
 602
 603 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 606         (wrssq, wrussq): Add Qword.
 607         * i386-tbl.h: Re-generate.
 608
 609 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-opc.h: Rename OTMax to OTNum.
 612         (OTNumOfUints): Adjust calculation.
 613         (OTUnused): Directly alias to OTNum.
 614
 615 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 616
 617         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 618         `reg_xys'.
 619         (lea_reg_xys): Likewise.
 620         (print_insn_loop_primitive): Rename `reg' local variable to
 621         `reg_dxy'.
 622
 623 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 624
 625         PR binutils/23242
 626         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 627
 628 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 629
 630         PR binutils/23369
 631         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 632         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 633
 634 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 635
 636         PR tdep/8282
 637         * mips-dis.c (mips_option_arg_t): New enumeration.
 638         (mips_options): New variable.
 639         (disassembler_options_mips): New function.
 640         (print_mips_disassembler_options): Reimplement in terms of
 641         `disassembler_options_mips'.
 642         * arm-dis.c (disassembler_options_arm): Adapt to using the
 643         `disasm_options_and_args_t' structure.
 644         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 645         * s390-dis.c (disassembler_options_s390): Likewise.
 646
 647 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 648
 649         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 650         expected result.
 651         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 652         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 653         * testsuite/ld-arm/tls-longplt.d: Likewise.
 654
 655 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 656
 657         PR binutils/23192
 658         * aarch64-asm-2.c: Regenerate.
 659         * aarch64-dis-2.c: Likewise.
 660         * aarch64-opc-2.c: Likewise.
 661         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 662         * aarch64-opc.c (operand_general_constraint_met_p,
 663         aarch64_print_operand): Likewise.
 664         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 665         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 666         fmlal2, fmlsl2.
 667         (AARCH64_OPERANDS): Add Em2.
 668
 669 2018-06-26  Nick Clifton  <nickc@redhat.com>
 670
 671         * po/uk.po: Updated Ukranian translation.
 672         * po/de.po: Updated German translation.
 673         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 674
 675 2018-06-26  Nick Clifton  <nickc@redhat.com>
 676
 677         * nfp-dis.c: Fix spelling mistake.
 678
 679 2018-06-24  Nick Clifton  <nickc@redhat.com>
 680
 681         * configure: Regenerate.
 682         * po/opcodes.pot: Regenerate.
 683
 684 2018-06-24  Nick Clifton  <nickc@redhat.com>
 685
 686         2.31 branch created.
 687
 688 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 689
 690         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 691         * aarch64-asm-2.c: Regenerate.
 692         * aarch64-dis-2.c: Likewise.
 693
 694 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 695
 696         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 697         `-M ginv' option description.
 698
 699 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 700
 701         PR gas/23305
 702         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 703         la and lla.
 704
 705 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 706
 707         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 708         * configure.ac: Remove AC_PREREQ.
 709         * Makefile.in: Re-generate.
 710         * aclocal.m4: Re-generate.
 711         * configure: Re-generate.
 712
 713 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 714
 715         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 716         mips64r6 descriptors.
 717         (parse_mips_ase_option): Handle -Mginv option.
 718         (print_mips_disassembler_options): Document -Mginv.
 719         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 720         (GINV): New macro.
 721         (mips_opcodes): Define ginvi and ginvt.
 722
 723 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 724             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 725
 726         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 727         * mips-opc.c (CRC, CRC64): New macros.
 728         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 729         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 730         crc32cd for CRC64.
 731
 732 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 733
 734         PR 20319
 735         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 736         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 737
 738 2018-06-06  Alan Modra  <amodra@gmail.com>
 739
 740         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 741         setjmp.  Move init for some other vars later too.
 742
 743 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 744
 745         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 746         (dis_private): Add new fields for property section tracking.
 747         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 748         (xtensa_instruction_fits): New functions.
 749         (fetch_data): Bump minimal fetch size to 4.
 750         (print_insn_xtensa): Make struct dis_private static.
 751         Load and prepare property table on section change.
 752         Don't disassemble literals. Don't disassemble instructions that
 753         cross property table boundaries.
 754
 755 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 756
 757         * configure: Regenerated.
 758
 759 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 760
 761         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 762         * i386-tbl.h: Re-generate.
 763
 764 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 765
 766         * i386-opc.tbl (sldt, str): Add NoRex64.
 767         * i386-tbl.h: Re-generate.
 768
 769 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 770
 771         * i386-opc.tbl (invpcid): Add Oword.
 772         * i386-tbl.h: Re-generate.
 773
 774 2018-06-01  Alan Modra  <amodra@gmail.com>
 775
 776         * sysdep.h (_bfd_error_handler): Don't declare.
 777         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 778         * rl78-decode.opc: Likewise.
 779         * msp430-decode.c: Regenerate.
 780         * rl78-decode.c: Regenerate.
 781
 782 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 783
 784         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 785         * i386-init.h : Regenerated.
 786
 787 2018-05-25  Alan Modra  <amodra@gmail.com>
 788
 789         * Makefile.in: Regenerate.
 790         * po/POTFILES.in: Regenerate.
 791
 792 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 793
 794         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 795         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 796         (insert_bab, extract_bab, insert_btab, extract_btab,
 797         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 798         (BAT, BBA VBA RBS XB6S): Delete macros.
 799         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 800         (BB, BD, RBX, XC6): Update for new macros.
 801         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 802         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 803         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 804         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 805
 806 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 807
 808         * Makefile.am: Add support for s12z architecture.
 809         * configure.ac: Likewise.
 810         * disassemble.c: Likewise.
 811         * disassemble.h: Likewise.
 812         * Makefile.in: Regenerate.
 813         * configure: Regenerate.
 814         * s12z-dis.c: New file.
 815         * s12z.h: New file.
 816
 817 2018-05-18  Alan Modra  <amodra@gmail.com>
 818
 819         * nfp-dis.c: Don't #include libbfd.h.
 820         (init_nfp3200_priv): Use bfd_get_section_contents.
 821         (nit_nfp6000_mecsr_sec): Likewise.
 822
 823 2018-05-17  Nick Clifton  <nickc@redhat.com>
 824
 825         * po/zh_CN.po: Updated simplified Chinese translation.
 826
 827 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 828
 829         PR binutils/23109
 830         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 831         * aarch64-dis-2.c: Regenerate.
 832
 833 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 834
 835         PR binutils/21446
 836         * aarch64-asm.c (opintl.h): Include.
 837         (aarch64_ins_sysreg): Enforce read/write constraints.
 838         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 839         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 840         (F_REG_READ, F_REG_WRITE): New.
 841         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 842         AARCH64_OPND_SYSREG.
 843         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 844         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 845         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 846         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 847         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 848         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 849         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 850         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 851         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 852         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 853         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 854         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 855         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 856         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 857         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 858         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 859         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 860
 861 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 862
 863         PR binutils/21446
 864         * aarch64-dis.c (no_notes: New.
 865         (parse_aarch64_dis_option): Support notes.
 866         (aarch64_decode_insn, print_operands): Likewise.
 867         (print_aarch64_disassembler_options): Document notes.
 868         * aarch64-opc.c (aarch64_print_operand): Support notes.
 869
 870 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 871
 872         PR binutils/21446
 873         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 874         and take error struct.
 875         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 876         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 877         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 878         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 879         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 880         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 881         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 882         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 883         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 884         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 885         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 886         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 887         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 888         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 889         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 890         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 891         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 892         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 893         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 894         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 895         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 896         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 897         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 898         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 899         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 900         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 901         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 902         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 903         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 904         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 905         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 906         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 907         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 908         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 909         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 910         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 911         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 912         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 913         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 914         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 915         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 916         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 917         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 918         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 919         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 920         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 921         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 922         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 923         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 924         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 925         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 926         (determine_disassembling_preference, aarch64_decode_insn,
 927         print_insn_aarch64_word, print_insn_data): Take errors struct.
 928         (print_insn_aarch64): Use errors.
 929         * aarch64-asm-2.c: Regenerate.
 930         * aarch64-dis-2.c: Regenerate.
 931         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 932         boolean in aarch64_insert_operan.
 933         (print_operand_extractor): Likewise.
 934         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 935
 936 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 937
 938         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 939
 940 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 941
 942         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 943
 944 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 945
 946         * cr16-opc.c (cr16_instruction): Comment typo fix.
 947         * hppa-dis.c (print_insn_hppa): Likewise.
 948
 949 2018-05-08  Jim Wilson  <jimw@sifive.com>
 950
 951         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 952         (match_c_slli64, match_srxi_as_c_srxi): New.
 953         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 954         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 955         <c.slli, c.srli, c.srai>: Use match_s_slli.
 956         <c.slli64, c.srli64, c.srai64>: New.
 957
 958 2018-05-08  Alan Modra  <amodra@gmail.com>
 959
 960         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 961         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 962         partition opcode space for index lookup.
 963
 964 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 965
 966         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 967         <insn_length>: ...with this.  Update usage.
 968         Remove duplicate call to *info->memory_error_func.
 969
 970 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 971             H.J. Lu  <hongjiu.lu@intel.com>
 972
 973         * i386-dis.c (Gva): New.
 974         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 975         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 976         (prefix_table): New instructions (see prefix above).
 977         (mod_table): New instructions (see prefix above).
 978         (OP_G): Handle va_mode.
 979         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 980         CPU_MOVDIR64B_FLAGS.
 981         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 982         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 983         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 984         * i386-opc.tbl: Add movidir{i,64b}.
 985         * i386-init.h: Regenerated.
 986         * i386-tbl.h: Likewise.
 987
 988 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 989
 990         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 991         AddrPrefixOpReg.
 992         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 993         (AddrPrefixOpReg): This.
 994         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 995         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 996
 997 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 998
 999         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1000         (vle_num_opcodes): Likewise.
1001         (spe2_num_opcodes): Likewise.
1002         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1003         initialization loop.
1004         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1005         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1006         only once.
1007
1008 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1009
1010         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1011
1012 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1013
1014         Makefile.am: Added nfp-dis.c.
1015         configure.ac: Added bfd_nfp_arch.
1016         disassemble.h: Added print_insn_nfp prototype.
1017         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1018         nfp-dis.c: New, for NFP support.
1019         po/POTFILES.in: Added nfp-dis.c to the list.
1020         Makefile.in: Regenerate.
1021         configure: Regenerate.
1022
1023 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1024
1025         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1026         templates into their base ones.
1027         * i386-tlb.h: Re-generate.
1028
1029 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1030
1031         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1032         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1033         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1034         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1035         * i386-init.h: Re-generate.
1036
1037 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1038
1039         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1040         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1041         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1042         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1043         comment.
1044         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1045         and CpuRegMask.
1046         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1047         CpuRegMask: Delete.
1048         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1049         cpuregzmm, and cpuregmask.
1050         * i386-init.h: Re-generate.
1051         * i386-tbl.h: Re-generate.
1052
1053 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1054
1055         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1056         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1057         * i386-init.h: Re-generate.
1058
1059 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1060
1061         * i386-gen.c (VexImmExt): Delete.
1062         * i386-opc.h (VexImmExt, veximmext): Delete.
1063         * i386-opc.tbl: Drop all VexImmExt uses.
1064         * i386-tlb.h: Re-generate.
1065
1066 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1067
1068         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1069         register-only forms.
1070         * i386-tlb.h: Re-generate.
1071
1072 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1073
1074         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1075
1076 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1077
1078         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1079         PREFIX_0F1C.
1080         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1081         (cpu_flags): Add CpuCLDEMOTE.
1082         * i386-init.h: Regenerate.
1083         * i386-opc.h (enum): Add CpuCLDEMOTE,
1084         (i386_cpu_flags): Add cpucldemote.
1085         * i386-opc.tbl: Add cldemote.
1086         * i386-tbl.h: Regenerate.
1087
1088 2018-04-16  Alan Modra  <amodra@gmail.com>
1089
1090         * Makefile.am: Remove sh5 and sh64 support.
1091         * configure.ac: Likewise.
1092         * disassemble.c: Likewise.
1093         * disassemble.h: Likewise.
1094         * sh-dis.c: Likewise.
1095         * sh64-dis.c: Delete.
1096         * sh64-opc.c: Delete.
1097         * sh64-opc.h: Delete.
1098         * Makefile.in: Regenerate.
1099         * configure: Regenerate.
1100         * po/POTFILES.in: Regenerate.
1101
1102 2018-04-16  Alan Modra  <amodra@gmail.com>
1103
1104         * Makefile.am: Remove w65 support.
1105         * configure.ac: Likewise.
1106         * disassemble.c: Likewise.
1107         * disassemble.h: Likewise.
1108         * w65-dis.c: Delete.
1109         * w65-opc.h: Delete.
1110         * Makefile.in: Regenerate.
1111         * configure: Regenerate.
1112         * po/POTFILES.in: Regenerate.
1113
1114 2018-04-16  Alan Modra  <amodra@gmail.com>
1115
1116         * configure.ac: Remove we32k support.
1117         * configure: Regenerate.
1118
1119 2018-04-16  Alan Modra  <amodra@gmail.com>
1120
1121         * Makefile.am: Remove m88k support.
1122         * configure.ac: Likewise.
1123         * disassemble.c: Likewise.
1124         * disassemble.h: Likewise.
1125         * m88k-dis.c: Delete.
1126         * Makefile.in: Regenerate.
1127         * configure: Regenerate.
1128         * po/POTFILES.in: Regenerate.
1129
1130 2018-04-16  Alan Modra  <amodra@gmail.com>
1131
1132         * Makefile.am: Remove i370 support.
1133         * configure.ac: Likewise.
1134         * disassemble.c: Likewise.
1135         * disassemble.h: Likewise.
1136         * i370-dis.c: Delete.
1137         * i370-opc.c: Delete.
1138         * Makefile.in: Regenerate.
1139         * configure: Regenerate.
1140         * po/POTFILES.in: Regenerate.
1141
1142 2018-04-16  Alan Modra  <amodra@gmail.com>
1143
1144         * Makefile.am: Remove h8500 support.
1145         * configure.ac: Likewise.
1146         * disassemble.c: Likewise.
1147         * disassemble.h: Likewise.
1148         * h8500-dis.c: Delete.
1149         * h8500-opc.h: Delete.
1150         * Makefile.in: Regenerate.
1151         * configure: Regenerate.
1152         * po/POTFILES.in: Regenerate.
1153
1154 2018-04-16  Alan Modra  <amodra@gmail.com>
1155
1156         * configure.ac: Remove tahoe support.
1157         * configure: Regenerate.
1158
1159 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1160
1161         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1162         umwait.
1163         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1164         64-bit mode.
1165         * i386-tbl.h: Regenerated.
1166
1167 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1168
1169         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1170         PREFIX_MOD_1_0FAE_REG_6.
1171         (va_mode): New.
1172         (OP_E_register): Use va_mode.
1173         * i386-dis-evex.h (prefix_table):
1174         New instructions (see prefixes above).
1175         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1176         (cpu_flags): Likewise.
1177         * i386-opc.h (enum): Likewise.
1178         (i386_cpu_flags): Likewise.
1179         * i386-opc.tbl: Add umonitor, umwait, tpause.
1180         * i386-init.h: Regenerate.
1181         * i386-tbl.h: Likewise.
1182
1183 2018-04-11  Alan Modra  <amodra@gmail.com>
1184
1185         * opcodes/i860-dis.c: Delete.
1186         * opcodes/i960-dis.c: Delete.
1187         * Makefile.am: Remove i860 and i960 support.
1188         * configure.ac: Likewise.
1189         * disassemble.c: Likewise.
1190         * disassemble.h: Likewise.
1191         * Makefile.in: Regenerate.
1192         * configure: Regenerate.
1193         * po/POTFILES.in: Regenerate.
1194
1195 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1196
1197         PR binutils/23025
1198         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1199         to 0.
1200         (print_insn): Clear vex instead of vex.evex.
1201
1202 2018-04-04  Nick Clifton  <nickc@redhat.com>
1203
1204         * po/es.po: Updated Spanish translation.
1205
1206 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1207
1208         * i386-gen.c (opcode_modifiers): Delete VecESize.
1209         * i386-opc.h (VecESize): Delete.
1210         (struct i386_opcode_modifier): Delete vecesize.
1211         * i386-opc.tbl: Drop VecESize.
1212         * i386-tlb.h: Re-generate.
1213
1214 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1215
1216         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1217         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1218         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1219         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1220         * i386-tlb.h: Re-generate.
1221
1222 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1223
1224         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1225         Fold AVX512 forms
1226         * i386-tlb.h: Re-generate.
1227
1228 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1229
1230         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1231         (vex_len_table): Drop Y for vcvt*2si.
1232         (putop): Replace plain 'Y' handling by abort().
1233
1234 2018-03-28  Nick Clifton  <nickc@redhat.com>
1235
1236         PR 22988
1237         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1238         instructions with only a base address register.
1239         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1240         handle AARHC64_OPND_SVE_ADDR_R.
1241         (aarch64_print_operand): Likewise.
1242         * aarch64-asm-2.c: Regenerate.
1243         * aarch64_dis-2.c: Regenerate.
1244         * aarch64-opc-2.c: Regenerate.
1245
1246 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1247
1248         * i386-opc.tbl: Drop VecESize from register only insn forms and
1249         memory forms not allowing broadcast.
1250         * i386-tlb.h: Re-generate.
1251
1252 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1253
1254         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1255         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1256         sha256*): Drop Disp<N>.
1257
1258 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1259
1260         * i386-dis.c (EbndS, bnd_swap_mode): New.
1261         (prefix_table): Use EbndS.
1262         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1263         * i386-opc.tbl (bndmov): Move misplaced Load.
1264         * i386-tlb.h: Re-generate.
1265
1266 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1267
1268         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1269         templates allowing memory operands and folded ones for register
1270         only flavors.
1271         * i386-tlb.h: Re-generate.
1272
1273 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1274
1275         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1276         256-bit templates. Drop redundant leftover Disp<N>.
1277         * i386-tlb.h: Re-generate.
1278
1279 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1280
1281         * riscv-opc.c (riscv_insn_types): New.
1282
1283 2018-03-13  Nick Clifton  <nickc@redhat.com>
1284
1285         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1286
1287 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1288
1289         * i386-opc.tbl: Add Optimize to clr.
1290         * i386-tbl.h: Regenerated.
1291
1292 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1293
1294         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1295         * i386-opc.h (OldGcc): Removed.
1296         (i386_opcode_modifier): Remove oldgcc.
1297         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1298         instructions for old (<= 2.8.1) versions of gcc.
1299         * i386-tbl.h: Regenerated.
1300
1301 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1302
1303         * i386-opc.h (EVEXDYN): New.
1304         * i386-opc.tbl: Fold various AVX512VL templates.
1305         * i386-tlb.h: Re-generate.
1306
1307 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1308
1309         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1310         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1311         vpexpandd, vpexpandq): Fold AFX512VF templates.
1312         * i386-tlb.h: Re-generate.
1313
1314 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1315
1316         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1317         Fold 128- and 256-bit VEX-encoded templates.
1318         * i386-tlb.h: Re-generate.
1319
1320 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1321
1322         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1323         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1324         vpexpandd, vpexpandq): Fold AVX512F templates.
1325         * i386-tlb.h: Re-generate.
1326
1327 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1328
1329         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1330         64-bit templates. Drop Disp<N>.
1331         * i386-tlb.h: Re-generate.
1332
1333 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1334
1335         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1336         and 256-bit templates.
1337         * i386-tlb.h: Re-generate.
1338
1339 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1340
1341         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1342         * i386-tlb.h: Re-generate.
1343
1344 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1345
1346         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1347         Drop NoAVX.
1348         * i386-tlb.h: Re-generate.
1349
1350 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1351
1352         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1353         * i386-tlb.h: Re-generate.
1354
1355 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1356
1357         * i386-gen.c (opcode_modifiers): Delete FloatD.
1358         * i386-opc.h (FloatD): Delete.
1359         (struct i386_opcode_modifier): Delete floatd.
1360         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1361         FloatD by D.
1362         * i386-tlb.h: Re-generate.
1363
1364 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1365
1366         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1367
1368 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1369
1370         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1371         * i386-tlb.h: Re-generate.
1372
1373 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1374
1375         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1376         forms.
1377         * i386-tlb.h: Re-generate.
1378
1379 2018-03-07  Alan Modra  <amodra@gmail.com>
1380
1381         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1382         bfd_arch_rs6000.
1383         * disassemble.h (print_insn_rs6000): Delete.
1384         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1385         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1386         (print_insn_rs6000): Delete.
1387
1388 2018-03-03  Alan Modra  <amodra@gmail.com>
1389
1390         * sysdep.h (opcodes_error_handler): Define.
1391         (_bfd_error_handler): Declare.
1392         * Makefile.am: Remove stray #.
1393         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1394         EDIT" comment.
1395         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1396         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1397         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1398         opcodes_error_handler to print errors.  Standardize error messages.
1399         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1400         and include opintl.h.
1401         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1402         * i386-gen.c: Standardize error messages.
1403         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1404         * Makefile.in: Regenerate.
1405         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1406         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1407         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1408         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1409         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1410         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1411         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1412         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1413         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1414         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1415         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1416         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1417         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1418
1419 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1420
1421         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1422         vpsub[bwdq] instructions.
1423         * i386-tbl.h: Regenerated.
1424
1425 2018-03-01  Alan Modra  <amodra@gmail.com>
1426
1427         * configure.ac (ALL_LINGUAS): Sort.
1428         * configure: Regenerate.
1429
1430 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1431
1432         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1433         macro by assignements.
1434
1435 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1436
1437         PR gas/22871
1438         * i386-gen.c (opcode_modifiers): Add Optimize.
1439         * i386-opc.h (Optimize): New enum.
1440         (i386_opcode_modifier): Add optimize.
1441         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1442         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1443         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1444         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1445         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1446         vpxord and vpxorq.
1447         * i386-tbl.h: Regenerated.
1448
1449 2018-02-26  Alan Modra  <amodra@gmail.com>
1450
1451         * crx-dis.c (getregliststring): Allocate a large enough buffer
1452         to silence false positive gcc8 warning.
1453
1454 2018-02-22  Shea Levy <shea@shealevy.com>
1455
1456         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1457
1458 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1459
1460         * i386-opc.tbl: Add {rex},
1461         * i386-tbl.h: Regenerated.
1462
1463 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1464
1465         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1466         (mips16_opcodes): Replace `M' with `m' for "restore".
1467
1468 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1469
1470         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1471
1472 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1473
1474         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1475         variable to `function_index'.
1476
1477 2018-02-13  Nick Clifton  <nickc@redhat.com>
1478
1479         PR 22823
1480         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1481         about truncation of printing.
1482
1483 2018-02-12  Henry Wong <henry@stuffedcow.net>
1484
1485         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1486
1487 2018-02-05  Nick Clifton  <nickc@redhat.com>
1488
1489         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1490
1491 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1492
1493         * i386-dis.c (enum): Add pconfig.
1494         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1495         (cpu_flags): Add CpuPCONFIG.
1496         * i386-opc.h (enum): Add CpuPCONFIG.
1497         (i386_cpu_flags): Add cpupconfig.
1498         * i386-opc.tbl: Add PCONFIG instruction.
1499         * i386-init.h: Regenerate.
1500         * i386-tbl.h: Likewise.
1501
1502 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1503
1504         * i386-dis.c (enum): Add PREFIX_0F09.
1505         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1506         (cpu_flags): Add CpuWBNOINVD.
1507         * i386-opc.h (enum): Add CpuWBNOINVD.
1508         (i386_cpu_flags): Add cpuwbnoinvd.
1509         * i386-opc.tbl: Add WBNOINVD instruction.
1510         * i386-init.h: Regenerate.
1511         * i386-tbl.h: Likewise.
1512
1513 2018-01-17  Jim Wilson  <jimw@sifive.com>
1514
1515         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1516
1517 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1518
1519         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1520         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1521         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1522         (cpu_flags): Add CpuIBT, CpuSHSTK.
1523         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1524         (i386_cpu_flags): Add cpuibt, cpushstk.
1525         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1526         * i386-init.h: Regenerate.
1527         * i386-tbl.h: Likewise.
1528
1529 2018-01-16  Nick Clifton  <nickc@redhat.com>
1530
1531         * po/pt_BR.po: Updated Brazilian Portugese translation.
1532         * po/de.po: Updated German translation.
1533
1534 2018-01-15  Jim Wilson  <jimw@sifive.com>
1535
1536         * riscv-opc.c (match_c_nop): New.
1537         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1538
1539 2018-01-15  Nick Clifton  <nickc@redhat.com>
1540
1541         * po/uk.po: Updated Ukranian translation.
1542
1543 2018-01-13  Nick Clifton  <nickc@redhat.com>
1544
1545         * po/opcodes.pot: Regenerated.
1546
1547 2018-01-13  Nick Clifton  <nickc@redhat.com>
1548
1549         * configure: Regenerate.
1550
1551 2018-01-13  Nick Clifton  <nickc@redhat.com>
1552
1553         2.30 branch created.
1554
1555 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1556
1557         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1558         * i386-tbl.h: Regenerate.
1559
1560 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1561
1562         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1563         * i386-tbl.h: Re-generate.
1564
1565 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1566
1567         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1568         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1569         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1570         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1571         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1572         Disp8MemShift of AVX512VL forms.
1573         * i386-tbl.h: Re-generate.
1574
1575 2018-01-09  Jim Wilson  <jimw@sifive.com>
1576
1577         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1578         then the hi_addr value is zero.
1579
1580 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1581
1582         * arm-dis.c (arm_opcodes): Add csdb.
1583         (thumb32_opcodes): Add csdb.
1584
1585 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1586
1587         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1588         * aarch64-asm-2.c: Regenerate.
1589         * aarch64-dis-2.c: Regenerate.
1590         * aarch64-opc-2.c: Regenerate.
1591
1592 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1593
1594         PR gas/22681
1595         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1596         Remove AVX512 vmovd with 64-bit operands.
1597         * i386-tbl.h: Regenerated.
1598
1599 2018-01-05  Jim Wilson  <jimw@sifive.com>
1600
1601         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1602         jalr.
1603
1604 2018-01-03  Alan Modra  <amodra@gmail.com>
1605
1606         Update year range in copyright notice of all files.
1607
1608 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1609
1610         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1611         and OPERAND_TYPE_REGZMM entries.
1612
1613 For older changes see ChangeLog-2017
1614 \f
1615 Copyright (C) 2018 Free Software Foundation, Inc.
1616
1617 Copying and distribution of this file, with or without modification,
1618 are permitted in any medium without royalty provided the copyright
1619 notice and this notice are preserved.
1620
1621 Local Variables:
1622 mode: change-log
1623 left-margin: 8
1624 fill-column: 74
1625 version-control: never
1626 End: