opcodes/ChangeLog

   1 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
   4         (ARMV8_5, V8_5_INSN): New.
   5
   6 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
   7
   8         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
   9
  10 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
  11
  12         * i386-dis.c (rm_table): Add enclv.
  13         * i386-opc.tbl: Add enclv.
  14         * i386-tbl.h: Regenerated.
  15
  16 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
  17
  18         * arm-dis.c (arm_opcodes): Add sb.
  19         (thumb32_opcodes): Likewise.
  20
  21 2018-10-05  Richard Henderson  <rth@twiddle.net>
  22             Stafford Horne  <shorne@gmail.com>
  23
  24         * or1k-desc.c: Regenerate.
  25         * or1k-desc.h: Regenerate.
  26         * or1k-opc.c: Regenerate.
  27         * or1k-opc.h: Regenerate.
  28         * or1k-opinst.c: Regenerate.
  29
  30 2018-10-05  Richard Henderson  <rth@twiddle.net>
  31
  32         * or1k-asm.c: Regenerated.
  33         * or1k-desc.c: Regenerated.
  34         * or1k-desc.h: Regenerated.
  35         * or1k-dis.c: Regenerated.
  36         * or1k-ibld.c: Regenerated.
  37         * or1k-opc.c: Regenerated.
  38         * or1k-opc.h: Regenerated.
  39         * or1k-opinst.c: Regenerated.
  40
  41 2018-10-05  Richard Henderson  <rth@twiddle.net>
  42
  43         * or1k-asm.c: Regenerate.
  44
  45 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  46
  47         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
  48         * aarch64-dis.c (print_operands): Refactor to take notes.
  49         (print_verifier_notes): New.
  50         (print_aarch64_insn): Apply constraint verifier.
  51         (print_insn_aarch64_word): Update call to print_aarch64_insn.
  52         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
  53
  54 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  55
  56         * aarch64-opc.c (init_insn_block): New.
  57         (verify_constraints, aarch64_is_destructive_by_operands): New.
  58         * aarch64-opc.h (verify_constraints): New.
  59
  60 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  61
  62         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
  63         * aarch64-opc.c (verify_ldpsw): Update arguments.
  64
  65 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  66
  67         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
  68         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
  69
  70 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  71
  72         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
  73         * aarch64-dis.c (insn_sequence): New.
  74
  75 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  76
  77         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
  78         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
  79         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
  80         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
  81         constraints.
  82         (_SVE_INSNC): New.
  83         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
  84         constraints.
  85         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
  86         F_SCAN flags.
  87         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
  88         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
  89         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
  90         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
  91         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
  92         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
  93         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
  94
  95 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
  96
  97         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
  98
  99 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 100
 101         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 102         are used when extracting signed fields and converting them to
 103         potentially 64-bit types.
 104
 105 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 106
 107         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 108         * Makefile.in: Re-generate.
 109         * aclocal.m4: Re-generate.
 110         * configure: Re-generate.
 111         * configure.ac: Remove check for -Wno-missing-field-initializers.
 112         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 113         (csky_v2_opcodes): Likewise.
 114
 115 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 116
 117         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 118
 119 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 120
 121         * nds32-asm.c (operand_fields): Remove the unused fields.
 122         (nds32_opcodes): Remove the unused instructions.
 123         * nds32-dis.c (nds32_ex9_info): Removed.
 124         (nds32_parse_opcode): Updated.
 125         (print_insn_nds32): Likewise.
 126         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 127         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 128         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 129         build_opcode_hash_table): New functions.
 130         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 131         nds32_opcode_table): New.
 132         (hw_ktabs): Declare it to a pointer rather than an array.
 133         (build_hash_table): Removed.
 134         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 135         SYN_ROPT and upadte HW_GPR and HW_INT.
 136         * nds32-dis.c (keywords): Remove const.
 137         (match_field): New function.
 138         (nds32_parse_opcode): Updated.
 139         * disassemble.c (disassemble_init_for_target):
 140         Add disassemble_init_nds32.
 141         * nds32-dis.c (eum map_type): New.
 142         (nds32_private_data): Likewise.
 143         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 144         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 145         (print_insn_nds32): Updated.
 146         * nds32-asm.c (parse_aext_reg): Add new parameter.
 147         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 148         are allowed to use.
 149         All callers changed.
 150         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 151         (operand_fields): Add new fields.
 152         (nds32_opcodes): Add new instructions.
 153         (keyword_aridxi_mx): New keyword.
 154         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 155         and NASM_ATTR_ZOL.
 156         (ALU2_1, ALU2_2, ALU2_3): New macros.
 157         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 158
 159 2018-09-17  Kito Cheng  <kito@andestech.com>
 160
 161         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 162
 163 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 164
 165         PR gas/23670
 166         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 167         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 168         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 169         (EVEX_LEN_0F7E_P_1): Likewise.
 170         (EVEX_LEN_0F7E_P_2): Likewise.
 171         (EVEX_LEN_0FD6_P_2): Likewise.
 172         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 173         (EVEX_LEN_TABLE): Likewise.
 174         (EVEX_LEN_0F6E_P_2): New enum.
 175         (EVEX_LEN_0F7E_P_1): Likewise.
 176         (EVEX_LEN_0F7E_P_2): Likewise.
 177         (EVEX_LEN_0FD6_P_2): Likewise.
 178         (evex_len_table): New.
 179         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 180         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 181         * i386-tbl.h: Regenerated.
 182
 183 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 184
 185         PR gas/23665
 186         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 187         VEX_LEN_0F7E_P_2 entries.
 188         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 189         * i386-tbl.h: Regenerated.
 190
 191 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         * i386-dis.c (VZERO_Fixup): Removed.
 194         (VZERO): Likewise.
 195         (VEX_LEN_0F10_P_1): Likewise.
 196         (VEX_LEN_0F10_P_3): Likewise.
 197         (VEX_LEN_0F11_P_1): Likewise.
 198         (VEX_LEN_0F11_P_3): Likewise.
 199         (VEX_LEN_0F2E_P_0): Likewise.
 200         (VEX_LEN_0F2E_P_2): Likewise.
 201         (VEX_LEN_0F2F_P_0): Likewise.
 202         (VEX_LEN_0F2F_P_2): Likewise.
 203         (VEX_LEN_0F51_P_1): Likewise.
 204         (VEX_LEN_0F51_P_3): Likewise.
 205         (VEX_LEN_0F52_P_1): Likewise.
 206         (VEX_LEN_0F53_P_1): Likewise.
 207         (VEX_LEN_0F58_P_1): Likewise.
 208         (VEX_LEN_0F58_P_3): Likewise.
 209         (VEX_LEN_0F59_P_1): Likewise.
 210         (VEX_LEN_0F59_P_3): Likewise.
 211         (VEX_LEN_0F5A_P_1): Likewise.
 212         (VEX_LEN_0F5A_P_3): Likewise.
 213         (VEX_LEN_0F5C_P_1): Likewise.
 214         (VEX_LEN_0F5C_P_3): Likewise.
 215         (VEX_LEN_0F5D_P_1): Likewise.
 216         (VEX_LEN_0F5D_P_3): Likewise.
 217         (VEX_LEN_0F5E_P_1): Likewise.
 218         (VEX_LEN_0F5E_P_3): Likewise.
 219         (VEX_LEN_0F5F_P_1): Likewise.
 220         (VEX_LEN_0F5F_P_3): Likewise.
 221         (VEX_LEN_0FC2_P_1): Likewise.
 222         (VEX_LEN_0FC2_P_3): Likewise.
 223         (VEX_LEN_0F3A0A_P_2): Likewise.
 224         (VEX_LEN_0F3A0B_P_2): Likewise.
 225         (VEX_W_0F10_P_0): Likewise.
 226         (VEX_W_0F10_P_1): Likewise.
 227         (VEX_W_0F10_P_2): Likewise.
 228         (VEX_W_0F10_P_3): Likewise.
 229         (VEX_W_0F11_P_0): Likewise.
 230         (VEX_W_0F11_P_1): Likewise.
 231         (VEX_W_0F11_P_2): Likewise.
 232         (VEX_W_0F11_P_3): Likewise.
 233         (VEX_W_0F12_P_0_M_0): Likewise.
 234         (VEX_W_0F12_P_0_M_1): Likewise.
 235         (VEX_W_0F12_P_1): Likewise.
 236         (VEX_W_0F12_P_2): Likewise.
 237         (VEX_W_0F12_P_3): Likewise.
 238         (VEX_W_0F13_M_0): Likewise.
 239         (VEX_W_0F14): Likewise.
 240         (VEX_W_0F15): Likewise.
 241         (VEX_W_0F16_P_0_M_0): Likewise.
 242         (VEX_W_0F16_P_0_M_1): Likewise.
 243         (VEX_W_0F16_P_1): Likewise.
 244         (VEX_W_0F16_P_2): Likewise.
 245         (VEX_W_0F17_M_0): Likewise.
 246         (VEX_W_0F28): Likewise.
 247         (VEX_W_0F29): Likewise.
 248         (VEX_W_0F2B_M_0): Likewise.
 249         (VEX_W_0F2E_P_0): Likewise.
 250         (VEX_W_0F2E_P_2): Likewise.
 251         (VEX_W_0F2F_P_0): Likewise.
 252         (VEX_W_0F2F_P_2): Likewise.
 253         (VEX_W_0F50_M_0): Likewise.
 254         (VEX_W_0F51_P_0): Likewise.
 255         (VEX_W_0F51_P_1): Likewise.
 256         (VEX_W_0F51_P_2): Likewise.
 257         (VEX_W_0F51_P_3): Likewise.
 258         (VEX_W_0F52_P_0): Likewise.
 259         (VEX_W_0F52_P_1): Likewise.
 260         (VEX_W_0F53_P_0): Likewise.
 261         (VEX_W_0F53_P_1): Likewise.
 262         (VEX_W_0F58_P_0): Likewise.
 263         (VEX_W_0F58_P_1): Likewise.
 264         (VEX_W_0F58_P_2): Likewise.
 265         (VEX_W_0F58_P_3): Likewise.
 266         (VEX_W_0F59_P_0): Likewise.
 267         (VEX_W_0F59_P_1): Likewise.
 268         (VEX_W_0F59_P_2): Likewise.
 269         (VEX_W_0F59_P_3): Likewise.
 270         (VEX_W_0F5A_P_0): Likewise.
 271         (VEX_W_0F5A_P_1): Likewise.
 272         (VEX_W_0F5A_P_3): Likewise.
 273         (VEX_W_0F5B_P_0): Likewise.
 274         (VEX_W_0F5B_P_1): Likewise.
 275         (VEX_W_0F5B_P_2): Likewise.
 276         (VEX_W_0F5C_P_0): Likewise.
 277         (VEX_W_0F5C_P_1): Likewise.
 278         (VEX_W_0F5C_P_2): Likewise.
 279         (VEX_W_0F5C_P_3): Likewise.
 280         (VEX_W_0F5D_P_0): Likewise.
 281         (VEX_W_0F5D_P_1): Likewise.
 282         (VEX_W_0F5D_P_2): Likewise.
 283         (VEX_W_0F5D_P_3): Likewise.
 284         (VEX_W_0F5E_P_0): Likewise.
 285         (VEX_W_0F5E_P_1): Likewise.
 286         (VEX_W_0F5E_P_2): Likewise.
 287         (VEX_W_0F5E_P_3): Likewise.
 288         (VEX_W_0F5F_P_0): Likewise.
 289         (VEX_W_0F5F_P_1): Likewise.
 290         (VEX_W_0F5F_P_2): Likewise.
 291         (VEX_W_0F5F_P_3): Likewise.
 292         (VEX_W_0F60_P_2): Likewise.
 293         (VEX_W_0F61_P_2): Likewise.
 294         (VEX_W_0F62_P_2): Likewise.
 295         (VEX_W_0F63_P_2): Likewise.
 296         (VEX_W_0F64_P_2): Likewise.
 297         (VEX_W_0F65_P_2): Likewise.
 298         (VEX_W_0F66_P_2): Likewise.
 299         (VEX_W_0F67_P_2): Likewise.
 300         (VEX_W_0F68_P_2): Likewise.
 301         (VEX_W_0F69_P_2): Likewise.
 302         (VEX_W_0F6A_P_2): Likewise.
 303         (VEX_W_0F6B_P_2): Likewise.
 304         (VEX_W_0F6C_P_2): Likewise.
 305         (VEX_W_0F6D_P_2): Likewise.
 306         (VEX_W_0F6F_P_1): Likewise.
 307         (VEX_W_0F6F_P_2): Likewise.
 308         (VEX_W_0F70_P_1): Likewise.
 309         (VEX_W_0F70_P_2): Likewise.
 310         (VEX_W_0F70_P_3): Likewise.
 311         (VEX_W_0F71_R_2_P_2): Likewise.
 312         (VEX_W_0F71_R_4_P_2): Likewise.
 313         (VEX_W_0F71_R_6_P_2): Likewise.
 314         (VEX_W_0F72_R_2_P_2): Likewise.
 315         (VEX_W_0F72_R_4_P_2): Likewise.
 316         (VEX_W_0F72_R_6_P_2): Likewise.
 317         (VEX_W_0F73_R_2_P_2): Likewise.
 318         (VEX_W_0F73_R_3_P_2): Likewise.
 319         (VEX_W_0F73_R_6_P_2): Likewise.
 320         (VEX_W_0F73_R_7_P_2): Likewise.
 321         (VEX_W_0F74_P_2): Likewise.
 322         (VEX_W_0F75_P_2): Likewise.
 323         (VEX_W_0F76_P_2): Likewise.
 324         (VEX_W_0F77_P_0): Likewise.
 325         (VEX_W_0F7C_P_2): Likewise.
 326         (VEX_W_0F7C_P_3): Likewise.
 327         (VEX_W_0F7D_P_2): Likewise.
 328         (VEX_W_0F7D_P_3): Likewise.
 329         (VEX_W_0F7E_P_1): Likewise.
 330         (VEX_W_0F7F_P_1): Likewise.
 331         (VEX_W_0F7F_P_2): Likewise.
 332         (VEX_W_0FAE_R_2_M_0): Likewise.
 333         (VEX_W_0FAE_R_3_M_0): Likewise.
 334         (VEX_W_0FC2_P_0): Likewise.
 335         (VEX_W_0FC2_P_1): Likewise.
 336         (VEX_W_0FC2_P_2): Likewise.
 337         (VEX_W_0FC2_P_3): Likewise.
 338         (VEX_W_0FD0_P_2): Likewise.
 339         (VEX_W_0FD0_P_3): Likewise.
 340         (VEX_W_0FD1_P_2): Likewise.
 341         (VEX_W_0FD2_P_2): Likewise.
 342         (VEX_W_0FD3_P_2): Likewise.
 343         (VEX_W_0FD4_P_2): Likewise.
 344         (VEX_W_0FD5_P_2): Likewise.
 345         (VEX_W_0FD6_P_2): Likewise.
 346         (VEX_W_0FD7_P_2_M_1): Likewise.
 347         (VEX_W_0FD8_P_2): Likewise.
 348         (VEX_W_0FD9_P_2): Likewise.
 349         (VEX_W_0FDA_P_2): Likewise.
 350         (VEX_W_0FDB_P_2): Likewise.
 351         (VEX_W_0FDC_P_2): Likewise.
 352         (VEX_W_0FDD_P_2): Likewise.
 353         (VEX_W_0FDE_P_2): Likewise.
 354         (VEX_W_0FDF_P_2): Likewise.
 355         (VEX_W_0FE0_P_2): Likewise.
 356         (VEX_W_0FE1_P_2): Likewise.
 357         (VEX_W_0FE2_P_2): Likewise.
 358         (VEX_W_0FE3_P_2): Likewise.
 359         (VEX_W_0FE4_P_2): Likewise.
 360         (VEX_W_0FE5_P_2): Likewise.
 361         (VEX_W_0FE6_P_1): Likewise.
 362         (VEX_W_0FE6_P_2): Likewise.
 363         (VEX_W_0FE6_P_3): Likewise.
 364         (VEX_W_0FE7_P_2_M_0): Likewise.
 365         (VEX_W_0FE8_P_2): Likewise.
 366         (VEX_W_0FE9_P_2): Likewise.
 367         (VEX_W_0FEA_P_2): Likewise.
 368         (VEX_W_0FEB_P_2): Likewise.
 369         (VEX_W_0FEC_P_2): Likewise.
 370         (VEX_W_0FED_P_2): Likewise.
 371         (VEX_W_0FEE_P_2): Likewise.
 372         (VEX_W_0FEF_P_2): Likewise.
 373         (VEX_W_0FF0_P_3_M_0): Likewise.
 374         (VEX_W_0FF1_P_2): Likewise.
 375         (VEX_W_0FF2_P_2): Likewise.
 376         (VEX_W_0FF3_P_2): Likewise.
 377         (VEX_W_0FF4_P_2): Likewise.
 378         (VEX_W_0FF5_P_2): Likewise.
 379         (VEX_W_0FF6_P_2): Likewise.
 380         (VEX_W_0FF7_P_2): Likewise.
 381         (VEX_W_0FF8_P_2): Likewise.
 382         (VEX_W_0FF9_P_2): Likewise.
 383         (VEX_W_0FFA_P_2): Likewise.
 384         (VEX_W_0FFB_P_2): Likewise.
 385         (VEX_W_0FFC_P_2): Likewise.
 386         (VEX_W_0FFD_P_2): Likewise.
 387         (VEX_W_0FFE_P_2): Likewise.
 388         (VEX_W_0F3800_P_2): Likewise.
 389         (VEX_W_0F3801_P_2): Likewise.
 390         (VEX_W_0F3802_P_2): Likewise.
 391         (VEX_W_0F3803_P_2): Likewise.
 392         (VEX_W_0F3804_P_2): Likewise.
 393         (VEX_W_0F3805_P_2): Likewise.
 394         (VEX_W_0F3806_P_2): Likewise.
 395         (VEX_W_0F3807_P_2): Likewise.
 396         (VEX_W_0F3808_P_2): Likewise.
 397         (VEX_W_0F3809_P_2): Likewise.
 398         (VEX_W_0F380A_P_2): Likewise.
 399         (VEX_W_0F380B_P_2): Likewise.
 400         (VEX_W_0F3817_P_2): Likewise.
 401         (VEX_W_0F381C_P_2): Likewise.
 402         (VEX_W_0F381D_P_2): Likewise.
 403         (VEX_W_0F381E_P_2): Likewise.
 404         (VEX_W_0F3820_P_2): Likewise.
 405         (VEX_W_0F3821_P_2): Likewise.
 406         (VEX_W_0F3822_P_2): Likewise.
 407         (VEX_W_0F3823_P_2): Likewise.
 408         (VEX_W_0F3824_P_2): Likewise.
 409         (VEX_W_0F3825_P_2): Likewise.
 410         (VEX_W_0F3828_P_2): Likewise.
 411         (VEX_W_0F3829_P_2): Likewise.
 412         (VEX_W_0F382A_P_2_M_0): Likewise.
 413         (VEX_W_0F382B_P_2): Likewise.
 414         (VEX_W_0F3830_P_2): Likewise.
 415         (VEX_W_0F3831_P_2): Likewise.
 416         (VEX_W_0F3832_P_2): Likewise.
 417         (VEX_W_0F3833_P_2): Likewise.
 418         (VEX_W_0F3834_P_2): Likewise.
 419         (VEX_W_0F3835_P_2): Likewise.
 420         (VEX_W_0F3837_P_2): Likewise.
 421         (VEX_W_0F3838_P_2): Likewise.
 422         (VEX_W_0F3839_P_2): Likewise.
 423         (VEX_W_0F383A_P_2): Likewise.
 424         (VEX_W_0F383B_P_2): Likewise.
 425         (VEX_W_0F383C_P_2): Likewise.
 426         (VEX_W_0F383D_P_2): Likewise.
 427         (VEX_W_0F383E_P_2): Likewise.
 428         (VEX_W_0F383F_P_2): Likewise.
 429         (VEX_W_0F3840_P_2): Likewise.
 430         (VEX_W_0F3841_P_2): Likewise.
 431         (VEX_W_0F38DB_P_2): Likewise.
 432         (VEX_W_0F3A08_P_2): Likewise.
 433         (VEX_W_0F3A09_P_2): Likewise.
 434         (VEX_W_0F3A0A_P_2): Likewise.
 435         (VEX_W_0F3A0B_P_2): Likewise.
 436         (VEX_W_0F3A0C_P_2): Likewise.
 437         (VEX_W_0F3A0D_P_2): Likewise.
 438         (VEX_W_0F3A0E_P_2): Likewise.
 439         (VEX_W_0F3A0F_P_2): Likewise.
 440         (VEX_W_0F3A21_P_2): Likewise.
 441         (VEX_W_0F3A40_P_2): Likewise.
 442         (VEX_W_0F3A41_P_2): Likewise.
 443         (VEX_W_0F3A42_P_2): Likewise.
 444         (VEX_W_0F3A62_P_2): Likewise.
 445         (VEX_W_0F3A63_P_2): Likewise.
 446         (VEX_W_0F3ADF_P_2): Likewise.
 447         (VEX_LEN_0F77_P_0): New.
 448         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 449         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 450         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 451         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 452         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 453         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 454         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 455         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 456         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 457         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 458         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 459         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 460         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 461         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 462         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 463         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 464         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 465         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 466         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 467         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 468         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 469         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 470         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 471         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 472         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 473         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 474         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 475         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 476         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 477         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 478         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 479         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 480         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 481         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 482         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 483         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 484         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 485         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 486         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 487         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 488         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 489         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 490         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 491         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 492         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 493         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 494         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 495         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 496         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 497         (vex_table): Update VEX 0F28 and 0F29 entries.
 498         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 499         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 500         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 501         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 502         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 503         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 504         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 505         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 506         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 507         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 508         VEX_LEN_0F3A0B_P_2 entries.
 509         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 510         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 511         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 512         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 513         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 514         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 515         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 516         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 517         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 518         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 519         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 520         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 521         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 522         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 523         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 524         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 525         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 526         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 527         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 528         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 529         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 530         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 531         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 532         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 533         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 534         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 535         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 536         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 537         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 538         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 539         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 540         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 541         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 542         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 543         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 544         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 545         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 546         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 547         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 548         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 549         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 550         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 551         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 552         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 553         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 554         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 555         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 556         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 557         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 558         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 559         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 560         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 561         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 562         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 563         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 564         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 565         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 566         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 567         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 568         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 569         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 570         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 571         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 572         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 573         VEX_W_0F3ADF_P_2 entries.
 574         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 575         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 576         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 577
 578 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 579
 580         * i386-opc.tbl (VexWIG): New.
 581         Replace VexW=3 with VexWIG.
 582
 583 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 584
 585         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 586         * i386-tbl.h: Regenerated.
 587
 588 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 589
 590         PR gas/23665
 591         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 592         VEX_LEN_0FD6_P_2 entries.
 593         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 594         * i386-tbl.h: Regenerated.
 595
 596 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 597
 598         PR gas/23642
 599         * i386-opc.h (VEXWIG): New.
 600         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 601         * i386-tbl.h: Regenerated.
 602
 603 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 604
 605         PR binutils/23655
 606         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 607         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 608         * i386-dis.c (EXxEVexR64): New.
 609         (evex_rounding_64_mode): Likewise.
 610         (OP_Rounding): Handle evex_rounding_64_mode.
 611
 612 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 613
 614         PR binutils/23655
 615         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 616         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 617         * i386-dis.c (Edqa): New.
 618         (dqa_mode): Likewise.
 619         (intel_operand_size): Handle dqa_mode as m_mode.
 620         (OP_E_register): Handle dqa_mode as dq_mode.
 621         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 622
 623 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         * i386-dis.c (OP_E_memory): Reformat.
 626
 627 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 628
 629         * i386-opc.tbl (crc32): Fold byte and word forms.
 630         * i386-tbl.h: Re-generate.
 631
 632 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 633
 634         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 635         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 636         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 637         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 638         * i386-tbl.h: Regenerated.
 639
 640 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 641
 642         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 643         meaningless.
 644         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 645         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 646         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 647         * i386-tbl.h: Re-generate.
 648
 649 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 650
 651         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 652         AVX512_4VNNIW insns.
 653         * i386-tbl.h: Re-generate.
 654
 655 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 656
 657         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 658         meaningless.
 659         * i386-tbl.h: Re-generate.
 660
 661 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 662
 663         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 664         meaningless.
 665         * i386-tbl.h: Re-generate.
 666
 667 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 668
 669         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 670         meaningless.
 671         * i386-tbl.h: Re-generate.
 672
 673 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 674
 675         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 676         meaningless.
 677         * i386-tbl.h: Re-generate.
 678
 679 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 680
 681         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 682         meaningless.
 683         * i386-tbl.h: Re-generate.
 684
 685 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 688         * i386-tbl.h: Re-generate.
 689
 690 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 691
 692         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 693         * i386-tbl.h: Re-generate.
 694
 695 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 696
 697         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 698         meaningless.
 699         * i386-tbl.h: Re-generate.
 700
 701 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 702
 703         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 704         meaningless.
 705         * i386-tbl.h: Re-generate.
 706
 707 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 708
 709         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 710         * i386-tbl.h: Re-generate.
 711
 712 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 715         * i386-tbl.h: Re-generate.
 716
 717 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 718
 719         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 720         * i386-tbl.h: Re-generate.
 721
 722 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 723
 724         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 725         meaningless.
 726         * i386-tbl.h: Re-generate.
 727
 728 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 729
 730         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 731         meaningless.
 732         * i386-tbl.h: Re-generate.
 733
 734 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 735
 736         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 737         meaningless.
 738         * i386-tbl.h: Re-generate.
 739
 740 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 741
 742         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 743         * i386-tbl.h: Re-generate.
 744
 745 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 746
 747         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 748         * i386-tbl.h: Re-generate.
 749
 750 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 751
 752         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 753         * i386-tbl.h: Re-generate.
 754
 755 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 756
 757         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 758         (vpbroadcastw, rdpid): Drop NoRex64.
 759         * i386-tbl.h: Re-generate.
 760
 761 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 764         store templates, adding D.
 765         * i386-tbl.h: Re-generate.
 766
 767 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 768
 769         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 770         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 771         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 772         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 773         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 774         Fold load and store templates where possible, adding D. Drop
 775         IgnoreSize where it was pointlessly present. Drop redundant
 776         *word.
 777         * i386-tbl.h: Re-generate.
 778
 779 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 780
 781         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 782         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 783         (intel_operand_size): Handle v_bndmk_mode.
 784         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 785
 786 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 787
 788         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 789
 790 2018-08-31  Kito Cheng  <kito@andestech.com>
 791
 792         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 793         compressed floating point instructions.
 794
 795 2018-08-30  Kito Cheng  <kito@andestech.com>
 796
 797         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 798         riscv_opcode.xlen_requirement.
 799         * riscv-opc.c (riscv_opcodes): Update for struct change.
 800
 801 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 802
 803         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 804         psr (PWRPSR) instruction.
 805
 806 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 807
 808         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 809
 810 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 811
 812         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 813
 814 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 815
 816         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 817         loongson3a as an alias of gs464 for compatibility.
 818         * mips-opc.c (mips_opcodes): Change Comments.
 819
 820 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 821
 822         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 823         option.
 824         (print_mips_disassembler_options): Document -M loongson-ext.
 825         * mips-opc.c (LEXT2): New macro.
 826         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 827
 828 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 829
 830          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 831          descriptors.
 832          (parse_mips_ase_option): Handle -M loongson-ext option.
 833          (print_mips_disassembler_options): Document -M loongson-ext.
 834          * mips-opc.c (IL3A): Delete.
 835          * mips-opc.c (LEXT): New macro.
 836          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 837          instructions.
 838
 839 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 840
 841         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 842         descriptors.
 843         (parse_mips_ase_option): Handle -M loongson-cam option.
 844         (print_mips_disassembler_options): Document -M loongson-cam.
 845         * mips-opc.c (LCAM): New macro.
 846         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 847         instructions.
 848
 849 2018-08-21  Alan Modra  <amodra@gmail.com>
 850
 851         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 852         (skip_optional_operands): Count optional operands, and update
 853         ppc_optional_operand_value call.
 854         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 855         (extract_vlensi): Likewise.
 856         (extract_fxm): Return default value for missing optional operand.
 857         (extract_ls, extract_raq, extract_tbr): Likewise.
 858         (insert_sxl, extract_sxl): New functions.
 859         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 860         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 861         flag and extra entry.
 862         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 863         extract_sxl.
 864
 865 2018-08-20  Alan Modra  <amodra@gmail.com>
 866
 867         * sh-opc.h (MASK): Simplify.
 868
 869 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 870
 871         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 872         BM_RESERVED0 or BM_RESERVED1
 873         (bm_rel_decode, bm_n_bytes): Ditto.
 874
 875 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 876
 877         * s12z.h: Delete.
 878
 879 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 880
 881         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 882         address with the addr32 prefix and without base nor index
 883         registers.
 884
 885 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 886
 887         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 888         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 889         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 890         (cpu_flags): Add CpuCMOV and CpuFXSR.
 891         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 892         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 893         * i386-init.h: Regenerated.
 894         * i386-tbl.h: Likewise.
 895
 896 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 897
 898         * arc-regs.h: Update auxiliary registers.
 899
 900 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 901
 902         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 903         (RegIP, RegIZ): Define.
 904         * i386-reg.tbl: Adjust comments.
 905         (rip): Use Qword instead of BaseIndex. Use RegIP.
 906         (eip): Use Dword instead of BaseIndex. Use RegIP.
 907         (riz): Add Qword. Use RegIZ.
 908         (eiz): Add Dword. Use RegIZ.
 909         * i386-tbl.h: Re-generate.
 910
 911 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 912
 913         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 914         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 915         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 916         * i386-tbl.h: Re-generate.
 917
 918 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 919
 920         * i386-gen.c (operand_types): Remove Mem field.
 921         * i386-opc.h (union i386_operand_type): Remove mem field.
 922         * i386-init.h, i386-tbl.h: Re-generate.
 923
 924 2018-08-01  Alan Modra  <amodra@gmail.com>
 925
 926         * po/POTFILES.in: Regenerate.
 927
 928 2018-07-31  Nick Clifton  <nickc@redhat.com>
 929
 930         * po/sv.po: Updated Swedish translation.
 931
 932 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 933
 934         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 935         * i386-init.h, i386-tbl.h: Re-generate.
 936
 937 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 938
 939         * i386-opc.h (ZEROING_MASKING) Rename to ...
 940         (DYNAMIC_MASKING): ... this. Adjust comment.
 941         * i386-opc.tbl (MaskingMorZ): Define.
 942         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 943         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 944         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 945         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 946         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 947         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 948         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 949         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 950         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 951
 952 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-opc.tbl: Use element rather than vector size for AVX512*
 955         scatter/gather insns.
 956         * i386-tbl.h: Re-generate.
 957
 958 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 959
 960         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 961         (cpu_flags): Drop CpuVREX.
 962         * i386-opc.h (CpuVREX): Delete.
 963         (union i386_cpu_flags): Remove cpuvrex.
 964         * i386-init.h, i386-tbl.h: Re-generate.
 965
 966 2018-07-30  Jim Wilson  <jimw@sifive.com>
 967
 968         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 969         fields.
 970         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 971
 972 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 973
 974         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 975         * Makefile.in: Regenerated.
 976         * configure.ac: Add C-SKY.
 977         * configure: Regenerated.
 978         * csky-dis.c: New file.
 979         * csky-opc.h: New file.
 980         * disassemble.c (ARCH_csky): Define.
 981         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 982         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 983
 984 2018-07-27  Alan Modra  <amodra@gmail.com>
 985
 986         * ppc-opc.c (insert_sprbat): Correct function parameter and
 987         return type.
 988         (extract_sprbat): Likewise, variable too.
 989
 990 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 991             Alan Modra  <amodra@gmail.com>
 992
 993         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 994         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 995         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 996         support disjointed BAT.
 997         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 998         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 999         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1000
1001 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1002             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1003
1004         * i386-gen.c (adjust_broadcast_modifier): New function.
1005         (process_i386_opcode_modifier): Add an argument for operands.
1006         Adjust the Broadcast value based on operands.
1007         (output_i386_opcode): Pass operand_types to
1008         process_i386_opcode_modifier.
1009         (process_i386_opcodes): Pass NULL as operands to
1010         process_i386_opcode_modifier.
1011         * i386-opc.h (BYTE_BROADCAST): New.
1012         (WORD_BROADCAST): Likewise.
1013         (DWORD_BROADCAST): Likewise.
1014         (QWORD_BROADCAST): Likewise.
1015         (i386_opcode_modifier): Expand broadcast to 3 bits.
1016         * i386-tbl.h: Regenerated.
1017
1018 2018-07-24  Alan Modra  <amodra@gmail.com>
1019
1020         PR 23430
1021         * or1k-desc.h: Regenerate.
1022
1023 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1024
1025         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1026         vcvtusi2ss, and vcvtusi2sd.
1027         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1028         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1029         * i386-tbl.h: Re-generate.
1030
1031 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1032
1033         * arc-opc.c (extract_w6): Fix extending the sign.
1034
1035 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1036
1037         * arc-tbl.h (vewt): Allow it for ARC EM family.
1038
1039 2018-07-23  Alan Modra  <amodra@gmail.com>
1040
1041         PR 23419
1042         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1043         opcode variants for mtspr/mfspr encodings.
1044
1045 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1046             Maciej W. Rozycki  <macro@mips.com>
1047
1048         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1049         loongson3a descriptors.
1050         (parse_mips_ase_option): Handle -M loongson-mmi option.
1051         (print_mips_disassembler_options): Document -M loongson-mmi.
1052         * mips-opc.c (LMMI): New macro.
1053         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1054         instructions.
1055
1056 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1057
1058         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1059         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1060         IgnoreSize and [XYZ]MMword where applicable.
1061         * i386-tbl.h: Re-generate.
1062
1063 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1066         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1067         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1068         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1069         * i386-tbl.h: Re-generate.
1070
1071 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1072
1073         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1074         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1075         VPCLMULQDQ templates into their respective AVX512VL counterparts
1076         where possible, using Disp8ShiftVL and CheckRegSize instead of
1077         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1078         * i386-tbl.h: Re-generate.
1079
1080 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1081
1082         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1083         AVX512VL counterparts where possible, using Disp8ShiftVL and
1084         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1085         IgnoreSize) as appropriate.
1086         * i386-tbl.h: Re-generate.
1087
1088 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1089
1090         * i386-opc.tbl: Fold AVX512BW templates into their respective
1091         AVX512VL counterparts where possible, using Disp8ShiftVL and
1092         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1093         IgnoreSize) as appropriate.
1094         * i386-tbl.h: Re-generate.
1095
1096 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1097
1098         * i386-opc.tbl: Fold AVX512CD templates into their respective
1099         AVX512VL counterparts where possible, using Disp8ShiftVL and
1100         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1101         IgnoreSize) as appropriate.
1102         * i386-tbl.h: Re-generate.
1103
1104 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1105
1106         * i386-opc.h (DISP8_SHIFT_VL): New.
1107         * i386-opc.tbl (Disp8ShiftVL):  Define.
1108         (various): Fold AVX512VL templates into their respective
1109         AVX512F counterparts where possible, using Disp8ShiftVL and
1110         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1111         IgnoreSize) as appropriate.
1112         * i386-tbl.h: Re-generate.
1113
1114 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1115
1116         * Makefile.am: Change dependencies and rule for
1117         $(srcdir)/i386-init.h.
1118         * Makefile.in: Re-generate.
1119         * i386-gen.c (process_i386_opcodes): New local variable
1120         "marker". Drop opening of input file. Recognize marker and line
1121         number directives.
1122         * i386-opc.tbl (OPCODE_I386_H): Define.
1123         (i386-opc.h): Include it.
1124         (None): Undefine.
1125
1126 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1127
1128         PR gas/23418
1129         * i386-opc.h (Byte): Update comments.
1130         (Word): Likewise.
1131         (Dword): Likewise.
1132         (Fword): Likewise.
1133         (Qword): Likewise.
1134         (Tbyte): Likewise.
1135         (Xmmword): Likewise.
1136         (Ymmword): Likewise.
1137         (Zmmword): Likewise.
1138         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1139         vcvttps2uqq.
1140         * i386-tbl.h: Regenerated.
1141
1142 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1143
1144         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1145         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1146         * aarch64-asm-2.c: Regenerate.
1147         * aarch64-dis-2.c: Regenerate.
1148         * aarch64-opc-2.c: Regenerate.
1149
1150 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1151
1152         PR binutils/23192
1153         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1154         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1155         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1156         sqdmulh, sqrdmulh): Use Em16.
1157
1158 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1159
1160         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1161         csdb together with them.
1162         (thumb32_opcodes): Likewise.
1163
1164 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1165
1166         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1167         requiring 32-bit registers as operands 2 and 3. Improve
1168         comments.
1169         (mwait, mwaitx): Fold templates. Improve comments.
1170         OPERAND_TYPE_INOUTPORTREG.
1171         * i386-tbl.h: Re-generate.
1172
1173 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1174
1175         * i386-gen.c (operand_type_init): Remove
1176         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1177         OPERAND_TYPE_INOUTPORTREG.
1178         * i386-init.h: Re-generate.
1179
1180 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1181
1182         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1183         (wrssq, wrussq): Add Qword.
1184         * i386-tbl.h: Re-generate.
1185
1186 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1187
1188         * i386-opc.h: Rename OTMax to OTNum.
1189         (OTNumOfUints): Adjust calculation.
1190         (OTUnused): Directly alias to OTNum.
1191
1192 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1193
1194         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1195         `reg_xys'.
1196         (lea_reg_xys): Likewise.
1197         (print_insn_loop_primitive): Rename `reg' local variable to
1198         `reg_dxy'.
1199
1200 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1201
1202         PR binutils/23242
1203         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1204
1205 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1206
1207         PR binutils/23369
1208         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1209         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1210
1211 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1212
1213         PR tdep/8282
1214         * mips-dis.c (mips_option_arg_t): New enumeration.
1215         (mips_options): New variable.
1216         (disassembler_options_mips): New function.
1217         (print_mips_disassembler_options): Reimplement in terms of
1218         `disassembler_options_mips'.
1219         * arm-dis.c (disassembler_options_arm): Adapt to using the
1220         `disasm_options_and_args_t' structure.
1221         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1222         * s390-dis.c (disassembler_options_s390): Likewise.
1223
1224 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1225
1226         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1227         expected result.
1228         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1229         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1230         * testsuite/ld-arm/tls-longplt.d: Likewise.
1231
1232 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1233
1234         PR binutils/23192
1235         * aarch64-asm-2.c: Regenerate.
1236         * aarch64-dis-2.c: Likewise.
1237         * aarch64-opc-2.c: Likewise.
1238         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1239         * aarch64-opc.c (operand_general_constraint_met_p,
1240         aarch64_print_operand): Likewise.
1241         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1242         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1243         fmlal2, fmlsl2.
1244         (AARCH64_OPERANDS): Add Em2.
1245
1246 2018-06-26  Nick Clifton  <nickc@redhat.com>
1247
1248         * po/uk.po: Updated Ukranian translation.
1249         * po/de.po: Updated German translation.
1250         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1251
1252 2018-06-26  Nick Clifton  <nickc@redhat.com>
1253
1254         * nfp-dis.c: Fix spelling mistake.
1255
1256 2018-06-24  Nick Clifton  <nickc@redhat.com>
1257
1258         * configure: Regenerate.
1259         * po/opcodes.pot: Regenerate.
1260
1261 2018-06-24  Nick Clifton  <nickc@redhat.com>
1262
1263         2.31 branch created.
1264
1265 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1266
1267         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1268         * aarch64-asm-2.c: Regenerate.
1269         * aarch64-dis-2.c: Likewise.
1270
1271 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1272
1273         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1274         `-M ginv' option description.
1275
1276 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1277
1278         PR gas/23305
1279         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1280         la and lla.
1281
1282 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1283
1284         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1285         * configure.ac: Remove AC_PREREQ.
1286         * Makefile.in: Re-generate.
1287         * aclocal.m4: Re-generate.
1288         * configure: Re-generate.
1289
1290 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1291
1292         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1293         mips64r6 descriptors.
1294         (parse_mips_ase_option): Handle -Mginv option.
1295         (print_mips_disassembler_options): Document -Mginv.
1296         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1297         (GINV): New macro.
1298         (mips_opcodes): Define ginvi and ginvt.
1299
1300 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1301             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1302
1303         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1304         * mips-opc.c (CRC, CRC64): New macros.
1305         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1306         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1307         crc32cd for CRC64.
1308
1309 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1310
1311         PR 20319
1312         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1313         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1314
1315 2018-06-06  Alan Modra  <amodra@gmail.com>
1316
1317         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1318         setjmp.  Move init for some other vars later too.
1319
1320 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1321
1322         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1323         (dis_private): Add new fields for property section tracking.
1324         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1325         (xtensa_instruction_fits): New functions.
1326         (fetch_data): Bump minimal fetch size to 4.
1327         (print_insn_xtensa): Make struct dis_private static.
1328         Load and prepare property table on section change.
1329         Don't disassemble literals. Don't disassemble instructions that
1330         cross property table boundaries.
1331
1332 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1333
1334         * configure: Regenerated.
1335
1336 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1337
1338         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1339         * i386-tbl.h: Re-generate.
1340
1341 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1342
1343         * i386-opc.tbl (sldt, str): Add NoRex64.
1344         * i386-tbl.h: Re-generate.
1345
1346 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1347
1348         * i386-opc.tbl (invpcid): Add Oword.
1349         * i386-tbl.h: Re-generate.
1350
1351 2018-06-01  Alan Modra  <amodra@gmail.com>
1352
1353         * sysdep.h (_bfd_error_handler): Don't declare.
1354         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1355         * rl78-decode.opc: Likewise.
1356         * msp430-decode.c: Regenerate.
1357         * rl78-decode.c: Regenerate.
1358
1359 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1360
1361         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1362         * i386-init.h : Regenerated.
1363
1364 2018-05-25  Alan Modra  <amodra@gmail.com>
1365
1366         * Makefile.in: Regenerate.
1367         * po/POTFILES.in: Regenerate.
1368
1369 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1370
1371         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1372         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1373         (insert_bab, extract_bab, insert_btab, extract_btab,
1374         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1375         (BAT, BBA VBA RBS XB6S): Delete macros.
1376         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1377         (BB, BD, RBX, XC6): Update for new macros.
1378         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1379         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1380         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1381         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1382
1383 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1384
1385         * Makefile.am: Add support for s12z architecture.
1386         * configure.ac: Likewise.
1387         * disassemble.c: Likewise.
1388         * disassemble.h: Likewise.
1389         * Makefile.in: Regenerate.
1390         * configure: Regenerate.
1391         * s12z-dis.c: New file.
1392         * s12z.h: New file.
1393
1394 2018-05-18  Alan Modra  <amodra@gmail.com>
1395
1396         * nfp-dis.c: Don't #include libbfd.h.
1397         (init_nfp3200_priv): Use bfd_get_section_contents.
1398         (nit_nfp6000_mecsr_sec): Likewise.
1399
1400 2018-05-17  Nick Clifton  <nickc@redhat.com>
1401
1402         * po/zh_CN.po: Updated simplified Chinese translation.
1403
1404 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1405
1406         PR binutils/23109
1407         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1408         * aarch64-dis-2.c: Regenerate.
1409
1410 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1411
1412         PR binutils/21446
1413         * aarch64-asm.c (opintl.h): Include.
1414         (aarch64_ins_sysreg): Enforce read/write constraints.
1415         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1416         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1417         (F_REG_READ, F_REG_WRITE): New.
1418         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1419         AARCH64_OPND_SYSREG.
1420         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1421         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1422         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1423         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1424         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1425         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1426         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1427         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1428         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1429         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1430         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1431         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1432         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1433         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1434         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1435         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1436         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1437
1438 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1439
1440         PR binutils/21446
1441         * aarch64-dis.c (no_notes: New.
1442         (parse_aarch64_dis_option): Support notes.
1443         (aarch64_decode_insn, print_operands): Likewise.
1444         (print_aarch64_disassembler_options): Document notes.
1445         * aarch64-opc.c (aarch64_print_operand): Support notes.
1446
1447 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1448
1449         PR binutils/21446
1450         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1451         and take error struct.
1452         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1453         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1454         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1455         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1456         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1457         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1458         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1459         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1460         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1461         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1462         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1463         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1464         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1465         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1466         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1467         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1468         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1469         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1470         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1471         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1472         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1473         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1474         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1475         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1476         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1477         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1478         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1479         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1480         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1481         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1482         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1483         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1484         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1485         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1486         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1487         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1488         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1489         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1490         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1491         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1492         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1493         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1494         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1495         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1496         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1497         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1498         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1499         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1500         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1501         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1502         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1503         (determine_disassembling_preference, aarch64_decode_insn,
1504         print_insn_aarch64_word, print_insn_data): Take errors struct.
1505         (print_insn_aarch64): Use errors.
1506         * aarch64-asm-2.c: Regenerate.
1507         * aarch64-dis-2.c: Regenerate.
1508         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1509         boolean in aarch64_insert_operan.
1510         (print_operand_extractor): Likewise.
1511         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1512
1513 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1514
1515         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1516
1517 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1518
1519         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1520
1521 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1522
1523         * cr16-opc.c (cr16_instruction): Comment typo fix.
1524         * hppa-dis.c (print_insn_hppa): Likewise.
1525
1526 2018-05-08  Jim Wilson  <jimw@sifive.com>
1527
1528         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1529         (match_c_slli64, match_srxi_as_c_srxi): New.
1530         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1531         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1532         <c.slli, c.srli, c.srai>: Use match_s_slli.
1533         <c.slli64, c.srli64, c.srai64>: New.
1534
1535 2018-05-08  Alan Modra  <amodra@gmail.com>
1536
1537         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1538         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1539         partition opcode space for index lookup.
1540
1541 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1542
1543         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1544         <insn_length>: ...with this.  Update usage.
1545         Remove duplicate call to *info->memory_error_func.
1546
1547 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1548             H.J. Lu  <hongjiu.lu@intel.com>
1549
1550         * i386-dis.c (Gva): New.
1551         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1552         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1553         (prefix_table): New instructions (see prefix above).
1554         (mod_table): New instructions (see prefix above).
1555         (OP_G): Handle va_mode.
1556         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1557         CPU_MOVDIR64B_FLAGS.
1558         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1559         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1560         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1561         * i386-opc.tbl: Add movidir{i,64b}.
1562         * i386-init.h: Regenerated.
1563         * i386-tbl.h: Likewise.
1564
1565 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1566
1567         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1568         AddrPrefixOpReg.
1569         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1570         (AddrPrefixOpReg): This.
1571         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1572         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1573
1574 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1575
1576         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1577         (vle_num_opcodes): Likewise.
1578         (spe2_num_opcodes): Likewise.
1579         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1580         initialization loop.
1581         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1582         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1583         only once.
1584
1585 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1586
1587         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1588
1589 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1590
1591         Makefile.am: Added nfp-dis.c.
1592         configure.ac: Added bfd_nfp_arch.
1593         disassemble.h: Added print_insn_nfp prototype.
1594         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1595         nfp-dis.c: New, for NFP support.
1596         po/POTFILES.in: Added nfp-dis.c to the list.
1597         Makefile.in: Regenerate.
1598         configure: Regenerate.
1599
1600 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1601
1602         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1603         templates into their base ones.
1604         * i386-tlb.h: Re-generate.
1605
1606 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1607
1608         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1609         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1610         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1611         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1612         * i386-init.h: Re-generate.
1613
1614 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1615
1616         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1617         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1618         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1619         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1620         comment.
1621         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1622         and CpuRegMask.
1623         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1624         CpuRegMask: Delete.
1625         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1626         cpuregzmm, and cpuregmask.
1627         * i386-init.h: Re-generate.
1628         * i386-tbl.h: Re-generate.
1629
1630 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1631
1632         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1633         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1634         * i386-init.h: Re-generate.
1635
1636 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1637
1638         * i386-gen.c (VexImmExt): Delete.
1639         * i386-opc.h (VexImmExt, veximmext): Delete.
1640         * i386-opc.tbl: Drop all VexImmExt uses.
1641         * i386-tlb.h: Re-generate.
1642
1643 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1644
1645         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1646         register-only forms.
1647         * i386-tlb.h: Re-generate.
1648
1649 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1650
1651         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1652
1653 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1654
1655         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1656         PREFIX_0F1C.
1657         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1658         (cpu_flags): Add CpuCLDEMOTE.
1659         * i386-init.h: Regenerate.
1660         * i386-opc.h (enum): Add CpuCLDEMOTE,
1661         (i386_cpu_flags): Add cpucldemote.
1662         * i386-opc.tbl: Add cldemote.
1663         * i386-tbl.h: Regenerate.
1664
1665 2018-04-16  Alan Modra  <amodra@gmail.com>
1666
1667         * Makefile.am: Remove sh5 and sh64 support.
1668         * configure.ac: Likewise.
1669         * disassemble.c: Likewise.
1670         * disassemble.h: Likewise.
1671         * sh-dis.c: Likewise.
1672         * sh64-dis.c: Delete.
1673         * sh64-opc.c: Delete.
1674         * sh64-opc.h: Delete.
1675         * Makefile.in: Regenerate.
1676         * configure: Regenerate.
1677         * po/POTFILES.in: Regenerate.
1678
1679 2018-04-16  Alan Modra  <amodra@gmail.com>
1680
1681         * Makefile.am: Remove w65 support.
1682         * configure.ac: Likewise.
1683         * disassemble.c: Likewise.
1684         * disassemble.h: Likewise.
1685         * w65-dis.c: Delete.
1686         * w65-opc.h: Delete.
1687         * Makefile.in: Regenerate.
1688         * configure: Regenerate.
1689         * po/POTFILES.in: Regenerate.
1690
1691 2018-04-16  Alan Modra  <amodra@gmail.com>
1692
1693         * configure.ac: Remove we32k support.
1694         * configure: Regenerate.
1695
1696 2018-04-16  Alan Modra  <amodra@gmail.com>
1697
1698         * Makefile.am: Remove m88k support.
1699         * configure.ac: Likewise.
1700         * disassemble.c: Likewise.
1701         * disassemble.h: Likewise.
1702         * m88k-dis.c: Delete.
1703         * Makefile.in: Regenerate.
1704         * configure: Regenerate.
1705         * po/POTFILES.in: Regenerate.
1706
1707 2018-04-16  Alan Modra  <amodra@gmail.com>
1708
1709         * Makefile.am: Remove i370 support.
1710         * configure.ac: Likewise.
1711         * disassemble.c: Likewise.
1712         * disassemble.h: Likewise.
1713         * i370-dis.c: Delete.
1714         * i370-opc.c: Delete.
1715         * Makefile.in: Regenerate.
1716         * configure: Regenerate.
1717         * po/POTFILES.in: Regenerate.
1718
1719 2018-04-16  Alan Modra  <amodra@gmail.com>
1720
1721         * Makefile.am: Remove h8500 support.
1722         * configure.ac: Likewise.
1723         * disassemble.c: Likewise.
1724         * disassemble.h: Likewise.
1725         * h8500-dis.c: Delete.
1726         * h8500-opc.h: Delete.
1727         * Makefile.in: Regenerate.
1728         * configure: Regenerate.
1729         * po/POTFILES.in: Regenerate.
1730
1731 2018-04-16  Alan Modra  <amodra@gmail.com>
1732
1733         * configure.ac: Remove tahoe support.
1734         * configure: Regenerate.
1735
1736 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1737
1738         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1739         umwait.
1740         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1741         64-bit mode.
1742         * i386-tbl.h: Regenerated.
1743
1744 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1745
1746         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1747         PREFIX_MOD_1_0FAE_REG_6.
1748         (va_mode): New.
1749         (OP_E_register): Use va_mode.
1750         * i386-dis-evex.h (prefix_table):
1751         New instructions (see prefixes above).
1752         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1753         (cpu_flags): Likewise.
1754         * i386-opc.h (enum): Likewise.
1755         (i386_cpu_flags): Likewise.
1756         * i386-opc.tbl: Add umonitor, umwait, tpause.
1757         * i386-init.h: Regenerate.
1758         * i386-tbl.h: Likewise.
1759
1760 2018-04-11  Alan Modra  <amodra@gmail.com>
1761
1762         * opcodes/i860-dis.c: Delete.
1763         * opcodes/i960-dis.c: Delete.
1764         * Makefile.am: Remove i860 and i960 support.
1765         * configure.ac: Likewise.
1766         * disassemble.c: Likewise.
1767         * disassemble.h: Likewise.
1768         * Makefile.in: Regenerate.
1769         * configure: Regenerate.
1770         * po/POTFILES.in: Regenerate.
1771
1772 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1773
1774         PR binutils/23025
1775         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1776         to 0.
1777         (print_insn): Clear vex instead of vex.evex.
1778
1779 2018-04-04  Nick Clifton  <nickc@redhat.com>
1780
1781         * po/es.po: Updated Spanish translation.
1782
1783 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1784
1785         * i386-gen.c (opcode_modifiers): Delete VecESize.
1786         * i386-opc.h (VecESize): Delete.
1787         (struct i386_opcode_modifier): Delete vecesize.
1788         * i386-opc.tbl: Drop VecESize.
1789         * i386-tlb.h: Re-generate.
1790
1791 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1792
1793         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1794         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1795         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1796         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1797         * i386-tlb.h: Re-generate.
1798
1799 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1800
1801         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1802         Fold AVX512 forms
1803         * i386-tlb.h: Re-generate.
1804
1805 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1806
1807         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1808         (vex_len_table): Drop Y for vcvt*2si.
1809         (putop): Replace plain 'Y' handling by abort().
1810
1811 2018-03-28  Nick Clifton  <nickc@redhat.com>
1812
1813         PR 22988
1814         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1815         instructions with only a base address register.
1816         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1817         handle AARHC64_OPND_SVE_ADDR_R.
1818         (aarch64_print_operand): Likewise.
1819         * aarch64-asm-2.c: Regenerate.
1820         * aarch64_dis-2.c: Regenerate.
1821         * aarch64-opc-2.c: Regenerate.
1822
1823 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1824
1825         * i386-opc.tbl: Drop VecESize from register only insn forms and
1826         memory forms not allowing broadcast.
1827         * i386-tlb.h: Re-generate.
1828
1829 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1830
1831         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1832         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1833         sha256*): Drop Disp<N>.
1834
1835 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1836
1837         * i386-dis.c (EbndS, bnd_swap_mode): New.
1838         (prefix_table): Use EbndS.
1839         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1840         * i386-opc.tbl (bndmov): Move misplaced Load.
1841         * i386-tlb.h: Re-generate.
1842
1843 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1844
1845         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1846         templates allowing memory operands and folded ones for register
1847         only flavors.
1848         * i386-tlb.h: Re-generate.
1849
1850 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1851
1852         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1853         256-bit templates. Drop redundant leftover Disp<N>.
1854         * i386-tlb.h: Re-generate.
1855
1856 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1857
1858         * riscv-opc.c (riscv_insn_types): New.
1859
1860 2018-03-13  Nick Clifton  <nickc@redhat.com>
1861
1862         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1863
1864 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1865
1866         * i386-opc.tbl: Add Optimize to clr.
1867         * i386-tbl.h: Regenerated.
1868
1869 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1870
1871         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1872         * i386-opc.h (OldGcc): Removed.
1873         (i386_opcode_modifier): Remove oldgcc.
1874         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1875         instructions for old (<= 2.8.1) versions of gcc.
1876         * i386-tbl.h: Regenerated.
1877
1878 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1879
1880         * i386-opc.h (EVEXDYN): New.
1881         * i386-opc.tbl: Fold various AVX512VL templates.
1882         * i386-tlb.h: Re-generate.
1883
1884 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1885
1886         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1887         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1888         vpexpandd, vpexpandq): Fold AFX512VF templates.
1889         * i386-tlb.h: Re-generate.
1890
1891 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1892
1893         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1894         Fold 128- and 256-bit VEX-encoded templates.
1895         * i386-tlb.h: Re-generate.
1896
1897 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1898
1899         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1900         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1901         vpexpandd, vpexpandq): Fold AVX512F templates.
1902         * i386-tlb.h: Re-generate.
1903
1904 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1905
1906         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1907         64-bit templates. Drop Disp<N>.
1908         * i386-tlb.h: Re-generate.
1909
1910 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1911
1912         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1913         and 256-bit templates.
1914         * i386-tlb.h: Re-generate.
1915
1916 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1917
1918         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1919         * i386-tlb.h: Re-generate.
1920
1921 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1922
1923         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1924         Drop NoAVX.
1925         * i386-tlb.h: Re-generate.
1926
1927 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1928
1929         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1930         * i386-tlb.h: Re-generate.
1931
1932 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1933
1934         * i386-gen.c (opcode_modifiers): Delete FloatD.
1935         * i386-opc.h (FloatD): Delete.
1936         (struct i386_opcode_modifier): Delete floatd.
1937         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1938         FloatD by D.
1939         * i386-tlb.h: Re-generate.
1940
1941 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1942
1943         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1944
1945 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1946
1947         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1948         * i386-tlb.h: Re-generate.
1949
1950 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1951
1952         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1953         forms.
1954         * i386-tlb.h: Re-generate.
1955
1956 2018-03-07  Alan Modra  <amodra@gmail.com>
1957
1958         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1959         bfd_arch_rs6000.
1960         * disassemble.h (print_insn_rs6000): Delete.
1961         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1962         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1963         (print_insn_rs6000): Delete.
1964
1965 2018-03-03  Alan Modra  <amodra@gmail.com>
1966
1967         * sysdep.h (opcodes_error_handler): Define.
1968         (_bfd_error_handler): Declare.
1969         * Makefile.am: Remove stray #.
1970         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1971         EDIT" comment.
1972         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1973         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1974         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1975         opcodes_error_handler to print errors.  Standardize error messages.
1976         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1977         and include opintl.h.
1978         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1979         * i386-gen.c: Standardize error messages.
1980         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1981         * Makefile.in: Regenerate.
1982         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1983         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1984         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1985         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1986         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1987         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1988         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1989         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1990         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1991         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1992         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1993         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1994         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1995
1996 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1997
1998         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1999         vpsub[bwdq] instructions.
2000         * i386-tbl.h: Regenerated.
2001
2002 2018-03-01  Alan Modra  <amodra@gmail.com>
2003
2004         * configure.ac (ALL_LINGUAS): Sort.
2005         * configure: Regenerate.
2006
2007 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2008
2009         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2010         macro by assignements.
2011
2012 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2013
2014         PR gas/22871
2015         * i386-gen.c (opcode_modifiers): Add Optimize.
2016         * i386-opc.h (Optimize): New enum.
2017         (i386_opcode_modifier): Add optimize.
2018         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2019         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2020         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2021         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2022         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2023         vpxord and vpxorq.
2024         * i386-tbl.h: Regenerated.
2025
2026 2018-02-26  Alan Modra  <amodra@gmail.com>
2027
2028         * crx-dis.c (getregliststring): Allocate a large enough buffer
2029         to silence false positive gcc8 warning.
2030
2031 2018-02-22  Shea Levy <shea@shealevy.com>
2032
2033         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2034
2035 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2036
2037         * i386-opc.tbl: Add {rex},
2038         * i386-tbl.h: Regenerated.
2039
2040 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2041
2042         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2043         (mips16_opcodes): Replace `M' with `m' for "restore".
2044
2045 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2046
2047         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2048
2049 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2050
2051         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2052         variable to `function_index'.
2053
2054 2018-02-13  Nick Clifton  <nickc@redhat.com>
2055
2056         PR 22823
2057         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2058         about truncation of printing.
2059
2060 2018-02-12  Henry Wong <henry@stuffedcow.net>
2061
2062         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2063
2064 2018-02-05  Nick Clifton  <nickc@redhat.com>
2065
2066         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2067
2068 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2069
2070         * i386-dis.c (enum): Add pconfig.
2071         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2072         (cpu_flags): Add CpuPCONFIG.
2073         * i386-opc.h (enum): Add CpuPCONFIG.
2074         (i386_cpu_flags): Add cpupconfig.
2075         * i386-opc.tbl: Add PCONFIG instruction.
2076         * i386-init.h: Regenerate.
2077         * i386-tbl.h: Likewise.
2078
2079 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2080
2081         * i386-dis.c (enum): Add PREFIX_0F09.
2082         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2083         (cpu_flags): Add CpuWBNOINVD.
2084         * i386-opc.h (enum): Add CpuWBNOINVD.
2085         (i386_cpu_flags): Add cpuwbnoinvd.
2086         * i386-opc.tbl: Add WBNOINVD instruction.
2087         * i386-init.h: Regenerate.
2088         * i386-tbl.h: Likewise.
2089
2090 2018-01-17  Jim Wilson  <jimw@sifive.com>
2091
2092         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2093
2094 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2095
2096         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2097         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2098         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2099         (cpu_flags): Add CpuIBT, CpuSHSTK.
2100         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2101         (i386_cpu_flags): Add cpuibt, cpushstk.
2102         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2103         * i386-init.h: Regenerate.
2104         * i386-tbl.h: Likewise.
2105
2106 2018-01-16  Nick Clifton  <nickc@redhat.com>
2107
2108         * po/pt_BR.po: Updated Brazilian Portugese translation.
2109         * po/de.po: Updated German translation.
2110
2111 2018-01-15  Jim Wilson  <jimw@sifive.com>
2112
2113         * riscv-opc.c (match_c_nop): New.
2114         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2115
2116 2018-01-15  Nick Clifton  <nickc@redhat.com>
2117
2118         * po/uk.po: Updated Ukranian translation.
2119
2120 2018-01-13  Nick Clifton  <nickc@redhat.com>
2121
2122         * po/opcodes.pot: Regenerated.
2123
2124 2018-01-13  Nick Clifton  <nickc@redhat.com>
2125
2126         * configure: Regenerate.
2127
2128 2018-01-13  Nick Clifton  <nickc@redhat.com>
2129
2130         2.30 branch created.
2131
2132 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2133
2134         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2135         * i386-tbl.h: Regenerate.
2136
2137 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2138
2139         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2140         * i386-tbl.h: Re-generate.
2141
2142 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2143
2144         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2145         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2146         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2147         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2148         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2149         Disp8MemShift of AVX512VL forms.
2150         * i386-tbl.h: Re-generate.
2151
2152 2018-01-09  Jim Wilson  <jimw@sifive.com>
2153
2154         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2155         then the hi_addr value is zero.
2156
2157 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2158
2159         * arm-dis.c (arm_opcodes): Add csdb.
2160         (thumb32_opcodes): Add csdb.
2161
2162 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2163
2164         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2165         * aarch64-asm-2.c: Regenerate.
2166         * aarch64-dis-2.c: Regenerate.
2167         * aarch64-opc-2.c: Regenerate.
2168
2169 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2170
2171         PR gas/22681
2172         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2173         Remove AVX512 vmovd with 64-bit operands.
2174         * i386-tbl.h: Regenerated.
2175
2176 2018-01-05  Jim Wilson  <jimw@sifive.com>
2177
2178         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2179         jalr.
2180
2181 2018-01-03  Alan Modra  <amodra@gmail.com>
2182
2183         Update year range in copyright notice of all files.
2184
2185 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2186
2187         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2188         and OPERAND_TYPE_REGZMM entries.
2189
2190 For older changes see ChangeLog-2017
2191 \f
2192 Copyright (C) 2018 Free Software Foundation, Inc.
2193
2194 Copying and distribution of this file, with or without modification,
2195 are permitted in any medium without royalty provided the copyright
2196 notice and this notice are preserved.
2197
2198 Local Variables:
2199 mode: change-log
2200 left-margin: 8
2201 fill-column: 74
2202 version-control: never
2203 End: